WO2021233141A1 - Ldpc的速率匹配的方法和通信装置 - Google Patents

Ldpc的速率匹配的方法和通信装置 Download PDF

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WO2021233141A1
WO2021233141A1 PCT/CN2021/092348 CN2021092348W WO2021233141A1 WO 2021233141 A1 WO2021233141 A1 WO 2021233141A1 CN 2021092348 W CN2021092348 W CN 2021092348W WO 2021233141 A1 WO2021233141 A1 WO 2021233141A1
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priority
information bits
matrix
repetition
mother
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French (fr)
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林伟
王慧
类先富
淦明
唐小虎
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6527—IEEE 802.11 [WLAN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H04L1/1845—Combining techniques, e.g. code combining

Definitions

  • This application relates to the field of channel coding, and more specifically, to a method and communication device for LDPC rate matching.
  • LDPC low-density parity check
  • IEEE protocols such as 802.11n, 802.11ac, and 802.11ax propose to use LDPC as a standard channel coding scheme for wireless local area networks (WLAN).
  • WLAN wireless local area networks
  • 802.11ac/ax a total of 12 LDPC check matrices are currently adopted, supporting 3 code lengths, and each code length supports 4 code rates.
  • the sender device selects a corresponding check matrix from 12 check matrices to perform LDPC encoding according to the target code length and code rate.
  • next-generation WLAN standard 802.11be proposes to introduce an incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism on the basis of 802.11ax.
  • IR-HARQ incremental redundancy-hybrid automatic repeat request
  • the IR-HARQ mechanism expects to increase redundant bits through retransmission and reduce the channel coding rate to improve the decoding performance of the receiving end.
  • the current LDPC coding scheme adopted by the WLAN standard cannot meet the requirement of continuously increasing redundant bits through retransmission in the IR-HARQ mechanism to obtain performance gains, and the decoding performance is low.
  • the present application provides a method and communication device for LDPC rate matching, which can improve decoding performance.
  • the present application provides a method for LDPC rate matching.
  • the method includes: the sending end sorts the K information bits of the LDPC mother code according to the repetition priority in the rate matching, and arranges the first bit rate of the first code rate.
  • the LDPC codeword performs rate matching to obtain a second LDPC codeword of the second code rate, where K is a positive integer; the sending end sends the second LDPC codeword.
  • the priority at which information bits are repeated in the rate matching process is referred to as the repetition priority of the information bits.
  • the sending end sorts the information bits of the LDPC codeword according to the repetition priority of the information bits in the rate matching process. Repeat to obtain performance gains at the receiving end. Since the repetition priority of information bits is sorted according to the sensitivity of LDPC codewords, in the repetition priority sorting, the higher the sensitivity of the information bit, the lower the repetition priority, and the lower the sensitivity of the information. The bit repetition priority is higher. Therefore, when the transmitting end repeats the information bits of the LDPC codeword, the information bits with lower sensitivity are preferentially repeated, which can improve the decoding performance of the receiving end.
  • the sending end performs rate matching on the first LDPC codeword of the first code rate according to the sorting of the repetition priority of the K information bits, including:
  • the sending end determines the first information bit in the first LDPC codeword in the order of repetition priority from high to low.
  • the L information bits in the set are repeatedly sent, wherein the repetition priority of the information bit with the lowest repetition priority among the L information bits included in the first information bit set is higher than or equal to the first LDPC
  • the repetition priority of the remaining information bits in the codeword except the information bits in the first information bit set is L ⁇ K, and L is an integer.
  • the first set of information bits refers to all the information bits of the first LDPC codeword, in order of repetition priority from high to low, and the L information bits with the highest repetition priority are repeated.
  • the sequence of the repetition priority of the K information bits is:
  • the number of information bits is K
  • the length of the mother code is N
  • the code rate of the LDPC check matrix is R.
  • the mother code length is 1944
  • the code rate is 1/2
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 10,6,8,11,4,3,12,7,2,5,9,1, where each element a in the sequence represents the parent The ath column of the matrix.
  • the mother code length is 1296
  • the code rate is 1/2
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 8,12,7,3,11,10,4,6,2,5,9,1, where each element a in the sequence represents the parent The ath column of the matrix.
  • the mother code length is 648
  • the code rate is 1/2
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 8,6,12,11,2,3,10,7,4,1,5,9, where each element a in the sequence represents the parent The ath column of the matrix.
  • the mother code has a length of 1944 and a code rate of 2/3.
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4, where the Each element a represents the a-th column of the mother matrix.
  • the mother code has a length of 1296, a code rate of 2/3, and in the order of repetition priority from high to low, the mother matrix corresponds to information
  • the sequence of the repetition priority of the bit column is as follows: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, where Each element a represents the a-th column of the mother matrix.
  • the mother code has a length of 648 and a code rate of 2/3.
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3, where Each element a represents the a-th column of the mother matrix.
  • the mother code has a length of 1944, a code rate of 3/4, and in the order of repetition priority from high to low, the mother matrix corresponds to information
  • the sequence of the repetition priority of the bit column is as follows: 12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6, where Each element a in the sorting represents the a-th column of the mother matrix.
  • the mother code length is 1296
  • the code rate is 3/4
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7, where Each element a in the sorting represents the a-th column of the mother matrix.
  • the mother code length is 648
  • the code rate is 3/4
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5, where Each element a in the sorting represents the a-th column of the mother matrix.
  • the mother code has a length of 1944, a code rate of 5/6, and in the order of repetition priority from high to low, the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10 , Wherein each element a in the sorting represents the a-th column of the mother matrix.
  • the mother code has a length of 1296, a code rate of 5/6, and in order of repetition priority from high to low, the mother matrix corresponds to information
  • the sequence of the repetition priority of the bit column is as follows: 17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 , Wherein each element a in the sorting represents the a-th column of the mother matrix.
  • the mother code has a length of 648 and a code rate of 5/6.
  • the mother matrix corresponds to the information
  • the sequence of the repetition priority of the bit column is as follows: 13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20 , Wherein each element a in the sorting represents the a-th column of the mother matrix.
  • the sending end is based on the number of bits to be repeated, L, and the ordering of the repetition priority of the K information bits, from high to high according to the repetition priority.
  • repeating the information bits with the repetition priority in the first L positions in the first LDPC codeword includes:
  • the sending end selects L information bits from the corresponding z information bits in the check matrix from the column with the highest repeat priority in the mother matrix for repetition;
  • the sending end selects from the mother matrix the mz corresponding to the first m columns with the highest repetition priority in the check matrix in the order of repetition priority from high to low Information bits are repeated, and m is a positive integer;
  • the sending end is based on the number of bits to be repeated, L, and the ordering of the repetition priority of the K information bits, from high to high according to the repetition priority.
  • the method further includes:
  • the sending end determines the repetition priority of the first LDPC codeword from high to low.
  • the repeated transmission of the L information bits included in the first information bit set includes:
  • the sending end is based on the number of repetitive bits L and the ordering of the repetition priority of the K information bits according to the repetition priority In order from high to low, repeatedly sending the L information bits included in the first set of information bits in the first LDPC codeword;
  • the method further includes:
  • the method further includes:
  • the sending end sends the punctured check bits in the first LDPC codeword according to the order of the puncturing priority of the check bits, wherein the check bit with the lower puncturing priority is sent first, so
  • the puncturing priority is used to indicate the priority of (NK) check bits being punctured in rate matching
  • N is the length of the mother code of LDPC
  • N ⁇ K is an integer.
  • the sending end is based on the number of bits to be repeated, L, and the ordering of the repetition priority of the K information bits, from high to high according to the repetition priority.
  • the method further includes:
  • the sending end sends the punctured check bits in the first LDPC codeword according to the priority order of the check bits, Among them, the check bits with the lower puncturing priority are sent first, and the puncturing priority is used to indicate the priority of (NK) check bits being punctured in the rate matching, and N is the length of the LDPC mother code. , N ⁇ K, N is an integer;
  • the sending end determines the repetition priority of the first LDPC codeword from high to low.
  • the repeated transmission of the L information bits included in the first information bit set includes:
  • the sending end follows the repetition priority of the K information bits , Sending the information bits of the first LDPC codeword.
  • the present application provides a communication device that has the function of implementing the method in the first aspect or any possible implementation manner thereof.
  • the function can be realized by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the above-mentioned functions.
  • the present application provides a communication device, including an interface circuit and a processor, the interface circuit is configured to receive computer code or instructions and transmit them to the processor, and the processor runs the computer code or instructions , The method in the first aspect or any of its implementation manners is implemented.
  • the present application provides a communication device, including at least one processor, the at least one processor is coupled to at least one memory, the at least one memory is used to store computer programs or instructions, and the at least one processor is used to The computer program or instruction is called and executed from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation manner thereof.
  • the communication device may be an encoder.
  • the present application provides a computer-readable storage medium in which computer instructions are stored.
  • the computer instructions are run on a computer, the first aspect or any of its possible implementations The method is implemented.
  • the present application provides a computer program product.
  • the computer program product includes computer program code.
  • the method in the first aspect or any possible implementation manner thereof Be realized.
  • the present application provides a wireless communication system, including the communication device according to the fourth aspect.
  • Figure 1 shows the check matrix H of the LDPC code.
  • Figure 2 is a Tanner graph of the parity check matrix H of the LDPC code.
  • FIG. 3 are system architecture diagrams applicable to the embodiments of the present application.
  • Fig. 4 is a flowchart of establishing a sensitivity ranking table of bit positions provided by this application.
  • Figure 5 shows an image of the function.
  • FIG. 6 is a schematic flowchart of a method for LDPC rate matching provided by this application.
  • Fig. 7 is an application example of the repetition scheme provided by this application in IR-HARQ.
  • FIG. 8 is an application example of the combination of the information bit repetition scheme and the check bit puncturing scheme provided in this application in IR-HARQ.
  • Figure 9-19 shows the FER curve and throughput curve of the system under various IR-HARQ transmission strategies.
  • FIG. 20 is a schematic block diagram of a communication device 1000 provided by this application.
  • LDPC low-density parity check
  • LDPC has become a standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE802.11n/ac/ax.
  • IEEE802.11n/ac/ax Low-frequency short-range WLAN communication systems
  • IEEE802.11ax is greater than or equal to 40MHz bandwidth.
  • HARQ hybrid automatic repeat request
  • HARQ roughly includes chase combination (CC) and incremental redundancy (incremental redundancy, IR), which can be called CC HARQ and IR HARQ, respectively.
  • the HARQ mechanism can be considered as two types: chase combination (CC) and incremental redundancy (IR-HARQ).
  • CC chase combination
  • IR-HARQ incremental redundancy
  • the receiving end directly discards the incorrectly received data packet. But in fact, although these incorrectly received data packets cannot be decoded correctly independently, they still contain some useful information.
  • CC-HARQ the process of CC is to use this part of information to store incorrectly received data packets in the memory, and combine them with the retransmitted data packets for decoding, which improves the transmission efficiency.
  • the IR HARQ mechanism means that the sender sends information bits and some redundant bits during the initial transmission, and sends additional redundant bits during retransmission.
  • the sender reduces the channel code rate by retransmitting more redundant bits, thereby increasing the decoding success rate. If the receiver fails to decode successfully after adding the retransmitted redundant bits, the sender performs retransmission again. As the number of retransmissions increases, redundant bits continue to increase, and the Cinda coding rate continues to decrease, so that a better decoding effect can be obtained.
  • next-generation standard of WLAN introduces the IR HARQ mechanism, it needs to be supported by a rate-compatible LDPC (RC-LDPC) encoding scheme that is compatible with multiple rates, so that new incremental redundant bits can be introduced during retransmission. .
  • RC-LDPC rate-compatible LDPC
  • LDPC is a linear block code
  • its check matrix is a sparse matrix, that is, the number of zero elements in the check matrix is far more than the number of non-zero elements, or in other words, the row weight and column of the check matrix The weight is very small compared with the code length of LDPC.
  • Tanner represented the LDPC codeword in a graph in 1981, and now this graphical representation is called a Tanner graph.
  • the Tanner graph corresponds to the check matrix and consists of two types of nodes.
  • One type of node represents the code character number, called variable node, and the other type of node is check node, which represents the check constraint relationship, and each check node represents A check constraint relationship is described below in conjunction with Figure 1 and Figure 2.
  • FIG 1 is the check matrix H of LDPC.
  • ⁇ V i ⁇ represents the variable node set
  • ⁇ C i ⁇ represents the check node set.
  • Each row of the check matrix H represents a check equation, and each column represents a codeword bit.
  • Fig. 2 is a Tanner graph of the check matrix H of the LDPC.
  • the Tanner graph represents the LDPC check matrix.
  • the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes.
  • the n variable nodes correspond to the n columns of the check matrix H
  • the m check nodes correspond to the m rows of the check matrix H.
  • the loop in the Tanner graph is composed of nodes that are connected to each other. The loop uses one node in the group of nodes as the start and end at the same time, and passes through each node only once.
  • the length of the loop is defined as the number of lines it contains, and the girth of the graph can also be called the size of the graph, which is defined as the smallest loop length in the figure, as shown in Figure 2, and the girth is 6, as shown in Figure 2.
  • the blackened connection is shown.
  • the variable node in the Tanner graph corresponds to each column of the check matrix H, that is, corresponds to each codeword bit of the LDPC codeword.
  • the check node in the Tanner graph corresponds to each row of the check matrix H, that is, the check bit of the LDPC codeword.
  • the connection between the two types of nodes corresponds to the value of the element in the H matrix.
  • a cycle refers to a closed loop composed of variable nodes, check nodes, and edges connected end to end.
  • LDPC is a linear block code.
  • the mapping relationship from k-bit information bits to a code group with a length of n bits is usually represented by a corresponding check matrix H. According to the check matrix H, the coding sequence can be generated accordingly to complete the coding process. After the encoded codeword is transmitted through the channel, the receiving end decodes the received signal accordingly, and determines the original information bits.
  • the check matrix H of the LDPC will be very large, so the check matrix H is usually represented by blocks: the check matrix H (specifically, the original check matrix) is regarded as consisting of multiple z ⁇ z Therefore, the check matrix H can be represented by a mother matrix, and each element in the mother matrix corresponds to a z ⁇ z sub-matrix, and each sub-matrix can be represented by a number of cyclic shifts. The storage space required by the check matrix H is greatly reduced. Each check matrix corresponds to a code rate and code length.
  • the embodiment of the application adopts the check matrix in the 802.11ac standard, and supports code lengths of 1944, 1296, and 648. These three code lengths all support code rates of 1/2, 2/3, 3/4, and 5/6. Based on the mother matrix and the expansion factor z given by the 802.11ac standard, the original check matrix H can be obtained.
  • the LDPC codes used in the IEEE 802.11ac and 802.11ax standards are quasi-cyclic low density parity check (QC-LDPC) codes.
  • QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding to reduce the encoding complexity of the LDPC code.
  • IEEE 802.11ac and 802.11ax adopted a total of 12 check matrices, among which 3 types of code lengths are supported.
  • the 3 types of code lengths are 648, 1296, and 1944, respectively.
  • Each code length supports 4 different code rates, namely 1/2, 2/3, 3/4 and 5/6.
  • the check bit parts of the 12 check matrices all have the same structure.
  • the code length is 1944 and the mother matrix of the LDPC check matrix H with a code rate of 5/6 is as follows:
  • the sender selects the corresponding check matrix from the 12 check matrices mentioned above according to the target code length and target code rate. Wherein, the 12 check matrices are different from each other.
  • a rate-compatible LDPC coding scheme needs to be introduced at the same time to obtain new incremental redundant bits during retransmission.
  • the technical solution of this application is mainly applicable to wireless communication systems.
  • the wireless communication system can comply with the wireless communication standards of the third generation partnership project (3GPP), and can also comply with other wireless communication standards, such as IEEE 802. A series of wireless communication standards (for example, 802.11, 802.15, or 802.20).
  • 3GPP third generation partnership project
  • IEEE 802. A series of wireless communication standards for example, 802.11, 802.15, or 802.20.
  • the wireless communication system includes at least one network device and one or more terminal devices.
  • the at least one network device and one or more terminal devices communicate using wireless communication technology.
  • Fig. 3(a) shows communication between a network device and a single terminal device.
  • Figure 3(b) shows that one network device communicates with multiple terminal devices.
  • the above communication between the network device and the terminal device may include downlink transmission of a signal sent by the network device to the terminal device, and uplink transmission of a signal sent by the terminal device to the network device, which is not limited herein.
  • the technical solution of the present application can be applied to the scenario of uplink and downlink data transmission.
  • the sending end in each embodiment is a terminal device, and the receiving end is a network device.
  • the sending end is a network device, and the receiving end is a terminal device.
  • the terminal equipment involved in the embodiments of this application may be user equipment (UE), terminal (terminal), mobile phone (mobile phone), tablet computer, laptop computer, wearable Devices (for example, smart watches, smart bracelets, smart helmets, smart glasses, etc.), and other devices with wireless access capabilities, such as smart cars, various Internet of Things (IOT) devices, including various Smart home devices (for example, smart meters and smart home appliances) and smart city devices (for example, security or monitoring equipment, smart road traffic facilities), 5G systems, or terminal devices in future communication systems, etc.
  • IOT Internet of Things
  • the network device involved in the embodiments of the present application may be a base station, which is sometimes also referred to as a wireless access point (access point, AP), a transmission reception point (TRP), or a transmission point (TP).
  • the base station may be a general node B (generation Node B, gNB) in the fifth generation (5G) system, or an evolution node B (evolutional Node B) in a long term evolution (LTE) system. eNB).
  • the base station can be divided into a macro base station or a micro base station. Micro base stations are sometimes called small base stations or small cells.
  • the network device may also be a network node that forms a gNB or TRP, for example, a baseband unit (building baseband unit, BBU), centralized unit (CU), or distributed unit (DU), etc.
  • This application provides a repetition scheme based on LDPC.
  • a part of the repeated information bits can be obtained during retransmission, so that these repeated information bits can be combined with the first time at the receiving end.
  • the corresponding information bits transmitted are combined.
  • the LDPC repetition scheme provided by the present application can also be used in combination with a puncturing (or puncturing) scheme, so that the information bits in the LDPC codeword bits can be repeated, and at the same time, the check of the LDPC codeword bits can be performed.
  • the bits are punctured, and the part of the information bits and the remaining part of the check bits after the puncturing are retransmitted, and finally a more flexible HARQ retransmission mechanism is obtained.
  • the receiving end can combine the initially transmitted bits and the retransmitted partial information bits and incremental redundant bits at the same time to obtain performance gains.
  • the basic idea of the LDPC repetition scheme based on the confidence criterion proposed in this application is: according to statistical confidence characteristics, for example, the absolute value of the likelihood rate (LLR) of iterative decoding, determine the sensitive information to be repeated The position of the bit.
  • IR-HARQ requires that the LDPC code rate of the receiving end is compatible, that is, the bits transmitted at the high code rate are included in the bits transmitted at the low code rate, and the retransmitted information bits need to meet this condition.
  • the system bits with low confidence are preferred to be repeated, because the lower the confidence, the easier it is to make mistakes, and only the system bits carry valid information.
  • the fixed source is a source with all "0"s.
  • is used as a confidence level
  • the fixed source is an all-“0” source.
  • the information bits of the LDPC to be repeated are sorted in the order of confidence from small to large (or from large to small), and the sorting relationship is stored in table T, which is the sensitivity sorting table of bit positions.
  • the table T may be represented by the following formula (1):
  • FIG. 4 is a flowchart of establishing a sensitivity ranking table of bit positions provided by this application.
  • a fixed all "0" source is passed through LDPC encoding with corresponding code rate and code length, and then modulated, for example, through binary phase shift keying (BPSK) Modulation, the initial decoding information is set to a fixed value ⁇ x, and then sent to the iterative decoder for decoding.
  • BPSK binary phase shift keying
  • the LLR of the parity bit is output, and the absolute value of the LLR is sorted, for example, in ascending order.
  • the iterative decoder may specifically be a log-SPA iterative decoder.
  • SPA stands for sum-product algorithm, which is a kind of LDPC decoding algorithm based on iterative decoding and belongs to a soft decision algorithm.
  • the initial decoding information of the additive white Gaussian noise (AWGN) channel is y/ ⁇ 2
  • y is the channel information
  • ⁇ 2 is the noise variance.
  • the noise variance is 0, the initial decoding information should be ⁇ . Taking into account that if you set this directly in the computer program, it will cause data overflow. Therefore, the function shown in formula (2) is used when solving the verification information:
  • the initial decoding value x can be set to 3, 4, 5, and so on.
  • this application proposes repeated priority sorting based on LDPC with code rates of 1/2, 2/3, 3/4, and 5/6 for the next-generation WLAN system based on the IR-HARQ mechanism.
  • the IR-HARQ mechanism can directly transmit the original LDPC codeword, or first puncture the check bits of the original LDPC codeword, and then transmit the punctured codeword.
  • part of the information bits are retransmitted in the order of priority from high to low (the confidence is from low to high), or, or, at the same time, part of the punctured parity bits are supplemented.
  • the number of retransmission bits is determined according to the new code rate required for retransmission or the number of channel resources of the channel allocated for retransmission.
  • FIG. 6 is a schematic flowchart of the LDPC rate matching method provided by this application.
  • the methods in the embodiments of the present application can be executed by the sending end, or executed by devices or modules such as chips, processors, processing circuits, etc., provided in the sending end.
  • the sending end is taken as an example of execution. .
  • the sending end performs rate matching on the first LDPC code word of the first code rate according to the repetition priority ordering of the K information bits of the LDPC mother code in the rate matching process to obtain the second LDPC code of the second code rate Character.
  • the priority at which the information bits in the LDPC codeword are repeated (or repeated transmission is performed) during the rate matching process is called the repetitive priority.
  • the sequence of the repetition priority of the K information bits reflects the reliability (or confidence) of the K information bits.
  • the higher the repetition priority of an information bit the higher the reliability of the information bit, and the higher the information bit is repeated during rate matching. Conversely, the lower the repetition priority of an information bit, the lower the reliability of the information bit. In rate matching, the information bit is repeated later in the K information bits.
  • the repetition priority of the K information bits can be sorted according to the priority from high to low. In this case, the higher the information bit's repetition priority, the higher the priority. Alternatively, it can also be sorted according to the priority level from low to high. In this case, the lower the position of the information bit, the higher the repetition priority.
  • a check matrix corresponding to the target code rate and the target code length is used to perform LDPC encoding on K information bits to obtain an LDPC mother code with a length of N.
  • K codeword bits correspond to the K information bits
  • NK codeword bits correspond to (NK) check bits, wherein, N and M are both positive integers, N>K.
  • the target code rate may be 1/2, 2/3, 3/4, and 5/6 as described above, and the target code length may be 1944, 1296, and 648.
  • the code rate corresponds to different check matrices, from a high code rate to a low code rate, or from a low code rate to a high code rate, it is necessary to select a different check matrix to achieve the change of the code rate. .
  • the IR-HARQ mechanism since the IR-HARQ mechanism requires compatibility between high bit rate and low bit rate, based on the same check matrix, it is also possible to achieve from a high bit rate to a low bit rate, or from a low bit rate.
  • the bit rate is up to a high bit rate. This process from a high bit rate to a low bit rate, or from a low bit rate to a high bit rate, is rate matching.
  • the first LDPC codeword in step 410 may be a mother code.
  • the first code rate of the first LDPC codeword is also the code rate of the mother code. That is, the check matrix of the target code length and the target code rate is used to perform LDPC encoding on the K information bits to obtain the first LDPC codeword.
  • the code length of the first LDPC is the target code length
  • the first code rate of the first LDPC codeword is the target code rate.
  • the above code length is 1944
  • the code rate is 5/6 LDPC check matrix as an example
  • the check matrix is used to perform LDPC encoding on K information bits
  • the code length is 1944
  • the code rate is 5/ The first LDPC codeword of 6.
  • rate matching can be performed on the first LDPC codeword of the first code rate to obtain the second LDPC codeword of the second code rate.
  • the sender can try a higher code rate.
  • a higher code rate is obtained.
  • the second LDPC codeword of the coding rate that is, the second coding rate is higher than the first coding rate.
  • the sending end may try to reduce the code rate to increase the probability of successful decoding at the receiving end.
  • the sending end can obtain a second LDPC codeword with a lower coding rate by performing rate matching on the first LDPC codeword of the first coding rate, that is, the second coding rate is lower than the first coding rate.
  • the code rate of the second LDPC codeword (ie, the second code Rate) is lower than the first code rate of the first LDPC codeword.
  • rate matching is performed based on the repetitive priority of information bits.
  • the repetition priority of the information bit and the puncturing priority of the check bit may also be used in combination.
  • the process of obtaining the repeated priority of the information bit based on the sensitivity of the codeword bit is described above.
  • the reliability (ie, confidence) of the check bits can also be sorted based on the sensitivity of the check bits, so as to obtain the puncturing priority of the check bits.
  • a check bit is more sensitive, it indicates that the reliability of the check bit is lower. In rate matching, the check bit is punctured first. Therefore, the check bit is punctured first. The higher the bit puncturing priority. Conversely, if the sensitivity of a check bit is lower, it indicates that the reliability of the check bit is higher, and in rate matching, the puncturing priority of the check bit is lower.
  • the first LDPC codeword may be an LDPC codeword after rate matching.
  • the first LDPC codeword may be an LDPC codeword obtained after puncturing the mother code.
  • the first LDPC codeword may be an LDPC codeword obtained after repeating part of the information bits of the mother code.
  • the sender can perform rate matching on the first LDPC codeword of the first code rate based on the repetition priority of the information bit, or based on the repetition priority of the information bit and the puncturing priority of the check bit, To get the desired second bit rate.
  • the sending end sends the LDPC codeword of the second coding rate.
  • the order of the repetition priority of information bits provided in this application is used for rate matching of LDPC codewords.
  • the sending end obtains an LDPC codeword with a lower coding rate by repeating the information bits with a higher priority of an LDPC codeword with a high coding rate.
  • the sender obtains a desired code by repeating the information bits with higher priority of a high code rate LDPC codeword, and at the same time, puncturing part of the LDPC codeword with check bits with higher priority. Rate.
  • the high bit rate and the low bit rate are compatible.
  • LDPC of each code rate (a total of 4 code rates, respectively, 1/2, 2/3, 3/4, and 5/6) in the current WLAN has 3 code lengths, which are 648, 1296, and 1944, respectively. Therefore, the present application respectively provides a ranking of the confidence levels of the corresponding information bits for the four code rates and the three code lengths.
  • the mother matrix (denoted as matrix 1) of the check matrix of the LDPC code with a code rate of 1/2 and a code length of 1944 is shown as follows:
  • "-" represents an 81 ⁇ 81 all-zero matrix.
  • the code rate is 1/2
  • of the check bits in the mother matrix of the check matrix corresponding to the LDPC with the code length of 1944 and the reliability ranking thereof may be as shown in Table 1.
  • a(b) represents the a-th column of the mother matrix
  • the column weight of the a-th column is b (that is, the column contains b 1s).
  • the check bit with a low confidence level is preferentially punctured.
  • the punctured check bits can also ensure the recoverability of the system variable nodes, especially when the number of punctured bits is large.
  • the ordering of the reliability of the columns corresponding to the information bits in the mother matrix is consistent with the ordering of the repetitive priority levels in the rate matching process. That is, the order of reliability from high to low is the order of repetition priority from high to low.
  • Table 2 ranks the repetition priority of the information bits given in this application.
  • a(b) represents the a-th column in the mother matrix, and its column weight is b. As shown in Table 2, the lower the confidence of the information bit, the higher the repetition priority.
  • the repetition priority of the information bit is given by the column of the mother matrix. Therefore, the repetition priority of the z codeword bits corresponding to each column in the mother matrix in the original check matrix is the same.
  • the LDPC check matrix with a code rate of 1/2 and a code length of 1944 has the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching order from high to low.
  • each element a in the ranking 1 represents the a-th column of the mother matrix of the check matrix.
  • the index of the column in the mother matrix starts from 1. For example, for a mother matrix with a size of 12 ⁇ 24, the value range of the index of its column is [1,24].
  • the index of the column of the mother matrix in the embodiments of the present application may also start from 0, which is not limited.
  • the index starts from 0 or starts from 1, and the sequence of the repetition priority of the column corresponding to the information bit in the mother matrix expressed by it is essentially the same.
  • the column of the mother matrix includes two parts, one part corresponds to the information bit, and the other part corresponds to the check bit.
  • the first to 12th columns of the 24 columns correspond to information bits
  • the 13th to 12th columns correspond to information bits.
  • the 24th column corresponds to the parity bit. Therefore, since this application mainly relates to the sorting of the repetition priority of information bits, the "columns in the mother matrix corresponding to the information bits" in the embodiments refer to all columns except the check part of the mother matrix. .
  • the information bits can be selected to perform the repeated operation according to the following rules.
  • the sending end selects L information bits from the z information bits corresponding to the column with the highest repeat priority in the mother matrix to perform the repeat operation.
  • the sending end can select the z information bits corresponding to the column with the highest repetition priority. Randomly select L information bits to perform repeated operations. For example, the sending end selects L information bits in a manner of from back to front, or from front to back, or randomly selected.
  • the sender selects the m columns with the highest repeat priority from the mother matrix and executes them on the corresponding mz information bits in the original check matrix. Repeat the operation.
  • the sender Since the number of information bits that need to be repeated is exactly equal to the number of information bits corresponding to the m columns in the mother matrix in the original check matrix, the sender will select the repeat priority from high to low in the order of repeat priority.
  • the m ⁇ z information bits corresponding to the first m columns in the original check matrix perform repeated operations.
  • the sender performs the execution on the 10th column, 6th column, 8th column and 11th column of the mother matrix corresponding to a total of 4 ⁇ 81 information bits in the original matrix Repeat the operation without repeating them one by one.
  • the sender selects the tenth column of the mother matrix in the original school.
  • the corresponding 81 information bits in the verification matrix and (100-81) information bits of the 81 information bits corresponding to the sixth column of the mother matrix in the original check matrix perform repeated operations.
  • the 6th column of the mother matrix is in the 81 information bits corresponding to the original check matrix, 19 information bits can be randomly selected, because the 6th column of the mother matrix corresponds to 81 information bits in the original check matrix
  • the repetition priority is the same.
  • the sender selects the 10th column of the mother matrix in the original
  • the corresponding 81 information bits in the check matrix, the 6th column of the mother matrix corresponds to 81 information bits in the original check matrix, and the 8th column of the mother matrix corresponds to 81 information bits in the original check matrix
  • the sender starts from the 8th column of the mother matrix in the original check matrix corresponding to the 81 information 8 information bits can be arbitrarily selected among the bits.
  • the set of repeated information bits at the transmitting end may be referred to as the first set of information bits.
  • the sender repeats the information bits in the first information bit set of the LDPC codeword.
  • the first information bit set includes L information bits, and the repetition priority of the information bit with the lowest repetition priority among the L information bits is higher than or equal to all the information bits of the LDPC codeword except for the The repetition priority of the remaining information bits other than the L information bits in the first information bit set.
  • the 10th column of the mother matrix corresponds to 81 information bits in the original check matrix
  • the 6th column of the mother matrix corresponds to 81 information bits in the original check matrix
  • the 8th column of the mother matrix Any 8 information bits among the 81 information bits that are listed in the original check matrix form the first information bit set.
  • Table 3 shows the comparison between the repetition scheme based on the confidence criterion provided by this application and the repetition scheme of the 802.11ac standard.
  • Table 3 lists the corresponding columns of the information bits that are preferentially repeated in the mother matrix. Column index. In contrast, the repeated priority of 802.11ac is from first to last.
  • the repetition scheme of the low code rate LDPC is compatible with the repetition scheme of the high code rate LDPC.
  • the repetition position of the information bit of the low coding rate LDPC includes the repetition position of the information bit of the high coding rate LDPC.
  • the index set of the repetition position of the LDPC information bits corresponding to the columns of the mother matrix is ⁇ 12,14 ⁇ .
  • the repetition position of the LDPC information bits corresponds to the index set of the columns of the mother matrix as ⁇ 12,14,15,17,19 ⁇ , Among them, the index set contains the 12th and 14th columns of the mother matrix.
  • the repetition position of the LDPC information bits corresponds to the index set of the columns of the mother matrix as ⁇ 12,14,15,17,19,13 ,20,11 ⁇ , where the index set includes not only the 12th and 14th columns of the mother matrix, that is, the case of repeating 2 columns, but also the 12th, 14th, and 15th columns of the mother matrix , The 17th column, and the 19th column, that is, the case of repeating 5 columns.
  • the higher the code rate of the LDPC code According to the principle of rate matching, it can be known that the more the number of information bits is repeated, the higher the code rate of the LDPC code. Therefore, in the repetitive scheme of the present application, the high bit rate and the low bit rate are compatible. That is, by adding a new repetition position on the basis of the repetition position of a low coding rate LDPC codeword, a higher coding rate LDPC codeword can be obtained.
  • the mother matrix (denoted as matrix 2) of the parity check matrix of an LDPC code with a code rate of 1/2 and a code length of 1296 is as follows:
  • "-" represents a 54 ⁇ 54 all-zero matrix.
  • Table 4 is the order of the repetition priority of LDPC information bits with a code rate of 1/2 and a code length of 1296 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 12th column of matrix 2 is given in Table 4, because the first column to the 12th column correspond to the information of the matrix ( In other words, the system) part.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column corresponds to 54 codeword bits of the original check matrix.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority.
  • Table 4 Take the eighth column with the highest repetition priority in Table 4 as an example, that is, the repetition priority of the 54 information bits corresponding to the eighth column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 2:
  • each element a in the ranking 2 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 3) of the parity check matrix of an LDPC code with a code rate of 1/2 and a code length of 648 is as follows:
  • "-" represents a 27 ⁇ 27 all-zero matrix.
  • Table 5 is the order of the repetition priority of LDPC information bits with a code rate of 1/2 and a code length of 648 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the twelfth column of the matrix 3 is given in Table 5, because the first column to the twelfth column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column corresponds to 27 codeword bits of the original check matrix.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority.
  • Table 5 Take the eighth column with the highest repetition priority in Table 5 as an example, that is, the repetition priority of the 27 information bits corresponding to the eighth column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 3:
  • each element a in the ranking 3 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 4) of the LDPC check matrix with a code rate of 1/2 and a code length of 648 is as follows:
  • "-" represents an 81 ⁇ 81 all-zero matrix.
  • Table 6 is the order of the repetition priority of LDPC information bits with a code rate of 2/3 and a code length of 1944 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b. As shown in Table 6, the lower the confidence of the information bit, the higher the repetition priority.
  • Table 6 shows the ordering of the first column to the 16th column of the matrix 4, because the first column to the 16th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column corresponds to 81 codeword bits of the original check matrix.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority.
  • Table 6 Take the 16th column with the highest repetition priority in Table 6 as an example, that is, the repetition priority of the 81 information bits corresponding to the 16th column of the mother matrix in the original check matrix is the same.
  • the LDPC check matrix with a code rate of 2/3 and a code length of 1944 has the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching order from high to low. It can be sorted as follows 4:
  • each element a in the ranking 4 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 5) of the parity check matrix of an LDPC code with a code rate of 2/3 and a code length of 1296 is as follows:
  • "-" represents a 54 ⁇ 54 all-zero matrix.
  • Table 7 is the order of the repetition priority of LDPC information bits with a code rate of 2/3 and a code length of 1296 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 16th column of the matrix 5 is given in Table 7, because the first column to the 16th column correspond to the information (or system) part of the check matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column of the matrix corresponds to 54 codeword bits of the original check matrix.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Taking the 16th column with the highest repetition priority in Table 7 as an example, it means that the repetition priority of the 54 information bits corresponding to the 16th column of the mother matrix in the original check matrix is the same.
  • the LDPC check matrix with a code rate of 2/3 and a code length of 1296 has the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching order from high to low. It can be sorted as follows 5:
  • each element a in the ranking 5 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 6) of the parity check matrix of an LDPC code with a code rate of 2/3 and a code length of 648 is as follows:
  • "-" represents a 27 ⁇ 27 all-zero matrix.
  • Table 8 is the order of the repetition priority of LDPC information bits with a code rate of 2/3 and a code length of 648 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 6 is a mother matrix, each column of the matrix corresponds to 27 codeword bits of the original check matrix. Taking the 16th column with the highest repetition priority in Table 7 as an example, it means that the repetition priority of the 27 information bits corresponding to the 16th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 6:
  • each element a in the ranking 6 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 7) of the parity check matrix of an LDPC code with a code rate of 3/4 and a code length of 1944 is as follows:
  • "-" represents an 81 ⁇ 81 all-zero matrix.
  • Table 9 is the order of the repetition priority of LDPC information bits with a code rate of 3/4 and a code length of 1944 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 18th column of the matrix 7 is given in Table 9, because the first column to the 18th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 7 is a mother matrix, each column corresponds to 81 codeword bits of the original check matrix. Taking the 18th column with the highest repetition priority in Table 9 as an example, it means that the repetition priority of the 81 information bits corresponding to the 18th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 7:
  • each element a in the ranking 7 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 8) of the parity check matrix of an LDPC code with a code rate of 3/4 and a code length of 1296 is as follows:
  • "-" represents a 54 ⁇ 54 all-zero matrix.
  • Table 10 shows the order of the repetition priority of LDPC information bits with a code rate of 3/4 and a code length of 1296.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • Table 10 shows the ordering of the 1st to 18th columns of the matrix 8 because the 1st to 18th columns correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 7 is a mother matrix, each column of the matrix corresponds to 54 codeword bits of the original check matrix. Taking the 9th column with the highest repetition priority in Table 10 as an example, the repetition priority of 54 information bits corresponding to the 9th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 8:
  • Sort 8 9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7.
  • each element a in the ranking 8 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 9) of the parity check matrix of an LDPC code with a code rate of 3/4 and a code length of 648 is as follows:
  • "-" represents a 27 ⁇ 27 all-zero matrix.
  • Table 11 gives the order of the repetition priority of LDPC information bits with a code rate of 3/4 and a code length of 648 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 18th column of the matrix 9 is given in Table 11, because the first column to the 18th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • Each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 9 is a mother matrix, each column corresponds to 27 codeword bits of the original check matrix. Taking the 18th column with the highest repetition priority in Table 10 as an example, it means that the repetition priority of the 27 information bits corresponding to the 18th column of the mother matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 9:
  • each element a in the ranking 9 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 10) of the parity check matrix of an LDPC code with a code rate of 5/6 and a code length of 1944 is as follows:
  • "-" represents an 81 ⁇ 81 all-zero matrix.
  • Table 12 is the order of the repetition priority of LDPC information bits with a code rate of 5/6 and a code length of 1944 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 20th column of the matrix 10 is given in Table 12, because the first column to the 20th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since the matrix 10 is a mother matrix, each column of the matrix corresponds to 81 codeword bits of the original check matrix. Taking the 12th column with the highest repetition priority in Table 12 as an example, it means that the repetition priority of the 81 information bits corresponding to the 12th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows 10:
  • each element a in the ranking 10 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 11) of the parity check matrix of an LDPC code with a code rate of 5/6 and a code length of 1296 is as follows:
  • "-" represents a 54 ⁇ 54 all-zero matrix.
  • Table 13 is the order of the repetition priority of LDPC information bits with a code rate of 5/6 and a code length of 1296 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the ordering of the first column to the 20th column of the matrix 11 is given in Table 13, because the first column to the 20th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 11 is a mother matrix, each column of the matrix corresponds to 54 codeword bits of the original check matrix. Taking the 17th column with the highest repetition priority in Table 13 as an example, it means that the repetition priority of the 54 information bits corresponding to the 17th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows11:
  • each element a in the ranking 11 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • the mother matrix (denoted as matrix 12) of the parity check matrix of an LDPC code with a code rate of 5/6 and a code length of 648 is as follows:
  • "-" represents a 27 ⁇ 27 all-zero matrix.
  • Table 14 is the order of the repetition priority of LDPC information bits with a code rate of 5/6 and a code length of 648 given in this application.
  • a(b) represents the a-th column of the mother matrix, and its column weight is b.
  • the order of the first column to the 20th column of the matrix 12 is given in Table 14, because the first column to the 20th column correspond to the information (or system) part of the matrix.
  • the codeword bits corresponding to this part of the columns are all original information bits.
  • each column in the mother matrix corresponds to z information bits of the original check matrix, and the z codeword bits have the same repetition priority. Since matrix 12 is a mother matrix, each column of the matrix corresponds to 27 codeword bits of the original check matrix. Taking the 13th column with the highest repetition priority in Table 14 as an example, it means that the repetition priority of the 27 information bits corresponding to the 13th column of the mother matrix in the original check matrix is the same.
  • the repetition priority of the column corresponding to the information bit in the mother matrix in the rate matching is in the order from high to low. It can be sorted as follows12:
  • Sort 12 13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20.
  • each element a in the ranking 12 represents the a-th column of the mother matrix of the check matrix. And, the index of the column in the mother matrix starts from 1.
  • FIG. 7 is an example of the application of the repetition scheme provided by this application in IR-HARQ.
  • the sending end generates an LDPC codeword suitable for channel transmission, for example, the code rate of the LDPC codeword is 1/2.
  • the sending end sends the LDPC codeword.
  • this transmission is defined as the first transmission.
  • the receiving end If the receiving end can correctly decode all the information bits (i.e., systematic bits), the transmission of this data packet is ended. If the receiving end cannot decode correctly, the receiving end requests the sending end to retransmit.
  • the retransmission process can be step 530 and subsequent steps.
  • the sending end obtains the sorting of the repetition priority of the information bits.
  • the sending end retransmits the t1 information bits with the highest repetition priority based on the sorting of the repetition priority.
  • the receiving end receives the t1 information bits retransmitted by the sending end, combines the t1 information bits with the corresponding information bits of the previously received sequence, and then decodes them. If the receiving end still cannot decode correctly, if the preset maximum number of retransmissions is not reached, the receiving end continues to request the sending end to retransmit.
  • the sender retransmits t2 information bits with the second highest repetition priority based on the sorting of the repetition priority.
  • the receiving end receives the t2 information bits retransmitted by the transmitting end, combines the t2 information bits with the t1 information bits previously received and the corresponding information bits of the sequence received in the initial transmission, and then decodes them.
  • the code rate of the lth transmission can satisfy the following formula (3):
  • the information bit repetition scheme provided in the present application can be used in combination with the check bit puncturing scheme, which will be described below with reference to FIG. 8 as an example.
  • FIG. 8 is an application example of the combination of the information bit repetition scheme and the check bit puncturing scheme provided in this application in IR-HARQ.
  • the sending end generates an original LDPC codeword suitable for channel transmission, for example, the code rate of the original LDPC codeword is 1/2.
  • the code length of the LDPC mother code is N
  • the number of information bits is K
  • the number of check bits is (N-K), where N and K are both positive integers.
  • the sending end obtains the sequence of the repetition priority of the K information bits, and the sequence of the puncturing priority of the (N-K) check bits.
  • the sender punctures the original LDPC codeword based on the puncturing priority ordering of the (NK) check bits (assuming only punctured check bits) to obtain the desired target code rate for the first transmission.
  • LDPC codeword (hereinafter referred to as the first LDPC codeword). For example, by puncturing the original LDPC codeword, the code rate of the first LDPC codeword obtained is 5/6.
  • the receiving end If the receiving end can decode all the information bits correctly, the transmission of this data packet is ended. If the receiving end cannot decode correctly, the receiving end requests the sending end to retransmit.
  • the retransmission process can be step 615 and subsequent steps.
  • the sending end preferentially sends t1 puncturing check bits with the highest reliability.
  • the t1 puncturing check bits with the highest reliability that is, the top t1 check bits are sorted in the order of puncturing priority from low to high.
  • the punctured check bit refers to the check bit that is punctured during the rate matching process of the first transmission.
  • the receiving end receives the t1 punctured check bits, and combines the t1 punctured check bits with the sequence received in the first transmission into a sequence, and then decodes it.
  • the receiving end continues to request the sending end to retransmit.
  • the sending end sends t2 puncturing check bits with the second highest reliability.
  • the t2 puncturing check bits with the highest reliability that is, in the order of puncturing priority from low to high, among all the puncturing check bits, the remaining ones except for the t1 puncturing check bits Among the punctured check bits, the top t2 punctured check bits in the top order.
  • the receiving end receives the t2 punctured check bits, and combines the t2 punctured check bits with the sequence received in the first transmission and the t1 punctured check bits into a sequence, and then decodes it .
  • the sending end sends s1 information bits with the highest repetition priority.
  • the receiving end receives the s1 information bits, combines the s1 information bits with the previous decoding sequence, and re-decodes the combined sequence. If the receiving end still cannot decode correctly, if the preset maximum number of retransmissions is not reached, the receiving end continues to request the sending end to retransmit.
  • the sending end sends s2 information bits with the second highest repetition priority.
  • the receiving end receives the s2 information bits, combines the s2 information bits with the previous decoding sequence, and re-decodes the combined sequence. And so on, until the sender repeatedly sends all the information bits. If at this time, the receiving end still cannot decode the information bits correctly, it means that the transmission of the data packet has failed and the transmission ends, and the transmission of the next data packet is performed.
  • the sender sends the first LDPC codeword. If the receiver fails to decode, the sender first sends the punctured check bits according to the puncturing priority of the check bits, until all the check bits are After being sent, if the receiving end still fails to decode successfully, the sending end will retransmit the information bits in the first LDPC codeword according to the repetition priority of the information bits.
  • the sender can first repeat the transmission of the information bits in the first LDPC codeword according to the repetition priority of the information bits until all of the information bits are sent. The information bits are all repeatedly sent. If the receiving end still fails to decode successfully, the sending end sends the punctured check bit according to the puncturing priority of the check bit.
  • the embodiment of the present application does not limit the sequence of combining the punching solution and the repeated solution. That is, if the LDCP codeword sent by the sending end is not successfully decoded by the receiving end, the sending end can execute the repetition scheme first and then the puncturing scheme, or it is feasible to execute the repetition scheme first and then the puncturing scheme.
  • the code rate of the lth transmission can satisfy the following formula (4):
  • R c k/n
  • n the length of the LDPC mother code codeword.
  • rate compatible HARQ rate compatible puncture latitude HARQ, RCPL-HARQ
  • rate compatible HARQ rate compatible repeat latitude HARQ, RCRL-HARQ
  • Free rate compatible HARQ rate compatible latitude HARQ, RCL-HARQ
  • Figure 9-19 shows the FER curve and throughput curve of the system under various IR-HARQ transmission strategies.
  • the simulation parameters of Figure 9-19 are set as follows: AWGAN channel; BPSK modulation; log-SPA decoding, the maximum number of iterative decoding is 10; using stop-wait retransmission request strategy; in order to restore each frame of data The maximum number of transmissions is 4 times.
  • the performance evaluation parameters considered in Figure 9-19 are mainly frame error rate (FER) and throughput.
  • throughput rate (number of correctly received frames ⁇ k)/total number of bits sent, k is the number of information bits in each frame.
  • E s /N 0 in each figure represents the symbol signal-to-noise ratio.
  • the LDPC code in the traditional method is a QC-LDPC code with a code length of 1944 or 972 in the 802.11ac standard.
  • Fig. 15 is a simulation result 1 of QC-LDPC with a code rate of 5/6 (1944, 1620) of IR-HARQ technology.
  • Figure 16 shows the second simulation result of QC-LDPC with a code rate of 5/6 (1944, 1620) for IR-HARQ technology.
  • Figure 17 is the third simulation result of QC-LDPC with a code rate of 1/2 (1944,972) of IR-HARQ technology.
  • Figure 18 shows the simulation result 4 of QC-LDPC with a code rate of 1/2 (1944,972) of IR-HARQ technology.
  • Figure 19 shows the simulation result 5 of QC-LDPC with a code rate of 1/2 (1944,972) of IR-HARQ technology.
  • the curve corresponding to "the reliability based repetition” represents the performance curve of the repetition scheme of this application
  • “the standard based puncturing” represents the performance curve of the traditional repetition scheme.
  • the number in parentheses after repetition indicates the number of repetitions of information bits, in units of columns. For example, repetition(2) means that the number of repetitions is 2 columns, and repetition(5) means that the number of repetitions is 5 columns.
  • FIG. 20 is a schematic block diagram of a communication device 1000 provided by this application. As shown in FIG. 20, the communication device 1000 includes a processing unit 1100 and a transceiving unit 1200.
  • the transceiving unit 1200 can also be replaced by a sending unit or a receiving unit.
  • the transceiving unit 1200 when it performs a sending action, it can be replaced by a sending unit.
  • the transceiver unit 1200 may be replaced by a receiving unit when performing receiving actions.
  • the processing unit 1100 is configured to perform rate matching on the first LDPC codeword of the first code rate according to the ordering of the repetition priority of the K information bits of the LDPC mother code in the rate matching process to obtain the second code rate of the second code.
  • LDPC codeword where K is the number of information bits contained in the LDPC mother code, and K is a positive integer;
  • the transceiver unit 1200 is configured to send the second LDPC codeword.
  • processing unit 1100 is further configured to:
  • the first LDPC codeword is sorted.
  • Information bits in an information bit set are repeated, wherein the repetition priority of the information bit with the lowest repetition priority in the first information bit set is higher than or equal to that of the first LDPC codeword except for the first LDPC codeword.
  • the repetition priority of the remaining information bits other than the information bits in an information bit set is L ⁇ K, and L is an integer.
  • the ordering of the repetition priority of the K information bits is specifically:
  • the number of information bits is K
  • the length of the mother code is N
  • the code rate of the LDPC check matrix is R.
  • the length of the mother code is 1944
  • the code rate is 1/2
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1296
  • the code rate is 1/2
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 648
  • the code rate is 1/2
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1944
  • the code rate is 2/3
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1296
  • the code rate is 2/3
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 648, and the code rate is 2/3.
  • the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1944, the code rate is 3/4, and in the order of repetition priority from high to low, the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1296
  • the code rate is 3/4
  • the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 648
  • the code rate is 3/4
  • the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1944, and the code rate is 5/6.
  • the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 1296
  • the code rate is 5/6
  • the repetition priority of the column corresponding to the information bit in the mother matrix is in the order of repetition priority.
  • the order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • the length of the mother code is 648, and the code rate is 5/6.
  • the repetition priority of the column corresponding to the information bit in the mother matrix is The order of the levels is as follows:
  • each element a in the sorting represents the a-th column of the mother matrix.
  • processing unit 1100 is specifically configured to:
  • the sending end selects from the mother matrix the mz corresponding to the first m columns with the highest repetition priority in the check matrix in the order of repetition priority from high to low Information bits are repeated, and m is a positive integer;
  • the transceiving unit 1200 is further configured to send the first LDPC codeword
  • the processing unit 1100 is configured to determine that the first LDPC codeword has not been successfully decoded by the receiving end;
  • the transceiving unit 1200 is specifically configured to sort the first LDPC code according to the number L of bits that need to be repeated and the repetition priority of the K information bits. L information bits included in the first information bit set in the word are repeatedly sent;
  • processing unit 1100 is further configured to determine that all the information bits contained in the first LDPC codeword have been repeatedly sent, and the receiving end has not successfully decoded it;
  • the transceiving unit 1200 is further configured to send the punctured check bits in the first LDPC codeword according to the order of the puncturing priority of the check bits, wherein the check bit with the lower puncturing priority is The check bit is sent first, and the puncturing priority is used to indicate the priority of (NK) check bits being punctured in the rate matching, N is the length of the LDPC mother code, N ⁇ K, and N is an integer.
  • the transceiving unit 1200 is further configured to send the first LDPC codeword
  • the processing unit 1100 is further configured to determine that the first LDPC codeword has not been successfully decoded by the receiving end;
  • the sending unit 1200 is further configured to send the punctured check bits in the first LDPC codeword according to the priority of the check bits, wherein the check bits with a lower puncturing priority are given priority Send, the puncturing priority is used to indicate the priority of (NK) check bits being punctured in rate matching, N is the length of the LDPC mother code, N ⁇ K, and N is an integer;
  • processing unit 1100 is further configured to determine that all the punctured check bits of the first LDPC codeword have been sent, and the receiving end has not successfully decoded it;
  • the transceiving unit 1200 is further configured to send the information bits of the first LDPC codeword according to the repetition priority of the K information bits.
  • the communication device 1000 may be a sending end, or the communication device 1000 may be a device, a module, etc. inside the sending end that has the function of implementing each method embodiment.
  • the communication device 1000 is the sending end in the foregoing method embodiments, and the communication device 1000 may have any function of the sending end in each method embodiment.
  • the processing unit 1100 may be a processor.
  • the transceiver unit 1200 may be a transceiver.
  • the transceiver may specifically include a receiver and a transmitter. Among them, the receiver is used to perform the function of receiving, and the transmitter is used to perform the function of transmitting.
  • the communication device 1000 may be a circuit system in the transmitting end.
  • the processing unit 1100 may be a chip, a logic circuit, an integrated circuit, a processing circuit, or a system on chip (SoC) chip, etc.
  • the transceiver unit 1200 may be a communication interface, and the communication interface may be an interface circuit. , Input and output interfaces, pins used to transmit signals on the chip, etc.
  • the communication device 1000 may be an encoder in the transmitting end.
  • the functions of the processing unit 1100 can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the processing unit 1100 may include one or more processors, and the one or more processors are configured to read and execute computer programs or instructions stored in the memory, so that the operations performed by the sending end in each method embodiment and/ Or the processing is executed.
  • the memory is located outside the one or more processors.
  • processing unit 1100 may also include one or more memories, and the one or more processors and the one or more memories are connected by a circuit/wire, and the one or more processors can read the The computer programs or instructions stored in one or more memories enable the operations and/or processing performed by the sending end in the method embodiments of the present application to be executed.
  • the processing unit 1100 is a processor
  • the transceiver unit 1200 may be an interface circuit.
  • the interface circuit is used to receive computer codes or instructions and transmit them to the processor, and the processor executes the computer codes or instructions so that the operations and/or processing performed by the sending end in the method embodiments of the present application are Be executed.
  • the processing unit 1100 may also be a processing circuit or a logic circuit.
  • this application also provides a computer-readable storage medium in which computer instructions are stored.
  • the computer instructions are run on a computer, the LDPC rate matching method provided in this application can be realized.
  • the present application also provides a computer program product.
  • the computer program product includes computer code or instructions.
  • the computer code or instructions run on a computer, the LDPC rate matching method of each method embodiment of the present application is implemented.
  • the present application also provides a communication device, including a processor and an interface circuit, the interface circuit is used to receive computer code or instructions, and transmit to the processor, the processor is used to run the computer code or instructions, so that The LDPC rate matching method provided in this application is implemented.
  • the application also provides a chip including one or more processors.
  • the one or more processors are used to execute a computer program stored in the memory to execute operations and/or processing performed by the sending end device in any method embodiment.
  • the memory is provided independently of the chip.
  • the chip may also include one or more communication interfaces.
  • the one or more communication interfaces may be input and output interfaces, interface circuits, and the like.
  • the chip may also include one or more of the memories.
  • the present application also provides a wireless communication system, including the sending end in the embodiment of the present application.
  • the sending end may be a network device (for example, a base station), or a terminal device, which is not limited.
  • the processor in the embodiment of the present application may be an integrated circuit chip, which has the ability to process signals.
  • the steps of the foregoing method embodiments can be completed by hardware integrated logic circuits in the processor or instructions in the form of software.
  • the processor can be a general-purpose processor, digital signal processor (digital signal processor, DSP), application specific integrated circuit (ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic Devices, discrete gates or transistor logic devices, discrete hardware components.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware encoding processor, or executed and completed by a combination of hardware and software modules in the encoding processor.
  • the software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • static random access memory static random access memory
  • dynamic RAM dynamic random access memory
  • DRAM dynamic random access memory
  • synchronous dynamic random access memory synchronous DRAM, SDRAM
  • double data rate synchronous dynamic random access memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous connection dynamic random access memory serial DRAM, SLDRAM
  • direct rambus RAM direct rambus RAM
  • unit used in this specification are used to denote computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution.
  • the component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and/or a computer running on a processor.
  • the application running on the computing device and the computing device can be components.
  • One or more components may reside in a process and/or thread of execution.
  • the components may be located on one computer and/or distributed between two or more computers.
  • these components can be executed from various computer readable media having various data structures stored thereon.
  • a component can be based on data that has one or more data packets (for example, data from two components that interact with another component between a local system, a distributed system, and/or a network, for example, the Internet that interacts with other systems through signals) Signals are communicated through local and/or remote processes.
  • data packets for example, data from two components that interact with another component between a local system, a distributed system, and/or a network, for example, the Internet that interacts with other systems through signals
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk and other media that can store program codes.

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Abstract

本申请提供一种 LDPC 的速率匹配的方法和通信装置，发送端在重传的时候，根据信息比特在速率匹配中的重复优先级的排序，对 LDPC 码字的信息比特进行重复发送，可以在接收端获得性能增益。由于信息比特的重复优先级的排序是根据 LDPC 码字的敏感性确定的，因此重复优先级的排序中，敏感性越高的信息比特的重复优先级越靠后，而敏感性越低的信息比特的重复优先级越靠前。由此，发送端在重复 LDPC 码字的信息比特时，敏感性越低的信息比特优先被重复，可以提高接收端的译码性能。

Description

LDPC的速率匹配的方法和通信装置
本申请要求于2020年05月22日提交中国专利局、申请号为202010439966.0、申请名称为“LDPC的速率匹配的方法和通信装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信道编码领域，并且更具体地，涉及一种LDPC的速率匹配的方法和通信装置。
背景技术
在信道编码领域，低密度奇偶校验码(low-density parity check,LDPC)是应用最为成熟和广泛的信道编码方案之一。LDPC具有接近香浓极限的性能，具有诸多的优点。因此，IEEE的802.11n、802.11ac、802.11ax等协议提出将LDPC作为无线局域网(wireless local area network,WLAN)的标准信道编码方案。802.11ac/ax标准中目前共采纳了LDPC的12个校验矩阵，支持3种码长，每种码长均支持4种码率。发送端设备根据目标码长和码率从12个校验矩阵中选择相应的校验矩阵进行LDPC编码。
为了进一步提高通信系统的吞吐率，下一代WLAN的标准802.11be提出，在802.11ax的基础上引入增量冗余-混合自动重传(incremental redundancy-hybrid automatic repeat request,IR-HARQ)机制。IR-HARQ机制期望通过重传增加冗余比特，降低信道编码速率，以提高接收端的解码性能。
但是，目前WLAN标准所采用的LDPC编码方案，无法满足在IR-HARQ机制中通过重传不断增加冗余比特从而获得性能增益的需求，译码性能低。
发明内容
本申请提供一种LDPC的速率匹配的方法和通信装置，可以提升译码性能。
第一方面，本申请提供一种LDPC的速率匹配的方法，该方法包括：发送端根据LDPC母码的K个信息比特在速率匹配中的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，得到第二码率的第二LDPC码字，K为正整数；发送端发送所述第二LDPC码字。
本申请各实施例中，信息比特在速率匹配过程中被重复的优先级称为该信息比特的重复优先级。
在本申请的技术方案中，发送端通过根据信息比特在速率匹配过程中的重复优先级的排序，在重传的时候，按照信息比特的重复优先级的排序，对LDPC码字的信息比特进行重复，以在接收端获得性能增益。由于信息比特的重复优先级的排序是根据LDPC码字的敏感性确定的，因此重复优先级的排序中，敏感性越高的信息比特的重复优先级越靠后， 而敏感性越低的信息比特的重复优先级越靠前。由此，发送端在重复LDPC码字的信息比特时，敏感性越低的信息比特优先被重复，可以提高接收端的译码性能。
结合第一方面，在第一方面的某些实现方式中，所述发送端根据K个信息比特的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，包括：
发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合中的L个信息比特进行重复发送，其中，所述第一信息比特集合包含的所述L个信息比特中重复优先级最低的信息比特的重复优先级，高于或者等于所述第一LDPC码字中的除了所述第一信息比特集合中的信息比特之外的剩余信息比特的重复优先级，L≤K，且L为整数。
应理解，第一信息比特集合，是指第一LDPC码字的全部信息比特中，按照重复优先级从高到低的排序，重复优先级最靠前的L个信息比特。
结合第一方面，在第一方面的某些实现方式中，所述K个信息比特的重复优先级的排序为：
信息比特个数为K，母码长度为N，码率为R的LDPC的校验矩阵的母矩阵中对应于信息比特的列的重复优先级的排序，所述母矩阵中的每个列对应所述LDPC的z个码字比特，其中，z＝N/n，n为所述母矩阵包含的列的总数，其中，所述LDPC的校验矩阵通过扩展所述母矩阵得到，所述母矩阵中的每个元素i表示一个z×z的循环移位矩阵，i表示循环移位值，i≥0，且i为整数，N≥K,N为整数，R＝K/N。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1944，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：10,6,8,11,4,3,12,7,2,5,9,1,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1296，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：8,12,7,3,11,10,4,6,2,5,9,1,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为648，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：8,6,12,11,2,3,10,7,4,1,5,9,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1944，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1296，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为648，码率为2/3， 按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1944，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1296，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为648，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1944，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为1296，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述母码长度为648，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20,其中，所述排序中的每个元素a表示所述母矩阵的第a列。
结合第一方面，在第一方面的某些实现方式中，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中重复优先级位于前L个位置的的信息比特进行重复，包括：
若L<z，所述发送端从所述母矩阵中重复优先级最高的一列在所述校验矩阵中对应的z个信息比特中选择L个信息比特进行重复；
若L＝m×z，所述发送端按照重复优先级从高到低的顺序，从所述母矩阵中选择重复优先级靠前的前m个列在所述校验矩阵中对应的mz个信息比特进行重复，m为正整数；
若(m-1)×z<L<m×z，所述发送端按照重复优先级从高到低的排序，从所述母矩阵中选择重复优先级靠前的前(m-1)列在所述校验矩阵中对应的(m-1)×z个信息比特，以及第m列在所述校验矩阵中对应的z个信息比特中的p个信息比特进行重复，其中，L＝(m-1)×z+p，p≥1且p为整数，m>1，且m为整数。
结合第一方面，在第一方面的某些实现方式中，所述发送端根据需要重复的比特个数 L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送之前，所述方法还包括：
所述发送端发送所述第一LDPC码字；
以及，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送，包括：
在所述第一LDPC码字未被接收端成功译码的情况下，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送；
以及，所述方法还包括：
在所述第一LDPC码字包含的全部信息比特都被重复发送，且接收端仍未成功译码信息比特的情况下，所述方法还包括：
所述发送端按照校验比特的打孔优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数。
结合第一方面，在第一方面的某些实现方式中，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送之前，所述方法还包括：
所述发送端发送所述第一LDPC码字；
在所述第一LDPC码字未被接收端成功译码的情况下，所述发送端按照校验比特的优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数；
以及，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送，包括：
在所述第一LDPC码字的所有被打孔的校验比特全部被发送，且所述接收端仍未成功译码的情况下，所述发送端按照所述K个信息比特的重复优先级，发送所述第一LDPC码字的信息比特。
第二方面，本申请提供了一种通信装置，所述通信装置具有实现第一方面或其任意可能的实现方式中的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
第三方面，本申请提供一种通信装置，包括接口电路和处理器，所述接口电路用于接收计算机代码或指令，并传输至所述处理器，所述处理器运行所述计算机代码或指令，第一方面或其任意实现方式中的方法被实现。
第四方面，本申请提供一种通信设备，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合，所述至少一个存储器用于存储计算机程序或指令，所述至少一个处 理器用于从所述至少一个存储器中调用并运行该计算机程序或指令，使得通信设备执行第一方面或其任意可能的实现方式中的方法。
在一个示例中，所述通信设备可以为编码器。
第五方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，所述第一方面或其任意可能的实现方式中的方法被实现。
第六方面，本申请提供一种计算机程序产品，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，所述第一方面或其任意可能的实现方式中的方法被实现。
第七方面，本申请提供一种无线通信系统，包括如第四方面的通信设备。
附图说明
图1为LDPC码的校验矩阵H。
图2为LDPC码的校验矩阵H的Tanner图。
图3的(a)和(b)为适用于本申请实施例的系统架构图。
图4为本申请提供的建立比特位置的敏感性排序表的流程图。
图5示出了函数的图像。
图6为本申请提供的LDPC的速率匹配的方法的示意性流程图。
图7为本申请提供的重复方案在IR-HARQ中的应用示例。
图8为本申请提供的信息比特的重复方案和校验比特的打孔方案的结合在IR-HARQ中的应用示例。
图9-图19为各种IR-HARQ传输策略下系统的FER曲线及吞吐率曲线。
图20为本申请提供的通信装置1000的示意性框图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
在电气电子工程师学会(institute of electrical and electronics engineers，IEEE)802.11n/ac/ax/be等无线局域网(wireless local area network,WLAN)传输标准主要演进在60GHz大带宽场景下提升用户的体验，包括提升用户平均吞吐量以及电池类供电设备的能量使用效率，这需要在有限的频率和功率资源上实现数据、时频等业务的高速可靠传输。因此，需要高可靠性和高效率的信道编译码方案。到目前为止，在信道编码领域，低密度奇偶校验码(low-density parity check,LDPC)是应用最为成熟和广泛的信道编码方案之一，已广泛应用到通信领域。LDPC具有接近香浓极限的性能，并具有诸多的优点，例如，不需要深度交织即可获得较好的误码性能、具有较好的误帧率性能、错误平层大大降低、译码不基于网络，以及支持并行译码、译码时延小等。因此，LDPC已经成为IEEE802.11n/ac/ax等低频短距WLAN通信系统的标准信道编码方案，同时，在IEEE 802.11ax大于或等于40MHz带宽情况下，成为必选的信道编码方案。
在新的802.11ax的下一代WLAN标准802.11be中，提出引入混合自动重传请求(hybrid automatic repeat request,HARQ)，以进一步提高系统的吞吐率。HARQ主要涉及 存储、请求重传以及合并解调。接收端在对数据解码失败的情况下，保存接收到的数据，并请求发送端重传数据。接收端将重传的数据和先前接收并保存的数据进行合并后再解码，实现了分集增益，减少了重传次数和时延，可以提高数据解码成功的概率。
HARQ大致可以包括追逐合并(chase combine,CC)和增量冗余(incremental redundancy,IR)两种类型，分别可以称为CC HARQ和IR HARQ。
HARQ机制可以认为追逐合并(chase combine,CC)和增量冗余(incremental redundancy,IR-HARQ)两种类型。在单纯的HARQ机制中，接收端对于未正确接收的数据包是直接丢弃的。但实际上，这些未正确接收的数据包虽然不能独立地正确解码，但是它们依然包含了部分有用的信息。对于CC-HARQ，CC的过程就是利用这部分信息，将未正确接收的数据包保存在存储器中，与重传的数据包合并在一起进行译码，提高了传输效率。IR HARQ机制，是指发送端在初次传输时发送信息比特和一部分冗余比特，并在重传中发送额外的冗余比特。如果初次传输没有成功解码，则发送端通过重传更多的冗余比特来降低信道码率，从而提高解码成功率。若接收端加上重传的冗余比特仍不能成功解码，则发送端再次进行重传。随着重传次数的增加，冗余比特不断增加，信达编码率不断降低，从而可以获得更好的解码效果。
若WLAN的下一代标准引入IR HARQ机制，则需要可以兼容多种速率的LDPC编码方案(rate-compatible LDPC,RC-LDPC)来支持，才能够在重传的时候引入新的增量冗余比特。
为了便于理解本申请的方案，首先对LDPC的相关概念进行介绍。
LDPC是一种线性分组码，其校验矩阵是一种稀疏矩阵，即校验矩阵中零元素的个数远远多于非零元素的个数，或者说，校验矩阵的行重和列重与LDPC的码长相比是很小的数。
Tanner在1981年将LDPC的码字用图的方式表示了出来，现在将这种图示的方式称为Tanner图。Tanner图和校验矩阵一一对应，由两类节点组成，一类节点代表码字符号，称为变量节点，另一类节点为校验节点，代表校验约束关系，每个校验节点代表一个校验约束关系，下面结合图1和图2进行说明。
参见图1，图1为LDPC的校验矩阵H。图1中，{V i}表示变量节点集，{C i}表示校验节点集。校验矩阵H的每行代表一个校验方程，每列代表一个码字比特。图1中，变量节点为8个，校验节点为4个。如果一个码字比特包含在相应的校验方程中，就用一条连线将所涉及的变量节点和校验节点连起来，得到Tanner图。
参见图2，图2为LDPC的校验矩阵H的Tanner图。如图2所示，Tanner图表示的即是LDPC的校验矩阵。例如，对于大小为m行n列的校验矩阵H，Tanner图中包含两类节点，分别为n个变量节点和m个校验节点。其中，所述n个变量节点分别和校验矩阵H的n个列对应，所述m个校验节点分别和校验矩阵H的m个行对应。Tanner图中的循环是由互相连接在一起的节点组成，循环以这群节点中的一个节点同时作为起点和终点，且只经过每个节点一次。循环的长度定义为它所包含的连线的数量，而图形的围长也可以称作图形的尺寸，定义为图中最小的循环长度，如图2中，围长为6，如图2中加黑连线所示。Tanner图中的变量节点对应校验矩阵H的每一列，也即对应LDPC码字的每一码字比特。Tanner图中的校验节点分别对应校验矩阵H的每一行，也即对应LDPC码 字的校验比特。两类节点之间的连接情况对应H矩阵中元素的取值。若第i个校验节点与第j个变量节点之间存在连接，则代表H矩阵中的元素(i,j)的取值为1，若无连接，则对应的元素为0。此外，在tanner图中，环(cycle)是指由变量节点、校验节点和边首尾相连组成的闭合环路。
如上文所述，LDPC是一种线性分组码，线性分组码是将待编码的信息序列以k个比特为单位划分成组，再由编码器对这k个信息比特进行线性运算，得到m个校验比特，接着将这k个信息比特与m个校验比特合并，得到长度n＝k+m的码组。从k比特的信息位到长度为n比特的码组的映射关系，通常由一个对应的校验矩阵H来表示。根据校验矩阵H可相应地生成编码序列，完成编码过程。编码后的码字通过信道传输之后，由接收端对接收到的信号进行相应地译码，判决出原有的信息比特。
在码长较长的情况下，LDPC的校验矩阵H会十分庞大，因此通常将校验矩阵H分块表示：校验矩阵H(具体指原始校验矩阵)视作由多个z×z的子矩阵生成，从而，校验矩阵H可由一个母矩阵表示，母矩阵中的每个元素对应一个z×z的子矩阵，每个子矩阵均可以由循环移位的位数表示。校验矩阵H所需的存储空间极大减小。每个校验矩阵分别对应一个码率和码长。
本申请实施例采用802.11ac标准中的校验矩阵，支持码长1944,1296以及648，这3种码长均支持码率为1/2，2/3,3/4和5/6。基于802.11ac标准给出的母矩阵以及扩展因子z，可以得出原始的校验矩阵H。
其中，IEEE 802.11ac以及802.11ax标准中采用的LDPC码为准循环低密度奇偶校验(quasi-cyclic low density parity check，QC-LDPC)码。QC-LDPC码是一类结构化的LDPC码。由于其校验矩阵的独特结构，编码时可以利用简单的反馈移位寄存器实现，降低LDPC码的编码复杂度。
IEEE 802.11ac和802.11ax共采纳了12个校验矩阵，其中支持3种码长，该3种码长分别为648、1296和1944。每种码长均支持4种不同的码率，分别为1/2，2/3，3/4和5/6。其中，所述12个校验矩阵的校验比特部分都具有相同的结构。
例如，802.11ac中码长为1944，码率为5/6的LDPC的校验矩阵H的母矩阵如下所示：
Figure PCTCN2021092348-appb-000001
可以看出，母矩阵的大小为4行24列，母矩阵中的每个元素表示一个z＝N/24阶的方阵，母矩阵中的“-”表示一个大小为z×z的全零方阵，母矩阵中的元素i表示循环移位值，其中，0≤i≤z-1，i为整数。例如，i＝0表示大小为81×81的单位阵，而i＝1表示如下循环移位矩阵：
Figure PCTCN2021092348-appb-000002
传统WLAN中进行LDPC编码时，发送端根据目标码长和目标码率，在上述12个校 验矩阵中选择相应的校验矩阵。其中，所述12个校验矩阵互不相同。
若在下一代WLAN标准中引入了IR-HARQ机制，则同时需要引入速率兼容的LDPC编码方案，以便在重传的时候获得新的增量冗余比特。
下面结合本申请提供的技术方案。
本申请的技术方案主要适用于无线通信系统，该无线通信系统可以遵从第三代合作伙伴计划(third generation partnership project,3GPP)的无线通信标准，也可以遵从其它无线通信标准，例如，IEEE的802系列(例如，802.11，802.15，或者802.20)的无线通信标准。
参见图3，图3的(a)和(b)为适用于本申请实施例的系统架构图。该无线通信系统包括至少一个网络设备以及一个或多个终端设备。所述至少一个网络设备以及一个或多个终端设备采用无线通信技术进行通信。例如，图3的(a)示出了一个网络设备与单个终端设备之间进行通信。图3的(b)中示出了一个网络设备与多个终端设备进行通信。可选地，以上网络设备与终端设备之间的通信又可以包括网络设备向终端设备发送信号的下行传输，以及终端设备向网络设备发送信号的上行传输，本文不作限定。
本申请的技术方案可以应用于上下行数据传输的场景下。例如，在上行传输中，各实施例中的发送端为终端设备，接收端为网络设备。在下行传输中，发送端为网络设备，接收端为终端设备。
本申请实施例涉及的终端设备，可以为用户设备(user equipment,UE)、终端(terminal)、移动电话(mobile phone)，平板电脑(tablet computer)，膝上型电脑(laptop computer)、可穿戴设备(例如，智能手表、智能手环、智能头盔、智能眼镜等)，以及其他具备无线接入能力的设备，例如，智能汽车，各种物联网(internet of thing，IOT)设备，包括各种智能家居设备(例如，智能电表和智能家电)以及智能城市设备(例如，安防或监控设备，智能道路交通设施)、5G系统或者未来的通信系统中的终端设备等。
本申请实施例涉及的网络设备，可以为基站，基站有时也称为无线接入点(access point,AP)、发送接收点(transmission reception point,TRP)或发送节点(transmission point,TP)。可选地，基站可以是第五代(5th generation,5G)系统中的通用节点B(generation Node B,gNB)、长期演进(long term evolution,LTE)系统中的演进节点B(evolutional Node B,eNB)。此外，根据基站的物理形态或发射功率的不同，基站可被分为宏基站(macro base station)或微基站(micro base station)。微基站有时也被称为小基站或小小区(small cell)。此外，网络设备还可以为构成gNB或TRP的网络节点，例如，基带单元(building baseband unit,BBU)、集中式单元(centralized unit,CU)或分布式单元(distributed unit,DU)等。
本申请提供一种基于LDPC的重复方案，通过对LDPC码字比特中的信息比特进行重复，从而可以在重传的时候获得部分重复的信息比特，以在接收端将这些重复的信息比特和首次传输的相应信息比特合并。
此外，本申请提供的LDPC的重复方案还可以与打孔(或者说，穿孔)方案组合使用，从而可以对LDPC码字比特中的信息比特进行重复，同时，对LDPC码字比特中的校验比特进行打孔，重传该部分信息比特以及打孔后剩余的部分校验比特，最终获得更加灵活的HARQ重传机制。接收端可以同时合并初传的比特和重传的部分信息比特以及增量冗余比特，以获得性能增益。
本申请提出的基于置信度准则的LDPC的重复方案的基本思想为：根据统计置信度特征，例如，迭代译码的对比似然比(likelihood rate,LLR)的绝对值，确定待重复的敏感信息比特的位置。IR-HARQ要求接收端的LDPC的码率是兼容的，即，高码率传输的比特包含在低码率传输的比特中，重传的信息比特需要满足该条件。在IR-HARQ机制中，对于置信度小的系统比特优先重复，因为置信度越小越容易出错，并且只有系统比特才携带有效信息。
为了说明置信度准则的基本原理，先定义码字比特的敏感性。
首先，固定信源为全“0”的信源。在无噪的情况下，对还未经过速率匹配的LDPC码字执行一定迭代次数的迭代计算，到迭代译码收敛后，将迭代译码的LLR的绝对值的大小|LLR|作为一个置信度特征，确定比特位置的敏感性。其中，|LLR|越小，则表示该|LLR对应的比特位置越敏感。
需要说明的是，由于LDPC码是线性码，并且采用不同的信源所确定的校验比特的位置具有类似的敏感性的排序，不同的信息比特所属的环和度分布特征一致，打孔性能基本相同。因此，本申请的技术方案中，固定信源为全“0”信源。
对待重复的LDPC的信息比特，按照置信度从小到大(或者从大到小)的顺序进行排序，并将排序关系存入表T中，表T即为比特位置的敏感性排序表。
可选地，作为一个示例，表T可以采用如下式(1)表示：
Figure PCTCN2021092348-appb-000003
下面再结合图4说明建立比特位置的敏感性排序表的流程。
参见图4，图4为本申请提供的建立比特位置的敏感性排序表的流程图。如图4，在无噪的环境中，固定全“0”信源，经过相应码率和码长的LDPC编码，再经过调制，例如，经过二进制相移键控(binary phase shift keying,BPSK)调制，将译码初始信息设为固定值±x，然后送入迭代译码器进行译码。经过一定迭代次数(例如，n次)之后，输出校验比特的LLR，并对LLR的绝对值进行排序，例如，按照从小到大排序。
可选地，迭代译码器具体可以为log-SPA迭代译码器。其中，SPA表示积算法(sum-product algorithm)，是基于迭代译码的LDPC译码算法的一种，属于一种软判决算法。在采用log-SPA译码算的情况下，加性高斯白噪声(additive white Gaussian noise,AWGN)信道的译码初始信息为y/σ 2，y为信道信息，σ 2为噪声方差。当噪声方差为0时，译码初始信息应为±∞。考虑到如果直接在计算机程序中这样设置，将会导致数据溢出。因此，在求解校验信息时用到如式(2)所示的函数：
Figure PCTCN2021092348-appb-000004
其中，
Figure PCTCN2021092348-appb-000005
的函数性质如图5，图5示出了函数
Figure PCTCN2021092348-appb-000006
的图像。
可选地，在实际译码中，译码初始值x可以设置为3,4,5等。
基于以上原理，本申请针对基于IR-HARQ机制的下一代WLAN系统，提出基于码率为1/2,2/3,3/4和5/6的LDPC的重复优先级排序。
首次传输时，IR-HARQ机制可以直接传输原始LDPC码字，或者先对原始LDPC码字的校验比特进行打孔后，再传输打孔后的码字。
第i次传输时，按照优先级从高到低(置信度从低到高)的顺序重传部分信息比特，或者，或者，同时补传已打孔的部分校验比特。重传比特的个数根据重传需要的新的码率或者重传分配的信道的信道资源的数目确定。
参见图6，图6为本申请提供的LDPC的速率匹配的方法的示意性流程图。本申请各实施例的方法，可以由发送端执行，或者由设置在发送端中的芯片、处理器、处理电路等器件或者模块等执行，以下实施例中以发送端作为执行主体为例进行说明。
410、发送端根据LDPC母码的K个信息比特在速率匹配过程中的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，得到第二码率的第二LDPC码字。
本申请中，LDPC码字中的信息比特在速率匹配过程中被重复(或者说，被执行重复发送)的优先级称为重复优先级。
其中，所述K个信息比特的重复优先级的排序反映了所述K个信息比特的可靠度(或者，置信度)的高低。
例如，一个信息比特的重复优先级越高，表明该信息比特的可靠度越高，则在速率匹配中，该信息比特优先被重复。反之，一个信息比特的重复优先级越低，表明该信息比特的可靠度越低，在速率匹配中，该信息比特在所述K个信息比特中越靠后被重复。
可选地，所述K个信息比特的重复优先级的排序，可以按照优先级从高到低排序，此时，位置越靠前的信息比特的重复优选级越高。或者，也可以按照优选级从低到高排序，此时，位置越靠后的信息比特的重复优先级越高。
应理解，在传统的WLAN中，使用目标码率和目标码长对应的校验矩阵，对K个信息比特进行LDPC编码，得到长度为N的LDPC的母码。其中，所述母码的N个码字比特中，K个码字比特对应于所述K个信息比特，剩余(N-K)个码字比特对应于对应于(N-K)个校验比特，其中，N,M均为正整数，N>K。目标码率可以如上文所述的1/2,2/3,3/4和5/6，目标码长可以如1944，1296和648。
由于码率对应不同的校验矩阵，因此，从一个高码率到一个低码率，或者从一个低码率到一个高码率，需要通过选择不同的校验矩阵，才能实现码率的变化。
而在本申请实施例中，由于IR-HARQ机制要求高码率和低码率兼容，因此，基于同一个校验矩阵，也可以实现从一个高码率到一个低码率，或者从一个低码率到一个高码率。这个从高码率到低码率，或者从低码率到高码率的过程，即为速率匹配。
在一个实施例中，步骤410中的第一LDPC码字可以为母码，在这种情况下，第一LDPC码字的第一码率也即母码的码率。也即，采用目标码长和目标码率的校验矩阵，对K个信息比特进行LDPC编码，即得到第一LDPC码字。其中，第一LDPC的码长为所述目标码长，第一LDPC码字的第一码率为所述目标码率。例如，以上文的码长为1944，码率为5/6的LDPC的校验矩阵为例，采用该校验矩阵对K个信息比特进行LDPC编码，得到码长为1944，码率为5/6的第一LDPC码字。
在此基础上，可以基于本申请提供的速率匹配的方案，对第一码率的第一LDPC码字进行速率匹匹配，得到第二码率的第二LDPC码字。
例如，若第一码率的第一LDPC码字的首次传输成功，发送端可以尝试更高的码率，此时，通过对第一码率的第一LDPC码字进行速率匹配，得到更高码率的第二LDPC码字，即，第二码率高于第一码率。
又例如，若第一码率的第一LDPC码字的首次传输失败，发送端可以尝试降低码率，以提高接收端成功解码的概率。在这种情况下，发送端可以通过对第一码率的第一LDPC码字进行速率匹配，得到较低码率的第二LDPC码字，即，第二码率低于第一码率。
具体地，若采用本申请实施例提供的信息比特的重复优先级，对第一LDPC码字进行速率匹配，得到第二LDPC码字，则第二LDPC码字的码率(即，第二码率)低于第一LDPC码字的第一码率。
在本申请中，速率匹配是基于信息比特的重复优先级执行的。或者，在另一些示例中，也可以将信息比特的重复优先级和校验比特的打孔优选级结合使用。
需要说明的是，上文介绍了基于码字比特的敏感性，获得信息比特的重复优先级的过程。基于相同的原理，也可以基于校验比特的敏感性，对校验比特的可靠度(即，置信度)进行排序，从而获得校验比特的打孔优先级。
与信息比特的重复优先级不同的是，如果一个校验比特越敏感，表明该校验比特的可靠度越低，则在速率匹配中，该校验比特优先被打孔，因此，该校验比特的打孔优先级越高。反之，如果一个校验比特敏感性越低，表明该校验比特的可靠度越高，则在速率匹配中，该校验比特的打孔优先级越低。
由于重传是为了提高接收端的译码成功率，因此，打孔优先级越高的校验比特，其可靠度越低，在重传过程中，其被发送端重传的优先级最低。反之，打孔优先级越低的校验比特，在重传过程中，其被发送端重传的优先级越高。
在另一个实施例中，第一LDPC码字可以是速率匹配之后的LDPC码字。例如，第一LDPC码字可以是对母码打孔之后得到的LDPC码字。或者，第一LDPC码字可以是对母码的部分信息比特进行重复之后得到的LDPC码字。在此基础上，发送端可以基于信息比特的重复优先级，或者，基于信息比特的重复优先级和校验比特的打孔优先级，对第一码率的第一LDPC码字进行速率匹配，以得到期望的第二码率。
420、发送端发送所述第二码率的LDPC码字。
因此，本申请提供的信息比特的重复优先级的排序用于LDPC码字的速率匹配。具体地，发送端通过重复一个高码率的LDPC码字的重复优先级较高的信息比特，而获得一个较低码率的LDPC码字。或者，发送端通过重复一个高码率的LDPC码字的重复优先级较高的信息比特，同时，打孔该LDPC码字的部分打孔优先级较高的校验比特，获得一个期望的码率。在本申请中，高码率和低码率是兼容的。
由于目前WLAN中每种码率(共4种码率，分别为1/2,2/3,3/4,5/6)的LDPC分别有3中码长，分别为648，1296和1944。因此，本申请针对所述四种码率和所述三种码长，分别给出相应的信息比特的置信度的排序。
(1)码率R＝1/2，码长L＝1944。
首先给出码率为1/2，码长为1944的LDPC码的校验矩阵的母矩阵(记为矩阵1)如下所示：
Figure PCTCN2021092348-appb-000007
如上所示，矩阵1的大小为12×24，矩阵1中的每个元素表示一个z＝1944/24＝81阶的方阵。其中，“-”表示81×81的全零矩阵。矩阵1中的每个元素i表示一个81×81的循环置换矩阵，i表示循环移位值，例如，i＝0表示大小为81×81的单位阵。
可选地，码率为1/2，码长为1944的LDPC对应的校验矩阵的母矩阵中校验比特的|LLR|及其可靠性排序可以如表1所示。
表1
可靠性的排序 19(2) 20(2) 18(2) 21(2) 17(2) 22(2)
|LLR| 26.9747 27.1948 27.3161 27.9524 28.1107 29.1414
可靠性的排序 16(2) 23(2) 15(2) 24(2) 14(2) 13(3)
|LLR| 29.2333 30.6309 30.6696 32.3636 32.5114 32.5925
在表1中，a(b)表示母矩阵的第a列，且第a列的列重为b(即，该列包含b个1)。
如表1所示，因为置信度越小越容易出错，可以为其它系统变量节点提供的有效信息越小，因此，置信度小的校验比特优先被打孔。并且，打孔的校验比特还可以保证系统变量节点的可恢复性，尤其是在被打孔的比特数目较多的情况下。
应理解，在本申请各实施例中，母矩阵中对应于信息比特的列的可靠性的排序，与其在速率匹配过程中的重复优先级级的排序是一致的。即，可靠性从高到低的顺序，即为重复优先级从高到低的顺序。
表2为本申请给出的信息比特的重复优先级的排序。
表2
可靠性的排序 10(3) 6(3) 8(3) 11(3) 4(3) 3(3)
|LLR| 35.1049 35.3955 35.3983 35.4292 35.4818 35.5749
可靠性的排序 12(3) 7(3) 2(4) 5(11) 9(11) 1(11)
|LLR| 35.6812 35.8946 47.0243 126.4571 126.7682 126.7955
在表2中，a(b)表示母矩阵中的第a列，其列重为b。如表2所示，置信度越小的信息比特，重复优先级越高。
由于本申请仅给出信息比特的重复优先级的排序，因此，表2中给出了矩阵1的第1列到第12列的排序，因为第1列至第12列对应于校验矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
根据上文介绍的原始校验矩阵和母矩阵的对应关系，对于大小为p×q的母矩阵，母矩阵的每个元素对应一个z＝N/q阶的方阵，母矩阵中的每一列对应于原始校验矩阵的z个码字比特。而信息比特的重复优先级是以母矩阵的列给出的，因此，母矩阵中的每个列在原始校验矩阵中对应的z个码字比特的重复优先级是相同的。
例如，码率R＝1/2，码长N＝1944的LDPC对应的母矩阵的大小为12×24，母矩阵中的每个元素对应于z＝1944/24＝81阶的方阵。因此，母矩阵的任意一列对应于原始校验矩阵的81个码字比特。以表2中可靠度排序最高的第10列为例，第10列对应于原始校验矩阵中的81个码字比特的重复优先级是相同的。
如表2中所示，码率为1/2，码长为1944的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序1：
排序1：10,6,8,11,4,3,12,7,2,5,9,1。
其中，排序1中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。例如，对于大小为12×24母矩阵，其列的索引的取值范围为[1,24]。
可选地，本申请各实施例中母矩阵的列的索引也可以从0开始，不作限制。索引从0开始或者从1开始，其表达的母矩阵中对应于信息比特的列的重复优先级的排序实质是相同的。
此外，应理解，母矩阵的列包括两部分，一部分对应于信息比特，另一部分对应于校验比特。例如，码率R＝1/2，码长N＝1944的LDPC对应的母矩阵的大小为12×24，所述24列中的第1列至第12列对应于信息比特，第13列至第24列对应于校验比特。因此，由于本申请主要涉及信息比特的重复优先级的排序，因此，各实施例中所述的“母矩阵中对应于信息比特的列”是指排除母矩阵的校验部分之外的所有列。例如，码率R＝1/2，码长N＝1944的LDPC对应的母矩阵，“对应于信息比特的列”即是指母矩阵的第1列至第12列。以下各实施例也是类似的，不再赘述。
若母矩阵的每个列对应于原始校验矩阵的z个码字比特，在速率匹配的过程中，根据需要重复的信息比特的个数L，可以按照如下规则选择信息比特执行重复操作。
在一种可能的情况下，若L<z，则发送端从所述母矩阵中重复优先级最高的一列对应的z个信息比特中选择L个信息比特执行重复操作。
具体地，由于母矩阵中的每个列对应的原始校验矩阵中的z个信息比特的重复优先级相同，因此，发送端可以从所述重复优先级最高的一列对应的z个信息比特中任意选取L个信息比特执行重复操作。例如，发送端按照从后往前，或者从前往后，或者随机选取的方式选择L个信息比特。
以表2为例，若需要重复的信息比特的个数L＝50，L<z＝81，发送端从母矩阵的第10列在原始矩阵中对应的81个信息比特中任意选取50个信息比特即可。
在另一种可能的情况下，若L＝m×z，m为正整数，则发送端从母矩阵中选择重复优先级最高的m个列在原始校验矩阵中对应的mz个信息比特执行重复操作。
由于需要重复的信息比特的个数恰好等于母矩阵中m个列在原始校验矩阵中对应的信息比特的个数，发送端则按照重复优先级从高到低的顺序，选择重复优先级靠前m个列在原始校验矩阵中对应的m×z个信息比特执行重复操作。
以表2为例，若需要重复的信息比特的个数L＝81，L＝z，发送端对母矩阵的第10列 在原始矩阵中对应的81个信息比特执行重复操作。若需要重复的信息比特的个数L＝162，L＝2×z，发送端对母矩阵的第10列在原始矩阵中对应的81个信息比特，以及第6列在原始校验矩阵中对应的81个信息比特执行重复操作。若需要重复的信息比特的个数L＝4×z，发送端对母矩阵的第10列，第6列，第8列以及第11列在原始矩阵中对应的共4×81个信息比特执行重复操作，不再一一赘述。
在再一种可能的情况下，若(m-1)×z<L<m×z，L为整数，m>1，且m为整数，则发送端按照重复优先级从高到低的排序，从母矩阵中选择重复优先级靠前的前(m-1)列在原始校验矩阵中对应的(m-1)×z个信息比特，以及第m列在原始校验矩阵中对应的z个信息比特中的p个信息比特执行重复操作，其中，L＝(m-1)×z+p，p≥1且p为整数。
以表2为例，例如，若需要重复的信息比特的个数L＝100，z<L<2×z，即，81<L<162，则发送端选择母矩阵的第10列在原始校验矩阵中对应的81个信息比特，以及母矩阵的第6列在原始校验矩阵中对应的81个信息比特中的(100-81)个信息比特执行重复操作。其中，母矩阵的第6列在原始校验矩阵中对应的81个信息比特中，可以随机选择19个信息比特，因为，母矩阵的第6列在原始校验矩阵中对应的81个信息比特的重复优先级是相同的。
又例如，若需要重复的信息比特的个数L＝170，2×z<L<3×z，即，2×81<L<3×81，则发送端选择母矩阵的第10列在原始校验矩阵中对应的81个信息比特，母矩阵的第6列在原始校验矩阵中对应的81个信息比特，以及母矩阵的第8列在原始校验矩阵中对应的81个信息比特中任意选择(170-2×81)个信息比特执行重复操作。同样地，由于母矩阵的每个列在原始校验矩阵中对应的z个信息比特的重复优先级相同，因此，发送端从母矩阵的第8列在原始校验矩阵中对应的81个信息比特中的任意选择8个信息比特即可。
可替换地，以上各种情况下，发送端重复的信息比特组成的集合可以称为第一信息比特集合。换句话说，根据需要重复的比特个数L，发送端对LDPC码字的第一信息比特集合中信息比特进行重复。其中，第一信息比特集合中包含L个信息比特，所述L个信息比特中重复优先级最低的信息比特的重复优先级，高于或者等于所述LDPC码字的全部信息比特中除了所述第一信息比特集合中的所述L个信息比特之外剩余的信息比特的重复优先级。
以表2为例，若L＝50，则母矩阵的第10列在原始矩阵中对应的81个信息比特中任意选取50个信息比特组成所述第一信息比特集合。若L＝81，则母矩阵的第10列在原始矩阵中对应的81个信息比特组成所述第一信息比特集合。若L＝162，则母矩阵的第10列在原始矩阵中对应的81个信息比特，以及母矩阵的第6列在原始校验矩阵中对应的81个信息比特，组成所述第一信息比特集合。若L＝170，则母矩阵的第10列在原始校验矩阵中对应的81个信息比特，母矩阵的第6列在原始校验矩阵中对应的81个信息比特，以及母矩阵的第8列在原始校验矩阵中对应的81个信息比特中的任意8个信息比特，组成所述第一信息比特集合。
表3示出了本申请提供的基于置信度准则的重复方案与802.11ac标准的重复方案的对比。
表3
Figure PCTCN2021092348-appb-000008
Figure PCTCN2021092348-appb-000009
如表3，以需要重复的信息比特的个数为2×81，5×81，8×81和10×81作为示例，表3中列举了优先重复的信息比特在母矩阵中对应的列的列索引。作为对比，802.11ac的重复优先级从从前往后。
此外，从表3中还可以发现，本申请的技术方案中，对于特定码长的LDPC码，低码率的LDPC的重复方案兼容了高码率的LDPC的重复方案。换句话说，低码率的LDPC的信息比特的重复位置包含了高码率的LDPC的信息比特的重复位置。
例如，在重复个数为2×81(也即母矩阵的2列)的情况下，LDPC的信息比特的重复位置对应于母矩阵的列的索引集合为{12,14}。
在重复个数为5×81(也即母矩阵的5列)的情况下，LDPC的信息比特的重复位置对应于母矩阵的列的索引集合为{12,14,15,17,19}，其中，该索引集合中包含了母矩阵的第12列和第14列。
在重复个数为8×81(也即母矩阵的8列)的情况下，LDPC的信息比特的重复位置对应于母矩阵的列的索引集合为{12,14,15,17,19,13,20,11}，其中，该索引集合中不仅包含了母矩阵的第12列和第14列，即重复2列的情况，并且包含了母矩阵的第12列,第14列,第15列,第17列,以及第19列，即重复5列的情况。
根据速率匹配的原理可以知道，信息比特的个数重复的越多，LDPC码的码率越高。因此，在本申请的重复方案中，高码率和低码率是兼容的。也即，在一个低码率的LDPC码字的重复位置的基础上增加新的重复位置，可以获得一个更高码率的LDPC码字。
(2)码率R＝1/2，码长L＝1296。
码率为1/2，码长为1296的LDPC码的校验矩阵的母矩阵(记为矩阵2)如下所示：
如上所示，矩阵2的大小为12×24，矩阵2中的每个元素表示一个z＝1296/24＝54阶的方阵。其中，“-”表示54×54的全零矩阵。矩阵2中的每个元素i表示一个54×54的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为54×54的单位阵。
Figure PCTCN2021092348-appb-000010
表4为本申请给出的码率为1/2，码长为1296的LDPC的信息比特的重复优先级的排序。
表4
可靠性的排序 8(3) 12(3) 7(3) 3(3) 11(3) 10(3)
|LLR| 39.2121 39.3214 39.7775 39.7809 40.3593 40.5239
可靠性的排序 4(3) 6(3) 2(4) 5(11) 9(11) 1(11)
|LLR| 40.9689 41.0671 52.9074 143.0869 144.3379 144.4487
在表4中，a(b)表示母矩阵的第a列，其列重为b。
由于本申请仅给出信息比特的重复优先级的排序，因此，表4中给出了矩阵2的第1列到第12列的排序，因为第1列至第12列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
由于矩阵2给出的是母矩阵，其中每一列对应于原始校验矩阵的54个码字比特。母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。以表4中重复优先级最高的第8列为例，即母矩阵的第8列在原始校验矩阵中所对应的54个信息比特的重复优先级是相同的。
如表4所示，码率为1/2，码长为1296的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序2：
排序2：8,12,7,3,11,10,4,6,2,5,9,1。
其中，排序2中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(3)码率R＝1/2，码长L＝648。
码率为1/2，码长为648的LDPC码的校验矩阵的母矩阵(记为矩阵3)如下所示：
Figure PCTCN2021092348-appb-000011
如上所示，矩阵3的大小为12×24，矩阵3中的每个元素表示一个z＝648/24＝27阶的方阵。其中，“-”表示27×27的全零矩阵。矩阵3中的每个元素i表示一个27×27的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为27×27的单位阵。
表5为本申请给出的码率为1/2，码长为648的LDPC的信息比特的重复优先级的排序。
表5
可靠性的排序 8(3) 6(3) 12(3) 11(3) 2(3) 3(3)
|LLR| 46.8189 48.0339 49.6489 50.3947 50.6030 50.0061
可靠性的排序 10(3) 7(3) 4(3) 1(12) 5(12) 9(12)
|LLR| 51.5432 52.8294 53.0404 199.0153 199.0153 199.0153
在表5中，a(b)表示母矩阵的第a列，其列重为b。另外，表5中给出了矩阵3的第1列到第12列的排序，因为第1列至第12列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
由于矩阵3给出的是母矩阵，其中每一列对应于原始校验矩阵的27个码字比特。母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。以表5中重复优先级最高的第8列为例，即母矩阵的第8列在原始校验矩阵中所对应的27个信息比特的重复优先级是相同的。
如表5所示，码率为1/2，码长为648的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序3：
排序3：8,6,12,11,2,3,10,7,4,1,5,9。
其中，排序3中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(4)码率R＝2/3，码长L＝1944。码率为1/2，码长为648的LDPC的校验矩阵的母矩阵(记为矩阵4)如下所示：
Figure PCTCN2021092348-appb-000012
如上所示，矩阵4的大小为8×24，矩阵4中的每个元素表示一个z＝1944/24＝81阶的方阵。其中，“-”表示81×81的全零矩阵。矩阵4中的每个元素i表示一个81×81的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为81×81的单位阵。
表6为本申请给出的码率为2/3，码长为1944的LDPC的信息比特的重复优先级的排序。
表6
Figure PCTCN2021092348-appb-000013
在表6中，a(b)表示母矩阵的第a列，其列重为b。如表6所示，置信度越小的信息 比特，重复优先级越高。
另外，表6中给出了矩阵4的第1列到第16列的排序，因为第1列至第16列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
由于矩阵4给出的是母矩阵，其中每一列对应于原始校验矩阵的81个码字比特。母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。以表6中重复优先级最高的第16列为例，即，母矩阵的第16列在原始校验矩阵中所对应的81个信息比特的重复优先级是相同的。
如表6所示，码率为2/3，码长为1944的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序4：
排序4：16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4。
其中，排序4中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(5)码率R＝2/3，码长L＝1296。
码率为2/3，码长为1296的LDPC码的校验矩阵的母矩阵(记为矩阵5)如下所示：
Figure PCTCN2021092348-appb-000014
如上所示，矩阵5的大小为8×24，矩阵5中的每个元素表示一个z＝1296/24＝54阶的方阵。其中，“-”表示54×54的全零矩阵。矩阵5中的每个元素i表示一个54×54的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为54×54的单位阵。
表7为本申请给出的码率为2/3，码长为1296的LDPC的信息比特的重复优先级的排序。
表7
Figure PCTCN2021092348-appb-000015
在表7中，a(b)表示母矩阵的第a列，其列重为b。其中，表7中给出了矩阵5的第1列到第16列的排序，因为第1列至第16列对应于校验矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
由于矩阵5给出的是母矩阵，其中每一列对应于原始校验矩阵的54个码字比特。母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。以表7中重复优先级最高的第16列为例，指的是母矩阵的第16列在原始校验矩阵 中所对应的54个信息比特的重复优先级是相同的。
如表7所示，码率为2/3，码长为1296的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序5：
排序5：16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3。
其中，排序5中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(6)码率R＝2/3，码长L＝648。
码率为2/3，码长为648的LDPC码的校验矩阵的母矩阵(记为矩阵6)如下所示：
Figure PCTCN2021092348-appb-000016
如上所示，矩阵6的大小为8×24，矩阵6中的每个元素表示一个z＝648/24＝27阶的方阵。其中，“-”表示27×27的全零矩阵。矩阵6中的每个元素i表示一个27×27的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为27×27的单位阵。
表8为本申请给出的码率为2/3，码长为648的LDPC的信息比特的重复优先级的排序。
表8
Figure PCTCN2021092348-appb-000017
在表8中，a(b)表示母矩阵的第a列，其列重为b。
另外，母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵6给出的是母矩阵，其中每一列对应于原始校验矩阵的27个码字比特。以表7中重复优先级最高的第16列为例，指的是母矩阵的第16列在原始校验矩阵中所对应的27个信息比特的重复优先级是相同的。
如表8所示，码率为2/3，码长为648的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序6：
排序6：16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3。
其中，排序6中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(7)码率R＝3/4，码长L＝1944。
码率为3/4，码长为1944的LDPC码的校验矩阵的母矩阵(记为矩阵7)如下所示：
Figure PCTCN2021092348-appb-000018
如上所示，矩阵7的大小为12×24，矩阵7中的每个元素表示一个z＝1944/24＝81阶的方阵。其中，“-”表示81×81的全零矩阵。矩阵7中的每个元素i表示一个81×81的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为81×81的单位阵。
表9为本申请给出的码率为3/4，码长为1944的LDPC的信息比特的重复优先级的排序。
表9
Figure PCTCN2021092348-appb-000019
在表9中，a(b)表示母矩阵的第a列，其列重为b。
另外，表9中给出了矩阵7的第1列到第18列的排序，因为第1列至第18列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵7给出的是母矩阵，其中每一列对应于原始校验矩阵的81个码字比特。以表9中重复优先级最高的第18列为例，指的是母矩阵的第18列在原始校验矩阵中对应的81个信息比特的重复优先级是相同的。
如表9所示，码率为3/4，码长为1944的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序7：
排序7：12,16,11,10,14,17,15,8,13,18,7,9,6,1,2,3,4,5,6。
其中，排序7中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(8)码率R＝3/4，码长L＝1296。
码率为3/4，码长为1296的LDPC码的校验矩阵的母矩阵(记为矩阵8)如下所示：
Figure PCTCN2021092348-appb-000020
如上所示，矩阵8的大小为12×24，矩阵8中的每个元素表示一个z＝1296/24＝54阶的方阵。其中，“-”表示54×54的全零矩阵。矩阵8中的每个元素i表示一个54×54的 循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为54×54的单位阵。
表10为码率为3/4，码长为1296的LDPC的信息比特的重复优先级的排序。
表10
Figure PCTCN2021092348-appb-000021
在表10中，a(b)表示母矩阵的第a列，其列重为b。
另外，表10中给出了矩阵8的第1列到第18列的排序，因为第1列至第18列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵7给出的是母矩阵，其中每一列对应于原始校验矩阵的54个码字比特。以表10中重复优先级最高的第9列为例，指的母矩阵的第9列在原始校验矩阵中对应的54个信息比特的重复优先级是相同的。
如表10所示，码率为3/4，码长为1296的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序8：
排序8：9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7。
其中，排序8中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(9)码率R＝3/4，码长L＝648。
码率为3/4，码长为648的LDPC码的校验矩阵的母矩阵(记为矩阵9)如下所示：
Figure PCTCN2021092348-appb-000022
如上所示，矩阵9的大小为12×24，矩阵9中的每个元素表示一个z＝648/24＝27阶的方阵。其中，“-”表示27×27的全零矩阵。矩阵9中的每个元素i表示一个27×27的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为27×27的单位阵。
表11为本申请给出的码率为3/4，码长为648的LDPC的信息比特的重复优先级的排序。
表11
Figure PCTCN2021092348-appb-000023
Figure PCTCN2021092348-appb-000024
在表11中，a(b)表示母矩阵的第a列，其列重为b。
另外，表11中给出了矩阵9的第1列到第18列的排序，因为第1列至第18列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵9给出的是母矩阵，其中每一列对应于原始校验矩阵的27个码字比特。以表10中重复优先级最高的第18列为例，指的是母矩阵的第18列所对应的27个信息比特的重复优先级是相同的。
如表11所示，码率为3/4，码长为648的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序9：
排序9：18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5。
其中，排序9中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(10)码率R＝5/6，码长L＝1944。
码率为5/6，码长为1944的LDPC码的校验矩阵的母矩阵(记为矩阵10)如下所示：
Figure PCTCN2021092348-appb-000025
如上所示，矩阵10的大小为8×24，矩阵10中的每个元素表示一个z＝1944/24＝81阶的方阵。其中，“-”表示81×81的全零矩阵。矩阵10中的每个元素i表示一个81×81的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为81×81的单位阵。
表12为本申请给出的码率为5/6，码长为1944的LDPC的信息比特的重复优先级的排序。
表12
Figure PCTCN2021092348-appb-000026
在表12中，a(b)表示母矩阵的第a列，其列重为b。
另外，表12中给出了矩阵10的第1列到第20列的排序，因为第1列至第20列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复 优先级相同。由于矩阵10给出的是母矩阵，其中每一列对应于原始校验矩阵的81个码字比特。以表12中重复优先级最高的第12列为例，指的是母矩阵的第12列在原始校验矩阵中对应的81个信息比特的重复优先级是相同的。
如表12所示，码率为5/6，码长为1944的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序10：
排序10：12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10。
其中，排序10中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(11)码率R＝5/6，码长L＝1296。
码率为5/6，码长为1296的LDPC码的校验矩阵的母矩阵(记为矩阵11)如下所示：
Figure PCTCN2021092348-appb-000027
如上所示，矩阵11的大小为8×24，矩阵11中的每个元素表示一个z＝1296/24＝54阶的方阵。其中，“-”表示54×54的全零矩阵。矩阵11中的每个元素i表示一个54×54的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为54×54的单位阵。
表13为本申请给出的码率为5/6，码长为1296的LDPC的信息比特的重复优先级的排序。
表13
Figure PCTCN2021092348-appb-000028
在表13中，a(b)表示母矩阵的第a列，其列重为b。
另外，表13中给出了矩阵11的第1列到第20列的排序，因为第1列至第20列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵11给出的是母矩阵，其中每一列对应于原始校验矩阵的54个码字比特。以表13中重复优先级最高的第17列为例，指的是母矩阵的第17列在原始校验矩阵中对应的54个信息比特的重复优先级是相同的。
如表13所示，码率为5/6，码长为1296的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序11：
排序11：17,20,19,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10。
其中，排序11中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
(12)码率R＝5/6，码长L＝648。
码率为5/6，码长为648的LDPC码的校验矩阵的母矩阵(记为矩阵12)如下所示：
Figure PCTCN2021092348-appb-000029
如上所示，矩阵12的大小为8×24，矩阵12中的每个元素表示一个z＝648/24＝27阶的方阵。其中，“-”表示27×27的全零矩阵。矩阵12中的每个元素i表示一个27×27的循环置换矩阵，i表示循环移位值。例如，i＝0表示大小为27×27的单位阵。
表14为本申请给出的码率为5/6，码长为648的LDPC的信息比特的重复优先级的排序。
表14
Figure PCTCN2021092348-appb-000030
在表14中，a(b)表示母矩阵的第a列，其列重为b。
另外，表14中给出了矩阵12的第1列到第20列的排序，因为第1列至第20列对应于矩阵的信息(或者说，系统)部分。这部分列对应的码字比特均为原始信息比特。
母矩阵中的每一列对应于原始校验矩阵的z个信息比特，且所述z个码字比特的重复优先级相同。由于矩阵12给出的是母矩阵，其中每一列对应于原始校验矩阵的27个码字比特。以表14中重复优先级最高的第13列为例，指的是母矩阵的第13列在原始校验矩阵中对应的27个信息比特的重复优先级是相同的。
如表14所示，码率为5/6，码长为648的LDPC的校验矩阵，其母矩阵中对应于信息比特的列在速率匹配中的重复优先级按照从高到低的顺序，可以为如下的排序12：
排序12：13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20。
其中，排序12中的每个元素a表示校验矩阵的母矩阵的第a列。并且，母矩阵中的列的索引从1开始。
以上给出了本申请提供的3种码长和4种码率下信息比特的重复优先级的排序。下举例说明该重复优先级在IR-HARQ中的应用。
参见图7，图7为本申请提供的重复方案在IR-HARQ中的应用示例。
510、发送端生成适用于信道传输的LDPC码字，例如，所述LDPC码字的码率为1/2。
520、发送端发送所述LDPC码字。
以下将此次发送定义为初次传输。
如果接收端能够正确译码全部的信息比特(即，系统比特)，则结束这个数据包的传 输。如果接收端不能正确译码，接收端请求发送端进行重传。重传的过程可以步骤530以及后续步骤。
530、发送端获取信息比特的重复优先级的排序。
540、发送端基于该重复优先级的排序，重传重复优先级最高的t1个信息比特。
接收端接收发送端重传的所述t1个的信息比特，将所述t1个信息比特与之前接收到的序列的相应信息比特合并，再译码。如果接收端仍然不能正确译码，在未达到预设的最大重传次数的情况下，接收端继续请求发送端进行重传。
550、发送端基于该重复优先级的排序，再重传重复优先级次高的t2个信息比特。
接收端接收发送端重传的所述t2个的信息比特，将所述t2个信息比特与之前接收到所述t1个信息比特以及初次传输接收到的序列的相应信息比特合并，再译码。
以此类推，直至发送端重复发送完所有的信息比特。如果接收端仍然不能正确恢复出信息比特，表示该数据包的传输失败并结束传输，进行下一个数据包的传输。
在以上传输过程中，第l次传输的码率可以满足如下式(3)：
Figure PCTCN2021092348-appb-000031
在式(3)中，R c为发送端第一次发送的LDPC码字的码率(例如，上述步骤510中列举的1/2)，k表示系统比特的个数，n表示LDPC的母码码字的长度。其中，第一次传输增加的冗余量t 0＝0。
另外，本申请提供的信息比特的重复方案可以与校验比特的打孔方案结合使用，下面结合图8举例说明。
参见图8，图8为本申请提供的信息比特的重复方案和校验比特的打孔方案的结合在IR-HARQ中的应用示例。
611、发送端生成适用于信道传输的原始LDPC码字，例如，所述原始LDPC码字的码率为1/2。
假设LDPC的母码的码长为N，其中信息比特的个数为K，校验比特的个数为(N-K)，其中，N和K均为正整数。
612、发送端获取K个信息比特的重复优先级的排序，以及所述(N-K)个校验比特的打孔优先级的排序。
应理解，信息比特的重复优先级越高，表明该信息比特的可靠度越高，因此，重传的优先级也越高。与之相反，校验比特的打孔优先级越高，表明该校验比特的可靠度越低，在速率匹配的过程中被打孔的优先级越高，但是重传的优先级越低。
613、发送端基于所述(N-K)个校验比特的打孔优先级的排序，对所述原始LDPC码字进行打孔(假设仅打孔校验比特)，获得初次传输期望的目标码率的LDPC码字(以下记作第一LDPC码字)。例如，通过对原始LDPC码字打孔，获得的第一LDPC码字的码率为5/6。
614、发送第一LDPC码字。
如果接收端能够正确译码全部的信息比特，则结束这个数据包的传输。如果接收端不能正确译码，接收端请求发送端进行重传。重传的过程可以步骤615以及后续步骤。
615、发送端优先发送可靠度最高的t1个打孔校验比特。
可靠度最高的t1个打孔校验比特，即，按照打孔优先级从低到高的顺序，排序靠前的前t1个校验比特。
在该实施例中，打孔校验比特是指在初次传输的速率匹配过程中被打孔的校验比特。
接收端接收所述t1个打孔校验比特，并将所述t1个打孔校验比特与初次传输接收到的序列合并为一个序列，再译码。
如果接收端仍然不能正确译码，在未达到预设的最大重传次数的情况下，接收端继续请求发送端进行重传。
616、发送端再发送可靠度次高的t2个打孔校验比特。
可靠度最高的t2个打孔校验比特，即，按照打孔优先级从低到高的顺序，在全部的打孔校验比特中，除了所述t1个打孔校验比特之外剩余的打孔校验比特中，排序靠前的前t2个打孔校验比特。
接收端接收所述t2个打孔校验比特，并将所述t2个打孔校验比特与初次传输接收到的序列，以及所述t1个打孔校验比特合并为一个序列，再译码。
依次类推，直至发送端发送了全部的打孔校验比特，如果接收端仍然不能正确译码，则发送端考虑发送信息比特。
617、发送端发送重复优先级最高的s1个信息比特。
接收端接收所述s1个信息比特，并将所述s1个信息比特与前一次的译码序列合并，对合并后的序列进行再译码。如果接收端仍然不能正确译码，在未达到预设的最大重传次数的情况下，接收端继续请求发送端进行重传。
618、发送端发送重复优先级次高的s2个信息比特。
接收端接收所述s2个信息比特，并将所述s2个信息比特与前一次的译码序列合并，对合并后的序列进行再译码。依次类推，直至发送端重复发送完全部的信息比特。如果此时，接收端仍然不能正确译码信息比特，则表示本数据包的传输失败并结束传输，进行下一个数据包的传输。
在图8的示例中，发送端发送第一LDPC码字，若接收端译码失败，发送端首先根据校验比特的打孔优先级发送被打孔的校验比特，直至全部的校验比特被发送完，如果接收端仍然未成功译码，发送端再根据信息比特的重复优先级对第一LDPC码字中的信息比特进行重复发送。
在另一个示例中，发送端方第一LDPC码字，若接收端译码失败，发送端可以首先根据信息比特的重复优先级对第一LDPC码字中的信息比特进行重复发送，直到全部的信息比特都被重复发送，如果接收端仍然未成功译码，发送端再根据校验比特的打孔优先级发送被打孔的校验比特。
换句话说，本申请实施例不限定打孔方案和重复方案的结合的先后顺序。即，发送端发送的LDCP码字未被接收端成功译码，发送端可以先执行重复方案再执行打孔方案，或者，也可以先执行重复方案再执行打孔方案都是可行的。
在以上传输过程中，第l次传输的码率可以满足如下式(4)：
Figure PCTCN2021092348-appb-000032
在式(4)中，R c＝k/n，
Figure PCTCN2021092348-appb-000033
n表示LDPC的母码码字的长度。
和基于打孔自由度速率兼容的HARQ(rate compatible puncture latitude HARQ,RCPL-HARQ)技术，以及基于重复自由度的速率建兼容的HARQ(rate compatible repeat latitude HARQ,RCRL-HARQ)技术相比较，基于自由度的速率兼容的HARQ(rate compatible latitude HARQ,RCL-HARQ)技术可以实现更灵活的码率。
以上结合图1-图8对本申请提供的LDPC的重复方案，以及重复方案和打孔方案的结合方案进行了详细说明。下面给出本申请提供的LDPC的重复方案与传统的重复方案的BER和FER的仿真结果的比较。
图9-图19为各种IR-HARQ传输策略下系统的FER曲线及吞吐率曲线。
其中，图9-图19的仿真参数设置如下：AWGAN信道；BPSK调制；log-SPA译码，最大迭代译码次数为10次；采用停止-等待的重传请求策略；为了恢复每一帧数据的最大传输次数为4次。
另外，图9-图19中考虑的性能评估参数主要为误帧率(frame error rate,FER)和吞吐率(throughput)。其中，吞吐率＝(正确接收到的帧数×k)/总共发送的比特数，k为每一帧的信息比特的个数。此外，各图中的E s/N 0表示符号信噪比。
传统方法中的LDPC码为802.11ac标准中码长为1944或972的QC-LDPC码。
具体地，图9为码长N＝1944，码率R＝1/2时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图10为母码码长N＝1944，码率R＝5/6时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图11为母码码长N＝1920，码率R＝1/2时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图12为母码码长N＝1920，码率R＝5/6时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图13为母码码长N＝648，码率R＝1/2时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图14为母码码长N＝648，码率R＝5/6时，不同信息比特重复数目下的本申请的重复方案与传统的重复方案的BER性能对比。
图15为IR-HARQ技术的码率为5/6的(1944,1620)的QC-LDPC的仿真结果一。
图16为IR-HARQ技术的码率为5/6的(1944,1620)的QC-LDPC的仿真结果二。
图17为IR-HARQ技术的码率为1/2的(1944,972)的QC-LDPC的仿真结果三。
图18为IR-HARQ技术的码率为1/2的(1944,972)的QC-LDPC的仿真结果四。
图19为IR-HARQ技术的码率为1/2的(1944,972)的QC-LDPC的仿真结果五。
其中，图9-图14中，“the reliability based repetition”对应的曲线表示本申请的重复方案的性能曲线，而“the standard based puncturing”表示传统的重复方案的性能曲线。其中，repetition后面括号内的数字表示信息比特的重复数目，以列为单位。例如，repetition(2) 表示重复数目为2列，repetition(5)表示重复数目为5列。
其中，图9-图19中的图例中，“proposed scheme”均表示本申请提出的方案，“standard scheme”均表示标准(即上文的802.11ac标准)的方案，也即传统方案。
从图15-图19可以看出，相同E s/N 0下，本申请的重复方案的FER更低，吞吐量更高，表明本申请的重复方案优于传统的重复方案。
下面介绍本申请提供的通信装置。
参见图20，图20为本申请提供的通信装置1000的示意性框图。如图20，通信装置1000包括处理单元1100和收发单元1200。
可选地，收发单元1200也可以由发送单元或接收单元代替。例如，收发单元1200在执行发送的动作时，可以由发送单元代替。收发单元1200在执行接收的动作时，可以由接收单元代替。
处理单元1100，用于根据LDPC母码的K个信息比特在速率匹配过程中的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，得到第二码率的第二LDPC码字，其中，K为LDPC母码包含的信息比特的个数，K为正整数；
收发单元1200，用于发送所述第二LDPC码字。
可选地，在一个实施例中，所述处理单元1100还用于：
根据需要重复的比特个数L，以及所述K个信息比特在速率匹配过程中的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合中的信息比特进行重复，其中，所述第一信息比特集合中重复优先级最低的信息比特的重复优先级，高于或者等于所述第一LDPC码字中的除了所述第一信息比特集合中的信息比特之外的剩余信息比特的重复优先级，L≤K，且L为整数。
可选地，在一个实施例中，所述K个信息比特的重复优先级的排序，具体为：
信息比特个数为K，母码长度为N，码率为R的LDPC的校验矩阵的母矩阵中对应于信息比特的列的重复优先级的排序，所述母矩阵中的每个列对应所述LDPC的z个码字比特，其中，z＝N/n，n为所述母矩阵包含的列的总数，其中，所述LDPC的校验矩阵通过扩展所述母矩阵得到，所述母矩阵中的每个元素i表示一个z×z的循环移位矩阵，i表示循环移位值，i≥0，且i为整数，N≥K,N为整数，R＝K/N。
可选地，在一个实施例中，所述母码长度为1944，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
10,6,8,11,4,3,12,7,2,5,9,1,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1296，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
8,12,7,3,11,10,4,6,2,5,9,1,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为648，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
8,6,12,11,2,3,10,7,4,1,5,9,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1944，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1296，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为648，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1944，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1296，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为648，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1944，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为1296，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述母码长度为648，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20,
其中，所述排序中的每个元素a表示所述母矩阵的第a列。
可选地，在一个实施例中，所述处理单元1100具体用于：
若L<z，从所述母矩阵中重复优先级最高的一列在所述校验矩阵中对应的z个信息比特中选择L个信息比特进行重复；
若L＝m×z，所述发送端按照重复优先级从高到低的顺序，从所述母矩阵中选择重复优先级靠前的前m个列在所述校验矩阵中对应的mz个信息比特进行重复，m为正整数；
若(m-1)×z<L<m×z，按照重复优先级从高到低的排序，从母矩阵中选择重复优先级靠前的前(m-1)列在所述校验矩阵中对应的(m-1)×z个信息比特，以及第m列在所述校验矩阵中对应的z个信息比特中的p个信息比特进行重复，其中，L＝(m-1)×z+p，p≥1且p为整数，m>1，且m为整数。
可选地，在一个实施例中，所述收发单元1200，还用于发送所述第一LDPC码字；
以及，所述处理单元1100，用于确定所述第一LDPC码字未被接收端成功译码；
所述收发单元1200，具体用于根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送；
以及，所述处理单元1100，还用于确定所述第一LDPC码字包含的全部信息比特都被重复发送，且接收端仍未成功译码；
以及，所述收发单元1200，还用于按照校验比特的打孔优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数。
可选地，在一个实施例中，所述收发单元1200，还用于发送所述第一LDPC码字；
所述处理单元1100，还用于确定所述第一LDPC码字未被接收端成功译码；
所述发送单元1200，还用于按照校验比特的优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数；
以及，所述处理单元1100，还用于确定所述第一LDPC码字的所有被打孔的校验比特全部被发送，且所述接收端仍未成功译码；
所述收发单元1200，还用于按照所述K个信息比特的重复优先级，发送所述第一LDPC码字的信息比特。
可选地，通信装置1000可以为发送端，或者，通信装置1000可以为发送端内部具有实现各方法实施例的功能的器件、模块等。
在一种实现中，通信装置1000为上述各方法实施例中的发送端，通信装置1000可以具有各方法实施例中发送端的任意功能。在这种情况下，处理单元1100可以为处理器。收发单元1200可以为收发器。收发器具体可以包括接收机和发射机。其中，接收机用于执行接收的功能，发射机用于执行发射的功能。
可选地，在另一种实现中，通信装置1000可以为发送端中的电路系统。在这种情况下，处理单元1100可以为芯片、逻辑电路、集成电路、处理电路或片上系统(system on chip,SoC)芯片等，收发单元1200可以为通信接口，所述通信接口可以为接口电路、输入输出接口、芯片上的用于传输信号的管脚等。
在一个实施例中，通信装置1000可以为发送端中的编码器。
在以上各实施例中，处理单元1100的功能可以通过硬件实现，也可以通过硬件执行 相应的软件实现。
例如，处理单元1100可以包括一个或多个处理器，所述一个或多个处理器用于读取并执行存储器中保存的计算机程序或指令，使得各方法实施例中由发送端执行的操作和/或处理被执行。其中，所述存储器位于所述一个或多个处理器之外。
进一步地，处理单元1100还可以包括一个或多个存储器，所述一个或多个处理器以及所述一个或多个存储器通过电路/电线连接，所述一个或多个处理器可以读取所述一个或多个存储器中存储的计算机程序或指令，使得本申请各方法实施例中由发送端执行的操作和/或处理被执行。
又例如，处理单元1100为处理器，收发单元1200可以为接口电路。其中，接口电路用于接收计算机代码或指令，并传输至所述处理器，所述处理器执行所述计算机代码或指令，使得本申请各方法实施例中由发送端执行的操作和/或处理被执行。
可选地，所述处理单元1100还可以为处理电路或者逻辑电路等。
此外，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得本申请提供的LDPC的速率匹配的方法被实现。
本申请还提供一种计算机程序产品，所述计算机程序产品包括计算机代码或指令，当所述计算机代码或指令在计算机上运行时，本申请各方法实施例的LDPC的速率匹配的方法被实现。
本申请还提供一种通信装置，包括处理器和接口电路，所述接口电路用于接收计算机代码或指令，并传输至所述处理器，所述处理器用于运行所述计算机代码或指令，使得本申请提供的LDPC的速率匹配的方法被实现。
本申请还提供一种芯片，所述芯片包括一个或多个处理器。所述一个或多个处理器用于执行存储器中存储的计算机程序，以执行任意一个方法实施例中由发送端设备执行的操作和/或处理。其中，所述存储器独立于所述芯片之外而设置。
进一步地，所述芯片还可以包括一个或多个通信接口。所述一个或多个通信接口可以是输入输出接口、接口电路等。进一步地，所述芯片还可以包括一个或多个所述存储器。
本申请还提供一种无线通信系统，包括本申请实施例中的发送端。
可选地，所述发送端可以为网络设备(例如，基站)，或者为终端设备，不作限定。
本申请实施例中的处理器可以是集成电路芯片，具有处理信号的能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。处理器可以是通用处理器、数字信号处理器(digital signal processor,DSP)、专用集成电路(application specific integrated circuit,ASIC)、现场可编程门阵列(field programmable gate array,FPGA)或其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。本申请实施例公开的方法的步骤可以直接体现为硬件编码处理器执行完成，或者用编码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和 非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory,ROM)、可编程只读存储器(programmable ROM,PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM,EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory,RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM,DRAM)、同步动态随机存取存储器(synchronous DRAM,SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM,DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM,ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM,SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM,DRRAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
在本说明书中使用的术语“单元”、“系统”等用于表示计算机相关的实体、硬件、固件、硬件和软件的组合、软件或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进程和/或执行线程中。部件可位于一个计算机上和/或分布在两个或更多个计算机之间。此外，这些部件可从上面存储有各种数据结构的各种计算机可读介质执行。部件可根据具有一个或多个数据分组(例如，来自与本地系统、分布式系统和/或网络间的另一部件交互的二个部件的数据，例如，通过信号与其它系统交互的互联网)的信号通过本地和/或远程进程来通信。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储 在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种LDPC的速率匹配的方法，其特征在于，包括：
    发送端根据低密度奇偶校验码LDPC母码的K个信息比特在速率匹配中的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，得到第二码率的第二LDPC码字，K为正整数；
    所述发送端发送所述第二LDPC码字。
  2. 根据权利要求1所述的方法，其特征在于，所述发送端根据K个信息比特在速率匹配中的重复优先级的排序，对第一码率的第一LDPC码字进行速率匹配，包括：
    所述发送端根据需要重复的比特个数L，以及所述K个信息比特在速率匹配中的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送；
    其中，所述第一信息比特集合包含的L个信息比特中重复优先级最低的信息比特的重复优先级，高于或者等于所述第一LDPC码字中的除了所述第一信息比特集合中的所述L个信息比特之外的剩余信息比特的重复优先级，L≤K，且L为整数。
  3. 根据权利要求1或2所述的方法，其特征在于，所述K个信息比特的重复优先级的排序为：
    信息比特个数为K，母码长度为N，码率为R的LDPC的校验矩阵的母矩阵中对应于信息比特的列的重复优先级的排序，所述母矩阵中的每个列对应所述LDPC的z个码字比特，其中，z＝N/n，n为所述母矩阵包含的列的总数，其中，所述LDPC的校验矩阵通过扩展所述母矩阵得到，所述母矩阵中的每个元素i表示一个z×z的循环移位矩阵，i表示循环移位值，i≥0，且i为整数，N≥K,N为整数，R＝K/N。
  4. 根据权利要求3所述的方法，其特征在于，所述母码长度为1944，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    10,6,8,11,4,3,12,7,2,5,9,1,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  5. 根据权利要求3所述的方法，其特征在于，所述母码长度为1296，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    8,12,7,3,11,10,4,6,2,5,9,1,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  6. 根据权利要求3所述的方法，其特征在于，所述母码长度为648，码率为1/2，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    8,6,12,11,2,3,10,7,4,1,5,9,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  7. 根据权利要求3所述的方法，其特征在于，所述母码长度为1944，码率为2/3， 按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    16,8,15,12,9,10,14,6,13,11,7,5,1,2,3,4,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  8. 根据权利要求3所述的方法，其特征在于，所述母码长度为1296，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  9. 根据权利要求3所述的方法，其特征在于，所述母码长度为648，码率为2/3，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    16,9,12,7,10,8,11,14,13,15,6,4,5,1,2,3,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  10. 根据权利要求3所述的方法，其特征在于，所述母码长度为1944，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    12,16,11,10,14,17,15,8,13,18,7,9,1,2,3,4,5,6,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  11. 根据权利要求3所述的方法，其特征在于，所述母码长度为1296，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    9,11,13,15,17,8,10,12,14,16,18,1,2,3,4,5,6,7,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  12. 根据权利要求3所述的方法，其特征在于，所述母码长度为648，码率为3/4，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    18,13,15,16,12,14,17,10,6,7,8,11,9,1,2,3,4,5,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  13. 根据权利要求3所述的方法，其特征在于，所述母码长度为1944，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    12,14,15,17,19,13,20,11,16,18,1,2,3,4,5,6,7,8,9,10,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  14. 根据权利要求3所述的方法，其特征在于，所述母码长度为1296，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    17,20,19,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  15. 根据权利要求3所述的方法，其特征在于，所述母码长度为648，码率为5/6，按照重复优先级从高到低的顺序，所述母矩阵中对应于信息比特的列的重复优先级的排序如下：
    13,1,2,3,4,5,6,7,8,9,10,11,12,14,15,16,17,18,19,20,
    其中，所述排序中的每个元素a表示所述母矩阵的第a列。
  16. 根据权利要求2-15中任一项所述的方法，其特征在于，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中重复优先级位于前L个位置的的信息比特进行重复，包括：
    若L<z，所述发送端从所述母矩阵中重复优先级最高的一列在所述校验矩阵中对应的z个信息比特中选择L个信息比特进行重复；
    若L＝m×z，所述发送端按照重复优先级从高到低的顺序，从所述母矩阵中选择重复优先级靠前的前m个列在所述校验矩阵中对应的mz个信息比特进行重复，m为正整数；
    若(m-1)×z<L<m×z，所述发送端按照重复优先级从高到低的排序，从所述母矩阵中选择重复优先级靠前的前(m-1)列在所述校验矩阵中对应的(m-1)×z个信息比特，以及第m列在所述校验矩阵中对应的z个信息比特中的p个信息比特进行重复，其中，L＝(m-1)×z+p，p≥1且p为整数，m>1，且m为整数。
  17. 根据权利要求2-16中任一项所述的方法，其特征在于，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送之前，所述方法还包括：
    所述发送端发送所述第一LDPC码字；
    以及，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送，包括：
    在所述第一LDPC码字未被接收端成功译码的情况下，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送；
    以及，所述方法还包括：
    在所述第一LDPC码字包含的全部信息比特都被重复发送，且接收端仍未成功译码信息比特的情况下，所述方法还包括：
    所述发送端按照校验比特的打孔优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数。
  18. 根据权利要求2-16中任一项所述的方法，其特征在于，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送之前，所述方法还包括：
    所述发送端发送所述第一LDPC码字；
    在所述第一LDPC码字未被接收端成功译码的情况下，所述发送端按照校验比特的优先级的排序，发送所述第一LDPC码字中被打孔的校验比特，其中，打孔优先级越低的校验比特优先被发送，所述打孔优先级用于指示(N-K)个校验比特在速率匹配中被打孔的优先级，N为LDPC的母码长度，N≥K,N为整数；
    以及，所述发送端根据需要重复的比特个数L，以及所述K个信息比特的重复优先级的排序，按照重复优先级从高到低的顺序，对所述第一LDPC码字中的第一信息比特集合包含的L个信息比特进行重复发送，包括：
    在所述第一LDPC码字的所有被打孔的校验比特全部被发送，且所述接收端仍未成功译码的情况下，所述发送端按照所述K个信息比特的重复优先级，发送所述第一LDPC码字的信息比特。
  19. 一种通信装置，其特征在于，包括用于实现如权利要求1-18中任一项所述的方法的功能的单元。
  20. 一种通信装置，其特征在于，包括：包括处理器和接口电路，所述接口电路用于接收计算机代码或指令，并传输至所述处理器，所述处理器运行所述计算机代码或指令，如权利要求1-18中任一项所述的方法被实现。
  21. 一种通信装置，其特征在于，包括至少一个处理器，所述至少一个处理器与至少一个存储器耦合，所述至少一个处理器用于执行所述至少一个存储器中存储的计算机程序或指令，以使得所述通信装置执行如权利要求1-18中任一项所述的方法。
  22. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，如权利要求1-18中任一项所述的方法被实现。
  23. 一种通信设备，其特征在于，包括如权利要求19中所述的通信装置。
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