WO2023050378A1 - 发光基板、背光模组及显示装置 - Google Patents

发光基板、背光模组及显示装置 Download PDF

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Publication number
WO2023050378A1
WO2023050378A1 PCT/CN2021/122358 CN2021122358W WO2023050378A1 WO 2023050378 A1 WO2023050378 A1 WO 2023050378A1 CN 2021122358 W CN2021122358 W CN 2021122358W WO 2023050378 A1 WO2023050378 A1 WO 2023050378A1
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WO
WIPO (PCT)
Prior art keywords
light
test
electrically connected
sub
test pad
Prior art date
Application number
PCT/CN2021/122358
Other languages
English (en)
French (fr)
Inventor
雷杰
王杰
许邹明
田�健
刘纯建
吴信涛
张建英
金枝
李永飞
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/122358 priority Critical patent/WO2023050378A1/zh
Priority to CN202180002819.XA priority patent/CN116210048A/zh
Priority to US17/795,414 priority patent/US20240186304A1/en
Publication of WO2023050378A1 publication Critical patent/WO2023050378A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light emitting substrate, a backlight module and a display device.
  • Micro Light-Emitting Diode Micro LED for short
  • Mini LED The sub-millimeter light-emitting diode (Mini Light-Emitting Diode, referred to as Mini LED) display device is considered to be a transitional product of the Micro LED display device. Long and other characteristics have received extensive attention and research.
  • a light emitting substrate in one aspect, includes a light-emitting area, and a test area located on at least one side of the light-emitting area.
  • the light emitting substrate includes a plurality of light emitting device groups, a plurality of driving circuits, a power supply line, a first test pad, a second test pad and a first test device group.
  • a plurality of light emitting device groups and a plurality of driving circuits are arranged in the light emitting area, and each driving circuit is electrically connected with at least one light emitting device group.
  • the plurality of driving circuits includes a selected driving circuit, the selected driving circuit includes at least one output terminal of a first type and at least one output terminal of a second type, the output terminal of the first type is electrically connected to the group of light emitting devices .
  • the power line is electrically connected to the plurality of light emitting device groups.
  • a first test pad and a second test pad are arranged in the test area, the first test pad is electrically connected to the second-type output end of the selected drive circuit, and the second test pad is connected to the selected drive circuit. Electrical connection of the power cord described above.
  • a first test device group is electrically connected to the first test pad and the second test pad.
  • the plurality of light emitting device groups and the plurality of driving circuits are arranged in multiple rows, and each row of light emitting device groups and each row of driving circuits are arranged along the first direction.
  • the light-emitting substrate further includes a binding area, and the binding area and the test area are respectively located on opposite sides of the light-emitting area along the second direction.
  • the multi-row light emitting device groups are respectively the 1st row to the Mth row of light emitting device groups
  • the multi-row driving circuits are respectively the 1st row to the Nth row driving circuits
  • M and N are integers greater than or equal to 2.
  • the light-emitting device group in the first row is electrically connected to the driving circuit in the first row, and the driving circuit in the first row includes the selected driving circuit.
  • the selected driving circuit includes two output terminals of the first type and two output terminals of the second type, and the two output terminals of the first type are respectively adjacent to the light-emitting device groups in the first row.
  • the two light-emitting device groups are electrically connected, and any one of the two second-type output terminals is electrically connected to the first test pad.
  • the light-emitting device groups in the second row to the Mth row include a plurality of device units, and each device unit includes two adjacent rows of light-emitting device groups, and the device units are connected to the driving circuits in the second row to the Nth row A row of driving circuits in the electrical connection.
  • the drive circuit includes four output terminals, which are respectively electrically connected to the four light emitting device groups in the device unit.
  • the power supply line includes a first sub-power supply line and a plurality of second sub-power supply lines
  • the first sub-power supply line extends along the first direction, and is arranged on the side of the light-emitting area close to the test area .
  • a plurality of second sub-power lines extend along the second direction and are electrically connected to the first sub-power lines.
  • the light-emitting substrate further includes a binding area, the test area and the binding area are respectively located on opposite sides of the light-emitting area along the second direction, and the first sub-power line is connected to the plurality of first sub-power lines. One end of the two sub-power lines close to the test area is electrically connected. The second test pad is electrically connected to the first sub power line.
  • the light-emitting substrate further includes a first connecting wire and a second connecting wire, one end of the first connecting wire is electrically connected to the first test pad, and the other end is electrically connected to the selected driving circuit.
  • One end of the second connection line is electrically connected to the second test pad, and the other end is electrically connected to the first sub-power line.
  • the light-emitting substrate includes a substrate, and a first conductive layer and a second conductive layer sequentially stacked on the substrate.
  • the first conductive layer includes a first sub-ground line extending along a first direction, the first sub-ground line is located on a side of the light-emitting area close to the test area, the first sub-power line and the The first test pad is located on the second conductive layer.
  • the selected driving circuit is located on a side of the first sub-ground line and the first sub-power line away from the first test pad.
  • the first connection line includes at least one first connection section located on the first conductive layer, and at least one second connection section located on the second conductive layer, the first connection section is on the substrate.
  • the orthographic projection of the first sub-power line at least partially overlaps the orthographic projection of the first sub-power line on the substrate, and the orthographic projection of the second connection section on the substrate overlaps with the first sub-ground line on the substrate.
  • the orthographic projections on the substrate are at least partially overlapping.
  • the connection section closest to the first test pad is the second connection section
  • the first test pad is the closest to the second connection section.
  • the connecting segments are electrically connected.
  • the second connecting wire extends approximately along the second direction, and the material of the second connecting wire and the first sub-power wire are the same and are arranged in the same layer.
  • the first set of test devices includes test light emitting devices and/or resistors.
  • the first set of test devices includes test light emitting devices and resistors.
  • the light-emitting substrate further includes a third test pad, one end of the test light-emitting device is electrically connected to the first test pad, and the other end is electrically connected to the third test pad.
  • One end of the resistor is electrically connected to the second test pad, and the other end is electrically connected to the third test pad.
  • the light emitting device group includes a plurality of light emitting devices and a plurality of wirings, and the plurality of light emitting devices are arranged in series through the plurality of wirings.
  • the light emitting substrate also includes fourth test pads, fifth test pads and a second test device group.
  • the fourth test pad and the fifth test pad are arranged on the test area.
  • the fourth test pad and the fifth test pad are respectively electrically connected to the same wire.
  • a part of the trace between the position where the fourth test pad is electrically connected to the trace and the position where the fifth test pad is electrically connected to the trace is disconnected.
  • a second test device group is electrically connected to the fourth test pad and the fifth test pad.
  • the light-emitting substrate further includes a binding area, and the test area and the binding area are respectively located on opposite sides of the light-emitting area along the second direction.
  • the plurality of light emitting device groups are arranged in multiple rows, and each row of light emitting device groups is arranged along the first direction. Along the second direction and from the test area to the binding area, the multiple rows of light-emitting device groups are respectively the first row to the Mth row of light-emitting device groups. Both the fourth test pad and the fifth test pad are electrically connected to any wiring in the first row of light emitting device groups.
  • the light-emitting substrate further includes two third connecting wires, one end of one third connecting wire is electrically connected to the fourth test pad, and the other end is electrically connected to the wiring.
  • One end of another third connection line is electrically connected to the fifth test pad, and the other end is electrically connected to the trace.
  • the light-emitting substrate includes a first conductive layer and a second conductive layer stacked in sequence, the first conductive layer includes a first sub-ground line extending along the first direction, and the second conductive layer It includes a first sub-power line extending along a first direction, and the fourth test pad and the fifth test pad are located on the second conductive layer.
  • Both the fourth test pad and the fifth test pad are located on a side of the first sub-ground line and the first sub-power line away from the trace.
  • the third connection line includes at least one third connection section located on the first conductive layer, and at least one fourth connection section located on the second conductive layer, and the third connection section is on the substrate.
  • the orthographic projection of the first sub-power line at least partially overlaps the orthographic projection of the first sub-power line on the substrate, and the orthographic projection of the fourth connecting section on the substrate overlaps with the first sub-ground line on the substrate.
  • the orthographic projections on the substrate are at least partially overlapping.
  • connection section closest to the fourth test pad is the fourth connection section
  • fourth test pad is the closest to the fourth connection section.
  • the fourth connecting segment is electrically connected.
  • connection section closest to the fifth test pad is the fourth connection section
  • the fifth test pad is the closest to the fifth test pad.
  • the fourth connecting segment is electrically connected.
  • the light-emitting substrate further includes at least one input signal line, a ground line, at least one sixth test pad, and at least one test point.
  • At least one input signal line extends along the second direction and is electrically connected to the plurality of driving circuits.
  • the ground line is electrically connected to the plurality of drive circuits.
  • At least one sixth test pad is arranged in the test area, and each sixth test pad is electrically connected to an input signal line.
  • At least one test point is set in the light-emitting area and electrically connected with the ground wire.
  • the light-emitting substrate further includes a binding area, and the binding area and the test area are respectively located on opposite sides of the light-emitting area along the second direction.
  • the light-emitting substrate further includes a signal connection line, one end is electrically connected to the sixth test pad, and the other end is electrically connected to an end of the input signal line close to the test area.
  • the light-emitting substrate includes a first conductive layer and a second conductive layer stacked in sequence, the first conductive layer includes a first sub-ground line extending along the first direction, and the second conductive layer It includes a first sub-power line extending along a first direction, and the sixth test pad is located on the second conductive layer.
  • the selected driving circuit is located on a side of the first sub-ground line and the first sub-power line away from the sixth test pad.
  • the signal connection line includes at least one fifth connection section located on the first conductive layer, and at least one sixth connection section located on the second conductive layer, the fifth connection section on the substrate.
  • the orthographic projection at least partially overlaps the orthographic projection of the first sub-power line on the substrate, and the orthographic projection of the sixth connection section on the substrate is at least partially overlapped with that of the first sub-grounding line on the substrate.
  • the orthographic projections on the base overlap at least partially.
  • the connection section closest to the sixth test pad is the sixth connection section
  • the sixth test pad is the closest to the sixth connection section.
  • the connecting segments are electrically connected.
  • the at least one input signal line includes at least one of a power supply voltage signal line, a clock signal line, and a data signal line.
  • the light-emitting substrate further includes a plurality of cascaded signal lines and a plurality of seventh test pads, two adjacent driving circuits along the first direction and/or two adjacent driving circuits along the second direction
  • the drive circuits are electrically connected through cascaded signal lines.
  • a plurality of seventh test pads are arranged in the test area, and each seventh test pad is electrically connected with a cascaded signal line.
  • the grounding line includes a first sub-grounding line and a plurality of second sub-grounding lines, the first sub-grounding line extends along the first direction, and is arranged on a side of the light-emitting area close to the test area .
  • a plurality of second sub-ground lines extend along the second direction and are electrically connected to the first sub-ground lines.
  • the light-emitting substrate further includes a binding area, the test area and the binding area are respectively located on opposite sides of the light-emitting area along the second direction, and the first sub-ground line is connected to the plurality of first sub-ground lines. One end of the two sub-ground wires close to the test area is electrically connected. The multiple test points are electrically connected to the first sub-ground wire.
  • the light-emitting substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer which are sequentially stacked.
  • the first sub-ground wire is located on the first conductive layer
  • the test point is located on the second conductive layer
  • the test point is connected to the first sub-ground through the via hole in the first insulating layer.
  • the ground wire is electrically connected, and the second insulating layer is opened with a first test hole exposing the test point.
  • the test point is a second test hole penetrating through the first insulating layer and the second insulating layer, and the second test hole exposes the first sub-ground wire.
  • the ground line further includes a plurality of connection patterns and a plurality of third sub-ground lines, each connection pattern is electrically connected to two adjacent second sub-ground lines, and is electrically connected to the driving circuit.
  • Multiple third sub-ground wires extend along the second direction, each third sub-ground wire is electrically connected to at least one connection pattern, and one end of the third sub-ground wire close to the test area is connected to the first sub-ground wire Wire connection.
  • the light-emitting substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer which are sequentially stacked.
  • the power line is located on the second conductive layer, and the second insulating layer is opened with a third test hole exposing the power line.
  • the second conductive layer further includes a plurality of second sub-ground wires, and the second insulating layer is opened with a fourth test hole exposing the second sub-ground wires.
  • the light-emitting substrate includes a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer which are sequentially stacked.
  • the second conductive layer includes a plurality of output signal lines and a plurality of conductive test patterns, and each output signal line is electrically connected to the light emitting device group and a corresponding driving circuit, and is electrically connected to a conductive test pattern.
  • the second insulating layer is provided with a fifth test hole exposing the conductive test pattern.
  • a backlight module in another aspect, includes the light-emitting substrate described in any one of the above-mentioned embodiments.
  • a display device in yet another aspect, includes a display panel, and the backlight module as described in the above embodiments, the display panel is disposed on the light emitting side of the backlight module.
  • FIG. 1 is a structural diagram of a light-emitting substrate according to some embodiments
  • FIG. 2A and 2B are partial enlarged views of the light-emitting substrate in FIG. 1 at A;
  • FIG. 2C is a partial cross-sectional view of the light-emitting substrate in FIG. 2B along the section line A-A';
  • FIG. 2D is a partial enlarged view of the light-emitting substrate in FIG. 2B at D;
  • FIG. 2E is a partial enlarged view of the light-emitting substrate in FIG. 2B at E;
  • FIG. 3 is a structural diagram of a driving circuit according to some embodiments.
  • FIG. 4A and 4B are partial enlarged views of the light-emitting substrate in FIG. 1 at B;
  • FIG. 4C is a partial cross-sectional view of the light-emitting substrate in FIG. 4B along the section line B-B';
  • 5A and 5B are partial enlarged views of the light-emitting substrate in FIG. 1 at C;
  • 5C and 5D are partial cross-sectional views of the light-emitting substrate in FIG. 5B along the section line C-C';
  • FIG. 6 is a structural diagram of a backlight module according to some embodiments.
  • FIG. 7A is a block diagram of a display device according to some embodiments.
  • FIG. 7B is a partial cross-sectional view of the display device in FIG. 7A along the section line D-D'.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used.
  • electrically connected may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, A Combination with B, combination of A and C, combination of B and C, and combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the light emitting substrate 100 includes a light emitting area A1 and a test area A2 located on at least one side of the light emitting area A1.
  • the light-emitting substrate 100 further includes a binding area A3 , and the binding area A3 and the test area A2 are respectively located on opposite sides of the light-emitting area A1 along the second direction Y.
  • the light-emitting substrate 100 includes a plurality of light-emitting device groups 1 and a plurality of driving circuits (such as micro integrated circuits, Micro Integrated Circuit) 2 arranged in the light-emitting area A1, and each driving circuit 2 is connected to at least One light emitting device group 1 is electrically connected to drive the light emitting device group 1 to emit light.
  • driving circuits such as micro integrated circuits, Micro Integrated Circuit
  • each driving circuit 2 is electrically connected to two light emitting device groups 1 . In other examples, each driving circuit 2 is electrically connected to four light emitting device groups 1 . The quantity of the light emitting device groups 1 electrically connected to each driving circuit 2 will be explained below.
  • a plurality of driving circuits 2 include a selected driving circuit 20, and the selected driving circuit 20 includes at least one first type output terminal 21 and at least one second type output terminal 22, the first type output terminal 21 is electrically connected to the light emitting device group 1 .
  • the first type of output terminals 21 of the selected drive circuit 20 are electrically connected to the light emitting device group 1, the number of the first type of output terminals 21 can meet the number of the electrically connected light emitting device groups 1, and the second type of output Terminal 22 does not have to be electrically connected to light emitting device group 1 .
  • the second-type output terminal 22 of the selected driving circuit 20 can also be electrically connected to the light emitting device group 1 .
  • the light-emitting substrate 100 also includes a power line 3 electrically connected to a plurality of light-emitting device groups 1 to transmit power voltage signals to the light-emitting device groups 1 to provide electric energy for the light-emitting device groups 1 to emit light.
  • the light-emitting substrate 100 further includes a first test pad P1, a second test pad P2, and a first test device group T1 arranged in the test area A2.
  • the first test pad P1 and the selected The second type of output terminal 22 of the driving circuit 20 is electrically connected
  • the second test pad P2 is electrically connected to the power line 3
  • the first test device group T1 is electrically connected to the first test pad P1 and the second test pad P2.
  • the plurality of driving circuits 2 include a selected driving circuit 20, and the selected driving circuit 20 includes at least one first-type output terminal 21 and at least one second-type output terminal 22, the first The class output 21 is electrically connected to the luminous means group 1 .
  • the first test pad P1 and the second test pad P2 are arranged in the test area A2 of the light-emitting substrate 100, and the first test pad P1 is electrically connected to the second-type output terminal 22 of the selected drive circuit 20, the second The second test pad P2 is electrically connected to the power line 3, and the first test device group T1 is connected between the first test pad P1 and the second test pad P2, forming the selected drive circuit 20, the first test pad P1 , the series circuit of the first test device group T1, the second test pad P2 and the power line 3 transmits electrical signals to the circuit on the light-emitting substrate 100 through the pins located in the binding area, so that the selected driving circuit 20 and its connection
  • the light-emitting device group 1 receives an electrical signal through the corresponding signal line.
  • the first test pad P1 and the second test pad P2 are tested with a test fixture, and the first test device group can be detected The current value in T1, and thus the current value in power line 3 is obtained.
  • the voltage drop (IR-Drop ), and then the designed resistance value of the power line 3 can be adjusted according to the voltage drop, or the input voltage of the power line 3 can be compensated to ensure normal light emission of the light emitting device.
  • the first test device group T1 may not be connected between the first test pad P1 and the second test pad P2, and the test fixtures are directly used to test the first test pad P1 and the second test pad P1.
  • Pad P2 is subjected to a needle stick test, forming a series circuit of the selected driving circuit 20, the first test pad P1, the test fixture, the second test pad P2 and the power line 3, and the test fixture is connected to the series circuit as a test device , use the test fixture to detect the current value passing through itself, so as to obtain the current value in the power line 3 .
  • the first test device group T1 includes a test light emitting device T11 and/or a resistor T12 .
  • the first test device group T1 includes a test light emitting device T11, one end of the test light emitting device T11 is electrically connected to the first test pad P1, and the other end is electrically connected to the second test pad P2.
  • the first test device group T1 includes a resistor T12, one end of the resistor T12 is electrically connected to the first test pad P1, and the other end is electrically connected to the second test pad P2.
  • the first test device group T1 includes a test light emitting device T11 and a resistor T12.
  • the light emitting substrate 100 further includes a third test pad P3, and one end of the test light emitting device T11 is connected to the resistor T12.
  • the first test pad P1 is electrically connected, and the other end is electrically connected to the third test pad P3.
  • One end of the resistor T12 is electrically connected to the second test pad P2, and the other end is electrically connected to the third test pad P3, so as to realize the series arrangement of the test light emitting device T11 and the resistor T12.
  • a plurality of light emitting device groups 1 are arranged in an array along the first direction X and a second direction Y
  • a plurality of driving circuits 2 are arranged in an array along the first direction X and the second direction Y .
  • the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.
  • the first direction X may be the row direction of the light emitting device group 1 and/or the driving circuit 2
  • the second direction Y may be the column direction of the light emitting device group 1 and/or the driving circuit 2 .
  • the multi-row light-emitting device groups 1 are respectively the first row to the M-th row of light-emitting device groups
  • the multi-row driving circuits 2 are respectively are driving circuits for the first row to the Nth row
  • M and N are integers greater than or equal to 2.
  • the light-emitting device group in the first row is electrically connected to the driving circuit in the first row
  • the driving circuit in the first row includes a selected driving circuit 20 , that is, the selected driving circuit 20 is located in the first row driving circuit of the multi-row driving circuit 2 .
  • a plurality of signal lines in the light-emitting substrate 100 (for example, a power line 3, a ground line 4, and a plurality of input signal lines 5 electrically connected to the drive circuit 2, etc.)
  • Area A3 makes the arrangement of the signal lines on the side of the light emitting area A1 close to the bonding area A3 more complicated.
  • connection line L needs to cross the binding area A3 to realize the electrical connection between the first test pad P1 and the selected driving circuit 20, or across the light-emitting area A3.
  • the area A1 realizes the electrical connection between the first test pad P1 and the selected driving circuit 20 , which brings great difficulties to the preparation of the connection line L connecting the first test pad P1 and the selected driving circuit 20 .
  • the selected driving circuit 20 in the first row driving circuit of the multi-row driving circuit 2, that is, disposing the selected driving circuit 20 on the side of the light emitting region A1 away from the binding region A3 , that is, the selected driving circuit 20 is disposed on the side of the light-emitting area A1 close to the test area A2.
  • the number of signal lines on the side of the light-emitting area A1 close to the test area A2 is less and the arrangement is simpler.
  • the selected driving circuit 20 It is arranged on the side of the light-emitting area A1 close to the test area A2, and the number of signal lines that the connecting line L needs to cross is relatively small, which reduces the difficulty of preparing the connecting line L.
  • the selected drive circuit 20 is disposed on the side of the light emitting area A1 close to the test area A2, and the first test pad P1 is disposed in the test area A2, the distance between the first test pad P1 and the selected drive circuit 20 can be shortened.
  • the length of the connection line L is shortened.
  • the selected driving circuit 20 includes two first-type output terminals 21 and two second-type output terminals 22, and the two first-type output terminals 21 are connected to the second-type output terminals respectively. Two adjacent light emitting device groups 1 in one row of light emitting device groups are electrically connected. Either one of the two second-type output terminals 22 is electrically connected to the first test pad P1.
  • the selected driving circuit 20 has four output terminals (CH1, CH2, CH3 and CH4), and the four output terminals include two first-type output terminals 21 and two The second type of output terminal 22 .
  • a selected drive circuit 20 is arranged between two adjacent light-emitting device groups 1, and the two first-type output terminals 21 of the selected drive circuit 20 are connected to two adjacent light-emitting device groups 1.
  • the device group 1 is electrically connected.
  • the light-emitting device groups in the second row to the M-th row include a plurality of device units 10, and each device unit 10 includes two adjacent rows of light-emitting device groups 1, and the device units 10 and The one-row drive circuits 2 among the second row to the N-th row drive circuits are electrically connected. That is, in the second row to the Mth row of light emitting device groups, two adjacent rows of light emitting device groups 1 are electrically connected to one row of driving circuits 2 .
  • the driving circuit 2 includes four output terminals (CH1, CH2, CH3 and CH4), and the four output terminals are electrically connected to the four light emitting device groups 1 in the device unit 10 respectively.
  • each device unit 10 includes a plurality of sub-device units 11, and each sub-device unit 11 includes four light-emitting device groups 1 in two rows of light-emitting device groups 1 and two columns of light-emitting device groups 1 , the four output terminals of each driving circuit 2 are respectively electrically connected to the four light emitting device groups 1 in each sub-device unit 11 .
  • the power line 3 includes a first sub-power line 31 and a plurality of second sub-power lines 32, the first sub-power line 31 extends along the first direction X, and the first sub-power line
  • the power line 31 is disposed on a side of the light-emitting area A1 close to the testing area A2.
  • a plurality of second sub-power lines 32 extend along the second direction Y, and the plurality of second sub-power lines 32 are electrically connected to the first sub-power lines 31, and the plurality of second sub-power lines 32 are connected to each other through the first sub-power lines 31.
  • the connection is equivalent to forming a plurality of parallel channels, which can reduce the overall resistance of the power line 3, thereby improving the stability of the power signal transmitted by the power line 3.
  • the power line 3 may include a plurality of first sub-power lines 31 extending along the first direction X, and the plurality of first sub-power lines 31 and the plurality of The second sub-power lines 32 form a grid structure, which can further reduce the overall resistance of the power line 3 and improve the stability of power signal transmission by the power line 3 .
  • the first sub-power line 31 is electrically connected to one end of the plurality of second sub-power lines 32 close to the test area A2
  • the second test pad P2 is electrically connected to the first sub-power line 31 .
  • the setting position of the first sub-power line 31 is close to the test area A2, and the second test pad P2 is electrically connected to the first sub-power line 31 through the connecting line L, so that the wiring length of the connecting line L can be shortened.
  • the number of signal lines crossed by the connection line L can be reduced, and the difficulty of preparing the connection line L can be reduced.
  • the light-emitting substrate 100 further includes a first connection line L1 and a second connection line L2, one end of the first connection line L1 is electrically connected to the first test pad P1, and the other end is electrically connected to the optional pad P1.
  • the selected driving circuit 20 is electrically connected to realize the electrical connection between the first test pad P1 and the selected driving circuit 20 .
  • connection line L2 One end of the second connection line L2 is electrically connected to the second test pad P2 , and the other end is electrically connected to the first sub-power line 31 , so as to realize the electrical connection between the second test pad P2 and the first sub-power line 31 .
  • first connection line L1 and the second connection line L2 will be described below in conjunction with the film layer structure of the light emitting substrate 100 .
  • the light-emitting substrate 100 includes a substrate 101 , and a first conductive layer 102 and a second conductive layer 104 sequentially stacked on the substrate 101 .
  • the first conductive layer 102 includes a first sub-ground wire 41 extending along the first direction X, and the first sub-ground wire 41 is located on a side of the light-emitting area A1 close to the test area A2.
  • the first sub-power line 31 and the first test pad P1 are located on the second conductive layer 104 .
  • the light-emitting substrate 100 further includes a first insulating layer 103 located between the first conductive layer 102 and the second conductive layer 104 to achieve insulation between the first conductive layer 102 and the second conductive layer 104 .
  • the light-emitting substrate 100 further includes a second insulating layer 105 disposed on a side of the second conductive layer 104 away from the substrate 101 to protect the second conductive layer 104 .
  • the selected driving circuit 20 is located on a side of the first sub-ground line 41 and the first sub-power line 31 away from the first test pad P1 . Therefore, the first connection line L1 needs to cross the first sub-ground line 41 and the first sub-power line 31 to be electrically connected to the first test pad P1 and the selected driving circuit 20 .
  • the first connection line L1 includes at least one first connection segment L11 located on the first conductive layer 102 and at least one second connection segment L12 located on the second conductive layer 104 .
  • the orthographic projection of the first connecting segment L11 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-power line 31 on the substrate 101 , so that the first connecting segment L11 crosses the first sub-power line 31 .
  • the orthographic projection of the second connection segment L12 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-ground line 41 on the substrate 101 , so that the second connection segment L12 crosses the first sub-ground line 41 .
  • connection section closest to the first test pad P1 is the second connection section L12
  • first test pad P1 is the closest to the first test pad P1.
  • the second connection section L12 is electrically connected.
  • both the first test pad P1 and the second connection segment L12 are located on the second conductive layer 104 , therefore, the first test pad P1 and the second connection segment L12 can be in direct electrical contact.
  • the first connection line L1 straddles the first sub-power supply line 31 and the first sub-ground line 41 .
  • the first connection line L1 includes two first connection segments L11 (first connection segment L11a and first connection segment L11b) located on the first conductive layer 102, and a first connection segment L11 located on the first conductive layer 102.
  • Three second connection segments L12 of the second conductive layer 104 (second connection segment L12a, second connection segment L12b, and second connection segment L12c).
  • the second connecting segment L12a, the first connecting segment L11a, the second connecting segment L12b, the first connecting segment L11b and the second connecting segment L12c are electrically connected in sequence, and two adjacent connecting segments pass through the first insulating layer 103 hole electrical connection.
  • an end of the second connection section L12a away from the first connection section L11a is electrically connected to the first test pad P1
  • an end of the second connection section L12c away from the first connection section L11b is electrically connected to the selected driving circuit 20 .
  • the first sub-ground wire 41 is provided with a first opening 41A, the first connection section L11a is located in the first opening 41A, and the first connection section L11a is connected to the first sub-ground wire 41
  • the insulation between the first connection section L11a and the first sub-ground line 41 can be realized without contact between them, and the first connection section L11a can be straddled over the first sub-power line 31 .
  • the second connection line L2 extends roughly along the second direction Y, and the second connection line L2 and the first sub-power line 31 are made of the same material and arranged on the same layer, that is, the second connection Both the line L2 and the first sub-power line 31 are located on the second conductive layer 104 . Therefore, the second connection line L2 may be in direct electrical contact with the first sub power supply line 31 .
  • the second test pad P2 is also located on the second conductive layer 104 , therefore, the second connection line L2 can also be in direct electrical contact with the second test pad P2 .
  • Some embodiments of the present disclosure also provide a solution for detecting current in each light emitting device group 1 , which will be described in the following embodiments.
  • the light emitting device group 1 includes a plurality of light emitting devices 1a and a plurality of wirings 1b, and the plurality of light emitting devices 1a are arranged in series through the plurality of wirings 1b.
  • the light-emitting device 1a is an inorganic light-emitting diode with a size of 50-500um, such as a Mini LED.
  • the light-emitting substrate 100 further includes a fourth test pad P4 and a fifth test pad P5 disposed in the test area A2 , and a second test device group T2 .
  • the fourth test pad P4 and the fifth test pad P5 are respectively electrically connected to the same wire 1b.
  • the second test device group T2 is electrically connected to the fourth test pad P4 and the fifth test pad P5.
  • the trace 1b connected to the fourth test pad P4 and the fifth test pad P5 (the trace 1b between the light emitting device LED-2 and the light emitting device LED-3) Including the first sub-wire 11b and the second sub-wire 12b, the first sub-wire 11b and the second sub-wire 12b are disconnected, the fourth test pad P4 is electrically connected to the first sub-wire 11b, the fifth The test pad P5 is electrically connected to the second sub-wire 12b to meet the test requirements.
  • the above-mentioned wiring 1b also includes a sub-connection wiring 13b. 12b are located on the second conductive layer 104, and the orthographic projections of the first sub-wiring 11b and the second sub-wiring 12b on the substrate 101 at least partially overlap with the orthographic projection of the sub-connecting wiring 13b on the substrate 101 .
  • the laser can be used to irradiate the overlapping parts of the first sub-wiring 11b and the second sub-wiring 12b and the sub-connecting wiring 13b, so that the first sub-wiring 11b and the second sub-wiring 12b are in contact with the sub-wiring
  • the connecting wires 13b are electrically connected to connect the disconnected wires 1b, so as to ensure the normal use of the light-emitting substrate 100 .
  • the fourth test pad P4 and the fifth test pad P5 are provided in the test area A2, and the fourth test pad P4 and the fifth test pad P5 are connected to the same wiring line respectively.
  • 1b is electrically connected by breaking the wiring 1b between the two and the connection position of the wiring 1b, and connecting the second test device group T2 between the fourth test pad P4 and the fifth test pad P5 to form A series circuit of the second test device group T2 and a plurality of light emitting devices 1a is established.
  • the electrical signal is transmitted to the circuit on the light-emitting substrate 100 through the pins located in the binding area, so that the selected driving circuit 20 and the light-emitting device group 1 connected to it receive the electrical signal through the corresponding signal line.
  • the jig performs a needle stick test on the fourth test pad P4 and the fifth test pad P5 to detect the current value in the second test device group T2, thereby obtaining the current value in the series circuit of the plurality of light emitting devices 1a.
  • each light-emitting device group 1 is electrically connected to the power supply line 3 and the driving circuit 2.
  • the series circuit of multiple light emitting devices 1a is also arranged in series with the driving circuit 2 and the grounding line 4, and the current value in the series circuit of multiple light emitting devices 1a flows into the grounding line 4 with the driving circuit 2 current values are equal.
  • the voltage drop between the end of the ground wire 4 close to the binding area A3 and the end far away from the binding area A3 can be calculated, and then according to the Adjust the designed resistance value of the grounding wire 4 to ensure that the current value in the series circuit of the plurality of light emitting devices 1a meets the product requirements, thereby ensuring the luminous effect of the plurality of light emitting devices 1a.
  • the second test device group T2 may not be connected between the fourth test pad P4 and the fifth test pad P5, and the test fixtures are directly used to test the fourth test pad P4 and the fifth test pad P5.
  • the pad P5 is subjected to the needle stick test, forming a series circuit of the test fixture and multiple light-emitting devices 1a.
  • the test fixture is connected to the series circuit as a test device, and the test fixture is used to detect the current value passing through itself, thereby obtaining a series circuit current value in .
  • the second test device group T2 includes a resistor T22 , one end of the resistor T22 is electrically connected to the fourth test pad P4 , and the other end is electrically connected to the fifth test pad P5 .
  • both the fourth test pad P4 and the fifth test pad P5 are electrically connected to any wire 1 b in the first row of light emitting device groups.
  • the first row of light-emitting device groups is disposed on the side of the light-emitting region A1 away from the binding region A3 , that is, it is disposed on the side of the light-emitting region A1 close to the test region A2 .
  • the number of signal lines on the side of the light-emitting area A1 close to the test area A2 is less and the arrangement is simpler.
  • the fourth test pad P4 and the fifth test pad The pads P5 are all electrically connected to any wiring 1b in the first row of light-emitting device groups, and the number of signal lines that need to be crossed by the connection line L between the fourth test pad P4 and the fifth test pad P5 and the wiring 1b less, which reduces the difficulty of preparing the connecting line L.
  • the fourth test pad P4 and the fifth test pad P5 are both arranged in the test region A2, and the fourth test pad P4 and the fifth test pad P4 are arranged in the test region A2.
  • the five test pads P5 are all electrically connected to any trace 1b in the light-emitting device group in the first row, which can shorten the trace length of the connection line L.
  • the light-emitting substrate 100 further includes two third connection lines L3, one end of one third connection line L3 is electrically connected to the fourth test pad P4, and the other end is electrically connected to the trace 1b. electrical connection, so as to realize the electrical connection between the fourth test pad P4 and the trace 1b.
  • One end of another third connection line L3 is electrically connected to the fifth test pad P5, and the other end is electrically connected to the trace 1b, so as to realize the electrical connection between the fifth test pad P5 and the trace 1b.
  • connection line L3 The specific structure of the third connection line L3 will be described below in conjunction with the film layer structure of the light emitting substrate 100 .
  • the fourth test pad P4 and the fifth test pad P5 are located on the second conductive layer 104 . Both the fourth test pad P4 and the fifth test pad P5 are located on the side of the first sub-ground line 41 and the first sub-power line 31 away from the trace 1b. Therefore, the third connection line L3 needs to cross the first sub-ground line 41 and the first sub-power line 31 .
  • the third connection line L3 includes at least one third connection segment L31 located on the first conductive layer 102 and at least one fourth connection segment L32 located on the second conductive layer 104 .
  • the orthographic projection of the third connection segment L31 on the substrate 101 at least partially overlaps the orthographic projection of the first sub power line 31 on the substrate 101 , so that the third connection segment L31 crosses the first sub power line 31 .
  • the orthographic projection of the fourth connection segment L32 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-ground line 41 on the substrate 101 , so that the fourth connection segment L32 crosses the first sub-ground line 41 .
  • the connection segment closest to the fourth test pad P4 is the fourth connection segment L32
  • the fourth test pad P4 is electrically connected to the nearest fourth connection segment L32.
  • both the fourth test pad P4 and the fourth connection segment L32 are located on the second conductive layer 104 , therefore, the fourth test pad P4 and the fourth connection segment L32 can be in direct electrical contact.
  • connection segment closest to the fifth test pad P5 is the fourth connection segment L32
  • the fifth test pad P5 is electrically connected to the closest fourth connection segment L32.
  • both the fifth test pad P5 and the fourth connection segment L32 are located on the second conductive layer 104 , therefore, the fifth test pad P5 and the fourth connection segment L32 can be in direct electrical contact.
  • the third connection line L3 can be realized to span the first sub-power supply line 31 and the first sub-ground line 41 .
  • the third connection line L3 includes a third connection segment L31 located on the first conductive layer 102, and two fourth connection segments L32 (the second segment) located on the second conductive layer 104.
  • the fourth connection segment L32 a , the third connection segment L31 and the fourth connection segment L32 b are electrically connected in sequence, and two adjacent connection segments are electrically connected through via holes in the first insulating layer 103 .
  • an end of the fourth connection section L32a away from the third connection section L31 is electrically connected to the fourth test pad P4, and an end of the fourth connection section L32b away from the third connection section L31 is electrically connected to the wire 1b.
  • some embodiments of the present disclosure also provide a solution for detecting the voltage of an input signal line electrically connected to the driving circuit 2 , which will be described in the following embodiments.
  • the light-emitting substrate 100 further includes at least one input signal line 5 extending along the second direction Y and electrically connected to a plurality of driving circuits 2 for providing input signals to the driving circuits 2 .
  • At least one input signal line 5 includes at least one of a power voltage signal line 51 , a clock signal line 52 and a data signal line 53 .
  • the drive circuit 2 includes a power supply voltage signal terminal Vcc, a clock signal terminal CLK, and a data signal terminal Dip
  • the power supply voltage signal line 51 is electrically connected to the power supply voltage signal terminal Vcc, and is configured to supply power to the power supply.
  • the voltage signal terminal Vcc transmits a power supply voltage signal
  • the clock signal line 52 is electrically connected to the clock signal terminal CLK, and is configured to transmit a clock signal to the clock signal terminal CLK
  • the data signal line 53 is electrically connected to the data signal terminal Dip, and is configured to transmit a clock signal to the data signal terminal CLK
  • the signal terminal Dip transmits data signals.
  • the light-emitting substrate 100 further includes a ground wire 4, which is electrically connected to a plurality of driving circuits 2, so as to ground the plurality of driving circuits 2.
  • the connection manner between the ground wire 4 and the driving circuit 2 will be described in detail below.
  • the driving circuit 2 further includes a ground terminal GND, and the ground wire 4 is electrically connected to the ground terminal GND and is configured to ground the driving circuit 2 .
  • the light-emitting substrate 100 further includes at least one sixth test pad P6 disposed in the test area A2, and at least one test point TP disposed in the light-emitting area A1, and each sixth test pad P6 is connected to a
  • the input signal line 5 is electrically connected, and each test point TP is electrically connected to the ground line 4 (that is, the voltage value of the test point TP is 0).
  • the light-emitting substrate 100 also includes a signal connection line L4, one end of the signal connection line L4 is electrically connected to the sixth test pad P6, and the other end is connected to the input signal line 5 close to the test area A2. One end is electrically connected.
  • At least one sixth test pad P6 is disposed in the test area A2, and each sixth test pad P6 is electrically connected to one input signal line 5 .
  • At least one test point TP is set in the light emitting area A1 , and each test point TP is electrically connected to the ground wire 4 .
  • electrical signals are transmitted to circuits on the light-emitting substrate 100 through the pins located in the binding area, so that the selected driving circuit 20 and the light-emitting device group 1 connected thereto receive electrical signals through corresponding signal lines.
  • the sixth test pad P6 and the test point TP are used to carry out the needle stick test with the test fixture, and the voltage value of the input signal line 5 electrically connected to the sixth test pad P6 can be detected (the part of the input signal line 5 that is far away from the binding area The voltage value at one end of A3).
  • the distance of the input signal line 5 close to the binding area A3 can be calculated.
  • the voltage drop between one end and the end far away from the bonding area A3 can then adjust the design resistance value of the input signal line 5 according to the voltage drop, so as to ensure that the voltage value of the input signal provided by the input signal line 5 to the drive circuit 2 can meet the requirements of the drive circuit. 2 works fine.
  • the number of signal lines on the side of the light-emitting area A1 close to the test area A2 is less and the arrangement is simpler.
  • the signal connection line L4 and the input signal line 5 One end close to the test area A2 is electrically connected, and the number of signal lines that the signal connection line L4 needs to cross is less, which reduces the difficulty of preparing the signal connection line L4.
  • the sixth test pad P6 is disposed in the test area A2, electrically connecting the signal connection line L4 to an end of the input signal line 5 close to the test area A2 can shorten the routing length of the signal connection line L4.
  • the specific structure of the signal connection line L4 will be described below in conjunction with the film layer structure of the light emitting substrate 100 .
  • the sixth test pad P6 is located on the second conductive layer 104 .
  • the selected driving circuit 20 is located on a side of the first sub-ground line 41 and the first sub-power line 31 away from the sixth test pad P6. Therefore, the signal connection line L4 needs to cross the first sub-ground line 41 and the first sub-power line 31 .
  • the signal connection line L4 includes at least one fifth connection segment L41 located on the first conductive layer 102 and at least one sixth connection segment L42 located on the second conductive layer 104 .
  • the orthographic projection of the fifth connection segment L41 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-power line 31 on the substrate 101 , so that the fifth connection segment L41 crosses the first sub-power line 31 .
  • the orthographic projection of the sixth connection segment L42 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-ground line 41 on the substrate 101 , so that the sixth connection segment L42 crosses the first sub-ground line 41 .
  • connection section closest to the sixth test pad P6 is the sixth connection section L42
  • the sixth test pad P6 is the closest to the sixth connection section L42.
  • the sixth connecting segment L42 is electrically connected.
  • both the sixth test pad P6 and the sixth connection segment L42 are located on the second conductive layer 104 , therefore, the sixth test pad P6 and the sixth connection segment L42 can be in direct electrical contact.
  • the signal connection line L4 can be realized to straddle the first sub-power supply line 31 and the first sub-ground line 41 .
  • the signal connection line L4 electrically connected to the power supply voltage signal line 51 includes two fifth connection sections L41 (fifth connection section L41a) located on the first conductive layer 102 and the fifth connecting segment L41b), and three sixth connecting segments L42 (the sixth connecting segment L42a, the sixth connecting segment L42b and the sixth connecting segment L42c) located on the second conductive layer 104 .
  • the sixth connection section L42a, the fifth connection section L41a, the sixth connection section L42b, the fifth connection section L41b and the sixth connection section L42c are electrically connected in sequence, and two adjacent connection sections pass through the gap in the first insulating layer 103. hole electrical connection.
  • the end of the sixth connection section L42a away from the fifth connection section L41a is electrically connected to the sixth test pad P6, and the end of the sixth connection section L42c away from the sixth connection section L42b is electrically connected to the selected driving circuit 20.
  • a second opening 41B is also provided in the first sub-ground wire 41
  • the fifth connecting section L41a is located in the second opening 41B
  • the fifth connecting section L41a is connected to the first sub-grounding wire. 41 without contact, the insulation between the fifth connection section L41a and the first sub-ground line 41 can be realized, and the fifth connection section L41a can span the first sub-power supply line 31 .
  • the sixth connection segment L42a ′, the fifth connection segment L41 ′ and the sixth connection segment L42b ′ are electrically connected in sequence, and two adjacent connection segments are electrically connected through the via holes in the first insulating layer 103 .
  • the end of the sixth connection section L42a' away from the fifth connection section L41' is electrically connected to the sixth test pad P6, and the end of the sixth connection section L42b' away from the fifth connection section L41' is electrically connected to the selected drive circuit 20 .
  • a third opening 41C is also provided in the first sub-ground wire 41, the fifth connecting section L41' is located in the third opening 41C, and the fifth connecting section L41' is connected to the first sub-grounding line 41.
  • the ground wires 41 are not in contact with each other, which can realize the insulation between the fifth connection section L41 ′ and the first sub-ground wire 41 , and realize that the fifth connection section L41 ′ straddles the first sub-power supply line 31 .
  • the sixth connection segment L42a ′′, the fifth connection segment L41 ′′ and the sixth connection segment L42b ′′ are electrically connected in sequence, and two adjacent connection segments are electrically connected through the via holes in the first insulating layer 103 .
  • the end of the sixth connection section L42a "away from the fifth connection section L41” is electrically connected to the sixth test pad P6, and the end of the sixth connection section L42b "far away from the fifth connection section L41" is electrically connected to the selected drive circuit 20 .
  • the fifth connection section L41" is located in the third opening 41C, and there is no contact between the fifth connection section L41" and the first sub-ground line 41, so that the fifth connection section L41" can be realized. Insulation between “" and the first sub-ground line 41, and the fifth connection segment L41" straddles the first sub-power line 31.
  • some embodiments of the present disclosure also provide a solution for detecting the voltage of the cascaded signal line electrically connected to the driving circuit 2 , which will be described in the following embodiments.
  • the light-emitting substrate 100 further includes a plurality of cascaded signal lines 6, two driving circuits 2 adjacent along the first direction X and/or two adjacent driving circuits 2 along the second direction Y
  • the two drive circuits 2 are electrically connected through the cascade signal line 6, and the cascade signal output by the drive circuit 2 is transmitted to the next-stage drive circuit 2 electrically connected thereto.
  • the drive circuit 2 further includes a cascade input signal terminal Dis and a cascade output signal terminal Dos
  • the cascade signal line 6 is electrically connected to the cascade input signal terminal Dis, and is configured as The cascade input signal is transmitted to the cascade input signal terminal Dis
  • the cascade signal line 6 is electrically connected to the cascade output signal terminal Dos, and is configured to use the cascade output signal output by the cascade output signal terminal Dos as the cascade input signal , which is transmitted to the cascaded input signal terminal Dis of the driving circuit 2 of the next stage.
  • each column driver circuit 2 is electrically connected through the cascaded signal line 6, along the second direction Y and from the test area A2 to the bonding area A3, the first of two adjacent column driver circuits 2
  • the driving circuits 2 are electrically connected to the two first driving circuits 2 through a cascaded signal line 6 (the cascaded signal line 6 extending along the first direction X shown in FIG. 5 ), thereby forming a cascaded unit 2A.
  • the last driving circuit 2 of a column of driving circuits 2 is the first-level driving circuit of the cascaded unit 2A.
  • the last drive circuit 2 of another column drive circuit 2 is the last stage drive circuit 2 lst of the cascade unit 2A
  • the cascade output signal output by the first stage drive circuit 2 fst is transmitted to the second cascade input signal as the cascade input signal
  • the light-emitting substrate 100 further includes a plurality of seventh test pads P7 disposed in the test area A2 , and each seventh test pad P7 is electrically connected to a cascaded signal line 6 .
  • FIG. 5A shows two seventh test pads P7, one of the seventh test pads P7 is electrically connected to the cascade signal line 6 and a cascade input signal terminal Dis of a drive circuit 2, and the other The seventh test pad P7 is electrically connected to the cascade signal line 6 and the cascade input signal terminal Dis of the next-level driving circuit 2 .
  • the electrical signal is transmitted to the circuit on the light-emitting substrate 100 through the pins located in the binding area, so that the selected driving circuit 20 and the light-emitting device group 1 connected to it receive the electrical signal through the corresponding signal line.
  • the The test fixture performs a needle stick test on a seventh test pad P7 and the test point TP to detect the voltage value of a cascaded input signal terminal Dis of the driving circuit 2 .
  • the test fixture is used to perform a needle-stick test on another seventh test pad P7 and the test point TP, so as to detect the voltage value of the cascaded input signal terminal Dis of the next-level drive circuit 2 .
  • a cascaded signal line 6 is connected between two adjacent driving circuits 2, the difference in voltage values of the cascaded input signal terminals Dis of two adjacent driving circuits 2 is approximately equal to two cascaded signal lines 6.
  • the voltage difference between terminals can be adjusted according to the voltage difference, and the design resistance value of the cascade signal line 6 can be adjusted to ensure that the voltage value of the cascade input signal provided by the cascade signal line 6 to the drive circuit 2 can meet the normal operation of the drive circuit 2.
  • the seventh test pad P7 is electrically connected to the cascaded signal line 6 close to the test area A2 through the cascaded signal connection line L5, and the number of signal lines that the cascaded signal connection line L5 needs to cross is relatively small, reducing This reduces the difficulty of preparing the cascaded signal connection line L5.
  • the cascade signal connection line L5 is electrically connected to the cascade signal line 6 close to the test area A2, so that the routing length of the cascade signal connection line L5 can be shortened.
  • the specific structure of the cascaded signal connection line L5 will be described below in conjunction with the film layer structure of the light emitting substrate 100 .
  • the seventh test pad P7 is located on the second conductive layer 104 .
  • the cascade signal line 6 is located on a side of the first sub-ground line 41 and the first sub-power line 31 away from the seventh test pad P7. Therefore, the cascade signal connection line L5 needs to span the first sub-ground line 41 and the first sub-power line 31 .
  • the cascade signal connection line L5 includes at least one seventh connection segment L51 located on the first conductive layer 102 and at least one eighth connection segment L52 located on the second conductive layer 104 .
  • the orthographic projection of the seventh connection section L51 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-power line 31 on the substrate 101 , so that the first sub-power line 31 is crossed by the seventh connection section L51 .
  • the orthographic projection of the eighth connection segment L52 on the substrate 101 at least partially overlaps the orthographic projection of the first sub-ground line 41 on the substrate 101 , so that the eighth connection segment L52 crosses the first sub-ground line 41 .
  • connection segment closest to the seventh test pad P7 is the eighth connection segment L52
  • the seventh test pad P7 is the closest to the seventh test pad P7.
  • the eighth connecting segment L52 is electrically connected.
  • both the seventh test pad P7 and the eighth connection segment L52 are located on the second conductive layer 104 , therefore, the seventh test pad P7 and the eighth connection segment L52 can be in direct electrical contact.
  • the cascaded signal connection line L5 can be realized to cross the first sub-power supply line 31 and the first sub-ground line 41 .
  • FIG. 5B shows two seventh test pads P7 and two cascaded signal connection lines L5, wherein the cascaded signal connection line L5 on the right includes two The seventh connection segment L51 (seventh connection segment L51a and seventh connection segment L51b ), and two eighth connection segments L52 (eighth connection segment L52a and eighth connection segment L52b ) located on the second conductive layer 104 .
  • the eighth connection segment L52a, the seventh connection segment L51a, the eighth connection segment L52b and the seventh connection segment L51b are electrically connected in sequence, and two adjacent connection segments are electrically connected through the via holes in the first insulating layer 103 .
  • the end of the eighth connection section L52a away from the seventh connection section L51a is electrically connected to the seventh test pad P7, and the end of the seventh connection section L51b away from the eighth connection section L52b is connected to the cascaded signal line 6.
  • a fourth opening 41D is opened in the first sub-ground wire 41
  • the seventh connecting section L51a is located in the fourth opening 41D
  • the seventh connecting section L51a is connected to the first sub-grounding wire 41 Without contact between them, the insulation between the seventh connection section L51a and the first sub-ground line 41 can be realized, and the seventh connection section L51a can span the first sub-power line 31 .
  • the specific structure of the cascade signal connection line L5 on the left is the same as that of the cascade signal connection line L5 on the right, and will not be described in detail here.
  • a test fixture is required to conduct a needle-stick test on the test point TP, and each test point TP is electrically connected to the ground line 4 .
  • the following describes how multiple test points TP are connected to the ground wire 4 .
  • the ground wire 4 includes a first sub-ground wire 41 extending along the first direction X, and a plurality of second sub-ground wires 42 extending along the second direction Y.
  • the first sub-ground wire 41 is disposed on the side of the light-emitting area A1 close to the test area A2 , and the first sub-ground wire 41 is electrically connected to a plurality of second sub-ground wires 42 .
  • the grounding stability of the grounding wire 4 can be improved by connecting multiple second sub-grounding wires 42 through the first sub-grounding wire 41 .
  • the ground wire 4 may include a plurality of first sub-ground wires 41, a plurality of first sub-ground wires 41 and a plurality of second sub-ground wires 42 Forming a grid structure can further improve the grounding stability of the grounding wire 4 .
  • the first sub-ground wire 41 is electrically connected to one end of the multiple second sub-ground wires 42 close to the test area A2, and the multiple test points TP are electrically connected to the first sub-ground wire 41, To realize the grounding of multiple test points TP.
  • the first sub-ground wire 41 is located on the first conductive layer 102
  • the test point TP is located on the second conductive layer 104
  • the test point TP passes through the via hole in the first insulating layer 103. It is electrically connected to the first sub-ground line 41 .
  • the second insulating layer 105 defines a first test hole H1 exposing the test point TP.
  • the pins of the test fixture can pass through the first test hole H1 and make electrical contact with the test point TP on the second conductive layer 104 , so that the needle stick test can be realized.
  • the test point TP is a second test hole H2 penetrating through the first insulating layer 103 and the second insulating layer 105 , and the second test hole H2 exposes the first sub-ground wire 41 .
  • test point TP is not prepared with a conductive layer, but penetrates through the first insulating layer 103 and the second insulating layer 105 in the form of a second test hole H2 and exposes the first sub-ground wire 41 .
  • the pins of the test fixture can pass through the second test hole H2 and directly make electrical contact with the first sub-ground wire 41 located on the first conductive layer 102 , so as to realize the needle stick test.
  • the ground wire 4 further includes a plurality of third sub-ground wires 43 and a plurality of connection patterns 44 .
  • each connection pattern 44 is electrically connected to two adjacent second sub-ground lines 42 , and is electrically connected to the driving circuit 2 .
  • the third sub-ground lines 43 extend along the second direction Y, each third sub-ground line 43 is electrically connected to at least one connection pattern 44, and one end of the third sub-ground lines 43 close to the test area A2 is connected to the first sub-ground line 41 electrical connection.
  • the grid density of the grid structure of the grounding wire 4 can be increased, so that the grounding stability of the grounding wire 4 can be further improved.
  • some embodiments of the present disclosure also provide a solution for detecting the voltage in the power line 3 , which will be described in the following embodiments.
  • the power line 3 is located on the second conductive layer 104 , and the second insulating layer 105 is opened with a third test hole H3 exposing the power line 3 .
  • the second conductive layer 104 further includes a plurality of second sub-ground wires 42 , and the second insulating layer 105 defines a fourth test hole H4 exposing the second sub-ground wires 42 .
  • a pin of the test fixture can pass through the third test hole H3 and make electrical contact with the second sub-power line 32 of the power line 3 on the second conductive layer 104 .
  • another pin of the test fixture can pass through the fourth test hole H4, and be in electrical contact with the second sub-ground wire 42 located on the second conductive layer 104, so that it can be detected that the corresponding position of the power line 3 is in contact with the second sub-ground wire 42.
  • the design resistance value of the power line 3 and/or grounding line 4 can be adjusted according to the difference, or the power line 3
  • the input voltage is compensated to ensure the normal light emission of the light emitting device.
  • a pin of the test fixture can pass through the third test hole H3 and be in electrical contact with the second sub-power line 32 of the power line 3 on the second conductive layer 104 .
  • another pin of the test fixture can be in electrical contact with the test point TP, so that the voltage value in the power line 3 can be detected.
  • some embodiments of the present disclosure also provide a solution for detecting the voltage of the output signal line electrically connected to the driving circuit 2 , which will be described in the following embodiments.
  • the second conductive layer 104 includes a plurality of output signal lines 7, each output signal line 7 is electrically connected to the light emitting device group 1 and the corresponding driving circuit 2, and the output signal of the driving circuit 2 is transmitted through the output signal line 7. It is transmitted to the driving circuit 2 to drive the light emitting device group 1 to emit light.
  • the second conductive layer 104 further includes a plurality of conductive test patterns 8 , and each output signal line 7 is also electrically connected to one conductive test pattern 8 .
  • the second insulating layer 105 defines a fifth test hole H5 exposing the conductive test pattern 8 .
  • a pin of the test fixture can pass through the fifth test hole H5 and make electrical contact with the conductive test pattern 8 on the second conductive layer 104 .
  • another pin of the test fixture can pass through the fourth test hole H4, and be in electrical contact with the second sub-ground wire 42 located on the second conductive layer 104, so that the voltage value in the output signal line 7 can be detected, thereby passing The voltage drop in the output signal line 7 is calculated, and then the designed resistance value of the output signal line 7 can be adjusted according to the voltage drop, so as to ensure normal light emission of the light emitting device.
  • some embodiments of the present disclosure also provide a solution for detecting the voltage of the sensor power line and the sensor connection line, which will be described in the following embodiments.
  • the light-emitting substrate 100 further includes a plurality of sensors S, a sensor power line S1 extending along the second direction Y, and a plurality of sensor connection lines S2 extending along the second direction Y.
  • a plurality of sensors S are arranged in a plurality of rows, and each row of sensors S is arranged along the second direction Y.
  • Each column of sensors S is electrically connected to a sensor power line S1, and the sensor power line S1 provides electrical energy to the sensors S electrically connected to it.
  • two adjacent sensors S are electrically connected through a sensor connection line S2.
  • the sensor S may be a temperature sensor, which can be used to detect the working temperature of the light emitting substrate 100 .
  • the light-emitting substrate 100 also includes a plurality of eighth test pads P8 arranged in the test area A2, at least one eighth test pad P8 is electrically connected to the sensor power line S1, and at least one of the eighth test pads P8 is electrically connected to the sensor power line S1.
  • the eight test pads P8 are electrically connected to the sensor connection line S2.
  • electrical signals are transmitted to circuits on the light-emitting substrate 100 through the pins located in the binding area, so that the selected driving circuit 20 and the light-emitting device group 1 connected thereto pass through the corresponding signal lines.
  • Receive the electrical signal in this case, use the test fixture to carry out the needle sticking test on the eighth test pad P8 (electrically connected with the sensor power line S1) and the test point TP, and the voltage value of the sensor power line S1 can be detected ( The voltage value of the end of the sensor power line S1 away from the bonding area A3).
  • the distance of the sensor power line S1 close to the binding area A3 can be calculated
  • the voltage drop between one end and the end far away from the binding area A3 can then adjust the design resistance value of the sensor power line S1 according to the voltage drop, so as to ensure that the voltage value of the input signal provided by the sensor power line S1 to the sensor S can meet the requirements of the sensor S normal work.
  • the voltage value of the sensor connection line S2 can be detected, so as to facilitate the adjustment of the sensor connection line S2 The design resistance value.
  • the backlight module 200 includes the light-emitting substrate 100 described in any of the above-mentioned embodiments.
  • the light-emitting substrate 100 is a Mini LED light-emitting substrate
  • the backlight module 200 is a Mini LED backlight module.
  • the backlight module 200 of the above-mentioned embodiments of the present disclosure can conveniently detect the voltage and current information in the circuit, so as to monitor the voltage and current information.
  • the display device 300 includes a display panel 301 and the backlight module 200 in the above-mentioned embodiments, and the display panel 301 is arranged on the backlight module
  • the light emitting side E of 200 can use the backlight module 200 to provide a backlight for the display panel 301 .
  • the above-mentioned display device 300 may be a liquid crystal display device (Liquid Crystal Display, LCD for short).
  • the display device 300 described above may be any device that displays an image regardless of whether it is moving (for example, video) or fixed (for example, still image) and regardless of text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or Laptop Computers GPS Receiv

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Abstract

一种发光基板，包括发光区，以及位于发光区至少一侧的测试区。所述发光基板包括多个发光器件组、多个驱动电路、电源线、第一测试衬垫、第二测试衬垫和第一测试器件组。多个发光器件组和多个驱动电路设置于发光区，每个驱动电路与至少一个发光器件组电连接。多个驱动电路包括选定驱动电路，选定驱动电路包括至少一个第一类输出端和至少一个第二类输出端，第一类输出端与发光器件组电连接。电源线与多个发光器件组电连接。第一测试衬垫和第二测试衬垫设置于测试区，第一测试衬垫与选定驱动电路的第二类输出端电连接，第二测试衬垫与电源线电连接。第一测试器件组与第一测试衬垫和第二测试衬垫电连接。

Description

发光基板、背光模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板、背光模组及显示装置。
背景技术
目前，在制备微米发光二极管(Micro Light-Emitting Diode，简称Micro LED)显示装置的过程中，由于巨量转移工艺技术的难度较大，给制备Micro LED显示装置带来了较大的挑战。
次毫米发光二极管(Mini Light-Emitting Diode，简称Mini LED)显示装置被认为是Micro LED显示装置的过渡产品，Mini LED显示装置凭借其较好的显示效果、轻薄化、较高的对比度以及使用寿命长等特点，受到了人们的广泛关注和研究。
公开内容
一方面，提供一种发光基板。所述发光基板包括发光区，以及位于所述发光区至少一侧的测试区。所述发光基板包括多个发光器件组、多个驱动电路、电源线、第一测试衬垫、第二测试衬垫和第一测试器件组。多个发光器件组和多个驱动电路设置于所述发光区，每个驱动电路与至少一个发光器件组电连接。所述多个驱动电路包括选定驱动电路，所述选定驱动电路包括至少一个第一类输出端和至少一个第二类输出端，所述第一类输出端与所述发光器件组电连接。电源线与所述多个发光器件组电连接。第一测试衬垫和第二测试衬垫设置于所述测试区，所述第一测试衬垫与所述选定驱动电路的第二类输出端电连接，所述第二测试衬垫与所述电源线电连接。第一测试器件组与所述第一测试衬垫和所述第二测试衬垫电连接。
在一些实施例中，所述多个发光器件组和所述多个驱动电路均排列成多行，每行发光器件组和每行驱动电路均沿第一方向排列。所述发光基板还包括绑定区，所述绑定区和所述测试区分别位于所述发光区沿第二方向的相对两侧。
沿第二方向且由所述测试区指向所述绑定区，多行发光器件组分别为第1行～第M行发光器件组，多行驱动电路分别为第1行～第N行驱动电路，M和N为大于或等于2的整数。第1行发光器件组与第1行驱动电路电连接，第1行驱动电路包括所述选定驱动电路。
在一些实施例中，所述选定驱动电路包括两个第一类输出端和两个第二 类输出端，所述两个第一类输出端分别与第1行发光器件组中的相邻两个发光器件组电连接，所述两个第二类输出端中的任一者与所述第一测试衬垫电连接。
在一些实施例中，第2行～第M行发光器件组包括多个器件单元，每个器件单元包括相邻的两行发光器件组，所述器件单元与第2行～第N行驱动电路中的一行驱动电路电连接。所述驱动电路包括四个输出端，分别与所述器件单元中的四个发光器件组电连接。
在一些实施例中，所述电源线包括第一子电源线和多条第二子电源线，第一子电源线沿第一方向延伸，设置于所述发光区靠近所述测试区的一侧。多条第二子电源线沿第二方向延伸，且与所述第一子电源线电连接。
其中，所述发光基板还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧，所述第一子电源线与所述多条第二子电源线的靠近所述测试区的一端电连接。所述第二测试衬垫与所述第一子电源线电连接。
在一些实施例中，所述发光基板还包括第一连接线和第二连接线，第一连接线一端与所述第一测试衬垫电连接，另一端与所述选定驱动电路电连接。第二连接线一端与所述第二测试衬垫电连接，另一端与所述第一子电源线电连接。
在一些实施例中，所述发光基板包括衬底，及依次层叠设置于所述衬底上的第一导电层和第二导电层。所述第一导电层包括沿第一方向延伸的第一子接地线，所述第一子接地线位于所述发光区靠近所述测试区的一侧，所述第一子电源线和所述第一测试衬垫位于所述第二导电层。
所述选定驱动电路位于所述第一子接地线和所述第一子电源线的远离所述第一测试衬垫的一侧。所述第一连接线包括位于所述第一导电层的至少一个第一连接段，和位于所述第二导电层的至少一个第二连接段，所述第一连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第二连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至少部分重叠。所述至少一个第一连接段和所述至少一个第二连接段中，最靠近所述第一测试衬垫的连接段为第二连接段，所述第一测试衬垫与最靠近的第二连接段电连接。
在一些实施例中，所述第二连接线大致沿第二方向延伸，且所述第二连接线和所述第一子电源线的材料相同且同层设置。
在一些实施例中，所述第一测试器件组包括测试发光器件和/或电阻器。
在一些实施例中，所述第一测试器件组包括测试发光器件和电阻器。所述发光基板还包括第三测试衬垫，所述测试发光器件的一端与所述第一测试衬垫电连接，另一端与所述第三测试衬垫电连接。所述电阻器的一端与所述第二测试衬垫电连接，另一端与所述第三测试衬垫电连接。
在一些实施例中，所述发光器件组包括多个发光器件和多条走线，所述多个发光器件通过所述多条走线串联设置。所述发光基板还包括第四测试衬垫、第五测试衬垫和第二测试器件组。第四测试衬垫和第五测试衬垫设置于所述测试区。所述第四测试衬垫和所述第五测试衬垫分别与同一条走线电连接。所述走线中，位于所述第四测试衬垫与所述走线电连接的位置，与，所述第五测试衬垫与所述走线电连接的位置之间的部分断开。第二测试器件组与所述第四测试衬垫和所述第五测试衬垫电连接。
在一些实施例中，所述发光基板还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧。所述多个发光器件组排列成多行，每行发光器件组沿第一方向排列。沿第二方向且由所述测试区指向所述绑定区，多行发光器件组分别为第1行～第M行发光器件组。所述第四测试衬垫和所述第五测试衬垫均与第1行发光器件组中的任一条走线电连接。
在一些实施例中，所述发光基板还包括两条第三连接线，其中一条第三连接线的一端与所述第四测试衬垫电连接，另一端与所述走线电连接。另一条第三连接线的一端与所述第五测试衬垫电连接，另一端与所述走线电连接。
在一些实施例中，所述发光基板包括依次层叠设置的第一导电层和第二导电层，所述第一导电层包括沿第一方向延伸的第一子接地线，所述第二导电层包括沿第一方向延伸的第一子电源线，所述第四测试衬垫和所述第五测试衬垫位于所述第二导电层。
所述第四测试衬垫和所述第五测试衬垫均位于所述第一子接地线和所述第一子电源线的远离所述走线的一侧。所述第三连接线包括位于所述第一导电层的至少一个第三连接段，和位于所述第二导电层的至少一个第四连接段，所述第三连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第四连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至少部分重叠。
一条第三连接线的至少一个第三连接段和至少一个第四连接段中，最靠近所述第四测试衬垫的连接段为第四连接段，所述第四测试衬垫与最靠近的第四连接段电连接。另一条第三连接线的至少一个第三连接段和至少一个第四连接段中，最靠近所述第五测试衬垫的连接段为第四连接段，所述第五测 试衬垫与最靠近的第四连接段电连接。
在一些实施例中，所述发光基板还包括至少一条输入信号线、接地线、至少一个第六测试衬垫和至少一个测试点位。至少一条输入信号线沿第二方向延伸，且与所述多个驱动电路电连接。接地线与所述多个驱动电路电连接。至少一个第六测试衬垫设置于所述测试区，每个第六测试衬垫与一条输入信号线电连接。至少一个测试点位设置于所述发光区，与所述接地线电连接。
在一些实施例中，所述发光基板还包括绑定区，所述绑定区和所述测试区分别位于所述发光区沿第二方向的相对两侧。所述发光基板还包括信号连接线，一端与所述第六测试衬垫电连接，另一端与所述输入信号线的靠近所述测试区的一端电连接。
在一些实施例中，所述发光基板包括依次层叠设置的第一导电层和第二导电层，所述第一导电层包括沿第一方向延伸的第一子接地线，所述第二导电层包括沿第一方向延伸的第一子电源线，所述第六测试衬垫位于所述第二导电层。
所述选定驱动电路位于所述第一子接地线和所述第一子电源线的远离所述第六测试衬垫的一侧。所述信号连接线包括位于所述第一导电层的至少一个第五连接段，和位于所述第二导电层的至少一个第六连接段，所述第五连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第六连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至少部分重叠。所述至少一个第五连接段和所述至少一个第六连接段中，最靠近所述第六测试衬垫的连接段为第六连接段，所述第六测试衬垫与最靠近的第六连接段电连接。
在一些实施例中，所述至少一条输入信号线包括电源电压信号线、时钟信号线和数据信号线中的至少一种。
在一些实施例中，所述发光基板还包括多条级联信号线和多个第七测试衬垫，沿第一方向相邻的两个驱动电路和/或沿第二方向相邻的两个驱动电路之间，通过级联信号线电连接。多个第七测试衬垫设置于所述测试区，每个第七测试衬垫与一条级联信号线电连接。
在一些实施例中，所述接地线包括第一子接地线和多条第二子接地线，第一子接地线沿第一方向延伸，设置于所述发光区靠近所述测试区的一侧。多条第二子接地线沿第二方向延伸，且与所述第一子接地线电连接。
其中，所述发光基板还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧，所述第一子接地线与所述多条第二子接 地线的靠近所述测试区的一端电连接。所述多个测试点位与所述第一子接地线电连接。
在一些实施例中，所述发光基板包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层。
所述第一子接地线位于所述第一导电层，所述测试点位位于所述第二导电层，所述测试点位通过所述第一绝缘层中的过孔与所述第一子接地线电连接，所述第二绝缘层开设有暴露所述测试点位的第一测试孔。或，所述测试点位为贯穿所述第一绝缘层和所述第二绝缘层的第二测试孔，所述第二测试孔暴露所述第一子接地线。
在一些实施例中，所述接地线还包括多个连接图案和多条第三子接地线，每个连接图案电连接相邻两条第二子接地线，且与所述驱动电路电连接。多条第三子接地线沿第二方向延伸，每条第三子接地线与至少一个连接图案电连接，且所述第三子接地线靠近所述测试区的一端与所述第一子接地线电连接。
在一些实施例中，所述发光基板包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层。所述电源线位于所述第二导电层，所述第二绝缘层开设有暴露所述电源线的第三测试孔。所述第二导电层还包括多条第二子接地线，所述第二绝缘层开设有暴露所述第二子接地线的第四测试孔。
在一些实施例中，所述发光基板包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层。所述第二导电层包括多条输出信号线和多个导电测试图案，每条输出信号线电连接所述发光器件组与对应的驱动电路，且与一个导电测试图案电连接。所述第二绝缘层开设有暴露所述导电测试图案的第五测试孔。
另一方面，提供一种背光模组。所述背光模组包括上述任一实施例所述的发光基板。
又一方面，提供一种显示装置。所述显示装置包括显示面板，及如上述实施例所述的背光模组，所述显示面板设置于所述背光模组的出光侧。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本 公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的发光基板的结构图；
图2A和图2B为图1中的发光基板在A处的局部放大图；
图2C为图2B中的发光基板沿剖面线A-A＇的局部剖面图；
图2D为图2B中的发光基板在D处的局部放大图；
图2E为图2B中的发光基板在E处的局部放大图；
图3为根据一些实施例的驱动电路的结构图；
图4A和图4B为图1中的发光基板在B处的局部放大图；
图4C为图4B中的发光基板沿剖面线B-B＇的局部剖面图；
图5A和图5B为图1中的发光基板在C处的局部放大图；
图5C和图5D为图5B中的发光基板沿剖面线C-C＇的局部剖面图；
图6为根据一些实施例的背光模组的结构图；
图7A为根据一些实施例的显示装置的结构图；
图7B为图7A中的显示装置沿剖面线D-D＇的局部剖面图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在 本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A、B和C中的至少一种”与“A、B或C中的至少一种”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，在制备发光基板的过程中，需要检测发光基板上的电路的电流和/或电压信息，以便于监测电路的开路或者短路情况。然而，由于发光基板中的发光器件的数量较多，发光基板上的电路排布较为复杂，且开短 路(Open-Short，简称OS)测试治具的针脚的数量较少，这给检测电路的电流和/或电压信息带来了较大的挑战。由于无法检测到电路的精确电流和/或电压信息，导致不能提供合适范围的电流和电压给发光基板中的发光器件，进而无法保证发光器件的正常发光。
为解决上述问题，如图1所示，本公开的一些实施例提供了一种发光基板100，发光基板100包括发光区A1，以及位于发光区A1至少一侧的测试区A2。
示例性地，如图1所示，发光基板100还包括绑定区A3，绑定区A3和测试区A2分别位于发光区A1的沿第二方向Y的相对两侧。
如图1和图2A所示，发光基板100包括设置于发光区A1的多个发光器件组1和多个驱动电路(例如为微型集成电路，Micro Integrated Circuit)2，每个驱动电路2与至少一个发光器件组1电连接，以驱动发光器件组1进行发光。
在一些示例中，每个驱动电路2与两个发光器件组1电连接。在另一些示例中，每个驱动电路2与四个发光器件组1电连接。下文会对每个驱动电路2所电连接的发光器件组1的数量进行解释说明。
如图2A和图3所示，多个驱动电路2包括选定驱动电路20，选定驱动电路20包括至少一个第一类输出端21和至少一个第二类输出端22，第一类输出端21与发光器件组1电连接。
可以理解的是，选定驱动电路20的第一类输出端21与发光器件组1电连接，第一类输出端21的数量即可满足电连接的发光器件组1的数量，第二类输出端22不必须与发光器件组1电连接。
当然，选定驱动电路20的第二类输出端22也是可以与发光器件组1电连接的。
如图2A所示，发光基板100还包括电源线3，电源线3与多个发光器件组1电连接，以向发光器件组1传输电源电压信号，为发光器件组1的发光提供电能。
如图1和图2A所示，发光基板100还包括设置于测试区A2的第一测试衬垫P1、第二测试衬垫P2和第一测试器件组T1，第一测试衬垫P1与选定驱动电路20的第二类输出端22电连接，第二测试衬垫P2与电源线3电连接，第一测试器件组T1与第一测试衬垫P1和第二测试衬垫P2电连接。
本公开的上述实施例的发光基板100中，多个驱动电路2包括选定驱动电路20，选定驱动电路20包括至少一个第一类输出端21和至少一个第二类 输出端22，第一类输出端21与发光器件组1电连接。
基于此，在发光基板100的测试区A2设置第一测试衬垫P1和第二测试衬垫P2，且第一测试衬垫P1与选定驱动电路20的第二类输出端22电连接，第二测试衬垫P2与电源线3电连接，在第一测试衬垫P1与第二测试衬垫P2之间连接第一测试器件组T1，形成了选定驱动电路20、第一测试衬垫P1、第一测试器件组T1、第二测试衬垫P2与电源线3的串联电路，通过位于绑定区的引脚向发光基板100上的电路传输电信号，使得选定驱动电路20及其连接的发光器件组1通过相应的信号线接收到电信号，在此情况下，采用测试治具对第一测试衬垫P1与第二测试衬垫P2进行扎针测试，可检测到第一测试器件组T1中的电流值，从而得到电源线3中的电流值。
并且，根据检测到的电源线3中的电流值以及电源线3的设计电阻值，可以计算得到电源线3靠近绑定区A3的一端与远离绑定区A3的一端的压降(IR-Drop)，进而可根据该压降调整电源线3的设计电阻值，或对电源线3的输入电压进行补偿，以保证发光器件的正常发光。
此外，在一些实施例中，第一测试衬垫P1与第二测试衬垫P2之间也可以不连接第一测试器件组T1，直接采用测试治具对第一测试衬垫P1与第二测试衬垫P2进行扎针测试，形成了选定驱动电路20、第一测试衬垫P1、测试治具、第二测试衬垫P2与电源线3的串联电路，测试治具作为测试器件接入串联电路中，利用测试治具检测通过其本身的电流值，从而得到电源线3中的电流值。
在一些实施例中，如图2A所示，第一测试器件组T1包括测试发光器件T11和/或电阻器T12。
示例性地，第一测试器件组T1包括测试发光器件T11，测试发光器件T11的一端与第一测试衬垫P1电连接，另一端与第二测试衬垫P2电连接。
示例性地，第一测试器件组T1包括电阻器T12，电阻器T12的一端与第一测试衬垫P1电连接，另一端与第二测试衬垫P2电连接。
示例性地，如图2A所示，第一测试器件组T1包括测试发光器件T11和电阻器T12，在此情况下，发光基板100还包括第三测试衬垫P3，测试发光器件T11的一端与第一测试衬垫P1电连接，另一端与第三测试衬垫P3电连接。电阻器T12的一端与第二测试衬垫P2电连接，另一端与第三测试衬垫P3电连接，以实现测试发光器件T11与电阻器T12的串联设置。
在一些实施例中，如图1所示，多个发光器件组1沿第一方向X与第二方向Y阵列排布，多个驱动电路2沿第一方向X与第二方向Y阵列排布。其 中，第一方向X与第二方向Y相交叉，示例性地，第一方向X与第二方向Y相垂直。第一方向X可以为发光器件组1和/或驱动电路2的行方向，第二方向Y可以为发光器件组1和/或驱动电路2的列方向。
如图1和图2A所示，沿第二方向Y且由测试区A2指向绑定区A3，多行发光器件组1分别为第1行～第M行发光器件组，多行驱动电路2分别为第1行～第N行驱动电路，M和N为大于或等于2的整数。其中，第1行发光器件组与第1行驱动电路电连接，第1行驱动电路包括选定驱动电路20，即选定驱动电路20位于多行驱动电路2的第1行驱动电路中。
需要说明的是，如图1所示，发光基板100中的多条信号线(例如，电源线3、接地线4及与驱动电路2电连接的多条输入信号线5等)汇集至绑定区A3，使得发光区A1靠近绑定区A3的一侧的信号线排布较为复杂。
若将选定驱动电路20设置于发光区A1靠近绑定区A3的一侧，连接线L需要跨越绑定区A3实现第一测试衬垫P1与选定驱动电路20的电连接，或者跨越发光区A1实现第一测试衬垫P1与选定驱动电路20的电连接，这给连接第一测试衬垫P1和选定驱动电路20的连接线L的制备造成了较大的困难。
因此，本公开的上述实施例，通过将选定驱动电路20设置于多行驱动电路2的第1行驱动电路中，即将选定驱动电路20设置于发光区A1远离绑定区A3的一侧，也即将选定驱动电路20设置于发光区A1靠近测试区A2的一侧。如图2B所示，相较于发光区A1靠近绑定区A3的一侧，发光区A1靠近测试区A2的一侧的信号线的数量较少且排布较简单，将选定驱动电路20设置于发光区A1靠近测试区A2的一侧，连接线L需要跨越的信号线的数量较少，降低了连接线L的制备难度。
并且，由于选定驱动电路20设置于发光区A1靠近测试区A2的一侧，第一测试衬垫P1设置于测试区A2，可缩短第一测试衬垫P1与选定驱动电路20之间的连接线L的走线长度。
在一些实施例中，如图2A和图3所示，选定驱动电路20包括两个第一类输出端21和两个第二类输出端22，两个第一类输出端21分别与第1行发光器件组中的相邻两个发光器件组1电连接。两个第二类输出端22中的任一者与第一测试衬垫P1电连接。
可以理解的是，如图2A和图3所示，选定驱动电路20具有四个输出端(CH1、CH2、CH3和CH4)，四个输出端包括两个第一类输出端21和两个第二类输出端22。并且，在第1行发光器件组中，相邻两个发光器件组1之间设置有一个选定驱动电路20，选定驱动电路20的两个第一类输出端21与 相邻两个发光器件组1电连接。
在保证发光基板上的所有发光器件组1都与对应的驱动电路2电连接的前提下，存在选定驱动电路20的两个第二类输出端22空置(即不与任何发光器件组1电连接)的情况，从而，可以将该选定驱动电路20的两个第二类输出端22中的任一者与第一测试衬垫P1电连接。
在一些实施例中，如图1所示，第2行～第M行发光器件组包括多个器件单元10，每个器件单元10包括相邻的两行发光器件组1，且器件单元10与第2行～第N行驱动电路中的一行驱动电路2电连接。即在第2行～第M行发光器件组中，相邻的两行发光器件组1与一行驱动电路2电连接。
如图1和图3所示，驱动电路2包括四个输出端(CH1、CH2、CH3和CH4)，四个输出端分别与器件单元10中的四个发光器件组1电连接。
可以理解的是，如图1所示，每个器件单元10包括多个子器件单元11，每个子器件单元11包括两行发光器件组1和两列发光器件组1中的四个发光器件组1，每个驱动电路2的四个输出端分别与每个子器件单元11中的四个发光器件组1电连接。
在一些实施例中，如图1所示，电源线3包括一条第一子电源线31和多条第二子电源线32，第一子电源线31沿第一方向X延伸，且第一子电源线31设置于发光区A1靠近测试区A2的一侧。多条第二子电源线32沿第二方向Y延伸，且多条第二子电源线32与第一子电源线31电连接，通过第一子电源线31将多条第二子电源线32连接起来，相当于形成了多个并联通道，可以降低电源线3整体的电阻，从而可提高电源线3传输电源信号的稳定性。
需要说明的是，在发光基板100上的排布空间允许的情况下，电源线3可以包括多条沿第一方向X延伸的第一子电源线31，多条第一子电源线31与多条第二子电源线32形成网格结构，可进一步降低电源线3整体的电阻，提高电源线3传输电源信号的稳定性。
如图1和图2A所示，第一子电源线31与多条第二子电源线32的靠近测试区A2的一端电连接，第二测试衬垫P2与第一子电源线31电连接。
通过上述设置方式，使第一子电源线31的设置位置靠近测试区A2，第二测试衬垫P2通过连接线L与第一子电源线31电连接，可以缩短连接线L的走线长度，可减少连接线L跨越的信号线的数量，降低连接线L的制备难度。
在一些实施例中，如图2A所示，发光基板100还包括第一连接线L1和第二连接线L2，第一连接线L1的一端与第一测试衬垫P1电连接，另一端与 选定驱动电路20电连接，以实现第一测试衬垫P1与选定驱动电路20的电连接。
第二连接线L2的一端与第二测试衬垫P2电连接，另一端与第一子电源线31电连接，以实现第二测试衬垫P2与第一子电源线31的电连接。
下面结合发光基板100的膜层结构，对第一连接线L1和第二连接线L2的具体结构进行描述。
在一些实施例中，如图2B和图2C所示，发光基板100包括衬底101，及依次层叠设置于衬底101上的第一导电层102和第二导电层104。第一导电层102包括沿第一方向X延伸的第一子接地线41，第一子接地线41位于发光区A1靠近测试区A2的一侧。第一子电源线31和第一测试衬垫P1位于第二导电层104。
需要说明的是，发光基板100还包括位于第一导电层102和第二导电层104之间的第一绝缘层103，以实现第一导电层102与第二导电层104的绝缘。
并且，发光基板100还包括设置于第二导电层104远离衬底101一侧的第二绝缘层105，起到保护第二导电层104的作用。
如图2B所示，选定驱动电路20位于第一子接地线41和第一子电源线31的远离第一测试衬垫P1的一侧。因此，第一连接线L1需要跨越第一子接地线41和第一子电源线31，与第一测试衬垫P1和选定驱动电路20电连接。
如图2B所示，第一连接线L1包括位于第一导电层102的至少一个第一连接段L11，和位于第二导电层104的至少一个第二连接段L12。其中，第一连接段L11在衬底101上的正投影与第一子电源线31在衬底101上的正投影至少部分重叠，从而通过第一连接段L11跨越第一子电源线31。第二连接段L12在衬底101上的正投影与第一子接地线41在衬底101上的正投影至少部分重叠，从而通过第二连接段L12跨越第一子接地线41。
如图2B所示，至少一个第一连接段L11和至少一个第二连接段L12中，最靠近第一测试衬垫P1的连接段为第二连接段L12，第一测试衬垫P1与最靠近的第二连接段L12电连接。
可以理解的是，第一测试衬垫P1和第二连接段L12均位于第二导电层104，因此，第一测试衬垫P1与第二连接段L12可以直接电接触。
通过上述第一连接线L1的结构设计，可实现第一连接线L1跨越第一子电源线31和第一子接地线41。
示例性地，如图2B和图2C所示，第一连接线L1包括位于第一导电层102的两个第一连接段L11(第一连接段L11a和第一连接段L11b)，和位于 第二导电层104的三个第二连接段L12(第二连接段L12a、第二连接段L12b和第二连接段L12c)。其中，第二连接段L12a、第一连接段L11a、第二连接段L12b、第一连接段L11b和第二连接段L12c依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第二连接段L12a远离第一连接段L11a的一端与第一测试衬垫P1电连接，第二连接段L12c远离第一连接段L11b的一端与选定驱动电路20电连接。
需要说明的是，如图2B所示，第一子接地线41中设置有第一开口41A，第一连接段L11a位于第一开口41A内，且第一连接段L11a与第一子接地线41之间不接触，可实现第一连接段L11a与第一子接地线41之间的绝缘，并且，实现了第一连接段L11a跨越第一子电源线31。
在一些实施例中，如图2B所示，第二连接线L2大致沿第二方向Y延伸，且第二连接线L2和第一子电源线31的材料相同且同层设置，即第二连接线L2和第一子电源线31均位于第二导电层104。因此，第二连接线L2可以与第一子电源线31直接电接触。
并且，如图2B所示，第二测试衬垫P2也位于第二导电层104，因此，第二连接线L2也可以与第二测试衬垫P2直接电接触。
本公开的一些实施例还提供了一种检测每个发光器件组1中的电流的方案，以下实施例将对该方案进行描述。
如图4A所示，发光器件组1包括多个发光器件1a和多条走线1b，多个发光器件1a通过多条走线1b串联设置。其中，发光器件1a为尺寸在50-500um的无机发光二极管，例如为Mini LED。
如图4A所示，发光基板100还包括设置于测试区A2的第四测试衬垫P4和第五测试衬垫P5，以及第二测试器件组T2。其中，第四测试衬垫P4和第五测试衬垫P5分别与同一条走线1b电连接。在该走线1b中，位于第四测试衬垫P4与该走线1b电连接的位置，与，第五测试衬垫P5与该走线1b电连接的位置之间的部分断开。第二测试器件组T2与第四测试衬垫P4和第五测试衬垫P5电连接。
需要说明的是，参见图4A和图4B，与第四测试衬垫P4和第五测试衬垫P5连接的走线1b(发光器件LED-2与发光器件LED-3之间的走线1b)包括第一子走线11b和第二子走线12b，第一子走线11b与第二子走线12b之间断开，第四测试衬垫P4与第一子走线11b电连接，第五测试衬垫P5与第二子走线12b电连接，以满足测试的需要。
请继续参见图4A和图4B，上述走线1b还包括子连接走线13b，需要说明的是，子连接走线13b位于第一导电层102，第一子走线11b和第二子走线12b均位于第二导电层104，且第一子走线11b和第二子走线12b在衬底101上的正投影，均与子连接走线13b在衬底101上的正投影至少部分重叠。在测试结束之后，可采用激光分别照射第一子走线11b和第二子走线12b与子连接走线13b重叠的部位，以使第一子走线11b和第二子走线12b与子连接走线13b电连接，使断开的走线1b连接起来，从而保证发光基板100的正常使用。
本公开的上述实施例的发光基板100中，在测试区A2设置第四测试衬垫P4和第五测试衬垫P5，第四测试衬垫P4和第五测试衬垫P5分别与同一条走线1b电连接，通过将二者与该走线1b连接位置之间的走线1b打断，并在第四测试衬垫P4与第五测试衬垫P5之间连接第二测试器件组T2，形成了第二测试器件组T2与多个发光器件1a的串联电路。
通过位于绑定区的引脚向发光基板100上的电路传输电信号，使得选定驱动电路20及其连接的发光器件组1通过相应的信号线接收到电信号，在此情况下，采用测试治具对第四测试衬垫P4和第五测试衬垫P5进行扎针测试，可检测到第二测试器件组T2中的电流值，从而得到多个发光器件1a的串联电路中的电流值。
并且，根据上文可知，每个发光器件组1与电源线3和驱动电路2电连接，参考图1，驱动电路2还与接地线4电连接(后文将对驱动电路2与接地线4的具体连接方式进行描述)，因此，多个发光器件1a的串联电路还与驱动电路2和接地线4串联设置，多个发光器件1a的串联电路中的电流值与驱动电路2流入接地线4的电流值相等。
根据驱动电路2流入接地线4的电流值，以及接地线4的当前电阻值，可以计算得到接地线4靠近绑定区A3的一端与远离绑定区A3的一端的压降，进而可根据该压降是否满足产品要求而调整接地线4的设计电阻值，保证多个发光器件1a的串联电路中的电流值满足产品要求，可以保证多个发光器件1a的发光效果。
此外，在一些实施例中，第四测试衬垫P4与第五测试衬垫P5之间也可以不连接第二测试器件组T2，直接采用测试治具对第四测试衬垫P4与第五测试衬垫P5进行扎针测试，形成了测试治具与多个发光器件1a的串联电路，测试治具作为测试器件接入串联电路中，利用测试治具检测通过其本身的电流值，从而得到串联电路中的电流值。
在一些实施例中，如图4A所示，第二测试器件组T2包括电阻器T22，电阻器T22的一端与第四测试衬垫P4电连接，另一端与第五测试衬垫P5电连接。
在一些实施例中，如图1和图4A所示，第四测试衬垫P4和第五测试衬垫P5均与第1行发光器件组中的任一条走线1b电连接。
本公开的上述实施例，由于第1行发光器件组设置于发光区A1远离绑定区A3的一侧，即设置于发光区A1靠近测试区A2的一侧。相较于发光区A1靠近绑定区A3的一侧，发光区A1靠近测试区A2的一侧的信号线的数量较少且排布较简单，将第四测试衬垫P4和第五测试衬垫P5均与第1行发光器件组中的任一条走线1b电连接，第四测试衬垫P4和第五测试衬垫P5与走线1b之间的连接线L需要跨越的信号线的数量较少，降低了连接线L的制备难度。
并且，由于第1行发光器件组设置于发光区A1靠近测试区A2的一侧，第四测试衬垫P4和第五测试衬垫P5均设置于测试区A2，第四测试衬垫P4和第五测试衬垫P5均与第1行发光器件组中的任一条走线1b电连接，可缩短连接线L的走线长度。
在一些实施例中，如图4A所示，发光基板100还包括两条第三连接线L3，其中一条第三连接线L3的一端与第四测试衬垫P4电连接，另一端与走线1b电连接，以实现第四测试衬垫P4与走线1b的电连接。
另一条第三连接线L3的一端与第五测试衬垫P5电连接，另一端与走线1b电连接，以实现第五测试衬垫P5与走线1b的电连接。
下面结合发光基板100的膜层结构，对第三连接线L3的具体结构进行描述。
在一些实施例中，如图4B所示，第四测试衬垫P4和第五测试衬垫P5位于第二导电层104。第四测试衬垫P4和第五测试衬垫P5均位于第一子接地线41和第一子电源线31的远离走线1b的一侧。因此，第三连接线L3需要跨越第一子接地线41和第一子电源线31。
如图4B和图4C所示，第三连接线L3包括位于第一导电层102的至少一个第三连接段L31，和位于第二导电层104的至少一个第四连接段L32。其中，第三连接段L31在衬底101上的正投影与第一子电源线31在衬底101上的正投影至少部分重叠，从而通过第三连接段L31跨越第一子电源线31。第四连接段L32在衬底101上的正投影与第一子接地线41在衬底101上的正投影至少部分重叠，从而通过第四连接段L32跨越第一子接地线41。
如图4B和图4C所示，一条第三连接线L3的至少一个第三连接段L31和至少一个第四连接段L32中，最靠近第四测试衬垫P4的连接段为第四连接段L32，第四测试衬垫P4与最靠近的第四连接段L32电连接。
可以理解的是，第四测试衬垫P4和第四连接段L32均位于第二导电层104，因此，第四测试衬垫P4与第四连接段L32可以直接电接触。
如图4B和图4C所示，另一条第三连接线L3的至少一个第三连接段L31和至少一个第四连接段L32中，最靠近第五测试衬垫P5的连接段为第四连接段L32，第五测试衬垫P5与最靠近的第四连接段L32电连接。
可以理解的是，第五测试衬垫P5和第四连接段L32均位于第二导电层104，因此，第五测试衬垫P5与第四连接段L32可以直接电接触。
通过上述第三连接线L3的结构设计，可实现第三连接线L3跨越第一子电源线31和第一子接地线41。
示例性地，如图4B和图4C所示，第三连接线L3包括位于第一导电层102的一个第三连接段L31，和位于第二导电层104的两个第四连接段L32(第四连接段L32a和第四连接段L32b)。其中，第四连接段L32a、第三连接段L31和第四连接段L32b依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第四连接段L32a远离第三连接段L31的一端与第四测试衬垫P4电连接，第四连接段L32b远离第三连接段L31的一端与走线1b电连接。
并且，本公开的一些实施例还提供了一种检测与驱动电路2电连接的输入信号线的电压的方案，以下实施例将对该方案进行描述。
如图5A所示，发光基板100还包括至少一条输入信号线5，输入信号线5沿第二方向Y延伸，且与多个驱动电路2电连接，用于向驱动电路2提供输入信号。
示例性地，如图5A所示，至少一条输入信号线5包括电源电压信号线51、时钟信号线52和数据信号线53中的至少一种。
并且，如图3和图5A所示，驱动电路2包括电源电压信号端Vcc、时钟信号端CLK和数据信号端Dip，电源电压信号线51与电源电压信号端Vcc电连接，被配置为向电源电压信号端Vcc传输电源电压信号；时钟信号线52与时钟信号端CLK电连接，被配置为向时钟信号端CLK传输时钟信号；数据信号线53与数据信号端Dip电连接，被配置为向数据信号端Dip传输数据信号。
如图3和图5A所示，发光基板100还包括接地线4，接地线4与多个驱 动电路2电连接，以使多个驱动电路2接地。下文将具体描述接地线4与驱动电路2的连接方式。
示例性地，驱动电路2还包括接地端GND，接地线4与接地端GND电连接，被配置为将驱动电路2接地。
如图5B所示，发光基板100还包括设置于测试区A2的至少一个第六测试衬垫P6，以及设置于发光区A1的至少一个测试点位TP，每个第六测试衬垫P6与一条输入信号线5电连接，每个测试点位TP与接地线4电连接(即测试点位TP的电压值为0)。
需要说明的是，如图5B所示，发光基板100还包括信号连接线L4，信号连接线L4的一端与第六测试衬垫P6电连接，另一端与输入信号线5的靠近测试区A2的一端电连接。
本公开的上述实施例的发光基板100中，在测试区A2设置有至少一个第六测试衬垫P6，每个第六测试衬垫P6与一条输入信号线5电连接。在发光区A1设置有至少一个测试点位TP，每个测试点位TP与接地线4电连接。
并且，通过位于绑定区的引脚向发光基板100上的电路传输电信号，使得选定驱动电路20及其连接的发光器件组1通过相应的信号线接收到电信号，在此情况下，采用测试治具对第六测试衬垫P6和测试点位TP进行扎针测试，可检测到与第六测试衬垫P6电连接的输入信号线5的电压值(输入信号线5的远离绑定区A3一端的电压值)。
根据检测到的输入信号线5的远离绑定区A3一端的电压值，以及输入信号线5在绑定区A3接收到的信号的电压值，可以计算得到输入信号线5靠近绑定区A3的一端与远离绑定区A3的一端的压降，进而可根据该压降调整输入信号线5的设计电阻值，保证输入信号线5向驱动电路2提供的输入信号的电压值，可以满足驱动电路2的正常工作。
此外，相较于发光区A1靠近绑定区A3的一侧，发光区A1靠近测试区A2的一侧的信号线的数量较少且排布较简单，将信号连接线L4与输入信号线5的靠近测试区A2的一端电连接，信号连接线L4需要跨越的信号线的数量较少，降低了信号连接线L4的制备难度。
并且，由于第六测试衬垫P6设置于测试区A2，将信号连接线L4与输入信号线5的靠近测试区A2的一端电连接，可缩短信号连接线L4的走线长度。
下面结合发光基板100的膜层结构，对信号连接线L4的具体结构进行描述。
在一些实施例中，如图5B所示，第六测试衬垫P6位于第二导电层104。 选定驱动电路20位于第一子接地线41和第一子电源线31的远离第六测试衬垫P6的一侧。因此，信号连接线L4需要跨越第一子接地线41和第一子电源线31。
如图5B所示，信号连接线L4包括位于第一导电层102的至少一个第五连接段L41，和位于第二导电层104的至少一个第六连接段L42。其中，第五连接段L41在衬底101上的正投影与第一子电源线31在衬底101上的正投影至少部分重叠，从而通过第五连接段L41跨越第一子电源线31。第六连接段L42在衬底101上的正投影与第一子接地线41在衬底101上的正投影至少部分重叠，从而通过第六连接段L42跨越第一子接地线41。
如图5B所示，至少一个第五连接段L41和至少一个第六连接段L42中，最靠近第六测试衬垫P6的连接段为第六连接段L42，第六测试衬垫P6与最靠近的第六连接段L42电连接。
可以理解的是，第六测试衬垫P6和第六连接段L42均位于第二导电层104，因此，第六测试衬垫P6与第六连接段L42可以直接电接触。
通过上述信号连接线L4的结构设计，可实现信号连接线L4跨越第一子电源线31和第一子接地线41。
示例性地，如图5B所示，与电源电压信号线51电连接的信号连接线L4，该信号连接线L4包括位于第一导电层102的两个第五连接段L41(第五连接段L41a和第五连接段L41b)，和位于第二导电层104的三个第六连接段L42(第六连接段L42a、第六连接段L42b和第六连接段L42c)。其中，第六连接段L42a、第五连接段L41a、第六连接段L42b、第五连接段L41b和第六连接段L42c依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第六连接段L42a远离第五连接段L41a的一端与第六测试衬垫P6电连接，第六连接段L42c远离第六连接段L42b的一端与选定驱动电路20电连接。
需要说明的是，如图5B所示，第一子接地线41中还设置有第二开口41B，第五连接段L41a位于第二开口41B内，且第五连接段L41a与第一子接地线41之间不接触，可实现第五连接段L41a与第一子接地线41之间的绝缘，并且，实现了第五连接段L41a跨越第一子电源线31。
示例性地，如图5B所示，与时钟信号线52电连接的信号连接线L4，该信号连接线L4包括位于第一导电层102的一个第五连接段L41＇，和位于第二导电层104的两个第六连接段L42＇(第六连接段L42a＇和第六连接段L42b＇)。其中，第六连接段L42a＇、第五连接段L41＇和第六连接段L42b＇ 依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第六连接段L42a＇远离第五连接段L41＇的一端与第六测试衬垫P6电连接，第六连接段L42b＇远离第五连接段L41＇的一端与选定驱动电路20电连接。
需要说明的是，如图5B所示，第一子接地线41中还设置有第三开口41C，第五连接段L41＇位于第三开口41C内，且第五连接段L41＇与第一子接地线41之间不接触，可实现第五连接段L41＇与第一子接地线41之间的绝缘，并且，实现了第五连接段L41＇跨越第一子电源线31。
示例性地，如图5B所示，与数据信号线53电连接的信号连接线L4，该信号连接线L4包括位于第一导电层102的一个第五连接段L41＂，和位于第二导电层104的两个第六连接段L42＂(第六连接段L42a＂和第六连接段L42b＂)。其中，第六连接段L42a＂、第五连接段L41＂和第六连接段L42b＂依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第六连接段L42a＂远离第五连接段L41＂的一端与第六测试衬垫P6电连接，第六连接段L42b＂远离第五连接段L41＂的一端与选定驱动电路20电连接。
需要说明的是，如图5B所示，第五连接段L41＂位于第三开口41C内，且第五连接段L41＂与第一子接地线41之间不接触，可实现第五连接段L41＂与第一子接地线41之间的绝缘，并且，实现了第五连接段L41＂跨越第一子电源线31。
并且，本公开的一些实施例还提供了一种检测与驱动电路2电连接的级联信号线的电压的方案，以下实施例将对该方案进行描述。
在一些实施例中，如图5A所示，发光基板100还包括多条级联信号线6，沿第一方向X相邻的两个驱动电路2和/或沿第二方向Y相邻的两个驱动电路2之间，通过级联信号线6电连接，驱动电路2输出的级联信号传输至与其电连接的下一级驱动电路2。
示例性地，如图3和图5A所示，驱动电路2还包括级联输入信号端Dis和级联输出信号端Dos，级联信号线6与级联输入信号端Dis电连接，被配置为向该级联输入信号端Dis传输级联输入信号；级联信号线6与级联输出信号端Dos电连接，被配置为将级联输出信号端Dos输出的级联输出信号作为级联输入信号，传输至下一级驱动电路2的级联输入信号端Dis。
结合图1和图5A，多个驱动电路2排列成多列，每列驱动电路2沿第一方向X排列，每相邻的两列驱动电路2为一个级联单元2A。在每个级联单元 2A中，每列驱动电路2通过级联信号线6电连接，沿第二方向Y且由测试区A2指向绑定区A3的相邻两列驱动电路2的第1个驱动电路2，这两个第1个驱动电路2通过级联信号线6(图5中示出的沿第一方向X延伸的级联信号线6)电连接，从而形成级联单元2A。
可以理解的是，如图1所示，沿第二方向Y且由测试区A2指向绑定区A3，其中一列驱动电路2的最后一个驱动电路2为该级联单元2A的第一级驱动电路2 fst，另一列驱动电路2的最后一个驱动电路2为该级联单元2A的最后一级驱动电路2 lst，第一级驱动电路2 fst输出的级联输出信号作为级联输入信号传输至第二级驱动电路，以此类推，直至最后一级驱动电路2 lst接收到级联输入信号。
如图5A所示，发光基板100还包括设置于测试区A2的多个第七测试衬垫P7，每个第七测试衬垫P7与一条级联信号线6电连接。
需要说明的是，图5A示出了两个第七测试衬垫P7，其中一个第七测试衬垫P7与级联信号线6和一个驱动电路2的级联输入信号端Dis电连接，另一个第七测试衬垫P7与级联信号线6和下一级驱动电路2的级联输入信号端Dis电连接。通过位于绑定区的引脚向发光基板100上的电路传输电信号，使得选定驱动电路20及其连接的发光器件组1通过相应的信号线接收到电信号，在此情况下，可采用测试治具对一个第七测试衬垫P7和测试点位TP进行扎针测试，以检测到一个驱动电路2的级联输入信号端Dis的电压值。采用测试治具对另一个第七测试衬垫P7和测试点位TP进行扎针测试，以检测到下一级驱动电路2的级联输入信号端Dis的电压值。
因为相邻两个驱动电路2之间连接有一条级联信号线6，所以相邻两个驱动电路2的级联输入信号端Dis的电压值的差值，大致等于该级联信号线6两端的电压差，进而可根据该电压差调整级联信号线6的设计电阻值，保证级联信号线6向驱动电路2提供的级联输入信号的电压值，可以满足驱动电路2的正常工作。
此外，相较于发光区A1靠近绑定区A3的一侧，发光区A1靠近测试区A2的一侧的信号线的数量较少且排布较简单。如图5A所示，第七测试衬垫P7通过级联信号连接线L5与靠近测试区A2的级联信号线6电连接，级联信号连接线L5需要跨越的信号线的数量较少，降低了级联信号连接线L5的制备难度。
并且，由于第七测试衬垫P7设置于测试区A2，将级联信号连接线L5与与靠近测试区A2的级联信号线6电连接，可缩短级联信号连接线L5的走线 长度。
下面结合发光基板100的膜层结构，对级联信号连接线L5的具体结构进行描述。
在一些实施例中，如图5B所示，第七测试衬垫P7位于第二导电层104。级联信号线6位于第一子接地线41和第一子电源线31的远离第七测试衬垫P7的一侧。因此，级联信号连接线L5需要跨越第一子接地线41和第一子电源线31。
如图5B所示，级联信号连接线L5包括位于第一导电层102的至少一个第七连接段L51，和位于第二导电层104的至少一个第八连接段L52。其中，第七连接段L51在衬底101上的正投影与第一子电源线31在衬底101上的正投影至少部分重叠，从而通过第七连接段L51跨越第一子电源线31。第八连接段L52在衬底101上的正投影与第一子接地线41在衬底101上的正投影至少部分重叠，从而通过第八连接段L52跨越第一子接地线41。
如图1所示，至少一个第七连接段L51和至少一个第八连接段L52中，最靠近第七测试衬垫P7的连接段为第八连接段L52，第七测试衬垫P7与最靠近的第八连接段L52电连接。
可以理解的是，第七测试衬垫P7和第八连接段L52均位于第二导电层104，因此，第七测试衬垫P7与第八连接段L52可以直接电接触。
通过上述级联信号连接线L5的结构设计，可实现级联信号连接线L5跨越第一子电源线31和第一子接地线41。
示例性地，图5B中示出了两个第七测试衬垫P7和两条级联信号连接线L5，其中，位于右侧的级联信号连接线L5包括位于第一导电层102的两个第七连接段L51(第七连接段L51a和第七连接段L51b)，和位于第二导电层104的两个第八连接段L52(第八连接段L52a和第八连接段L52b)。其中，第八连接段L52a、第七连接段L51a、第八连接段L52b和第七连接段L51b依次电连接，相邻两条连接段通过第一绝缘层103中的过孔电连接。
并且，第八连接段L52a远离第七连接段L51a的一端与第七测试衬垫P7电连接，第七连接段L51b远离第八连接段L52b的一端与级联信号线6。
需要说明的是，如图5B所示，第一子接地线41中开设有第四开口41D，第七连接段L51a位于第四开口41D内，且第七连接段L51a与第一子接地线41之间不接触，可实现第七连接段L51a与第一子接地线41之间的绝缘，并且，实现了第七连接段L51a跨越第一子电源线31。
示例性地，如图5B所示，位于左侧的级联信号连接线L5的具体结构， 与位于右侧的级联信号连接线L5的具体结构相同，这里不再详细描述。
根据前文可知，在检测输入信号线5和级联信号线6电压的方案中，均需要测试治具对测试点位TP进行扎针测试，每个测试点位TP与接地线4电连接。下面介绍多个测试点位TP与接地线4的连接方式。
在一些实施例中，如图5A和图5B所示，接地线4包括沿第一方向X延伸的第一子接地线41，以及沿第二方向Y延伸的多条第二子接地线42。其中，第一子接地线41设置于发光区A1靠近测试区A2的一侧，第一子接地线41与多条第二子接地线42电连接。通过第一子接地线41将多条第二子接地线42连接起来，可提高接地线4接地的稳定性。
需要说明的是，在发光基板100上的排布空间允许的情况下，接地线4可以包括多条第一子接地线41，多条第一子接地线41与多条第二子接地线42形成网格结构，可进一步提高接地线4接地的稳定性。
如图5A和图5B所示，第一子接地线41与多条第二子接地线42的靠近测试区A2的一端电连接，多个测试点位TP与第一子接地线41电连接，以实现多个测试点位TP的接地。
在一些实施例中，如图5C所示，第一子接地线41位于第一导电层102，测试点位TP位于第二导电层104，测试点位TP通过第一绝缘层103中的过孔与第一子接地线41电连接。第二绝缘层105开设有暴露测试点位TP的第一测试孔H1。
通过上述设置方式，在检测的过程中，测试治具的针脚可穿过第一测试孔H1，与位于第二导电层104的测试点位TP电接触，从而可实现扎针测试。
在一些实施例中，如图5D所示，测试点位TP为贯穿第一绝缘层103和第二绝缘层105的第二测试孔H2，第二测试孔H2暴露第一子接地线41。
可以理解的是，测试点位TP没有采用导电层制备，而是以第二测试孔H2的形式贯穿第一绝缘层103和第二绝缘层105并暴露第一子接地线41。在检测的过程中，测试治具的针脚可穿过第二测试孔H2，直接与位于第一导电层102的第一子接地线41电接触，从而可实现扎针测试。
在一些实施例中，如图5A和图5B所示，接地线4还包括多条第三子接地线43和多个连接图案44。其中，每个连接图案44电连接相邻两条第二子接地线42，且与驱动电路2电连接。第三子接地线43沿第二方向Y延伸，每条第三子接地线43与至少一个连接图案44电连接，且第三子接地线43靠近测试区A2的一端与第一子接地线41电连接。
通过上述设置方式，可提高接地线4的网格结构的网格密度，从而可进 一步提高接地线4的接地稳定性。
并且，本公开的一些实施例还提供了一种检测电源线3中的电压的方案，以下实施例将对该方案进行描述。
如图5B所示，电源线3位于第二导电层104，第二绝缘层105开设有暴露电源线3的第三测试孔H3。第二导电层104还包括多条第二子接地线42，第二绝缘层105开设有暴露第二子接地线42的第四测试孔H4。
通过上述设置方式，在检测的过程中，测试治具的一个针脚可穿过第三测试孔H3，与位于第二导电层104的电源线3的第二子电源线32电接触。并且，测试治具的另一个针脚可穿过第四测试孔H4，与位于第二导电层104的第二子接地线42电接触，从而可检测到电源线3对应位置与第二子接地线42对应位置中的电压差值，从而通过计算得到该电压差值与标准电压差值的差异，进而可根据该差异调整电源线3和/或接地线4的设计电阻值，或对电源线3的输入电压进行补偿，以保证发光器件的正常发光。
或者，在检测的过程中，测试治具的一个针脚可穿过第三测试孔H3，与位于第二导电层104的电源线3的第二子电源线32电接触。并且，测试治具的另一个针脚可与测试点位TP电接触，从而可检测到电源线3中的电压值。
并且，本公开的一些实施例还提供了一种检测与驱动电路2电连接的输出信号线的电压的方案，以下实施例将对该方案进行描述。
如图5B所示，第二导电层104包括多条输出信号线7，每条输出信号线7电连接发光器件组1与对应的驱动电路2，通过输出信号线7将驱动电路2的输出信号传输至驱动电路2，以驱动发光器件组1发光。
如图5B所示，第二导电层104还包括多个导电测试图案8，每条输出信号线7还与一个导电测试图案8电连接。第二绝缘层105开设有暴露导电测试图案8的第五测试孔H5。
通过上述设置方式，在检测的过程中，测试治具的一个针脚可穿过第五测试孔H5，与位于第二导电层104的导电测试图案8电接触。并且，测试治具的另一个针脚可穿过第四测试孔H4，与位于第二导电层104的第二子接地线42电接触，从而可检测到输出信号线7中的电压值，从而通过计算得到输出信号线7中的压降，进而可根据该压降调整输出信号线7的设计电阻值，以保证发光器件的正常发光。
此外，本公开的一些实施例还提供了一种检测传感器电源线和传感器连接线的电压的方案，以下实施例将对该方案进行描述。
如图2B、2D和图2E所示，发光基板100还包括多个传感器S，沿第二 方向Y延伸的传感器电源线S1，以及沿第二方向Y延伸的多条传感器连接线S2。
多个传感器S排列成多列，每列传感器S沿第二方向Y排列。每列传感器S与一条传感器电源线S1电连接，传感器电源线S1向与其电连接的传感器S提供电能。在每列传感器S中，相邻两个传感器S之间通过传感器连接线S2电连接。
示例性地，传感器S可以是温度传感器，可用于检测发光基板100的工作温度。
如图2B、2D和图2E所示，发光基板100还包括设置于测试区A2的多个第八测试衬垫P8，至少一个第八测试衬垫P8与传感器电源线S1电连接，至少一个第八测试衬垫P8与传感器连接线S2电连接。
本公开的上述实施例的发光基板100中，通过位于绑定区的引脚向发光基板100上的电路传输电信号，使得选定驱动电路20及其连接的发光器件组1通过相应的信号线接收到电信号，在此情况下，采用测试治具对第八测试衬垫P8(与传感器电源线S1电连接)和测试点位TP进行扎针测试，可检测到传感器电源线S1的电压值(传感器电源线S1的远离绑定区A3一端的电压值)。
根据检测到的传感器电源线S1的远离绑定区A3一端的电压值，以及传感器电源线S1在绑定区A3接收到的信号的电压值，可以计算得到传感器电源线S1靠近绑定区A3的一端与远离绑定区A3的一端的压降，进而可根据该压降调整传感器电源线S1的设计电阻值，保证传感器电源线S1向传感器S提供的输入信号的电压值，可以满足传感器S的正常工作。
同理，采用测试治具对第八测试衬垫P8(与传感器连接线S2电连接)和测试点位TP进行扎针测试，可检测到传感器连接线S2的电压值，以便于调整传感器连接线S2的设计电阻值。
本公开的一些实施例还提供了一种背光模组，如图6所示，背光模组200包括上述任一实施例所述的发光基板100。
示例性地，发光基板100为Mini LED发光基板，背光模组200为Mini LED背光模组。
本公开的上述实施例的背光模组200，可方便检测到电路中的电压和电流信息，以便于对电压和电流信息进行监控。
本公开的一些实施例还提供了一种显示装置，如图7A和图7B所示，显示装置300包括显示面板301，以及上述实施例中的背光模组200，显示面板 301设置于背光模组200的出光侧E，可采用背光模组200为显示面板301提供背光源。
上述显示装置300可以为液晶显示装置(Liquid Crystal Display，简称LCD)。
本公开的上述实施例中的显示装置300所能实现的有益效果，与上述背光模组200所能达到的有益效果相同，可方便检测到电路中的电压和电流信息，以便于对电压和电流信息进行监控。
上述显示装置300可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种发光基板，包括发光区，以及位于所述发光区至少一侧的测试区；
    所述发光基板包括：
    多个发光器件组，设置于所述发光区；
    多个驱动电路，设置于所述发光区，每个驱动电路与至少一个发光器件组电连接；所述多个驱动电路包括选定驱动电路，所述选定驱动电路包括至少一个第一类输出端和至少一个第二类输出端，所述第一类输出端与所述发光器件组电连接；
    电源线，与所述多个发光器件组电连接；
    第一测试衬垫和第二测试衬垫，设置于所述测试区；所述第一测试衬垫与所述选定驱动电路的第二类输出端电连接，所述第二测试衬垫与所述电源线电连接；
    第一测试器件组，与所述第一测试衬垫和所述第二测试衬垫电连接。
  2. 根据权利要求1所述的发光基板，其中，所述多个发光器件组和所述多个驱动电路均排列成多行，每行发光器件组和每行驱动电路均沿第一方向排列；
    所述发光基板还包括绑定区，所述绑定区和所述测试区分别位于所述发光区沿第二方向的相对两侧；
    沿第二方向且由所述测试区指向所述绑定区，多行发光器件组分别为第1行～第M行发光器件组，多行驱动电路分别为第1行～第N行驱动电路，M和N为大于或等于2的整数；第1行发光器件组与第1行驱动电路电连接，第1行驱动电路包括所述选定驱动电路。
  3. 根据权利要求2所述的发光基板，其中，所述选定驱动电路包括两个第一类输出端和两个第二类输出端；
    所述两个第一类输出端分别与第1行发光器件组中的相邻两个发光器件组电连接；
    所述两个第二类输出端中的任一者与所述第一测试衬垫电连接。
  4. 根据权利要求2或3所述的发光基板，其中，第2行～第M行发光器件组包括多个器件单元，每个器件单元包括相邻的两行发光器件组，所述器件单元与第2行～第N行驱动电路中的一行驱动电路电连接；
    所述驱动电路包括四个输出端，分别与所述器件单元中的四个发光器件组电连接。
  5. 根据权利要求1～4中任一项所述的发光基板，其中，所述电源线包括：
    第一子电源线，沿第一方向延伸，设置于所述发光区靠近所述测试区的 一侧；
    多条第二子电源线，沿第二方向延伸，且与所述第一子电源线电连接；
    其中，所述发光基板还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧，所述第一子电源线与所述多条第二子电源线的靠近所述测试区的一端电连接；
    所述第二测试衬垫与所述第一子电源线电连接。
  6. 根据权利要求5所述的发光基板，还包括：
    第一连接线，一端与所述第一测试衬垫电连接，另一端与所述选定驱动电路电连接；
    第二连接线，一端与所述第二测试衬垫电连接，另一端与所述第一子电源线电连接。
  7. 根据权利要求6所述的发光基板，包括衬底，及依次层叠设置于所述衬底上的第一导电层和第二导电层；所述第一导电层包括沿第一方向延伸的第一子接地线，所述第一子接地线位于所述发光区靠近所述测试区的一侧；所述第一子电源线和所述第一测试衬垫位于所述第二导电层；
    所述选定驱动电路位于所述第一子接地线和所述第一子电源线的远离所述第一测试衬垫的一侧；
    所述第一连接线包括位于所述第一导电层的至少一个第一连接段，和位于所述第二导电层的至少一个第二连接段，所述第一连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第二连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至少部分重叠；
    所述至少一个第一连接段和所述至少一个第二连接段中，最靠近所述第一测试衬垫的连接段为第二连接段，所述第一测试衬垫与最靠近的第二连接段电连接。
  8. 根据权利要求6或7所述的发光基板，其中，所述第二连接线大致沿第二方向延伸，且所述第二连接线和所述第一子电源线的材料相同且同层设置。
  9. 根据权利要求1～8中任一项所述的发光基板，其中，所述第一测试器件组包括测试发光器件和/或电阻器。
  10. 根据权利要求9所述的发光基板，其中，所述第一测试器件组包括测试发光器件和电阻器；
    所述发光基板还包括：
    第三测试衬垫，所述测试发光器件的一端与所述第一测试衬垫电连接，另一端与所述第三测试衬垫电连接；所述电阻器的一端与所述第二测试衬垫电连接，另一端与所述第三测试衬垫电连接。
  11. 根据权利要求1～10中任一项所述的发光基板，其中，所述发光器件组包括多个发光器件和多条走线，所述多个发光器件通过所述多条走线串联设置；
    所述发光基板还包括：
    第四测试衬垫和第五测试衬垫，设置于所述测试区；所述第四测试衬垫和所述第五测试衬垫分别与同一条走线电连接；所述走线中，位于所述第四测试衬垫与所述走线电连接的位置，与，所述第五测试衬垫与所述走线电连接的位置之间的部分断开；
    第二测试器件组，与所述第四测试衬垫和所述第五测试衬垫电连接。
  12. 根据权利要求11所述的发光基板，还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧；
    所述多个发光器件组排列成多行，每行发光器件组沿第一方向排列；沿第二方向且由所述测试区指向所述绑定区，多行发光器件组分别为第1行～第M行发光器件组；
    所述第四测试衬垫和所述第五测试衬垫均与第1行发光器件组中的任一条走线电连接。
  13. 根据权利要求12所述的发光基板，还包括：
    两条第三连接线，其中一条第三连接线的一端与所述第四测试衬垫电连接，另一端与所述走线电连接；另一条第三连接线的一端与所述第五测试衬垫电连接，另一端与所述走线电连接。
  14. 根据权利要求13所述的发光基板，包括依次层叠设置的第一导电层和第二导电层，所述第一导电层包括沿第一方向延伸的第一子接地线，所述第二导电层包括沿第一方向延伸的第一子电源线；所述第四测试衬垫和所述第五测试衬垫位于所述第二导电层；
    所述第四测试衬垫和所述第五测试衬垫均位于所述第一子接地线和所述第一子电源线的远离所述走线的一侧；
    所述第三连接线包括位于所述第一导电层的至少一个第三连接段，和位于所述第二导电层的至少一个第四连接段，所述第三连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第四连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至 少部分重叠；
    一条第三连接线的至少一个第三连接段和至少一个第四连接段中，最靠近所述第四测试衬垫的连接段为第四连接段，所述第四测试衬垫与最靠近的第四连接段电连接；
    另一条第三连接线的至少一个第三连接段和至少一个第四连接段中，最靠近所述第五测试衬垫的连接段为第四连接段，所述第五测试衬垫与最靠近的第四连接段电连接。
  15. 根据权利要求1～14中任一项所述的发光基板，还包括：
    至少一条输入信号线，沿第二方向延伸，且与所述多个驱动电路电连接；
    接地线，与所述多个驱动电路电连接；
    至少一个第六测试衬垫，设置于所述测试区，每个第六测试衬垫与一条输入信号线电连接；
    至少一个测试点位，设置于所述发光区，与所述接地线电连接。
  16. 根据权利要求15所述的发光基板，还包括绑定区，所述绑定区和所述测试区分别位于所述发光区沿第二方向的相对两侧；
    所述发光基板还包括：
    信号连接线，一端与所述第六测试衬垫电连接，另一端与所述输入信号线的靠近所述测试区的一端电连接。
  17. 根据权利要求16所述的发光基板，包括依次层叠设置的第一导电层和第二导电层，所述第一导电层包括沿第一方向延伸的第一子接地线，所述第二导电层包括沿第一方向延伸的第一子电源线；所述第六测试衬垫位于所述第二导电层；
    所述选定驱动电路位于所述第一子接地线和所述第一子电源线的远离所述第六测试衬垫的一侧；
    所述信号连接线包括位于所述第一导电层的至少一个第五连接段，和位于所述第二导电层的至少一个第六连接段，所述第五连接段在所述衬底上的正投影与所述第一子电源线在所述衬底上的正投影至少部分重叠，所述第六连接段在所述衬底上的正投影与所述第一子接地线在所述衬底上的正投影至少部分重叠；
    所述至少一个第五连接段和所述至少一个第六连接段中，最靠近所述第六测试衬垫的连接段为第六连接段，所述第六测试衬垫与最靠近的第六连接段电连接。
  18. 根据权利要求15～17中任一项所述的发光基板，其中，所述至少一 条输入信号线包括电源电压信号线、时钟信号线和数据信号线中的至少一种。
  19. 根据权利要求15～18中任一项所述的发光基板，还包括：
    多条级联信号线，沿第一方向相邻的两个驱动电路和/或沿第二方向相邻的两个驱动电路之间，通过级联信号线电连接；
    多个第七测试衬垫，设置于所述测试区，每个第七测试衬垫与一条级联信号线电连接。
  20. 根据权利要求15～19中任一项所述的发光基板，其中，所述接地线包括：
    第一子接地线，沿第一方向延伸，设置于所述发光区靠近所述测试区的一侧；
    多条第二子接地线，沿第二方向延伸，且与所述第一子接地线电连接；
    其中，所述发光基板还包括绑定区，所述测试区和所述绑定区分别位于所述发光区沿第二方向的相对两侧，所述第一子接地线与所述多条第二子接地线的靠近所述测试区的一端电连接；
    所述多个测试点位与所述第一子接地线电连接。
  21. 根据权利要求20所述的发光基板，包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层；
    所述第一子接地线位于所述第一导电层，所述测试点位位于所述第二导电层；所述测试点位通过所述第一绝缘层中的过孔与所述第一子接地线电连接；所述第二绝缘层开设有暴露所述测试点位的第一测试孔；或，
    所述测试点位为贯穿所述第一绝缘层和所述第二绝缘层的第二测试孔，所述第二测试孔暴露所述第一子接地线。
  22. 根据权利要求20或21所述的发光基板，其中，所述接地线还包括：
    多个连接图案，每个连接图案电连接相邻两条第二子接地线，且与所述驱动电路电连接；
    多条第三子接地线，沿第二方向延伸；每条第三子接地线与至少一个连接图案电连接，且所述第三子接地线靠近所述测试区的一端与所述第一子接地线电连接。
  23. 根据权利要求1～22中任一项所述的发光基板，包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层；
    所述电源线位于所述第二导电层，所述第二绝缘层开设有暴露所述电源线的第三测试孔；
    所述第二导电层还包括多条第二子接地线，所述第二绝缘层开设有暴露 所述第二子接地线的第四测试孔。
  24. 根据权利要求1～23中任一项所述的发光基板，包括依次层叠设置的第一导电层、第一绝缘层、第二导电层和第二绝缘层；
    所述第二导电层包括多条输出信号线和多个导电测试图案；每条输出信号线电连接所述发光器件组与对应的驱动电路，且与一个导电测试图案电连接；所述第二绝缘层开设有暴露所述导电测试图案的第五测试孔。
  25. 一种背光模组，包括如权利要求1～24中任一项所述的发光基板。
  26. 一种显示装置，包括：
    显示面板；
    如权利要求25所述的背光模组，所述显示面板设置于所述背光模组的出光侧。
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Citations (3)

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Publication number Priority date Publication date Assignee Title
CN211654192U (zh) * 2020-05-13 2020-10-09 京东方科技集团股份有限公司 阵列基板及拼接显示面板
CN112750397A (zh) * 2019-10-31 2021-05-04 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN113130463A (zh) * 2021-04-16 2021-07-16 京东方科技集团股份有限公司 一种发光基板及其制备方法、显示装置

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Publication number Priority date Publication date Assignee Title
CN112750397A (zh) * 2019-10-31 2021-05-04 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN211654192U (zh) * 2020-05-13 2020-10-09 京东方科技集团股份有限公司 阵列基板及拼接显示面板
CN113130463A (zh) * 2021-04-16 2021-07-16 京东方科技集团股份有限公司 一种发光基板及其制备方法、显示装置

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