WO2023024764A1 - Power management circuit and control method and system thereof - Google Patents

Abstract

Disclosed are a power management circuit and a control method and system thereof; the power management circuit comprises: a first power management chip and a reserved resistor position; the first power management chip comprises a state machine module, a first control pin and a first power pin; two ends of the reserved resistor position are respectively connected to the first control pin and to the first power pin; wherein, the state machine module is configured to trigger a power-on function or a reset function of the first power management chip via the first control pin when a first resistor is attached to the reserved resistor position; or, when the first resistor is not attached to the reserved resistor position, the state machine module is configured to trigger a power-on function or a reset function of the first power management chip by means of an external control module and the first control pin. Three pins in a first power management chip are combined into a single control pin, thus reducing chip area and manufacturing costs, and further reducing the risk of interference with key signals and improving system stability.

Description

A power management circuit and its control method and system

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202110983933.7 and the application name "A power management circuit and its control method and system" submitted to the China Patent Office on August 25, 2021, the entire contents of which are incorporated by reference in this application.

technical field

The present application relates to the technical field of power management, in particular to a power management circuit and its control method and system.

Background technique

The baseband chip (Baseband IC, BBIC) refers to the chip used to synthesize the baseband signal to be transmitted, or to decode the received baseband signal, which mainly completes the information processing function of the terminal equipment.

At present, BBIC generally uses a dedicated Baseband Power Management IC (BB_PMIC) to power and control it. In order to implement multiple control methods on the BB_PMIC, the control pins of the BB_PMIC will at least include three independent power key signal pins (PON), enable signal pins (EN), and reset signal pins (RESETIN). control pins, and their control logic varies. However, since BB_PMIC separately sets three control pins with different control logics, the chip area of BB_PMIC is relatively large, and the manufacturing cost is relatively high; moreover, these control signals are key signals of the system, and are easy to be manipulated on the circuit board. Other signal interference directly affects the system stability.

Contents of the invention

The technical scheme of the present application is realized like this:

In the first aspect, the embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control pin and a second A power supply pin, the two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein,

The state machine module is used to trigger the power-on function or reset function of the first power management chip through the first control pin when the first resistor is mounted on the reserved resistance position; or, if the reserved resistance position is not mounted In the case of the first resistor, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

In the second aspect, the embodiment of the present application provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; the method includes:

Detecting the signal level state at the first control pin through the state machine module;

According to the state of the signal level, it is determined to be applied to an independent power management circuit or a combined power management circuit;

When it is determined to be applied to an independent power management circuit, the power-on function or reset function of the first power management chip is triggered through the first control pin;

When it is determined to be applied to the combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

In the third aspect, the embodiment of the present application provides a power management system, the power management system at least includes the power management circuit and the baseband chip as described in the first aspect; power-up or reset control.

Description of drawings

FIG. 1 is a schematic diagram of the internal composition structure of a BB_PMIC;

Fig. 2 provides a schematic diagram of the composition structure of a BBIC independent system;

Fig. 3 provides a schematic diagram of the composition structure of a BBIC combined system;

FIG. 4 is a schematic diagram of the composition and structure of a power management circuit provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of the composition and structure of another power management circuit provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of the composition and structure of an independent power management circuit provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of the composition and structure of a combined power management circuit provided by an embodiment of the present application;

FIG. 8 is a schematic flowchart of a power control method provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of the composition and structure of a power management system provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of the composition and structure of an independent power management system provided by the embodiment of the present application;

FIG. 11 is a schematic diagram of the composition and structure of a combined power management system provided by an embodiment of the present application;

FIG. 12 is a schematic flowchart of a detailed power control method provided by an embodiment of the present application.

Detailed ways

In the first aspect, the embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control tube pin and the first power supply pin, and the two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein,

The state machine module is configured to trigger the power-on function or reset function of the first power management chip through the first control pin when the first resistor is mounted at the reserved resistor position; or, In the case that no first resistor is attached to the reserved resistor position, the power-on function or reset function of the first power management chip is triggered through an external control module and the first control pin.

In some embodiments, the first power management chip further includes a first conversion circuit and a second power pin, and the second power pin is connected to an external power supply; wherein,

The second power supply pin is used to provide an input voltage for the first power management chip;

The first conversion circuit is configured to perform voltage conversion on the input voltage to generate a supply voltage;

The first power supply pin is specifically used to receive the power supply voltage, and supply power to the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module.

In some embodiments, the first conversion circuit is a low dropout linear regulator LDO circuit.

In some embodiments, when the first resistor is mounted at the reserved resistor position, the signal level state at the first control pin is the first level state; or, the reserved resistor In the case where the first resistor is not mounted, the signal level state at the first control pin is the second level state.

In some embodiments, the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein,

The state machine module is further configured to determine to apply to the independent power management circuit if it is detected that the signal level state at the first control pin is the first level state; or, if it is detected that If the signal level state at the first control pin is the second level state, it is determined to be applied to the combined power management circuit;

Wherein, the independent power management circuit is composed of the power management circuit alone, and the combined power management circuit is composed of the power management circuit and the external control module.

In some embodiments, the independent power management circuit includes the first power management chip and the first resistor, and the two ends of the first resistor are respectively connected to the first control pin and the first power pin connections; where,

The state machine module is specifically configured to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the first power supply is triggered. Manage the power-on function or reset function of the chip.

In some embodiments, the independent power management circuit further includes a power key, one end of the power key is connected to the first control pin, and the other end of the power key is grounded; wherein,

The power key is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the After the second level state lasts for a first preset time, the power-on operation of the first power management chip is triggered to realize the power-on function.

In some embodiments, the power key is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction. level state, and after the second level state lasts for a second preset time, trigger a power-off and restart operation of the first power management chip, so as to realize the reset function.

In some embodiments, the first preset time is shorter than the second preset time.

In some embodiments, the combined power management circuit includes the first power management chip and the external control module, the external control module includes a second power management chip and an application processor, and the second power management chip Including a second control pin and a general-purpose input and output pin, the general-purpose input and output pin is connected to the first control pin; wherein,

The state machine module is specifically configured to configure the function of the first control pin to enable a reset function, so that when the signal level state at the first control pin changes, trigger the first The power-on function or reset function of the power management chip.

In some embodiments, the combined power management circuit further includes a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein,

The power key is used to control the second power management chip to start powering on when receiving the third operation instruction;

The second power management chip is configured to control the signal level at the first control pin to be adjusted from the second level state to the The first level state triggers the power-on operation of the first power management chip to realize the power-on function.

In some embodiments, the application processor is configured to send a reset command to the second power management chip;

The second power management chip is further configured to control the signal level at the first control pin to be adjusted from the first level state to the The second level state triggers the power-off operation of the first power management chip; and after the third preset time, controls the signal level at the first control pin again through the general-purpose input and output pin Adjusting from the second level state to the first level state triggers a power-on operation of the first power management chip to realize the reset function.

In some embodiments, the first level state is high level, and the second level state is low level.

In the second aspect, the embodiment of the present application provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; the method includes:

Detecting the signal level state at the first control pin through the state machine module;

Determine to apply to the independent power management circuit or the combined power management circuit according to the signal level state;

When it is determined to be applied to the independent power management circuit, triggering a power-on function or a reset function of the first power management chip through the first control pin;

When it is determined to be applied to the combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

In some embodiments, the determining to apply to the independent power management circuit or the combined power management circuit according to the signal level state includes:

If it is detected that the signal level state is the first level state, it is determined to be applied to the independent power management circuit; or,

If it is detected that the signal level state is the second level state, it is determined to be applied to the combined power management circuit.

In some embodiments, before the state machine module detects the signal level state at the first control pin, the method further includes:

In the case of mounting the first resistor at the reserved resistor position, determine that the signal level state at the first control pin is the first level state; or,

If the first resistor is not installed in the reserved resistor position, it is determined that the signal level state at the first control pin is the second level state.

In some embodiments, the first level state is high level, and the second level state is low level.

In some embodiments, before the state machine module detects the signal level state at the first control pin, the method further includes:

receiving an input voltage provided by an external power supply for the first power management chip;

performing voltage conversion on the input voltage to generate a supply voltage;

Powering the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module.

In some embodiments, when it is determined to be applied to the independent power management circuit, the triggering the power-on function or reset function of the first power management chip through the first control pin includes:

When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and the second level state lasts for the first preset After a period of time, trigger the power-on operation of the first power management chip to realize the power-on function; or,

When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and continue in the second level state After a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.

In some embodiments, the first preset time is shorter than the second preset time.

In some embodiments, when it is determined to be applied to the combined power management circuit, the triggering the power-on function or reset function of the first power management chip through the external control module and the first control pin includes:

According to receiving the third operation instruction, after the second power management chip starts to be powered on, control the signal level at the first control pin to be adjusted from the second level state to the first level state, triggering a power-on operation of the first power management chip to realize the power-on function; or,

After the second power management chip receives the reset command sent by the application processor, control the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the power-off operation of the first power management chip; and controlling the signal level at the first control pin to be adjusted from the second level state to the first power level state again after a third preset time In the flat state, trigger the power-on operation of the first power management chip to realize the reset function.

In the third aspect, the embodiment of the present application provides a power management system, the power management system at least includes the power management circuit and the baseband chip according to any one of the first aspect; wherein, the power management circuit is the The baseband chip is powered on or reset controlled.

In order to understand the features and technical content of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict. It should also be pointed out that the term "first\second\third" involved in the embodiment of the present application is only used to distinguish similar objects, and does not represent a specific ordering of objects. Understandably, "first\second\ The specific order or sequence of "third" can be interchanged where allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

With the continuous development of electronic technology, terminal devices such as smart phones and handheld computers are becoming more and more popular. At present, the baseband chip (Baseband IC, BBIC) of the terminal platform generally has two application scenarios. One application scenario is to form a system together with an application processor (Application Processor, AP), such as applied to terminal equipment; the other One application scenario is that BBIC independently forms a system, for example, it is applied to Customer Premise Equipment (CPE).

Here, BBIC generally uses a dedicated baseband power management IC (BB_PMIC) to power and control it. For the above two application scenarios, the control logic of BB_PMIC's power-on and reset is completely different. In order to implement multiple control methods on the BB_PMIC, the current control pins of the BB_PMIC include three independent pins, PON, EN, and RESETIN, and their control logics are also different.

Referring to FIG. 1 , it provides a schematic diagram of the internal structure of the BB_PMIC. As shown in Figure 1, the BB_PMIC includes a first conversion circuit, a state machine module, a second conversion circuit and a first pin (Vsys), a second pin (VPMIC), a third pin (PON), a fourth pin (EN) and the fifth pin (RESETIN). Wherein, the first pin (Vsys) is connected to an external power supply (indicated by Vsys power supply), and the second pin (VPMIC) is connected to an external capacitor (indicated by C1).

Vsys power supply: The input power of BB_PMIC is generally powered by the battery in the terminal device.

The first transformation circuit: performs voltage transformation on the input voltage Vsys, and outputs a VPMIC voltage. In the embodiment of the present application, the first conversion circuit may be a low dropout regulator (Low Dropout Regulator, LDO) circuit.

The second conversion circuit: performs voltage conversion on the input voltage Vsys, converts it into a voltage available to the BBIC and outputs it. In the embodiment of the present application, the second conversion circuit may be a DC conversion (Direct Current-Direct Current, DC-DC) circuit.

VPMIC voltage: It is obtained by transforming the input voltage Vsys through the LDO circuit, and supplies power to the digital circuit inside the PMIC. In addition, a capacitor C1 is externally connected to the second pin (VPMIC), which can function as a filter.

State machine module: realize the control logic of PMIC, and control the power-on/power-off sequence of the DC-DC circuit.

PON: Power key signal, default high level. After the level is pulled low for a period of time (eg T1), the state machine module triggers the power-on sequence to control the power-on of the DC-DC circuit, and BB_PMIC starts the power-on process.

EN: Enable signal, low level when power off. When the level is pulled high, the state machine module immediately triggers the power-on sequence, controls the power-on of the DC-DC circuit, and BB_PMIC starts the power-on process.

RESETIN: reset signal, when BB_PMIC is working normally, keep high level. When the level is pulled low, the state machine module triggers the power-off sequence to control the power-off of the DC-DC circuit, and the BBIC is powered-off and reset.

The related technologies will be described below in combination with the system block diagrams of the two application scenarios.

(1) BBIC constitutes a separate system

When applied to an independent scenario, the BBIC alone forms a system at this time, that is, the block diagram corresponding to the BBIC independent system is shown in Figure 2 . The system block diagram may include a first power management chip (BB_PMIC), a baseband chip (BBIC), a power button and a reset button.

Among them, the power key is connected to the PON pin of BB_PMIC, the reset key is connected to the RESETIN pin, and the EN pin is suspended. After the user presses the power button for a period of time (such as T1), the BB_PMIC power-on sequence is triggered to supply power to the BBIC.

In the case of booting, if the BBIC works abnormally, such as the software running dead, unable to shut down or restart the system through the software, the user can force reset the BB_PMIC by pressing the reset button, trigger the power-off sequence of the BB_PMIC, and then power off the BBIC , to complete the reset and restart of the BBIC.

(2) AP+BBIC jointly form a system

When applied to a combination scenario, the BBIC is used in conjunction with the AP at this time, for example, it is applied to a terminal device, that is, a corresponding block diagram of the BBIC combination system is shown in FIG. 3 . The system block diagram may include a first power management chip (BB_PMIC), a baseband chip (BBIC), an application processor (AP), a second power management chip (Main_PMIC) and a power key.

Among them, the AP is the application processor of the terminal device, and Main_PMIC is the main power management chip of the terminal device, which is responsible for powering on and off of the terminal device and supplying power to the AP. The power button is hung on Main_PMIC, and BB_PMIC needs to be powered on by Main_PMIC. Since there is a strict power-on sequence relationship between Main_PMIC and BB_PMIC, in order to strictly control the sequence, the power-on control signal sent by Main_PMIC needs to immediately trigger the power-on of BB_PMIC without delay, so the PON pin control of BB_PMIC cannot be used at this time To power on BB_PMIC, you need to use the EN signal of BB_PMIC to control the power on of BB_PMIC. In addition, the power button of the terminal device is connected to the PON pin of Main_PMIC. Main_PMIC also includes two general-purpose input/output (General-Purpose Input/Output, GPIO) pins: GPIO_01 pin and GPIO_02 pin; among them, the GPIO_01 pin is connected to the RESETIN pin of BB_PMIC to control the reset of BB_PMIC; GPIO_02 The pin is connected to the EN pin of BB_PMIC to control the power-on enable of BB_PMIC. The PON pin of BB_PMIC is left floating and not used.

After the user presses the power button for a period of time (such as T1), Main_PMIC triggers the boot process, outputs power to supply power to the AP, and pulls up the EN pin of BB_PMIC by pulling up the level of the GPIO_02 pin. At this time, BB_PMIC The power-on sequence is triggered immediately, and the BBIC is powered on and started.

When the AP detects that the BBIC software is running dead, or the BBIC cannot be restarted through the software, the AP will notify the Main_PMIC, specifically by pulling down the level of the GPIO_01 pin, and then pull down the RESETIN pin of the BB_PMIC. At this time, the BB_PMIC is reset. , trigger the BB_PMIC power-off sequence, and BBIC power-off and restart.

It can be seen that, in related technologies, BB_PMIC separately sets three control pins with different control logics (specifically including: PON pin, EN pin and RESETIN pin), so as to achieve the purpose of application in different scenarios. If the functions of these control pins can be combined into one pin, then the number of chip pins can be reduced, thereby reducing the chip area, and the chip area directly determines the manufacturing cost of the chip, so if the chip can be reduced The number of feet can reduce the cost. In addition, these control signals are key signals of the system. If these control signals are interfered by other signals on the circuit board, it will directly affect the stability of the system. The greater the number of signals, the greater the possibility of interference; therefore, if you can Combining pins to reduce the number of key signals on the board can also reduce the risk of interference and enhance system stability.

Based on this, an embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control pin and a first The two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein, the state machine module is used to mount the first resistance at the reserved resistance position, through the second A control pin triggers the power-on function or reset function of the first power management chip; or, in the case where the first resistor is not mounted in the reserved resistance position, triggers the first power management through the external control module and the first control pin The power-on function or reset function of the chip. In this way, since the three pins of the power key signal pin (PON), the enable signal pin (EN) and the reset signal pin (RESETIN) in BB_PMIC are combined into one control pin, it is not only possible to reduce the BB_PMIC The chip area saves manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

Various embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, refer to FIG. 4 , which shows a schematic structural diagram of a power management circuit provided by an embodiment of the present application. As shown in Figure 4, the power management circuit 40 may include a first power management chip 41 and a reserved resistor position 42, and the first power management chip 41 may include a state machine module 411, a first control pin and a first power tube pin, and the two ends of the reserved resistance position 42 are respectively connected to the first control pin and the first power supply pin; wherein,

The state machine module 411 is used to trigger the power-on function or reset function of the first power management chip 41 through the first control pin when the first resistor R1 is mounted on the reserved resistor position 42; If the first resistor R1 is not installed at the position 42, the power-on function or reset function of the first power management chip 41 is triggered through the external control module and the first control pin.

It should be noted that the power management circuit 40 of the embodiment of the present application can adapt to different application scenarios according to whether the first resistor R1 is mounted on the reserved resistor position 42 . In Fig. 4, if the first resistor R1 is mounted on the reserved resistance position 42, then the first control pin can be pulled up to the level state of the first power supply pin; otherwise, if the reserved resistance position 42 is not pasted Install the first resistor R1, then the first control pin is in a floating state at this time. That is to say, by selecting whether to mount the first resistor R1 at the reserved resistor position 42 , the application scenario of the power management circuit 40 can be identified by the state machine module 411 .

It should also be noted that the power management circuit 40 of the embodiment of the present application realizes the combination of three pins PON, EN and RESETIN on the first power management chip 41 into one first control pin (indicated by PON). It is mainly by setting different components (such as the first resistor R1) on the circuit board, so that the application scene corresponding to the power management circuit 40 can be identified when the state machine module 411 is initialized, and then the state machine module can be used to 411 assigns different control logics to the first control pins to implement different control functions, so that multiple control logics can be implemented on one pin (ie, the first control pin).

In some embodiments, on the basis of the power management circuit 40 shown in FIG. 4, referring to FIG. 5, the first power management chip 41 may further include a first conversion circuit 412 and a second power pin; wherein,

The second power supply pin is connected to an external power supply, and is used to provide an input voltage for the first power management chip;

The first conversion circuit 412 is configured to perform voltage conversion on the input voltage to generate a supply voltage;

The first power supply pin is used to receive the power supply voltage, and supply power to the state machine module 411 according to the power supply voltage, so as to realize the initialization of the state machine module 411 .

In a specific example, the first conversion circuit 412 may be an LDO circuit.

It should be noted that, in this embodiment of the application, the external power supply can be represented by Vsys power supply, the first control pin can be represented by PON pin, the first power supply pin can be represented by VPMIC pin, and the second power supply pin can be represented by Represented by the Vsys pin.

It should also be noted that the second power supply pin is connected to the Vsys power supply. At this time, the input voltage provided for the first power management chip 41 can be represented by the Vsys voltage; and the power supply voltage generated by the first conversion circuit 412 can be represented by the VPMIC voltage. express. In this way, after the voltage of Vsys is established, the voltage of VPMIC is established, and the initialization of the state machine module 411 can be implemented at this time.

Further, in some embodiments, referring to FIG. 5 , the power management circuit 40 may further include a first capacitor C1; wherein, one end of the first capacitor C1 is connected to the first power supply pin, and the other end of the first capacitor C1 is grounded. . Here, the first capacitor C1 mainly functions to filter the VPMIC voltage at the first power supply pin.

Further, in some embodiments, referring to FIG. 5 , the first power management chip 41 may also include a second conversion circuit 413; wherein,

The state machine module 411 is further configured to generate a control power supply sequence according to the signal level state at the first control pin;

The second conversion circuit 413 is configured to perform voltage conversion on the input voltage according to the control power sequence to generate a target voltage.

In a specific example, the second conversion circuit 413 may be a DC-DC circuit.

It should be noted that the first power management chip 41 may be a baseband power management chip (BB_PMIC). In this way, in the power management system, in addition to the power management circuit 40, a baseband chip (BBIC) can also be included, wherein the first power management chip 41 can supply power and power control for the baseband chip (BBIC), where the target voltage It is the power output provided by BB_PMIC to BBIC.

It should also be noted that after the state machine module 411 is initialized, the signal level state at the first control pin is related to whether the first resistor R1 is mounted or not. Specifically, when the first resistor R1 is mounted on the reserved resistance position 42, the signal level state at the first control pin is the first level state; or, the second resistor R1 is not mounted on the reserved resistance position 42 In the case of a resistor R1, the signal level state at the first control pin is the second level state.

In a more specific example, the first level state is high level, and the second level state is low level.

That is to say, after the Vsys voltage is established, the VPMIC voltage is established. At this time, if the first resistor R1 is mounted on the reserved resistance position 42, then the first control pin is pulled up to the VPMIC voltage. At this time, the first control pin The signal level state at the position is high; if the reserved resistance position 42 is not mounted with the first resistor R1, then the first control pin is in a floating state, and the signal level state at the first control pin is low at this time level.

Further, whether the reserved resistor position 42 is mounted with the first resistor R1 can also be used to identify the corresponding application scenario of the power management circuit 40 when the state machine module 411 is initialized. Specifically, in some embodiments, for the state machine module 411, it can also be used to determine whether the signal level state at the first control pin is the first level state, and then determine the circuit; or, if it is detected that the signal level state at the first control pin is the second level state, it is determined to be applied to the combined power management circuit.

In the embodiment of the present application, the power management circuit 40 can be at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein, if it is applied to an independent scenario, it can be an independent power management circuit at this time, which is determined by the power management The circuit 40 is composed alone; if it is applied to a combined scenario, it may be a combined power management circuit, which is composed of the power management circuit 40 and an external control module.

In some embodiments, for an independent power management circuit, referring to FIG. 6 , the independent power management circuit 60 may include a first power management chip 41 and a first resistor R1, and the two ends of the first resistor R1 are respectively connected to the first control The pin is connected to the first power supply pin; wherein,

The state machine module 411 is specifically used to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the power-on function of the first power management chip 41 is triggered or reset function.

Further, in some embodiments, referring to FIG. 6 , the independent power management circuit 60 may further include a power key K1, one end of the power key K1 is connected to the first control pin, and the other end of the power key K1 is grounded; wherein,

The power key K1 is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the second level state lasts for the first time After a preset time, the power-on operation of the first power management chip 41 is triggered to realize the power-on function.

In addition, in some embodiments, when the terminal device works abnormally, for example, the software of the baseband chip runs to death, or cannot be shut down or restarted normally through the software, it is necessary to reset the first power management chip 41 at this time. in,

The power key K1 is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction, and the second level state lasts for the second time After a preset time, the power-off and restart operation of the first power management chip 41 is triggered to realize the reset function.

Wherein, the first level state is high level, and the second level state is low level.

It should be noted that the first operation instruction is generated according to the user pressing the power key for a first preset time, and the second operation instruction is generated according to the user pressing the power key for a second preset time. .

In the embodiment of the present application, the first preset time is shorter than the second preset time. Wherein, the first preset time may be represented by T1, and the second preset time may be represented by T2. In a specific example, the first preset time can be set to 1 second, and the second preset time can be set to 10 seconds.

That is to say, when the power button is pressed, the PON signal at the first control pin is pulled down, and after a duration of T1, the state machine module 411 triggers the power-on sequence, and the first power management chip 41 starts to power on, The baseband chip is powered on and started. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, it is also possible to press the power button for a long time, and after T2 time, the state machine module 411 triggers the power-off sequence, and the first power management chip 41 performs a forced reset operation. , the baseband chip is powered off and restarted.

In some embodiments, for combined power management circuits, the external control module may include a second power management chip and an application processor. Referring to FIG. 7, the combined power management circuit 70 may include a first power management chip 41, a second power management chip 71 and an application processor 72, and the second power management chip 71 may include a second control pin and a general input and output pin, And the general-purpose input and output pins are connected to the first control pin; wherein,

The state machine module 411 is specifically used to configure the function of the first control pin to enable the reset function, so that when the signal level state at the first control pin changes, the power-on of the first power management chip 41 is triggered function or reset function.

Further, in some embodiments, referring to FIG. 7 , the combined power management circuit 70 may further include a power key K1, one end of the power key K1 is connected to the second control pin, and the other end of the power key K1 is grounded; wherein,

The power key K1 is used to control the second power management chip 71 to start powering on when receiving the third operation instruction;

The second power management chip 71 is used to control the signal level at the first control pin from the second level state to the first level state through the general-purpose input and output pins after the power-on, and trigger the first The power-on operation of the power management chip is used to realize the power-on function.

In addition, in some embodiments, when the terminal device works abnormally, for example, the software of the baseband chip runs to death, and cannot be shut down or restarted normally through the software, it is necessary to use the second power management chip 71 and the application processor 72 to control the first power supply. The management chip 41 is reset. in,

The application processor 72 is configured to send a reset command to the second power management chip 71;

The second power management chip 71 is also used to control the signal level at the first control pin from the first level state to the second level state through the general-purpose input and output pins according to the reset command, and trigger the first power supply The power-off operation of the management chip 41; and after the third preset time, the signal level at the first control pin is controlled again by the general-purpose input and output pins to be adjusted from the second level state to the first level state, triggering The power-on operation of the first power management chip 41 is implemented to realize the reset function.

Wherein, the first level state is high level, and the second level state is low level.

It should be noted that the third operation instruction is generated according to the user pressing the power key. In addition, the third preset time is denoted by T3, and the value of the third preset time can be set to a millisecond level. Exemplarily, the third preset time is 20 milliseconds, but it is not limited thereto.

It should also be noted that the second control pin may also be represented by a PON pin, and the general-purpose input and output pin may be represented by a GPIO_0 pin. In the embodiment of the present application, the PON pin of the second power management chip 71 is connected to the power key, and the GPIO_01 pin of the second power management chip 71 is connected to the PON pin of the first power management chip 41 to realize the first The power-on function or reset function of the power management chip 41 .

That is to say, when the power key is pressed, the PON signal at the second control pin is pulled low, and the second power management chip 71 starts to power on, and then the PON signal at the first control pin is pulled high, so that The first power management chip 41 starts to be powered on, and the baseband chip is powered on to start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, the application processor 72 notifies the second power management chip 71 to pull down the PON signal at the first control pin, and the first power management chip 41 is powered off. After the time T3 elapses, the second power management chip 71 pulls the PON signal at the first control pin high again, and the baseband chip is powered on again.

This embodiment provides a power management circuit, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control pin and a first power pin, The two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein, the state machine module is used to mount the first resistor at the reserved resistance position, through the first control pin Trigger the power-on function or reset function of the first power management chip; or, when the first resistor is not mounted in the reserved resistance position, trigger the power-on of the first power management chip through the external control module and the first control pin function or reset function. Like this, because three pins of PON, EN and RESETIN on the first power management chip are merged into one control pin, thereby not only can reduce chip area, save manufacturing cost; The risk of key signal being interfered can be reduced, and the system stability is improved.

In another embodiment of the present application, refer to FIG. 8 , which shows a schematic flowchart of a power control method provided in an embodiment of the present application. As shown in Figure 8, the method may include:

S801: Detect the signal level state at the first control pin through the state machine module.

It should be noted that this method is applied to the power management circuit 40 described in the foregoing embodiments. In the power management circuit, it may include a first power management chip and a reserved resistance position, and the first power management chip may include a state machine module, a first control pin and a first power pin, and the reserved resistance position The two ends are respectively connected to the first control pin and the first power supply pin.

In some embodiments, before the state machine module detects the signal level state at the first control pin, the method may further include:

receiving an input voltage provided by an external power supply for the first power management chip;

Perform voltage conversion on the input voltage to generate a supply voltage;

Power the state machine module according to the supply voltage to realize the initialization of the state machine module.

In this embodiment of the present application, the external power supply may be represented by a Vsys power supply. The second power supply pin is connected to the Vsys power supply. At this time, the input voltage provided for the first power management chip can be represented by the Vsys voltage; and the power supply voltage generated through voltage conversion can be represented by the VPMIC voltage. In this way, after the voltage of Vsys is established, the voltage of VPMIC is established, and the initialization of the state machine module can be realized at this time.

Further, after the state machine module is initialized, the signal level state at the first control pin has a correlation with whether the first resistor is mounted at the reserved resistor position. Therefore, in some embodiments, the method may further include: in the case of mounting the first resistor at the reserved resistor position, determining that the signal level state at the first control pin is the first level state; or, at If the first resistor is not placed in the reserved resistor position, it is determined that the signal level state at the first control pin is the second level state.

In a specific example, the first level state is high level, and the second level state is low level.

That is to say, after the Vsys voltage is established, the VPMIC voltage is established. At this time, if the first resistor is mounted in the reserved resistance position, then the first control pin is pulled up to the VPMIC voltage. At this time, the first control pin. The signal level state is high level; if the first resistor is not placed in the reserved resistance position, then the first control pin is in a floating state, and the signal level state at the first control pin is low level at this time.

S802: Determine whether to apply to an independent power management circuit or a combined power management circuit according to a signal level state.

It should be noted that different application scenarios can be adapted according to whether the first resistor is mounted at the reserved resistor position, which is mainly related to the signal level state at the first control pin. Specifically, the determining to apply to the independent power management circuit or combined power management circuit according to the signal level state may include: if it is detected that the signal level state is the first level state, then determining to apply to the independent power management circuit ; or, if it is detected that the signal level state is the second level state, it is determined to apply to the combined power management circuit.

In the embodiment of the present application, the first level state is high level, and the second level state is low level. In other words, if it is detected that the signal level state is the first level state, then it can be determined to be applied to the independent power management circuit; if it is detected that the signal level state is the second level state, then it can be determined to be applied to the combined power management circuit circuit.

S803: When it is determined to be applied to an independent power management circuit, trigger a power-on function or a reset function of the first power management chip through the first control pin.

It should be noted that the state machine module in the embodiment of the present application configures the function of the first control pin as a power button function. For S803, the triggering the power-on function or reset function of the first power management chip through the first control pin may include:

When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and after the second level state lasts for the first preset time, trigger The power-on operation of the first power management chip, so as to realize the power-on function; or,

When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and after the second level state lasts for a second preset time, trigger The power-off and restart operation of the first power management chip is implemented to realize the reset function.

In the embodiment of the present application, the first operation instruction is generated according to the user pressing the power button for a first preset time, and the second operation instruction is generated according to the user pressing the power button for a second preset time Generated.

In the embodiment of the present application, the first preset time is shorter than the second preset time. Wherein, the first preset time may be represented by T1, and the second preset time may be represented by T2. In a specific example, the first preset time can be set to 1 second, and the second preset time can be set to 10 seconds.

That is to say, when the power button is pressed, the PON signal at the first control pin is pulled low, and after a duration of T1, the state machine module triggers the power-on sequence, the first power management chip starts to power on, and the baseband chip Power on and start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, you can also press the power button for a long time, and after T2 time, the state machine module triggers the power-off sequence, and the first power management chip performs a forced reset operation. The chip is powered off and restarted.

S804: When it is determined to be applied to a combined power management circuit, trigger a power-on function or a reset function of the first power management chip through the external control module and the first control pin.

It should be noted that, in the state machine module of the embodiment of the present application, the function of configuring the first control pin is to enable a reset function. For S804, the triggering the power-on function or reset function of the first power management chip through the external control module and the first control pin may include:

According to receiving the third operation instruction, after the second power management chip starts to be powered on, control the signal level at the first control pin to be adjusted from the second level state to the first level state, triggering the first power management chip The power-on operation to realize the power-on function; or,

After the second power management chip receives the reset command sent by the application processor, it controls the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the first power management chip to switch off. Electrical operation; and after the third preset time, control the signal level at the first control pin again to be adjusted from the second level state to the first level state, triggering the re-power-on operation of the first power management chip, to Realize the reset function.

In the embodiment of the present application, the external control module may include a second power management chip and an application processor. Wherein, the second control pin of the second power management chip is connected to the power key, and the general-purpose input and output pins of the second power management chip are connected to the first control pin of the first power management chip, so as to realize the first power management chip power-on function or reset function.

That is to say, when the power button is pressed, the PON signal at the second control pin is pulled low, the second power management chip starts to power on, and then the PON signal at the first control pin is pulled high, so that the first A power management chip starts to be powered on, and the baseband chip is powered on to start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, the application processor notifies the second power management chip to pull down the PON signal at the first control pin, the first power management chip is powered off, and after the third After a preset time, the second power management chip pulls up the PON signal at the first control pin, and the baseband chip is powered on again.

This embodiment provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios. The signal level state at the first control pin is detected by the state machine module; according to the signal level state, it is determined to be applied to an independent power management circuit or a combined power management circuit; when it is determined to be applied to an independent power management circuit, through the first control The pin triggers the power-on function or reset function of the first power management chip; when it is determined to be used in a combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin. In this way, multiple pins such as PON, EN, and RESETIN are combined into one control pin, and different peripheral components are used to identify different application scenarios, and the pins are configured into corresponding functions; thus not only reducing the chip area, but also saving Manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

In yet another embodiment of the present application, refer to FIG. 9 , which shows a schematic diagram of the composition and structure of a power management system 90 provided in an embodiment of the present application. As shown in FIG. 9 , the power management system 90 may at least include any power management circuit 40 and a baseband chip 91 described in the foregoing embodiments; wherein, the power management circuit 40 may perform power-on or reset control for the baseband chip 91 .

In the embodiment of the present application, the application scenarios include at least an independent scenario and a combined scenario, and correspondingly, the power management system 90 can be at least divided into an independent power management system and a combined power management system. Wherein, the independent power management system can be regarded as composed of an independent power management circuit and a baseband chip, and the combined power management system can be regarded as composed of a combined power management circuit and a baseband chip.

The power management systems in these two application scenarios will be described in detail below.

In a possible implementation manner, when the first power management chips 41 form a system in a single group, the first resistor R1 needs to be mounted on the circuit board at this time. Referring to FIG. 10 , it shows a schematic diagram of the composition and structure of an independent power management system provided by an embodiment of the present application. As shown in FIG. 10 , the independent power management system 100 may include a first power management chip 41 , a first resistor R1 , a power key K1 and a baseband chip 91 .

Here, the first power management chip 41 may be a BB_PMIC, and the baseband chip 91 may be a BBIC. Specifically, the BB_PMIC may include a state machine module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second power supply pin. Wherein, the first control pin is represented by a PON pin, the first power supply pin is represented by a VPMIC pin, the second power supply pin is represented by a Vsys pin, and the two ends of the first resistor R1 are respectively connected to the PON pin and the VPMIC tube The two ends of the power button K1 are respectively connected to the PON pin and the ground; in addition, the first capacitor C1 can also be connected to the VPMIC pin for filtering.

In another possible implementation manner, when the first power management chip 41 and the external control module together form a system, it is not necessary to mount the first resistor R1 on the circuit board at this time. Referring to FIG. 11 , it shows a schematic diagram of the composition and structure of a combined power management system provided by an embodiment of the present application. As shown in FIG. 11 , the combined power management system 110 may include a first power management chip 41 , a second power management chip 111 , an application processor 112 , a power key K1 and a baseband chip 91 .

Here, the first power management chip 41 may be a BB_PMIC, the second power management chip 111 may be a Main_PMIC, the application processor 112 may be an AP, and the baseband chip 91 may be a BBIC. Specifically, BB_PMIC may include a state machine module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second power supply pin, and Main_PMIC may include a second control pin and a general input output pin. Wherein, the first control pin of BB_PMIC is represented by a PON pin, the first power supply pin is represented by a VPMIC pin, and the second power supply pin is represented by a Vsys pin; the second control pin of Main_PMIC is represented by a PON pin, The general-purpose input and output pins are represented by GPIO_01 pins; and the PON pins of Main_PMIC are connected to the power button K1, and the GPIO_01 pins of Main_PMIC are connected to the PON pins of BB_PMIC. In addition, the first capacitor C1 can also be connected to the VPMIC pin of the BB_PMIC for filtering.

Referring to FIG. 10 and FIG. 11 , refer to FIG. 12 , which shows a detailed flowchart of a power control method provided by an embodiment of the present application. As shown in Figure 12, the detailed process may include:

S1201: Vsys voltage is established.

S1202: VPMIC voltage is established, and the state machine module is initialized.

S1203: The state machine module detects the signal level state at the first control pin.

S1204: If the signal level state is high level, the state machine module configures the function of the first control pin as a power button function.

S1205: After pressing the power button for T1 time, the BB_PMIC starts to be powered on, and the BBIC is powered on and started.

S1206: After the power button is pressed for T2, the BB_PMIC is reset, and the BBIC is powered off and restarted.

S1207: If the signal level state is low level, the state machine module configures the function of the first control pin to enable the reset function.

S1208: Press the power button, after the Main_PMIC starts to be powered on, pull up the signal level at the first control pin, the BB_PMIC starts to be powered on, and the BBIC starts to be powered on.

S1209: AP sends a reset command to Main_PMIC, Main_PMIC pulls down the signal level at the first control pin, and powers off BBIC; after T3 time, Main_PMIC pulls up the signal level at the first control pin, and BBIC restarts electricity.

It should be noted that the technical solution of the embodiment of this application is to combine the three pins PON, EN and RESETIN in the related art into one control pin, and by adding the first resistor R1 on the circuit board, it can Pulled up to the VPMIC voltage at the first supply pin. In this way, by choosing whether to mount the first resistor R1 on the circuit board, different functions of the first control pin in two scenarios can be realized.

When BBIC constitutes a system alone, the system block diagram is shown in Figure 10. At this time, the first resistor R1 needs to be mounted on the circuit board, and the power button is connected to the first control pin (ie PON pin) of BB_PMIC.

For the independent power management system 100 shown in FIG. 10 , the boot process is as follows:

In the first step, the Vsys voltage is established;

In the second step, the VPMIC voltage is established, and the state machine module is initialized;

In the third step, the state machine module detects the signal level state of the PON pin, because the first resistor R1 is mounted on the circuit board, so the signal level state at this time is high;

Step 4: The state machine module configures the function of the PON pin as the power button function: when the signal at the PON pin is pulled down for a period of time (such as T1 time), the state machine module will trigger the power-on sequence to control the second conversion Power on the circuit;

Step 5, BB_PMIC waits for the power button to be pressed. When the power button is pressed, the signal at the PON pin is pulled down, and after a period of time (such as T1 time), BB_PMIC starts the power-on process, and BBIC is powered on and started;

Step 6. When the terminal device is working abnormally, such as BBIC software running dead, unable to shut down or restart normally through the software, you can press and hold the power button for a period of time (such as T2 time), and the state machine module will trigger the power-off sequence. Control the second conversion circuit to be powered off, the BB_PMIC performs a reset operation, and the BBIC is powered off and restarted.

In this embodiment of the application, both the T1 time and the T2 time can be configured according to product requirements. Generally, T1 is less than T2. Exemplarily, T1 is set to 1 second, and T2 is set to 10 seconds, but this is not specifically limited.

When BBIC and AP form a system together, the system block diagram is shown in Figure 11. At this time, there is no need to mount the first resistor R1 on the circuit board, and the power button is connected to the second control pin (PON pin) of Main_PMIC. The general-purpose input and output pin (ie, GPIO_01 pin) is connected to the first control pin (PON pin) of BB_PMIC.

For the combined power management system 110 shown in FIG. 11 , the boot process is as follows:

In the first step, the Vsys voltage is established;

In the second step, the VPMIC voltage is established, and the state machine module is initialized;

In the third step, the state machine module detects the signal level state of the PON pin, because the first resistor R1 is not mounted on the circuit board, so the signal level state at this time is low;

In the fourth step, the state machine module configures the function of the PON pin to enable the reset function: when the signal at the PON pin is pulled up from the low level, the state machine module will trigger the power-on sequence to control the second conversion circuit. When the signal at the PON pin is pulled down from high level, the state machine module will trigger the power-off sequence to control the power-off of the second conversion circuit;

Step 5, BB_PMIC waits for the PON pin to be pulled high by Main_PMIC. After Main_PMIC starts to be powered on, pull the PON pin of BB_PMIC high, BB_PMIC starts the power-on process, and BBIC is powered on to start;

Step 6, when the terminal equipment is working abnormally, such as BBIC software running dead, the AP can notify Main_PMIC to pull down the PON pin of BB_PMIC, and BBIC is powered off and reset. The pin is pulled high, and the BBIC is powered on again.

The embodiment of the present application provides a power management system. Whether the first resistor R1 is mounted on the circuit board can determine whether it is applied to an independent power management system or a combined power management system. Moreover, whether it is an independent power management system or a combined power management system, BB_PMIC has reduced two pins, which can reduce the chip area of BB_PMIC and save manufacturing costs; in addition, it also reduces the control signals on the circuit board and reduces the number of key signals. The risk of being disturbed improves the system stability.

The above are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

It should be noted that in this application, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above embodiments of the present application are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in this application can be combined arbitrarily to obtain new method embodiments under the condition of no conflict.

The features disclosed in several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Industrial Applicability

In the embodiment of the present application, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control pin and a first power pin, and the reserved resistance position The two ends are respectively connected to the first control pin and the first power pin; wherein, the state machine module is used to trigger the first power management through the first control pin when the first resistor is mounted at the reserved resistor position The power-on function or reset function of the chip; or, when the first resistor is not mounted in the reserved resistance position, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin. In this way, since the three pins of the power key signal pin (PON), the enable signal pin (EN) and the reset signal pin (RESETIN) in BB_PMIC are combined into one control pin, it is not only possible to reduce the BB_PMIC The chip area saves manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

Claims (22)

1. A power management circuit, the power management circuit includes a first power management chip and a reserved resistance position, and the first power management chip includes a state machine module, a first control pin and a first power pin, the Both ends of the reserved resistor position are respectively connected to the first control pin and the first power supply pin; wherein,

   The state machine module is configured to trigger the power-on function or reset function of the first power management chip through the first control pin when the first resistor is mounted at the reserved resistor position; or, In the case that no first resistor is attached to the reserved resistor position, the power-on function or reset function of the first power management chip is triggered through an external control module and the first control pin.
2. The power management circuit according to claim 1, wherein the first power management chip further includes a first conversion circuit and a second power pin, and the second power pin is connected to an external power supply; wherein,

   The second power supply pin is used to provide an input voltage for the first power management chip;

   The first conversion circuit is configured to perform voltage conversion on the input voltage to generate a supply voltage;

   The first power supply pin is specifically used to receive the power supply voltage, and supply power to the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module.
3. The power management circuit according to claim 2, wherein the first conversion circuit is a low dropout linear regulator LDO circuit.
4. The power management circuit according to claim 1, wherein,

   In the case where the first resistor is mounted at the reserved resistor position, the signal level state at the first control pin is the first level state; or,

   In the case that no first resistor is mounted on the reserved resistor position, the signal level state at the first control pin is the second level state.
5. The power management circuit according to claim 4, wherein the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein,

   The state machine module is further configured to determine to apply to the independent power management circuit if it is detected that the signal level state at the first control pin is the first level state; or, if it is detected that If the signal level state at the first control pin is the second level state, it is determined to be applied to the combined power management circuit;

   Wherein, the independent power management circuit is composed of the power management circuit alone, and the combined power management circuit is composed of the power management circuit and the external control module.
6. The power management circuit according to claim 5, wherein the independent power management circuit comprises the first power management chip and the first resistor, and the two ends of the first resistor are respectively connected to the first control The pin is connected to the first power supply pin; wherein,

   The state machine module is specifically configured to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the first power supply is triggered. Manage the power-on function or reset function of the chip.
7. The power management circuit according to claim 6, wherein the independent power management circuit further includes a power key, one end of the power key is connected to the first control pin, and the other end of the power key is grounded; wherein ,

   The power key is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the After the second level state lasts for a first preset time, the power-on operation of the first power management chip is triggered to realize the power-on function.
8. The power management circuit according to claim 7, wherein,

   The power key is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction, and After the second level state lasts for a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.
9. The power management circuit according to claim 8, wherein the first preset time is shorter than the second preset time.
10. The power management circuit according to claim 5, wherein the combined power management circuit includes the first power management chip and the external control module, and the external control module includes a second power management chip and an application processor, The second power management chip includes a second control pin and a general-purpose input and output pin, and the general-purpose input and output pin is connected to the first control pin; wherein,

    The state machine module is specifically configured to configure the function of the first control pin to enable a reset function, so that when the signal level state at the first control pin changes, trigger the first The power-on function or reset function of the power management chip.
11. The power management circuit according to claim 10, wherein the combined power management circuit further comprises a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein ,

    The power key is used to control the second power management chip to start powering on when receiving the third operation instruction;

    The second power management chip is configured to control the signal level at the first control pin to be adjusted from the second level state to the The first level state triggers the power-on operation of the first power management chip to realize the power-on function.
12. The power management circuit of claim 11, wherein,

    The application processor is configured to send a reset command to the second power management chip;

    The second power management chip is further configured to control the signal level at the first control pin to be adjusted from the first level state to the The second level state triggers the power-off operation of the first power management chip; and after the third preset time, controls the signal level at the first control pin again through the general-purpose input and output pin Adjusting from the second level state to the first level state triggers a power-on operation of the first power management chip to realize the reset function.
13. The power management circuit according to any one of claims 4 to 12, wherein the first level state is high level, and the second level state is low level.
14. A power control method, applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; the method includes:

    Detecting the signal level state at the first control pin through the state machine module;

    Determine to apply to the independent power management circuit or the combined power management circuit according to the signal level state;

    When it is determined to be applied to the independent power management circuit, triggering a power-on function or a reset function of the first power management chip through the first control pin;

    When it is determined to be applied to the combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.
15. The method according to claim 14, wherein, according to the signal level state, determining to apply to the independent power management circuit or the combined power management circuit comprises:

    If it is detected that the signal level state is the first level state, it is determined to be applied to the independent power management circuit; or,

    If it is detected that the signal level state is the second level state, it is determined to be applied to the combined power management circuit.
16. The method according to claim 14, wherein, before the state machine module detects the signal level state at the first control pin, the method further comprises:

    In the case of mounting the first resistor at the reserved resistor position, determine that the signal level state at the first control pin is the first level state; or,

    If the first resistor is not installed in the reserved resistor position, it is determined that the signal level state at the first control pin is the second level state.
17. The method according to claim 15 or 16, wherein the first level state is a high level, and the second level state is a low level.
18. The method according to claim 14, before the state machine module detects the signal level state at the first control pin, the method further comprises:

    receiving an input voltage provided by an external power supply for the first power management chip;

    performing voltage conversion on the input voltage to generate a supply voltage;

    Powering the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module.
19. The method according to any one of claims 14 to 18, wherein when it is determined to be applied to the independent power management circuit, the power-on function of the first power management chip is triggered through the first control pin or reset functions, including:

    When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and the second level state lasts for the first preset After a period of time, trigger the power-on operation of the first power management chip to realize the power-on function; or,

    When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and continue in the second level state After a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.
20. The method of claim 19, wherein the first predetermined time is less than the second predetermined time.
21. The method according to any one of claims 14 to 18, wherein when it is determined to be applied to the combined power management circuit, the first power management chip is triggered by the external control module and the first control pin The power-on function or reset function, including:

    According to receiving the third operation instruction, after the second power management chip starts to be powered on, control the signal level at the first control pin to be adjusted from the second level state to the first level state, triggering a power-on operation of the first power management chip to realize the power-on function; or,

    After the second power management chip receives the reset command sent by the application processor, control the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the power-off operation of the first power management chip; and controlling the signal level at the first control pin to be adjusted from the second level state to the first power level state again after a third preset time In the flat state, trigger the power-on operation of the first power management chip to realize the reset function.
22. A power management system, the power management system at least comprising a power management circuit and a baseband chip according to any one of claims 1 to 13; wherein, the power management circuit performs power-on or reset control for the baseband chip .

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