CN113726127A

CN113726127A - Power management circuit and control method and system thereof

Info

Publication number: CN113726127A
Application number: CN202110983933.7A
Authority: CN
Inventors: 周洁
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2021-08-25
Filing date: 2021-08-25
Publication date: 2021-11-30
Anticipated expiration: 2041-08-25
Also published as: CN117060680A; CN113726127B; WO2023024764A1

Abstract

The embodiment of the application discloses a power management circuit and a control method and a control system thereof, wherein the power management circuit comprises a first power management chip and a reserved resistance position, the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistance position are respectively connected with the first control pin and the first power pin; the state machine module is used for triggering the power-on function or the reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, the power-on function or the reset function of the first power management chip is triggered through the external control module and the first control pin. Three pins in the first power management chip are combined into one control pin, so that the chip area is reduced, and the manufacturing cost is saved; and moreover, the risk that the key signals are interfered is reduced, and the stability of the system is improved.

Description

Power management circuit and control method and system thereof

Technical Field

The present disclosure relates to the field of power management technologies, and in particular, to a power management circuit and a control method and system thereof.

Background

The Baseband chip (Baseband IC, BBIC) is a chip used for synthesizing a Baseband signal to be transmitted or decoding a received Baseband signal, and mainly performs an information processing function of a terminal device.

Currently, a BBIC typically uses a dedicated Baseband Power Management chip (BB _ PMIC) to Power and control the BBIC. In order to realize a plurality of control modes on the BB _ PMIC, the control pins of the BB _ PMIC include at least three independent control pins, such as a power key signal Pin (PON), an enable signal pin (EN), and a reset signal pin (RESETIN), and the control logic of the control pins is different. However, since the BB _ PMIC has three control pins with different control logic, the chip area of the BB _ PMIC is large, and the manufacturing cost is relatively high; moreover, the control signals are all system key signals, and are easily interfered by other signals on a circuit board, so that the stability of the system is directly influenced.

Disclosure of Invention

The application provides a power management circuit and a control method and system thereof, which can reduce the chip area of BB _ PMIC and save the manufacturing cost; and the risk that the key signal is interfered can be reduced, and the stability of the system is improved.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a power management circuit, where the power management circuit includes a first power management chip and a reserved resistance position, the first power management chip includes a state machine module, a first control pin and a first power pin, and two ends of the reserved resistance position are connected to the first control pin and the first power pin respectively; wherein,

the state machine module is used for triggering the power-on function or the reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, the power-on function or the reset function of the first power management chip is triggered through the external control module and the first control pin.

In a second aspect, an embodiment of the present application provides a power control method, which is applied to a power management circuit, and the power management circuit is divided into at least an independent power management circuit and a combined power management circuit according to an application scenario; the method comprises the following steps:

detecting, by a state machine module, a signal level state at a first control pin;

determining to be applied to the independent power management circuit or the combined power management circuit according to the signal level state;

when the power supply is determined to be applied to the independent power supply management circuit, triggering a power-on function or a reset function of a first power supply management chip through a first control pin;

and when the power supply is determined to be applied to the combined power supply management circuit, triggering the power-on function or the reset function of the first power supply management chip through the external control module and the first control pin.

In a third aspect, an embodiment of the present application provides a power management system, where the power management system at least includes the power management circuit and the baseband chip as described in the first aspect; the power management circuit performs power-on or reset control on the baseband chip.

The power management circuit comprises a first power management chip and a reserved resistor position, wherein the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin; the state machine module is used for triggering the power-on function or the reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, the power-on function or the reset function of the first power management chip is triggered through the external control module and the first control pin. Thus, three pins, namely a power key signal Pin (PON), an enable signal pin (EN) and a reset signal pin (RESETIN) in the BB _ PMIC are combined into one control pin, so that the chip area of the BB _ PMIC can be reduced, and the manufacturing cost is saved; and because the control signals on the circuit board are reduced, the risk that the key signals are interfered can be reduced, and the stability of the system is improved.

Drawings

FIG. 1 is a schematic diagram illustrating the internal structure of a BB _ PMIC;

FIG. 2 is a schematic diagram of a BBIC independent system;

FIG. 3 is a schematic diagram of a BBIC combined system;

fig. 4 is a schematic structural diagram of a power management circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another power management circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an independent power management circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a combined power management circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic flowchart of a power control method according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a power management system according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of an independent power management system according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a combined power management system according to an embodiment of the present application;

fig. 12 is a detailed flowchart of a power control method according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that reference to the terms "first \ second \ third" in the embodiments of the present application is only used for distinguishing similar objects and does not represent a specific ordering for the objects, and it should be understood that "first \ second \ third" may be interchanged with a specific order or sequence where possible so that the embodiments of the present application described herein can be implemented in an order other than that shown or described herein.

With the continuous development of electronic technology, terminal devices such as smart phones and palm computers are becoming more and more popular. At present, a Baseband chip (Baseband IC, BBIC) of a terminal platform generally has two Application scenarios, one Application scenario is a system formed by matching with one Application Processor (AP), for example, the system is applied to a terminal device; another application scenario is a BBIC independent component system, such as a Customer Premise Equipment (CPE).

Here, the BBIC generally uses a dedicated Baseband Power Management chip (BB _ PMIC) to supply Power and control. For the two application scenarios, the control logics for starting, resetting and the like of the BB _ PMIC are completely different. In order to realize various control modes on the BB _ PMIC, the control pins of the current BB _ PMIC include three independent pins such as PON, EN, RESETIN, etc., and the control logic is different.

Referring to fig. 1, a schematic diagram of the internal structure of BB _ PMIC is provided. As shown in fig. 1, the BB _ PMIC includes a first inverter circuit, a state machine module, a second inverter circuit, and a first pin (Vsys), a second pin (VPMIC), a third Pin (PON), a fourth pin (EN), and a fifth pin (RESETIN). The first pin (Vsys) is connected with an external power supply (represented by Vsys power supply), and the second pin (VPMIC) is connected with an external capacitor (represented by C1).

Vsys power supply: the input power supply of BB _ PMIC is typically powered by a battery in the terminal device.

A first conversion circuit: the input voltage Vsys is voltage-converted to output a VPMIC voltage. In an embodiment of the present application, the first converting circuit may be a Low Dropout Regulator (LDO) circuit.

A second conversion circuit: the input voltage Vsys is voltage-converted, converted into a voltage usable for the BBIC, and output. In this embodiment, the second conversion circuit may be a Direct Current-Direct Current (DC-DC) circuit.

VPMIC voltage: the input voltage Vsys is converted by the LDO circuit, and the digital circuit in the PMIC is supplied with power. In addition, a capacitor C1 is externally hung on the second pin (VPMIC) to play a role in filtering.

A state machine module: and the control logic of the PMIC is realized, and the power-on/power-off sequence of the DC-DC circuit is controlled.

PON: power key signal, default high. After the level is pulled down for a period of time (e.g., T1), the state machine module triggers a power-up sequence to control the DC-DC circuit to power up, and the BB _ PMIC starts the power-up procedure.

EN: the enable signal is low when the device is turned off. When the level is pulled high, the state machine module immediately triggers a power-on time sequence to control the DC-DC circuit to be powered on, and the BB _ PMIC starts a power-on process.

RESETIN: and a reset signal keeping high level when BB _ PMIC works normally. When the level is pulled down, the state machine module triggers a power-down time sequence to control the power-down of the DC-DC circuit, and the BBIC is reset by the power-down.

The following description of the related art will be made in conjunction with system block diagrams of two application scenarios.

BBIC independent composition system

When applied to an independent scenario, the BBIC alone forms a system at this time, i.e., a corresponding block diagram of the BBIC independent system is shown in fig. 2. The system block diagram may include a first power management chip (BB _ PMIC), a baseband chip (BBIC), a power key, and a reset key.

The power supply key is connected to a PON pin of the BB _ PMIC, the reset key is connected to a RESETIN pin, and the EN pin is suspended. After the user presses the power key for a certain period of time (e.g., T1), the BB _ PMIC power-up sequence is triggered to supply power to the BBIC.

Under the condition of starting, if the BBIC works abnormally, such as the software runs dead, and the BBIC cannot be shut down or a system is restarted through the software, a user can forcibly reset the BB _ PMIC by pressing a reset key, trigger a power-down time sequence of the BB _ PMIC, and then power down the BBIC, so that the BBIC is reset and restarted.

(II) AP + BBIC jointly-composing system

When applied to a combined scenario, the BBIC is used with the AP, for example, a block diagram corresponding to a terminal device, i.e., a BBIC combined system, is shown in fig. 3. The system block diagram may include a first power management chip (BB _ PMIC), a baseband chip (BBIC), an Application Processor (AP), a second power management chip (Main _ PMIC), and a power key.

The AP is an application processor of the terminal equipment, and the Main _ PMIC is a Main power management chip of the terminal equipment and is responsible for power-on and power-off operations of the terminal equipment and power supply for the AP. The power key is hung on the Main _ PMIC, and the BB _ PMIC needs to be controlled to be powered on by the Main _ PMIC. Because a strict power-on timing sequence relationship is needed between the Main _ PMIC and the BB _ PMIC, in order to strictly control the timing sequence, a power-on control signal sent by the Main _ PMIC needs to immediately trigger the BB _ PMIC to be powered on, and no delay exists, so that the PON pin of the BB _ PMIC cannot be used for controlling the BB _ PMIC to be powered on at this time, and an EN signal of the BB _ PMIC needs to be used for controlling the BB _ PMIC to be powered on. In addition, the power key of the terminal device is connected to the PON pin of the Main _ PMIC. The Main _ PMIC also includes two General-Purpose Input/Output (GPIO) pins: a GPIO _01 pin and a GPIO _02 pin; the GPIO-01 pin is connected with a RESETIN pin of the BB-PMIC and is used for controlling the reset of the BB-PMIC; and the GPIO _02 pin is connected with an EN pin of the BB _ PMIC and is used for controlling the power-on enabling of the BB _ PMIC. The PON pin of BB _ PMIC is suspended and not used.

After the user presses the power key for a period of time (e.g., T1), the Main _ PMIC triggers the power-on process, outputs the power to the AP, and further pulls up the EN pin of the BB _ PMIC by pulling up the level of the GPIO _02 pin, at which time the BB _ PMIC immediately triggers the power-on timing sequence, and the BBIC is powered on and started.

When the AP detects that BBIC software runs to death or the BBIC cannot be restarted through the software, the AP informs the Main _ PMIC, specifically, the level of the GPIO _01 pin is pulled down, then the RESETIN pin of the BB _ PMIC is pulled down, at the moment, the BB _ PMIC is reset, a power-off time sequence of the BB _ PMIC is triggered, and the BBIC is powered off and restarted.

Therefore, in the related art, the BB _ PMIC is separately provided with three control pins (specifically, a PON pin, an EN pin and a RESETIN pin) of different control logics so as to achieve the purpose of application in different scenes. If the functions of these several control pins can be combined into one pin, the number of pins of the chip can be reduced, and thus the chip area, which directly determines the manufacturing cost of the chip, so that if the number of pins of the chip can be reduced, the cost can be reduced. In addition, the control signals are all system key signals, if the control signals are interfered by other signals on a circuit board, the stability of the system can be directly influenced, and the interference possibility is higher when the number of the signals is larger; therefore, if the pins can be combined to reduce the number of key signals on the circuit board, the risk of interference can be reduced, and the system stability is enhanced.

Based on this, an embodiment of the present application provides a power management circuit, where the power management circuit includes a first power management chip and a reserved resistance position, the first power management chip includes a state machine module, a first control pin and a first power pin, and two ends of the reserved resistance position are connected to the first control pin and the first power pin respectively; the state machine module is used for triggering the power-on function or the reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, the power-on function or the reset function of the first power management chip is triggered through the external control module and the first control pin. Thus, three pins, namely a power key signal Pin (PON), an enable signal pin (EN) and a reset signal pin (RESETIN) in the BB _ PMIC are combined into one control pin, so that the chip area of the BB _ PMIC can be reduced, and the manufacturing cost is saved; and because the control signals on the circuit board are reduced, the risk that the key signals are interfered can be reduced, and the stability of the system is improved.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, referring to fig. 4, a schematic diagram of a composition structure of a power management circuit provided in the embodiment of the present application is shown. As shown in fig. 4, the power management circuit 40 may include a first power management chip 41 and a reserved resistance location 42, and the first power management chip 41 may include a state machine module 411, a first control pin and a first power pin, where two ends of the reserved resistance location 42 are respectively connected to the first control pin and the first power pin; wherein,

the state machine module 411 is configured to trigger a power-on function or a reset function of the first power management chip 41 through the first control pin when the first resistor R1 is mounted at the reserved resistor position 42; alternatively, in the case where the first resistor R1 is not mounted at the reserved resistor location 42, the power-on function or the reset function of the first power management chip 41 is triggered by the external control module and the first control pin.

It should be noted that the power management circuit 40 of the embodiment of the present application can adapt to different application scenarios according to whether the first resistor R1 is mounted at the reserved resistor position 42. In fig. 4, if the reserved resistance location 42 mounts the first resistance R1, the first control pin may be pulled up to the level state of the first power supply pin; otherwise, if the reserved resistor location 42 does not mount the first resistor R1, the first control pin at this time is in a floating state. That is, by selecting whether to mount the first resistor R1 at the reserved resistor location 42, the application scenario of the power management circuit 40 can be identified by the state machine module 411.

It should be further noted that the power management circuit 40 according to the embodiment of the present application implements a combination of three pins, namely PON, EN and RESETIN, on the first power management chip 41 into one first control pin (denoted as PON). Different components (such as a first resistor R1) are arranged on a circuit board, so that an application scene corresponding to the power management circuit 40 can be identified when the state machine module 411 is initialized, and different control logics are given to a first control pin by using the state machine module 411 to realize different control functions, so that various control logics can be realized on one pin (namely, the first control pin).

In some embodiments, based on the power management circuit 40 shown in fig. 4, referring to fig. 5, the first power management chip 41 may further include a first converting circuit 412 and a second power pin; wherein,

the second power supply pin is connected with an external power supply and used for providing input voltage for the first power supply management chip;

a first conversion circuit 412 for performing voltage conversion on the input voltage to generate a supply voltage;

the first power pin is configured to receive a power supply voltage, and supply power to the state machine module 411 according to the power supply voltage, so as to initialize the state machine module 411.

In a specific example, the first conversion circuit 412 can be an LDO circuit.

It should be noted that, in the embodiment of the present application, the external power supply may be represented by a Vsys power supply, the first control pin may be represented by a PON pin, the first power supply pin may be represented by a VPMIC pin, and the second power supply pin may be represented by a Vsys pin.

It should be noted that the second power supply pin is connected to a Vsys power supply, and the input voltage supplied to the first power management chip 41 at this time can be represented by a Vsys voltage; and the supply voltage generated by the first translation circuit 412 may be represented by the VPMIC voltage. Thus, after the Vsys voltage is established, the VPMIC voltage is established, at which time initialization of the state machine module 411 may be achieved.

Further, in some embodiments, referring to fig. 5, the power management circuit 40 may further include a first capacitor C1; one end of the first capacitor C1 is connected to the first power pin, and the other end of the first capacitor C1 is grounded. Here, the first capacitor C1 mainly filters the VPMIC voltage at the first power supply pin.

Further, in some embodiments, referring to fig. 5, the first power management chip 41 may further include a second conversion circuit 413; wherein,

the state machine module 411 is further configured to generate a control power timing sequence according to a signal level state at the first control pin;

the second conversion circuit 413 is configured to perform voltage conversion on the input voltage according to the control power supply timing, and generate a target voltage.

In a specific example, the second conversion circuit 413 may be a DC-DC circuit.

It should be noted that the first power management chip 41 may be a baseband power management chip (BB _ PMIC). Thus, in the power management system, besides the power management circuit 40, a baseband chip (BBIC) may be further included, where the first power management chip 41 can supply power and control power for the baseband chip (BBIC), and the target voltage here is the power output provided by the BB _ PMIC to the BBIC.

It should be noted that, after the state machine module 411 is initialized, the signal level state at the first control pin at this time is related to whether the first resistor R1 is mounted. Specifically, in the case where the reserved resistance position 42 mounts the first resistance R1, the signal level state at the first control pin is the first level state; alternatively, in the case where the first resistor R1 is not mounted at the pre-resistor location 42, the signal level state at the first control pin is the second level state.

In a more specific example, the first level state is a high level and the second level state is a low level.

That is, after the Vsys voltage is established, the VPMIC voltage is established, at which time if the reserved resistance location 42 mounts the first resistance R1, the first control pin is pulled up to the VPMIC voltage, at which time the signal level state at the first control pin is high; if the reserved resistor location 42 does not have the first resistor R1 mounted, the first control pin is in a floating state, and the signal level state at the first control pin is low.

Further, whether the reserved resistor location 42 mounts the first resistor R1 or not can also be used to identify the application scenario corresponding to the power management circuit 40 when the state machine module 411 is initialized. Specifically, in some embodiments, the state machine module 411 may be further configured to determine to apply to the independent power management circuit if the signal level state at the first control pin is detected to be the first level state; or, if the signal level state at the first control pin is detected to be the second level state, determining to apply to the combined power management circuit.

In the embodiment of the present application, the power management circuit 40 may be at least divided into an independent power management circuit and a combined power management circuit according to an application scenario; if the method is applied to an independent scene, the method can be an independent power management circuit which is composed of the power management circuit 40; if applied to a combined scenario, this time a combined power management circuit, which is composed of the power management circuit 40 and an external control module.

In some embodiments, for the independent power management circuit, referring to fig. 6, the independent power management circuit 60 may include a first power management chip 41 and a first resistor R1, and two ends of the first resistor R1 are connected to the first control pin and the first power pin, respectively; wherein,

the state machine module 411 is specifically configured to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the power-on function or the reset function of the first power management chip 41 is triggered.

Further, in some embodiments, referring to fig. 6, the stand-alone power management circuit 60 may further include a power key K1, one end of the power key K1 is connected to the first control pin, and the other end of the power key K1 is connected to ground; wherein,

the power key K1 is configured to, when receiving the first operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and trigger the power-on operation of the first power management chip 41 after the second level state lasts for the first preset time, so as to implement the power-on function.

In addition, in some embodiments, when the terminal device is abnormally operated, for example, the software of the baseband chip runs out, and cannot be normally shut down or restarted by the software, the first power management chip 41 needs to be reset at this time. Wherein,

the power key K1 is further configured to, when receiving a second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and trigger the power-off restart operation of the first power management chip 41 after the second level state lasts for a second preset time, so as to implement the reset function.

The first level state is a high level, and the second level state is a low level.

The first operation instruction is generated according to a pressing operation of the power key for a first preset time by the user, and the second operation instruction is generated according to a pressing operation of the power key for a second preset time by the user.

In the embodiment of the present application, the first preset time is less than the second preset time. Wherein the first preset time may be represented by T1, and the second preset time may be represented by T2. In a specific example, the first preset time may be set to 1 second, and the second preset time may be set to 10 seconds.

That is, when the power key is pressed, the PON signal at the first control pin is pulled low, and after a time T1, the state machine module 411 triggers the power-on sequence, the first power management chip 41 starts to power on, and the baseband chip starts to power on. If the terminal device works abnormally and cannot be normally shut down or restarted through software, the state machine module 411 can trigger a power-down time sequence after a power-down key is pressed for a long time and lasts for T2 time, the first power management chip 41 performs forced reset operation, and the baseband chip is powered down and restarted.

In some embodiments, for a combined power management circuit, the external control module may include a second power management chip and an application processor. Referring to fig. 7, the combined power management circuit 70 may include a first power management chip 41, a second power management chip 71 and an application processor 72, the second power management chip 71 may include a second control pin and a general purpose input output pin, and the general purpose input output pin is connected with the first control pin; wherein,

the state machine module 411 is specifically configured to configure the function of the first control pin as an enable reset function, so that when the signal level state at the first control pin changes, the power-on function or the reset function of the first power management chip 41 is triggered.

Further, in some embodiments, referring to fig. 7, the combined power management circuit 70 may further include a power key K1, one end of the power key K1 is connected to the second control pin, and the other end of the power key K1 is connected to ground; wherein,

a power key K1, configured to control the second power management chip 71 to start powering on when receiving the third operation instruction;

and the second power management chip 71 is configured to, after the power-on, control the signal level at the first control pin to be adjusted from the second level state to the first level state through the general input output pin, and trigger a power-on operation of the first power management chip, so as to implement a power-on function.

In addition, in some embodiments, when the terminal device is abnormally operated, for example, the software of the baseband chip runs out, and cannot be normally shut down or restarted by the software, the first power management chip 41 needs to be reset by the second power management chip 71 and the application processor 72 at this time. Wherein,

an application processor 72 for sending a reset command to the second power management chip 71;

the second power management chip 71 is further configured to control the signal level at the first control pin to be adjusted from the first level state to the second level state through the general input output pin according to the reset command, and trigger a power-down operation of the first power management chip 41; and after the third preset time, controlling the signal level at the first control pin again through the general input/output pin to be adjusted from the second level state to the first level state, and triggering the power-on operation of the first power management chip 41 again to realize the reset function.

The third operation instruction is generated by the user pressing the power key. In addition, the third preset time is denoted by T3, and the value of the third preset time may be set to the order of milliseconds, and illustratively, the third preset time is 20 milliseconds, but is not limited in any way.

It should be noted that the second control pin may also be represented by a PON pin, and the general purpose input/output pin may be represented by a GPIO _0 pin. In this embodiment of the application, the PON pin of the second power management chip 71 is connected to a power key, and the GPIO _01 pin of the second power management chip 71 is connected to the PON pin of the first power management chip 41, so as to implement a power-on function or a reset function of the first power management chip 41.

That is, when the power key is pressed, the PON signal at the second control pin is pulled low, the second power management chip 71 starts to power up, and then the PON signal at the first control pin is pulled high, so that the first power management chip 41 starts to power up, and the baseband chip starts to power up. If the terminal device is abnormal and cannot be normally shut down or restarted by software, the application processor 72 notifies the second power management chip 71 to pull down the PON signal at the first control pin, the first power management chip 41 is powered off, and after T3 time, the second power management chip 71 pulls up the PON signal at the first control pin, and the baseband chip is powered on again.

The embodiment provides a power management circuit, which comprises a first power management chip and a reserved resistor position, wherein the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin; the state machine module is used for triggering the power-on function or the reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, the power-on function or the reset function of the first power management chip is triggered through the external control module and the first control pin. Therefore, the three pins of the PON, the EN and the RESETIN on the first power management chip are combined into one control pin, so that the area of the chip can be reduced, and the manufacturing cost is saved; and because the control signals on the circuit board are reduced, the risk that the key signals are interfered can be reduced, and the stability of the system is improved.

In another embodiment of the present application, referring to fig. 8, a flowchart of a power control method provided in the embodiment of the present application is shown. As shown in fig. 8, the method may include:

s801: a signal level state at the first control pin is detected by a state machine module.

It should be noted that the method is applied to the power management circuit 40 described in the foregoing embodiment. In the power management circuit, the power management circuit may include a first power management chip and a reserved resistor position, the first power management chip may include a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin.

In some embodiments, prior to detecting, by the state machine module, the signal level state at the first control pin, the method may further comprise:

receiving an input voltage provided by an external power supply for a first power management chip;

performing voltage conversion on the input voltage to generate a power supply voltage;

and supplying power to the state machine module according to the power supply voltage so as to realize the initialization of the state machine module.

In the embodiment of the present application, the external power source may be represented by a Vsys power source. The second power supply pin is connected with a Vsys power supply, and the input voltage provided for the first power management chip at the moment can be represented by the Vsys voltage; and the supply voltage generated by the voltage transformation may be represented by the VPMIC voltage. Thus, after the Vsys voltage is established, the VPMIC voltage is established, at which time initialization of the state machine module can be achieved.

Further, after the state machine module is initialized, the signal level state at the first control pin has an association relation with whether the reserved resistor position is used for mounting the first resistor. Thus, in some embodiments, the method may further comprise: under the condition that a first resistor is mounted at the position of a reserved resistor, determining that the signal level state at a first control pin is a first level state; or, in the case that the first resistor is not mounted at the reserved resistor position, determining that the signal level state at the first control pin is the second level state.

In a specific example, the first level state is a high level and the second level state is a low level.

That is, after the Vsys voltage is established, the VPMIC voltage is established, at which time if the first resistor is attached at the reserved resistor location, the first control pin is pulled up to the VPMIC voltage, at which time the signal level state at the first control pin is a high level; if the first resistor is not mounted at the position of the reserved resistor, the first control pin is in a floating state, and the signal level state at the first control pin is a low level.

S802: and determining to be applied to the independent power management circuit or the combined power management circuit according to the signal level state.

It should be noted that different application scenarios can be adapted according to whether the first resistor is mounted at the reserved resistor position, which is mainly related to the signal level state at the first control pin. Specifically, the determining to apply to the independent power management circuit or the combined power management circuit according to the signal level state may include: if the signal level state is detected to be the first level state, determining to be applied to the independent power management circuit; or, if the signal level state is detected to be the second level state, determining to apply to the combined power management circuit.

In the embodiment of the present application, the first level state is a high level, and the second level state is a low level. In other words, if the signal level state is detected as the first level state, it can be determined to be applied to the independent power management circuit; if the signal level state is detected as the second level state, then it may be determined to apply to the combined power management circuit.

S803: and when the power supply is determined to be applied to the independent power supply management circuit, triggering the power-on function or the reset function of the first power supply management chip through the first control pin.

It should be noted that the state machine module in the embodiment of the present application configures the function of the first control pin as a power key function. For S803, the triggering the power-on function or the reset function of the first power management chip through the first control pin may include:

when a first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from a first level state to a second level state, and after the second level state lasts for a first preset time, the power-on operation of the first power management chip is triggered to realize the power-on function; or,

and when a second operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and after the second level state lasts for a second preset time, the power-off restarting operation of the first power management chip is triggered to realize the reset function.

In the embodiment of the application, the first operation instruction is generated according to a pressing operation of a user on the power key for a first preset time, and the second operation instruction is generated according to a pressing operation of the user on the power key for a second preset time.

That is, when the power key is pressed, the PON signal at the first control pin is pulled low and lasts for T1 time, the state machine module triggers the power-on sequence, the first power management chip starts to power on, and the baseband chip starts to power on. If the terminal equipment works abnormally and cannot be normally shut down or restarted through software, the power key can be pressed for a long time, and after the time lasts for T2 time, the state machine module triggers a power-off time sequence, the first power management chip carries out forced reset operation, and the baseband chip is powered off and restarted.

S804: and when the power supply is determined to be applied to the combined power supply management circuit, triggering the power-on function or the reset function of the first power supply management chip through the external control module and the first control pin.

It should be noted that the state machine module of the embodiment of the present application configures the function of the first control pin as an enable reset function. For S804, the triggering the power-on function or the reset function of the first power management chip through the external control module and the first control pin may include:

according to the received third operation instruction, after the second power management chip starts to be powered on, the signal level at the first control pin is controlled to be adjusted from the second level state to the first level state, and the power-on operation of the first power management chip is triggered to realize the power-on function; or,

after the second power management chip receives a reset command sent by the application processor, the signal level at the first control pin is controlled to be adjusted from a first level state to a second level state, and the power-off operation of the first power management chip is triggered; and after a third preset time, controlling the signal level at the first control pin to be adjusted from the second level state to the first level state again, and triggering the power-on operation of the first power management chip again to realize a reset function.

In an embodiment of the present application, the external control module may include a second power management chip and an application processor. The second control pin of the second power management chip is connected with the power key, and the general input/output pin of the second power management chip is connected with the first control pin of the first power management chip, so that the power-on function or the reset function of the first power management chip is realized.

That is, when the power key is pressed, the PON signal at the second control pin is pulled low, the second power management chip starts to power up, and then the PON signal at the first control pin is pulled high, so that the first power management chip starts to power up, and the baseband chip starts to power up. If the terminal equipment works abnormally and cannot be normally shut down or restarted through software, the application processor informs the second power management chip to pull down the PON signal at the first control pin, the first power management chip is powered off, after a third preset time, the second power management chip pulls up the PON signal at the first control pin, and the baseband chip is powered on again.

The embodiment provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to an application scene. Detecting, by a state machine module, a signal level state at a first control pin; determining to be applied to the independent power management circuit or the combined power management circuit according to the signal level state; when the power supply is determined to be applied to the independent power supply management circuit, triggering a power-on function or a reset function of a first power supply management chip through a first control pin; and when the power supply is determined to be applied to the combined power supply management circuit, triggering the power-on function or the reset function of the first power supply management chip through the external control module and the first control pin. Thus, a plurality of pins such as PON, EN, RESETIN and the like are combined into a control pin, different application scenes are identified by using different peripheral components, and the pins are configured into corresponding functions; therefore, the area of the chip can be reduced, and the manufacturing cost is saved; and because the control signals on the circuit board are reduced, the risk that the key signals are interfered can be reduced, and the stability of the system is improved.

In another embodiment of the present application, referring to fig. 9, a schematic structural diagram of a power management system 90 provided in the embodiment of the present application is shown. As shown in fig. 9, the power management system 90 may include at least any one of the power management circuits 40 and the baseband chip 91 described in the previous embodiments; the power management circuit 40 may perform power-on or reset control on the baseband chip 91.

In the embodiment of the present application, the application scenarios at least include an independent scenario and a combined scenario, and correspondingly, the power management system 90 can be at least divided into an independent power management system and a combined power management system. The independent power management system can be regarded as being composed of an independent power management circuit and a baseband chip, and the combined power management system can be regarded as being composed of a combined power management circuit and a baseband chip.

The following will describe the power management system in these two application scenarios in detail.

In one possible implementation, when the first power management chip 41 is singly combined to form a system, the first resistor R1 is mounted on the circuit board at this time. Referring to fig. 10, a schematic diagram of a component structure of an independent power management system according to an embodiment of the present application is shown. As shown in fig. 10, the independent power management system 100 may include a first power management chip 41, a first resistor R1, a power key K1, and a baseband chip 91.

Here, the first power management chip 41 may be BB _ PMIC, and the baseband chip 91 may be BBIC. Specifically, the BB _ PMIC may include a state machine module, a first translation circuit, a second translation circuit, a first control pin, a first power pin, and a second power pin. The first control pin is represented by a PON pin, the first power supply pin is represented by a VPMIC pin, the second power supply pin is represented by a Vsys pin, two ends of a first resistor R1 are respectively connected with the PON pin and the VPMIC pin, and two ends of a power supply key K1 are respectively connected with the PON pin and the ground; in addition, a first capacitor C1 can be externally hung at the VPMIC pin to play a role in filtering.

In another possible implementation manner, when the first power management chip 41 and the external control module form a system together, the first resistor R1 does not need to be mounted on the circuit board at this time. Referring to fig. 11, a schematic diagram of a component structure of a combined power management system provided in an embodiment of the present application is shown. As shown in fig. 11, the combined power management system 110 may include a first power management chip 41, a second power management chip 111, an application processor 112, a power key K1, and a baseband chip 91.

Here, the first power management chip 41 may be BB _ PMIC, the second power management chip 111 may be Main _ PMIC, the application processor 112 may be AP, and the baseband chip 91 may be BBIC. Specifically, the BB _ PMIC may include a state machine module, a first translation circuit, a second translation circuit, a first control pin, a first power pin, and a second power pin, and the Main _ PMIC may include a second control pin and a general purpose input output pin. Wherein, a first control pin of BB _ PMIC is represented by a PON pin, a first power supply pin is represented by a VPMIC pin, and a second power supply pin is represented by a Vsys pin; a second control pin of the Main _ PMIC is represented by a PON pin, and a general input/output pin is represented by a GPIO-01 pin; and the PON pin of the Main _ PMIC is connected with a power key K1, and the GPIO-01 pin of the Main _ PMIC is connected with the PON pin of the BB _ PMIC. In addition, a first capacitor C1 can be externally hung at the VPMIC pin of the BB _ PMIC to play a role in filtering.

Referring to fig. 12 in conjunction with fig. 10 and fig. 11, a detailed flow chart of a power supply control method provided in an embodiment of the present application is shown. As shown in fig. 12, the detailed flow may include:

s1201: the Vsys voltage builds.

S1202: VPMIC voltage is established and the state machine module is initialized.

S1203: the state machine module detects a signal level state at the first control pin.

S1204: if the signal level state is high level, the state machine module configures the function of the first control pin as a power key function.

S1205: after pressing the power key for T1 time, BB _ PMIC starts to power up and BBIC starts to power up.

S1206: after pressing the power key for time T2, BB _ PMIC is reset and BBIC is powered down and restarted.

S1207: if the signal level state is low, the state machine module configures the function of the first control pin to be an enable reset function.

S1208: and pressing a power key, pulling the signal level at the first control pin high after the Main _ PMIC starts to be powered on, starting the BB _ PMIC to be powered on, and starting the BBIC to be powered on.

S1209: the AP sends a reset command to the Main _ PMIC, the Main _ PMIC pulls down the signal level at the first control pin, and the BBIC is powered down; after time T3, Main _ PMIC pulls the signal level at the first control pin high and BBIC powers up again.

It should be noted that, the technical solution of the embodiment of the present application is to combine three pins of PON, EN and RESETIN related technologies into one control pin, and to pull up the control pin to the VPMIC voltage at the first power supply pin by adding a first resistor R1 to the circuit board. Thus, by selecting whether to mount the first resistor R1 on the circuit board, different functions of the first control pin can be realized in two scenarios.

When the BBIC alone constitutes the system, the system block diagram is shown in fig. 10, and this time, a first resistor R1 is mounted on the circuit board, and the power key is connected to the first control pin (i.e., PON pin) of BB _ PMIC.

For the stand-alone power management system 100 shown in fig. 10, the boot process is as follows:

first, the Vsys voltage is established;

secondly, establishing VPMIC voltage, and initializing a state machine module;

thirdly, the state machine module detects the signal level state of the PON pin, and the signal level state is high level at the moment because the circuit board is provided with the first resistor R1;

fourthly, the state machine module configures the function of the PON pin as a power key function: when the signal at the PON pin is pulled down for a period of time (e.g., T1 time), the state machine module triggers a power-on sequence to control the second conversion circuit to be powered on;

in the fifth step, BB _ PMIC waits for the power key to be pressed. When the power key is pressed, the signal at the PON pin is pulled low, and after a period of time (such as T1 time), the BB _ PMIC starts the power-on process, and the BBIC is powered on;

sixthly, when the terminal device works abnormally, such as BBIC software runs to death, cannot be shut down normally through the software or is restarted, the state machine module triggers a power-down time sequence to control the power-down of the second conversion circuit after a period of time (such as T2 time) is continuously pressed through a long power key, the BB _ PMIC performs reset operation, and the BBIC is powered down and restarted.

In the embodiment of the application, both the T1 time and the T2 time can be configured according to the product requirements, and generally, T1 is smaller than T2. Illustratively, T1 is set to 1 second and T2 is set to 10 seconds, but is not particularly limited.

When the BBIC and the AP form a system together, the system block diagram is shown in FIG. 11, and at this time, the first resistor R1 is not required to be mounted on the circuit board, and the power key is connected to the second control pin (PON pin) of the Main _ PMIC, and the general input/output pin (i.e., pin 01) of the Main _ PMIC is connected to the first control pin (PON pin) of the GPIO _ PMIC.

For the combined power management system 110 shown in fig. 11, the boot process is as follows:

first, the Vsys voltage is established;

secondly, establishing VPMIC voltage, and initializing a state machine module;

thirdly, the state machine module detects the signal level state of the PON pin, and the signal level state is low level at the moment because the first resistor R1 is not mounted on the circuit board;

fourthly, the state machine module configures the function of the PON pin as an enabling reset function: when the signal at the PON pin is pulled up from the low level, the state machine module triggers a power-on time sequence to control the second conversion circuit to be powered on; when the signal at the PON pin is pulled down from a high level, the state machine module triggers a power-down time sequence to control the power-down of the second conversion circuit;

in the fifth step, BB _ PMIC waits for the PON pin to be pulled high by Main _ PMIC. After the Main _ PMIC starts to be electrified, pulling up a PON pin of the BB _ PMIC, starting an electrifying process of the BB _ PMIC, and electrifying and starting the BBIC;

sixthly, when the terminal device works abnormally, for example, BBIC software runs dead, the AP may notify the Main _ PMIC to pull the PON pin of the BB _ PMIC low, the BBIC is powered off and reset, and after a period of time (for example, T3 time), the Main _ PMIC pulls the PON pin of the BB _ PMIC high again, and the BBIC is powered on again.

The embodiment of the application provides a power management system, which can determine whether to be applied to an independent power management system or a combined power management system by whether a first resistor R1 is mounted on a circuit board. In addition, no matter the power management system is independent or combined, the BB _ PMIC reduces two pins, so that the chip area of the BB _ PMIC can be reduced, and the manufacturing cost is saved; in addition, control signals on the circuit board are reduced, the risk that key signals are interfered is reduced, and the stability of the system is improved.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.

It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A power management circuit is characterized by comprising a first power management chip and a reserved resistor position, wherein the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin; wherein,

the state machine module is used for triggering a power-on function or a reset function of the first power management chip through the first control pin under the condition that the first resistor is attached to the reserved resistor position; or, under the condition that the first resistor is not mounted in the reserved resistor position, triggering a power-on function or a reset function of the first power management chip through an external control module and the first control pin.

2. The power management circuit of claim 1, wherein the first power management chip further comprises a first converting circuit and a second power pin, and the second power pin is connected to an external power supply; wherein,

the second power supply pin is used for providing input voltage for the first power supply management chip;

the first conversion circuit is used for performing voltage conversion on the input voltage to generate a power supply voltage;

the first power supply pin is specifically configured to receive the power supply voltage and supply power to the state machine module according to the power supply voltage, so as to initialize the state machine module.

3. The power management circuit of claim 2, wherein the first conversion circuit is a low dropout linear regulator (LDO) circuit.

4. The power management circuit of claim 1,

under the condition that a first resistor is mounted at the position of the reserved resistor, the signal level state at the first control pin is a first level state; or,

and under the condition that a first resistor is not mounted at the position of the reserved resistor, the signal level state at the first control pin is a second level state.

5. The power management circuit according to claim 4, wherein the power management circuit is divided into at least an independent power management circuit and a combined power management circuit according to application scenarios; wherein,

the state machine module is further configured to determine to apply the signal level state to the independent power management circuit if the signal level state at the first control pin is detected to be the first level state; or, if the signal level state at the first control pin is detected to be the second level state, determining to apply to the combined power management circuit;

the independent power management circuit is composed of the power management circuits independently, and the combined power management circuit is composed of the power management circuits and the external control module together.

6. The power management circuit of claim 5, wherein the independent power management circuit comprises the first power management chip and the first resistor, and two ends of the first resistor are respectively connected to the first control pin and the first power pin; wherein,

the state machine module is specifically configured to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, a power-on function or a reset function of the first power management chip is triggered.

7. The power management circuit of claim 6, wherein the stand-alone power management circuit further comprises a power key, one end of the power key being connected to the first control pin, the other end of the power key being connected to ground; wherein,

the power key is used for controlling the signal level at the first control pin to be adjusted from the first level state to the second level state when a first operation instruction is received, and triggering the power-on operation of the first power management chip after the second level state lasts for a first preset time so as to realize the power-on function.

8. The power management circuit of claim 7,

the power key is further configured to control the signal level at the first control pin to be adjusted from the first level state to the second level state when a second operation instruction is received, and trigger a power-down restart operation of the first power management chip after the second level state lasts for a second preset time, so as to implement the reset function.

9. The power management circuit of claim 8, wherein the first predetermined time is less than the second predetermined time.

10. The power management circuit of claim 5, wherein the combined power management circuit comprises the first power management chip and the external control module, wherein the external control module comprises a second power management chip and an application processor, wherein the second power management chip comprises a second control pin and a general purpose input/output pin, and wherein the general purpose input/output pin is connected to the first control pin; wherein,

the state machine module is specifically configured to configure the function of the first control pin as an enable reset function, so that when the signal level state at the first control pin changes, a power-on function or a reset function of the first power management chip is triggered.

11. The power management circuit of claim 10, wherein the combined power management circuit further comprises a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein,

the power key is used for controlling the second power management chip to start to be powered on when a third operation instruction is received;

and the second power management chip is used for controlling the signal level at the first control pin to be adjusted from the second level state to the first level state through the general input output pin after the power-on, and triggering the power-on operation of the first power management chip so as to realize the power-on function.

12. The power management circuit of claim 11,

the application processor is used for sending a reset command to the second power management chip;

the second power management chip is further configured to control, according to the reset command, the signal level at the first control pin to be adjusted from the first level state to the second level state through the general input output pin, and trigger a power-down operation of the first power management chip; and after a third preset time, controlling the signal level at the first control pin to be adjusted from the second level state to the first level state again through the general input/output pin, and triggering the power-on operation of the first power management chip again to realize the reset function.

13. The power management circuit according to any of claims 4 to 12, wherein the first level state is a high level and the second level state is a low level.

14. A power supply control method is characterized in that the method is applied to a power supply management circuit, and the power supply management circuit is at least divided into an independent power supply management circuit and a combined power supply management circuit according to an application scene; the method comprises the following steps:

determining whether to apply the independent power management circuit or the combined power management circuit according to the signal level state;

when the independent power management circuit is determined to be applied to the independent power management circuit, triggering a power-on function or a reset function of a first power management chip through the first control pin;

and when the power supply is determined to be applied to the combined power supply management circuit, triggering a power-on function or a reset function of the first power supply management chip through an external control module and the first control pin.

15. The method of claim 14, wherein determining whether to apply to the stand-alone power management circuit or the combined power management circuit based on the signal level status comprises:

if the signal level state is detected to be a first level state, determining to be applied to the independent power management circuit; or,

and if the signal level state is detected to be a second level state, determining to be applied to the combined power management circuit.

16. The method of claim 14, wherein prior to the detecting, by the state machine module, the signal level state at the first control pin, the method further comprises:

under the condition that a first resistor is mounted at a reserved resistor position, determining that the signal level state at the first control pin is a first level state; or,

and under the condition that the first resistor is not mounted at the position of the reserved resistor, determining that the signal level state at the first control pin is a second level state.

17. The method of claim 15 or 16, wherein the first level state is a high level and the second level state is a low level.

18. The method of claim 14, prior to the detecting, by the state machine module, the signal level state at the first control pin, the method further comprising:

receiving an input voltage provided by an external power supply for the first power management chip;

19. The method according to any of claims 14 to 18, wherein the triggering a power-up function or a reset function of the first power management chip via the first control pin when determining to apply to the independent power management circuit comprises:

when a first operation instruction is received, controlling the signal level at the first control pin to be adjusted from a first level state to a second level state, and triggering the power-on operation of the first power management chip after the second level state lasts for a first preset time so as to realize the power-on function; or,

and when a second operation instruction is received, controlling the signal level at the first control pin to be adjusted from the first level state to the second level state, and triggering the power-off restarting operation of the first power management chip after the second level state lasts for a second preset time so as to realize the reset function.

20. The method of claim 19, wherein the first predetermined time is less than the second predetermined time.

21. The method according to any one of claims 14 to 18, wherein the triggering a power-on function or a reset function of the first power management chip via the external control module and the first control pin when determining to apply to the combined power management circuit comprises:

according to a received third operation instruction, after a second power management chip starts to be powered on, controlling the signal level at the first control pin to be adjusted from the second level state to the first level state, and triggering the power-on operation of the first power management chip to realize the power-on function; or,

after the second power management chip receives a reset command sent by an application processor, controlling the signal level at the first control pin to be adjusted from the first level state to the second level state, and triggering the power-off operation of the first power management chip; and after a third preset time, controlling the signal level at the first control pin to be adjusted from the second level state to the first level state again, and triggering the power-on operation of the first power management chip again to realize the reset function.

22. A power management system, characterized in that the power management system comprises at least a power management circuit according to any one of claims 1 to 13 and a baseband chip; the power management circuit performs power-on or reset control on the baseband chip.