WO2023024764A1 - Circuit de gestion d'alimentation, et procédé et système de commande associés - Google Patents

Circuit de gestion d'alimentation, et procédé et système de commande associés Download PDF

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Publication number
WO2023024764A1
WO2023024764A1 PCT/CN2022/106467 CN2022106467W WO2023024764A1 WO 2023024764 A1 WO2023024764 A1 WO 2023024764A1 CN 2022106467 W CN2022106467 W CN 2022106467W WO 2023024764 A1 WO2023024764 A1 WO 2023024764A1
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Prior art keywords
power management
power
level state
pin
management circuit
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PCT/CN2022/106467
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English (en)
Chinese (zh)
Inventor
周洁
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Oppo广东移动通信有限公司
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Publication of WO2023024764A1 publication Critical patent/WO2023024764A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiment of the present application provides a power management system, the power management system at least includes the power management circuit and the baseband chip as described in the first aspect; power-up or reset control.
  • FIG. 6 is a schematic diagram of the composition and structure of an independent power management circuit provided by an embodiment of the present application.
  • the embodiment of the present application provides a power management circuit
  • the power management circuit includes a first power management chip and a reserved resistance position
  • the first power management chip includes a state machine module, a first control tube pin and the first power supply pin, and the two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin;
  • the first power management chip further includes a first conversion circuit and a second power pin, and the second power pin is connected to an external power supply; wherein,
  • the second power supply pin is used to provide an input voltage for the first power management chip
  • the first conversion circuit is configured to perform voltage conversion on the input voltage to generate a supply voltage
  • the first power supply pin is specifically used to receive the power supply voltage, and supply power to the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module.
  • the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein,
  • the independent power management circuit is composed of the power management circuit alone, and the combined power management circuit is composed of the power management circuit and the external control module.
  • the state machine module is specifically configured to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the first power supply is triggered. Manage the power-on function or reset function of the chip.
  • the power key is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the After the second level state lasts for a first preset time, the power-on operation of the first power management chip is triggered to realize the power-on function.
  • the power key is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction. level state, and after the second level state lasts for a second preset time, trigger a power-off and restart operation of the first power management chip, so as to realize the reset function.
  • the combined power management circuit includes the first power management chip and the external control module, the external control module includes a second power management chip and an application processor, and the second power management chip Including a second control pin and a general-purpose input and output pin, the general-purpose input and output pin is connected to the first control pin;
  • the state machine module is specifically configured to configure the function of the first control pin to enable a reset function, so that when the signal level state at the first control pin changes, trigger the first The power-on function or reset function of the power management chip.
  • the combined power management circuit further includes a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein,
  • the power key is used to control the second power management chip to start powering on when receiving the third operation instruction
  • the second power management chip is further configured to control the signal level at the first control pin to be adjusted from the first level state to the The second level state triggers the power-off operation of the first power management chip; and after the third preset time, controls the signal level at the first control pin again through the general-purpose input and output pin Adjusting from the second level state to the first level state triggers a power-on operation of the first power management chip to realize the reset function.
  • the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.
  • the determining to apply to the independent power management circuit or the combined power management circuit according to the signal level state includes:
  • the signal level state is the second level state, it is determined to be applied to the combined power management circuit.
  • the method before the state machine module detects the signal level state at the first control pin, the method further includes:
  • the method before the state machine module detects the signal level state at the first control pin, the method further includes:
  • the first preset time is shorter than the second preset time.
  • the second power management chip After the second power management chip receives the reset command sent by the application processor, control the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the power-off operation of the first power management chip; and controlling the signal level at the first control pin to be adjusted from the second level state to the first power level state again after a third preset time In the flat state, trigger the power-on operation of the first power management chip to realize the reset function.
  • BBIC Baseband chip
  • AP Application Processor
  • CPE Customer Premise Equipment
  • the first transformation circuit performs voltage transformation on the input voltage Vsys, and outputs a VPMIC voltage.
  • the first conversion circuit may be a low dropout regulator (Low Dropout Regulator, LDO) circuit.
  • VPMIC voltage It is obtained by transforming the input voltage Vsys through the LDO circuit, and supplies power to the digital circuit inside the PMIC.
  • a capacitor C1 is externally connected to the second pin (VPMIC), which can function as a filter.
  • State machine module realize the control logic of PMIC, and control the power-on/power-off sequence of the DC-DC circuit.
  • the system block diagram may include a first power management chip (BB_PMIC), a baseband chip (BBIC), a power button and a reset button.
  • BB_PMIC first power management chip
  • BBIC baseband chip
  • Main_PMIC triggers the boot process, outputs power to supply power to the AP, and pulls up the EN pin of BB_PMIC by pulling up the level of the GPIO_02 pin.
  • BB_PMIC The power-on sequence is triggered immediately, and the BBIC is powered on and started.
  • the AP When the AP detects that the BBIC software is running dead, or the BBIC cannot be restarted through the software, the AP will notify the Main_PMIC, specifically by pulling down the level of the GPIO_01 pin, and then pull down the RESETIN pin of the BB_PMIC. At this time, the BB_PMIC is reset. , trigger the BB_PMIC power-off sequence, and BBIC power-off and restart.
  • BB_PMIC separately sets three control pins with different control logics (specifically including: PON pin, EN pin and RESETIN pin), so as to achieve the purpose of application in different scenarios. If the functions of these control pins can be combined into one pin, then the number of chip pins can be reduced, thereby reducing the chip area, and the chip area directly determines the manufacturing cost of the chip, so if the chip can be reduced The number of feet can reduce the cost.
  • these control signals are key signals of the system. If these control signals are interfered by other signals on the circuit board, it will directly affect the stability of the system. The greater the number of signals, the greater the possibility of interference; therefore, if you can Combining pins to reduce the number of key signals on the board can also reduce the risk of interference and enhance system stability.
  • an embodiment of the present application provides a power management circuit
  • the power management circuit includes a first power management chip and a reserved resistance position
  • the first power management chip includes a state machine module, a first control pin and a first The two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein, the state machine module is used to mount the first resistance at the reserved resistance position, through the second A control pin triggers the power-on function or reset function of the first power management chip; or, in the case where the first resistor is not mounted in the reserved resistance position, triggers the first power management through the external control module and the first control pin The power-on function or reset function of the chip.
  • the state machine module 411 is used to trigger the power-on function or reset function of the first power management chip 41 through the first control pin when the first resistor R1 is mounted on the reserved resistor position 42; If the first resistor R1 is not installed at the position 42, the power-on function or reset function of the first power management chip 41 is triggered through the external control module and the first control pin.
  • the power management circuit 40 of the embodiment of the present application can adapt to different application scenarios according to whether the first resistor R1 is mounted on the reserved resistor position 42 .
  • the first control pin can be pulled up to the level state of the first power supply pin; otherwise, if the reserved resistance position 42 is not pasted Install the first resistor R1, then the first control pin is in a floating state at this time. That is to say, by selecting whether to mount the first resistor R1 at the reserved resistor position 42 , the application scenario of the power management circuit 40 can be identified by the state machine module 411 .
  • the power management circuit 40 of the embodiment of the present application realizes the combination of three pins PON, EN and RESETIN on the first power management chip 41 into one first control pin (indicated by PON). It is mainly by setting different components (such as the first resistor R1) on the circuit board, so that the application scene corresponding to the power management circuit 40 can be identified when the state machine module 411 is initialized, and then the state machine module can be used to 411 assigns different control logics to the first control pins to implement different control functions, so that multiple control logics can be implemented on one pin (ie, the first control pin).
  • different components such as the first resistor R1
  • the second power supply pin is connected to an external power supply, and is used to provide an input voltage for the first power management chip
  • the first power supply pin is used to receive the power supply voltage, and supply power to the state machine module 411 according to the power supply voltage, so as to realize the initialization of the state machine module 411 .
  • the first conversion circuit 412 may be an LDO circuit.
  • the external power supply can be represented by Vsys power supply
  • the first control pin can be represented by PON pin
  • the first power supply pin can be represented by VPMIC pin
  • the second power supply pin can be represented by Represented by the Vsys pin.
  • the second power supply pin is connected to the Vsys power supply.
  • the input voltage provided for the first power management chip 41 can be represented by the Vsys voltage; and the power supply voltage generated by the first conversion circuit 412 can be represented by the VPMIC voltage. express. In this way, after the voltage of Vsys is established, the voltage of VPMIC is established, and the initialization of the state machine module 411 can be implemented at this time.
  • the power management circuit 40 may further include a first capacitor C1; wherein, one end of the first capacitor C1 is connected to the first power supply pin, and the other end of the first capacitor C1 is grounded.
  • the first capacitor C1 mainly functions to filter the VPMIC voltage at the first power supply pin.
  • the first power management chip 41 may also include a second conversion circuit 413; wherein,
  • the second conversion circuit 413 is configured to perform voltage conversion on the input voltage according to the control power sequence to generate a target voltage.
  • the second conversion circuit 413 may be a DC-DC circuit.
  • the first power management chip 41 may be a baseband power management chip (BB_PMIC).
  • BB_PMIC baseband power management chip
  • BBIC baseband chip
  • the first power management chip 41 can supply power and power control for the baseband chip (BBIC), where the target voltage It is the power output provided by BB_PMIC to BBIC.
  • the power management circuit 40 can be at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein, if it is applied to an independent scenario, it can be an independent power management circuit at this time, which is determined by the power management
  • the circuit 40 is composed alone; if it is applied to a combined scenario, it may be a combined power management circuit, which is composed of the power management circuit 40 and an external control module.
  • the state machine module 411 is specifically used to configure the function of the first control pin as a power key function, so that when the signal level state at the first control pin changes, the power-on function of the first power management chip 41 is triggered or reset function.
  • the independent power management circuit 60 may further include a power key K1, one end of the power key K1 is connected to the first control pin, and the other end of the power key K1 is grounded; wherein,
  • the power key K1 is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the second level state lasts for the first time After a preset time, the power-on operation of the first power management chip 41 is triggered to realize the power-on function.
  • the terminal device works abnormally, for example, the software of the baseband chip runs to death, or cannot be shut down or restarted normally through the software, it is necessary to reset the first power management chip 41 at this time. in,
  • the first level state is high level
  • the second level state is low level
  • the first operation instruction is generated according to the user pressing the power key for a first preset time
  • the second operation instruction is generated according to the user pressing the power key for a second preset time.
  • the external control module may include a second power management chip and an application processor.
  • the combined power management circuit 70 may include a first power management chip 41, a second power management chip 71 and an application processor 72, and the second power management chip 71 may include a second control pin and a general input and output pin, And the general-purpose input and output pins are connected to the first control pin;
  • the combined power management circuit 70 may further include a power key K1, one end of the power key K1 is connected to the second control pin, and the other end of the power key K1 is grounded; wherein,
  • the power key K1 is used to control the second power management chip 71 to start powering on when receiving the third operation instruction;
  • the second power management chip 71 is used to control the signal level at the first control pin from the second level state to the first level state through the general-purpose input and output pins after the power-on, and trigger the first
  • the power-on operation of the power management chip is used to realize the power-on function.
  • the terminal device works abnormally, for example, the software of the baseband chip runs to death, and cannot be shut down or restarted normally through the software, it is necessary to use the second power management chip 71 and the application processor 72 to control the first power supply.
  • the management chip 41 is reset. in,
  • the second power management chip 71 is also used to control the signal level at the first control pin from the first level state to the second level state through the general-purpose input and output pins according to the reset command, and trigger the first power supply The power-off operation of the management chip 41; and after the third preset time, the signal level at the first control pin is controlled again by the general-purpose input and output pins to be adjusted from the second level state to the first level state, triggering The power-on operation of the first power management chip 41 is implemented to realize the reset function.
  • the first level state is high level
  • the second level state is low level
  • the application processor 72 notifies the second power management chip 71 to pull down the PON signal at the first control pin, and the first power management chip 41 is powered off. After the time T3 elapses, the second power management chip 71 pulls the PON signal at the first control pin high again, and the baseband chip is powered on again.
  • This embodiment provides a power management circuit
  • the power management circuit includes a first power management chip and a reserved resistance position
  • the first power management chip includes a state machine module, a first control pin and a first power pin, The two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein, the state machine module is used to mount the first resistor at the reserved resistance position, through the first control pin Trigger the power-on function or reset function of the first power management chip; or, when the first resistor is not mounted in the reserved resistance position, trigger the power-on of the first power management chip through the external control module and the first control pin function or reset function.
  • the power management circuit includes a first power management chip and a reserved resistance position
  • the first power management chip includes a state machine module, a first control pin and a first power pin, The two ends of the reserved resistance position are respectively connected to the first control pin and the first power supply pin; wherein, the state machine module is used to mount the first resistor at the reserved resistance position, through the first control
  • FIG. 8 shows a schematic flowchart of a power control method provided in an embodiment of the present application. As shown in Figure 8, the method may include:
  • the power management circuit may include a first power management chip and a reserved resistance position
  • the first power management chip may include a state machine module, a first control pin and a first power pin, and the reserved resistance position The two ends are respectively connected to the first control pin and the first power supply pin.
  • the method may further include:
  • the external power supply may be represented by a Vsys power supply.
  • the second power supply pin is connected to the Vsys power supply.
  • the input voltage provided for the first power management chip can be represented by the Vsys voltage; and the power supply voltage generated through voltage conversion can be represented by the VPMIC voltage.
  • the voltage of Vsys is established, the voltage of VPMIC is established, and the initialization of the state machine module can be realized at this time.
  • the method may further include: in the case of mounting the first resistor at the reserved resistor position, determining that the signal level state at the first control pin is the first level state; or, at If the first resistor is not placed in the reserved resistor position, it is determined that the signal level state at the first control pin is the second level state.
  • the first level state is high level
  • the second level state is low level
  • the VPMIC voltage is established.
  • the first resistor is mounted in the reserved resistance position, then the first control pin is pulled up to the VPMIC voltage. At this time, the first control pin.
  • the signal level state is high level; if the first resistor is not placed in the reserved resistance position, then the first control pin is in a floating state, and the signal level state at the first control pin is low level at this time.
  • the determining to apply to the independent power management circuit or combined power management circuit according to the signal level state may include: if it is detected that the signal level state is the first level state, then determining to apply to the independent power management circuit ; or, if it is detected that the signal level state is the second level state, it is determined to apply to the combined power management circuit.
  • the first level state is high level
  • the second level state is low level.
  • the state machine module in the embodiment of the present application configures the function of the first control pin as a power button function.
  • the triggering the power-on function or reset function of the first power management chip through the first control pin may include:
  • the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and after the second level state lasts for the first preset time, trigger The power-on operation of the first power management chip, so as to realize the power-on function; or,
  • the first operation instruction is generated according to the user pressing the power button for a first preset time
  • the second operation instruction is generated according to the user pressing the power button for a second preset time Generated.
  • the first preset time is shorter than the second preset time.
  • the first preset time may be represented by T1
  • the second preset time may be represented by T2.
  • the first preset time can be set to 1 second
  • the second preset time can be set to 10 seconds.
  • the state machine module when the power button is pressed, the PON signal at the first control pin is pulled low, and after a duration of T1, the state machine module triggers the power-on sequence, the first power management chip starts to power on, and the baseband chip Power on and start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, you can also press the power button for a long time, and after T2 time, the state machine module triggers the power-off sequence, and the first power management chip performs a forced reset operation. The chip is powered off and restarted.
  • the function of configuring the first control pin is to enable a reset function.
  • the triggering the power-on function or reset function of the first power management chip through the external control module and the first control pin may include:
  • the second power management chip After the second power management chip receives the reset command sent by the application processor, it controls the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the first power management chip to switch off. Electrical operation; and after the third preset time, control the signal level at the first control pin again to be adjusted from the second level state to the first level state, triggering the re-power-on operation of the first power management chip, to Realize the reset function.
  • the application processor notifies the second power management chip to pull down the PON signal at the first control pin, the first power management chip is powered off, and after the third After a preset time, the second power management chip pulls up the PON signal at the first control pin, and the baseband chip is powered on again.
  • This embodiment provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios.
  • the signal level state at the first control pin is detected by the state machine module; according to the signal level state, it is determined to be applied to an independent power management circuit or a combined power management circuit; when it is determined to be applied to an independent power management circuit, through the first control
  • the pin triggers the power-on function or reset function of the first power management chip; when it is determined to be used in a combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.
  • FIG. 9 shows a schematic diagram of the composition and structure of a power management system 90 provided in an embodiment of the present application.
  • the power management system 90 may at least include any power management circuit 40 and a baseband chip 91 described in the foregoing embodiments; wherein, the power management circuit 40 may perform power-on or reset control for the baseband chip 91 .
  • the application scenarios include at least an independent scenario and a combined scenario
  • the power management system 90 can be at least divided into an independent power management system and a combined power management system.
  • the independent power management system can be regarded as composed of an independent power management circuit and a baseband chip
  • the combined power management system can be regarded as composed of a combined power management circuit and a baseband chip.
  • the first power management chip 41 may be a BB_PMIC
  • the baseband chip 91 may be a BBIC
  • the BB_PMIC may include a state machine module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second power supply pin.
  • the first power management chip 41 may be a BB_PMIC
  • the second power management chip 111 may be a Main_PMIC
  • the application processor 112 may be an AP
  • the baseband chip 91 may be a BBIC.
  • BB_PMIC may include a state machine module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second power supply pin
  • Main_PMIC may include a second control pin and a general input output pin.
  • the first control pin of BB_PMIC is represented by a PON pin
  • the first power supply pin is represented by a VPMIC pin
  • the second power supply pin is represented by a Vsys pin
  • the second control pin of Main_PMIC is represented by a PON pin
  • the general-purpose input and output pins are represented by GPIO_01 pins
  • the PON pins of Main_PMIC are connected to the power button K1
  • the GPIO_01 pins of Main_PMIC are connected to the PON pins of BB_PMIC.
  • the first capacitor C1 can also be connected to the VPMIC pin of the BB_PMIC for filtering.
  • the state machine module detects the signal level state at the first control pin.
  • S1208 Press the power button, after the Main_PMIC starts to be powered on, pull up the signal level at the first control pin, the BB_PMIC starts to be powered on, and the BBIC starts to be powered on.
  • S1209 AP sends a reset command to Main_PMIC, Main_PMIC pulls down the signal level at the first control pin, and powers off BBIC; after T3 time, Main_PMIC pulls up the signal level at the first control pin, and BBIC restarts electricity.
  • the technical solution of the embodiment of this application is to combine the three pins PON, EN and RESETIN in the related art into one control pin, and by adding the first resistor R1 on the circuit board, it can Pulled up to the VPMIC voltage at the first supply pin. In this way, by choosing whether to mount the first resistor R1 on the circuit board, different functions of the first control pin in two scenarios can be realized.
  • the boot process is as follows:
  • the Vsys voltage is established
  • the VPMIC voltage is established, and the state machine module is initialized
  • the state machine module detects the signal level state of the PON pin, because the first resistor R1 is mounted on the circuit board, so the signal level state at this time is high;
  • Step 4 The state machine module configures the function of the PON pin as the power button function: when the signal at the PON pin is pulled down for a period of time (such as T1 time), the state machine module will trigger the power-on sequence to control the second conversion Power on the circuit;
  • Step 5 BB_PMIC waits for the power button to be pressed.
  • the power button is pressed, the signal at the PON pin is pulled down, and after a period of time (such as T1 time), BB_PMIC starts the power-on process, and BBIC is powered on and started;
  • Step 6 When the terminal device is working abnormally, such as BBIC software running dead, unable to shut down or restart normally through the software, you can press and hold the power button for a period of time (such as T2 time), and the state machine module will trigger the power-off sequence. Control the second conversion circuit to be powered off, the BB_PMIC performs a reset operation, and the BBIC is powered off and restarted.
  • both the T1 time and the T2 time can be configured according to product requirements.
  • T1 is less than T2.
  • T1 is set to 1 second
  • T2 is set to 10 seconds, but this is not specifically limited.
  • the boot process is as follows:
  • the Vsys voltage is established
  • the VPMIC voltage is established, and the state machine module is initialized
  • the state machine module detects the signal level state of the PON pin, because the first resistor R1 is not mounted on the circuit board, so the signal level state at this time is low;
  • the state machine module configures the function of the PON pin to enable the reset function: when the signal at the PON pin is pulled up from the low level, the state machine module will trigger the power-on sequence to control the second conversion circuit. When the signal at the PON pin is pulled down from high level, the state machine module will trigger the power-off sequence to control the power-off of the second conversion circuit;
  • Step 6 when the terminal equipment is working abnormally, such as BBIC software running dead, the AP can notify Main_PMIC to pull down the PON pin of BB_PMIC, and BBIC is powered off and reset. The pin is pulled high, and the BBIC is powered on again.
  • the embodiment of the present application provides a power management system. Whether the first resistor R1 is mounted on the circuit board can determine whether it is applied to an independent power management system or a combined power management system. Moreover, whether it is an independent power management system or a combined power management system, BB_PMIC has reduced two pins, which can reduce the chip area of BB_PMIC and save manufacturing costs; in addition, it also reduces the control signals on the circuit board and reduces the number of key signals. The risk of being disturbed improves the system stability.
  • the power management circuit includes a first power management chip and a reserved resistance position
  • the first power management chip includes a state machine module, a first control pin and a first power pin, and the reserved resistance position The two ends are respectively connected to the first control pin and the first power pin; wherein, the state machine module is used to trigger the first power management through the first control pin when the first resistor is mounted at the reserved resistor position The power-on function or reset function of the chip; or, when the first resistor is not mounted in the reserved resistance position, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Power Sources (AREA)

Abstract

Sont divulgués un circuit de gestion d'alimentation ainsi qu'un procédé et un système de commande associés. Le circuit de gestion d'alimentation comprend : une première puce de gestion d'alimentation et une position de résistance réservée ; la première puce de gestion d'alimentation comprend un module de machine d'état, une première broche de commande et une première broche d'alimentation ; deux extrémités de la position de résistance réservée sont respectivement reliées à la première broche de commande et à la première broche d'alimentation ; le module de machine d'état étant configuré pour déclencher une fonction de mise sous tension ou une fonction de réinitialisation de la première puce de gestion d'alimentation par l'intermédiaire de la première broche de commande lorsqu'une première résistance est fixée à la position de résistance réservée ; ou, lorsque la première résistance n'est pas fixée à la position de résistance réservée, le module de machine d'état étant configuré pour déclencher une fonction de mise sous tension ou une fonction de réinitialisation de la première puce de gestion d'alimentation au moyen d'un module de commande externe et de la première broche de commande. Trois broches dans une première puce de gestion d'alimentation sont combinées en une seule broche de commande, ce qui réduit ainsi la superficie de puce et les coûts de fabrication, et réduit en outre le risque d'interférence avec des signaux clés et améliore la stabilité du système.
PCT/CN2022/106467 2021-08-25 2022-07-19 Circuit de gestion d'alimentation, et procédé et système de commande associés WO2023024764A1 (fr)

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