WO2023024788A1

WO2023024788A1 - Power management circuit and control method therefor, and power management system

Info

Publication number: WO2023024788A1
Application number: PCT/CN2022/107681
Authority: WO
Inventors: 周洁
Original assignee: Oppo广东移动通信有限公司
Priority date: 2021-08-25
Filing date: 2022-07-25
Publication date: 2023-03-02
Also published as: CN113726126A; CN113726126B

Abstract

Disclosed in the embodiments of the present application are a power management circuit and a control method therefor, and a power management system. The power management circuit comprises a first power management IC and a first resistor, the first power management IC comprising a second resistor, a first switch, an analog-digital conversion module, a state machine module, a first control pin and a first power pin, wherein inside the first power management IC, the first switch and the second resistor are connected in series between the first power pin and the first control pin, the first power pin is connected to the state machine module, and the first control pin is respectively connected to the state machine module and the analog-digital conversion module; and outside the first power management IC, the first resistor is connected in series between the first control pin and the ground. In this way, three pins in a first power management IC are combined into one control pin, such that the area of the IC is reduced, and the manufacturing cost is reduced; and the risk of a key signal being interfered with is also reduced, thereby improving the stability of a system.

Description

A power management circuit and its control method and system

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202110983161.7 and the application name "A power management circuit and its control method and system" submitted to the China Patent Office on August 25, 2021, the entire contents of which are incorporated by reference in this application.

technical field

The present application relates to the technical field of power management, in particular to a power management circuit and its control method and system.

Background technique

The baseband chip (Baseband IC, BBIC) refers to the chip used to synthesize the baseband signal to be transmitted, or to decode the received baseband signal, which mainly completes the information processing function of the terminal equipment.

At present, BBIC generally uses a dedicated Baseband Power Management IC (BB_PMIC) to power and control it. In order to implement multiple control methods on the BB_PMIC, the control pins of the BB_PMIC will at least include three independent power key signal pins (PON), enable signal pins (EN), and reset signal pins (RESETIN). control pins, and their control logic varies. However, since BB_PMIC separately sets three control pins with different control logics, the chip area of BB_PMIC is relatively large, and the manufacturing cost is relatively high; moreover, these control signals are key signals of the system, and are easy to be manipulated on the circuit board. Other signal interference directly affects the system stability.

Contents of the invention

The technical scheme of the present application is realized like this:

In the first aspect, the embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a first resistor, the first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, A state machine module, a first control pin and a first power supply pin; wherein,

Inside the first power management chip, the first switch and the second resistor are connected in series between the first power supply pin and the first control pin, the first power supply pin is connected to the state machine module, and the first control pin is respectively connected to the The state machine module is connected with the analog-to-digital conversion module;

Outside the first power management chip, the first resistor is connected in series between the first control pin and the ground.

In the second aspect, the embodiment of the present application provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; the method includes:

After closing the first switch, reading the signal voltage at the first control pin through the analog-to-digital conversion module;

The signal voltage is compared with the preset interval through the state machine module, and the application to the independent power management circuit or combined power management circuit is determined according to the comparison result;

When it is determined to be applied to an independent power management circuit, the power-on function or reset function of the first power management chip is triggered through the first control pin;

When it is determined to be applied to the combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

In the third aspect, the embodiment of the present application provides a power management system, the power management system at least includes the power management circuit and the baseband chip as described in the first aspect; power-up or reset control.

Description of drawings

FIG. 1 is a schematic diagram of the internal composition structure of a BB_PMIC;

Fig. 2 provides a schematic diagram of the composition structure of a BBIC independent system;

Fig. 3 provides a schematic diagram of the composition structure of a BBIC combined system;

FIG. 4 is a schematic diagram of the composition and structure of a power management circuit provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of the composition and structure of another power management circuit provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of the composition and structure of an independent power management circuit provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of the composition and structure of a combined power management circuit provided by an embodiment of the present application;

FIG. 8 is a schematic flowchart of a power control method provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of the composition and structure of a power management system provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of the composition and structure of an independent power management system provided by the embodiment of the present application;

FIG. 11 is a schematic diagram of the composition and structure of a combined power management system provided by an embodiment of the present application;

FIG. 12 is a schematic flowchart of a detailed power control method provided by an embodiment of the present application.

Detailed ways

In the first aspect, the embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a first resistor, the first power management chip includes a second resistor, a first switch, a modulus A conversion module, a state machine module, a first control pin and a first power supply pin; wherein,

Inside the first power management chip, the first switch and the second resistor are connected in series between the first power supply pin and the first control pin, and the first power supply pin is also Connected to the state machine module, the first control pin is also connected to the state machine module and the analog-to-digital conversion module respectively;

Outside the first power management chip, the first resistor is connected in series between the first control pin and ground.

In some embodiments, the analog-to-digital conversion module is configured to read the signal voltage at the first control pin after closing the first switch;

The state machine module is configured to trigger the power-on function or reset function of the first power management chip through the first control pin when the signal voltage satisfies a first preset interval; or, in the When the signal voltage satisfies the second preset interval, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.

In some embodiments, the state machine module includes a register unit; wherein,

The register unit is configured to store the signal voltage read by the analog-to-digital conversion module, and disconnect the first switch after the storage is completed;

The state machine module is specifically configured to read the signal voltage from the register unit, and compare the signal voltage with a preset interval; wherein, when the signal voltage satisfies the first preset interval , triggering the power-on function or reset function of the first power management chip through the first control pin; or, when the signal voltage satisfies the second preset range, through the external control module and the second A control pin triggers a power-on function or a reset function of the first power management chip.

In some embodiments, the first resistor is used to make the signal voltage read by the analog-to-digital conversion module satisfy the first preset interval when the resistance value is a first value; Or, when the resistance value is the second value, the signal voltage read by the analog-to-digital conversion module satisfies the second preset interval.

In some embodiments, the first power management chip further includes a first conversion circuit and a second power supply pin, and the second power supply pin is connected to an external power supply; wherein,

The second power supply pin is used to provide an input voltage for the first power management chip;

The first conversion circuit is configured to perform voltage conversion on the input voltage to generate a supply voltage;

The first power supply pin is specifically used to receive the power supply voltage, and supply power to the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module and the analog-to-digital conversion module.

In some embodiments, the first conversion circuit is a low dropout linear regulator LDO circuit.

In some embodiments, the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein,

The state machine module is further configured to determine to apply to the independent power management circuit if the signal voltage satisfies the first preset interval; or, if the signal voltage satisfies the second preset interval, Then it is determined to be applied to the combined power management circuit;

Wherein, the independent power management circuit is composed of the power management circuit alone, and the combined power management circuit is composed of the power management circuit and an external control module.

In some embodiments, the independent power management circuit includes the first power management chip and the first resistor; wherein,

The state machine module is specifically configured to configure the function of the first control pin as a power button function, so that after the first switch is turned off, when the signal level state at the first control pin is When a change occurs, the power-on function or reset function of the first power management chip is triggered.

In some embodiments, the independent power management circuit further includes a power key, one end of the power key is connected to the first control pin, and the other end of the power key is grounded; wherein,

The power button is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the second power level After the flat state lasts for a first preset time, a power-on operation of the first power management chip is triggered to realize the power-on function.

In some embodiments, the power key is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction. level state, and after the second level state lasts for a second preset time, trigger a power-off and restart operation of the first power management chip, so as to realize the reset function.

In some embodiments, the first preset time is shorter than the second preset time.

In some embodiments, the combined power management circuit includes the first power management chip, the first resistor, and the external control module, and the external control module includes a second power management chip and an application processor, so The second power management chip includes a second control pin and a general-purpose input and output pin, and the general-purpose input and output pin is connected to the first control pin; wherein,

The state machine module is specifically configured to configure the function of the first control pin to enable a reset function, so that after the first switch is turned off, when the signal level at the first control pin is When the state changes, the power-on function or reset function of the first power management chip is triggered.

In some embodiments, the combined power management circuit further includes a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein,

The power key is used to control the second power management chip to start powering on when receiving the third operation instruction;

The second power management chip is configured to control the signal level at the first control pin to be adjusted from the second level state to the first level through the general-purpose input and output pin after the power-on state, triggering a power-on operation of the first power management chip, so as to realize the power-on function.

In some embodiments, the application processor is configured to send a reset command to the second power management chip;

The second power management chip is further configured to control the signal level at the first control pin to be adjusted from the first level state to the The second level state triggers the power-off operation of the first power management chip; and after the third preset time, controls the signal level at the first control pin again through the general-purpose input and output pin Adjusting from the second level state to the first level state triggers a power-on operation of the first power management chip to realize the reset function.

In some embodiments, the first level state is high level, and the second level state is low level.

Comparing the signal voltage with a preset interval through a state machine module, and determining whether to apply to the independent power management circuit or the combined power management circuit according to the comparison result;

When it is determined to be applied to the independent power management circuit, triggering a power-on function or a reset function of the first power management chip through the first control pin;

In some embodiments, after reading the signal voltage at the first control pin through the analog-to-digital conversion module, the method further includes:

storing the signal voltage to a register unit in the state machine module, and turning off the first switch after the storage is completed.

In some embodiments, the determining to apply to the independent power management circuit or the combined power management circuit according to the comparison result includes:

If the signal voltage satisfies the first preset interval, determine to apply to the independent power management circuit; or,

If the signal voltage satisfies the second preset interval, it is determined to be applied to the combined power management circuit.

In some embodiments, the method also includes:

When the resistance value of the first resistor is the first value, it is determined that the signal voltage satisfies the first preset interval; or,

When the resistance of the first resistor is the second value, it is determined that the signal voltage satisfies the second preset interval.

In some embodiments, before closing the first switch, the method further includes:

receiving an input voltage provided by an external power supply for the first power management chip;

performing voltage conversion on the input voltage to generate a supply voltage;

Powering the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module and the analog-to-digital conversion module.

In some embodiments, when it is determined to be applied to the independent power management circuit, the triggering the power-on function or reset function of the first power management chip through the first control pin includes:

When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and the second level state lasts for the first preset After a period of time, trigger the power-on operation of the first power management chip to realize the power-on function; or,

When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and continue in the second level state After a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.

In some embodiments, when it is determined to be applied to the combined power management circuit, the triggering the power-on function or reset function of the first power management chip through the external control module and the first control pin includes:

According to receiving the third operation instruction, after the second power management chip starts to be powered on, the signal level at the first control pin is controlled to be adjusted from the second level state to the first level state, triggering the second power management chip. A power-on operation of a power management chip to realize the power-on function; or,

After the second power management chip receives the reset command sent by the application processor, control the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the power-off operation of the first power management chip; and controlling the signal level at the first control pin to be adjusted from the second level state to the first power level state again after a third preset time In the flat state, trigger the power-on operation of the first power management chip to realize the reset function.

In the third aspect, the embodiment of the present application provides a power management system, the power management system at least includes the power management circuit and the baseband chip according to any one of the first aspect; wherein, the power management circuit is the The baseband chip is powered on or reset controlled.

In order to understand the characteristics and technical contents of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict. It should also be pointed out that the term "first\second\third" involved in the embodiment of the present application is only used to distinguish similar objects, and does not represent a specific ordering of objects. Understandably, "first\second\ The specific order or sequence of "third" can be interchanged where allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

With the continuous development of electronic technology, terminal devices such as smart phones and handheld computers are becoming more and more popular. At present, the baseband chip (Baseband IC, BBIC) of the terminal platform generally has two application scenarios. One application scenario is to form a system together with an application processor (Application Processor, AP), such as applied to terminal equipment; One application scenario is that BBIC independently forms a system, for example, it is applied to Customer Premise Equipment (CPE).

Here, BBIC generally uses a dedicated baseband power management IC (BB_PMIC) to power and control it. For the above two application scenarios, the control logic of BB_PMIC's power-on and reset is completely different. In order to implement multiple control methods on the BB_PMIC, the current control pins of the BB_PMIC include three independent pins, PON, EN, and RESETIN, and their control logics are also different.

Referring to FIG. 1 , it provides a schematic diagram of the internal structure of the BB_PMIC. As shown in Figure 1, the BB_PMIC includes a first conversion circuit, a state machine module, a second conversion circuit and a first pin (Vsys), a second pin (VPMIC), a third pin (PON), a fourth pin (EN) and the fifth pin (RESETIN). Wherein, the first pin (Vsys) is connected to an external power supply (indicated by Vsys power supply), and the second pin (VPMIC) is connected to an external capacitor (indicated by C1).

Vsys power supply: The input power of BB_PMIC is generally powered by the battery in the terminal device.

The first transformation circuit: performs voltage transformation on the input voltage Vsys, and outputs a VPMIC voltage. In the embodiment of the present application, the first conversion circuit may be a low dropout regulator (Low Dropout Regulator, LDO) circuit.

The second conversion circuit: performs voltage conversion on the input voltage Vsys, converts it into a voltage available to the BBIC and outputs it. In the embodiment of the present application, the second conversion circuit may be a DC conversion (Direct Current-Direct Current, DC-DC) circuit.

VPMIC voltage: It is obtained by transforming the input voltage Vsys through the LDO circuit, and supplies power to the digital circuit inside the PMIC. In addition, a capacitor C1 is externally connected to the second pin (VPMIC), which can function as a filter.

State machine module: realize the control logic of PMIC, and control the power-on/power-off sequence of the DC-DC circuit.

PON: Power key signal, default high level. After the level is pulled low for a period of time (eg T1), the state machine module triggers the power-on sequence to control the power-on of the DC-DC circuit, and BB_PMIC starts the power-on process.

EN: Enable signal, low level when power off. When the level is pulled high, the state machine module immediately triggers the power-on sequence, controls the power-on of the DC-DC circuit, and BB_PMIC starts the power-on process.

RESETIN: reset signal, when BB_PMIC is working normally, keep high level. When the level is pulled low, the state machine module triggers the power-off sequence to control the power-off of the DC-DC circuit, and the BBIC is powered-off and reset.

The related technologies will be described below in combination with the system block diagrams of the two application scenarios.

(1) BBIC constitutes a separate system

When applied to an independent scenario, the BBIC alone forms a system at this time, that is, the block diagram corresponding to the BBIC independent system is shown in FIG. 2 . The system block diagram may include a first power management chip (BB_PMIC), a baseband chip (BBIC), a power button and a reset button.

Among them, the power key is connected to the PON pin of BB_PMIC, the reset key is connected to the RESETIN pin, and the EN pin is suspended. After the user presses the power button for a period of time (such as T1), the BB_PMIC power-on sequence is triggered to supply power to the BBIC.

In the case of booting, if the BBIC works abnormally, such as the software running dead, unable to shut down or restart the system through the software, the user can force reset the BB_PMIC by pressing the reset button, trigger the power-off sequence of the BB_PMIC, and then power off the BBIC , to complete the reset and restart of the BBIC.

(2) AP+BBIC jointly form a system

When applied to a combination scenario, the BBIC is used in conjunction with the AP at this time, for example, it is applied to a terminal device, that is, a corresponding block diagram of the BBIC combination system is shown in FIG. 3 . The system block diagram may include a first power management chip (BB_PMIC), a baseband chip (BBIC), an application processor (AP), a second power management chip (Main_PMIC) and a power key.

Among them, the AP is the application processor of the terminal device, and Main_PMIC is the main power management chip of the terminal device, which is responsible for powering on and off of the terminal device and supplying power to the AP. The power button is hung on Main_PMIC, and BB_PMIC needs to be powered on by Main_PMIC. Since there is a strict power-on sequence relationship between Main_PMIC and BB_PMIC, in order to strictly control the sequence, the power-on control signal sent by Main_PMIC needs to immediately trigger the power-on of BB_PMIC without delay, so the PON pin control of BB_PMIC cannot be used at this time To power on BB_PMIC, you need to use the EN signal of BB_PMIC to control the power on of BB_PMIC. In addition, the power button of the terminal device is connected to the PON pin of Main_PMIC. Main_PMIC also includes two general-purpose input/output (General-Purpose Input/Output, GPIO) pins: GPIO_01 pin and GPIO_02 pin; among them, the GPIO_01 pin is connected to the RESETIN pin of BB_PMIC to control the reset of BB_PMIC; GPIO_02 The pin is connected to the EN pin of BB_PMIC to control the power-on enable of BB_PMIC. The PON pin of BB_PMIC is left floating and not used.

After the user presses the power button for a period of time (such as T1), Main_PMIC triggers the boot process, outputs power to supply power to the AP, and pulls up the EN pin of BB_PMIC by pulling up the level of the GPIO_02 pin. At this time, BB_PMIC The power-on sequence is triggered immediately, and the BBIC is powered on and started.

When the AP detects that the BBIC software is running dead, or the BBIC cannot be restarted through the software, the AP will notify the Main_PMIC, specifically by pulling down the level of the GPIO_01 pin, and then pull down the RESETIN pin of the BB_PMIC. At this time, the BB_PMIC is reset. , trigger the BB_PMIC power-off sequence, and BBIC power-off and restart.

It can be seen that, in the related art, BB_PMIC separately sets three control pins of different control logics (specifically including: PON pin, EN pin and RESETIN pin), so as to achieve the purpose of application in different scenarios. If the functions of these control pins can be combined into one pin, then the number of chip pins can be reduced, thereby reducing the chip area, and the chip area directly determines the manufacturing cost of the chip, so if the chip can be reduced The number of feet can reduce the cost. In addition, these control signals are key signals of the system. If these control signals are interfered by other signals on the circuit board, it will directly affect the stability of the system. The greater the number of signals, the greater the possibility of interference; therefore, if you can Combining pins to reduce the number of key signals on the board can also reduce the risk of interference and enhance system stability.

Based on this, an embodiment of the present application provides a power management circuit, the power management circuit includes a first power management chip and a first resistor, the first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, a state machine module, the first control pin and the first power pin; wherein, inside the first power management chip, the first switch and the second resistor are connected in series between the first power pin and the first control pin, and the second A power supply pin is connected to the state machine module, and the first control pin is respectively connected to the state machine module and the analog-to-digital conversion module; outside the first power management chip, the first resistor is connected in series between the first control pin and the ground . In this way, since the three pins of the power key signal pin (PON), the enable signal pin (EN) and the reset signal pin (RESETIN) in BB_PMIC are combined into one control pin, it is not only possible to reduce the BB_PMIC The chip area saves manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

Various embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, refer to FIG. 4 , which shows a schematic structural diagram of a power management circuit provided in an embodiment of the present application. As shown in FIG. 4, the power management circuit 40 may include a first power management chip 41 and a first resistor R1, and the first power management chip 41 may include a state machine module 411, a second resistor R2, a first switch S1, a module A digital conversion module (Analog-to-Digital Converter, ADC) 412, a first control pin and a first power supply pin; wherein,

Inside the first power management chip 41, the first switch S1 and the second resistor R2 are connected in series between the first power supply pin and the first control pin, and the first power supply pin is also connected to the state machine module 411, the first The control pins are also connected to the state machine module 411 and the analog-to-digital conversion module 412 respectively;

Outside the first power management chip 41 , the first resistor R1 is connected in series between the first control pin and the ground.

It should be noted that the power management circuit 40 of the embodiment of the present application can adapt to different application scenarios according to the resistance value of the first resistor R1. In FIG. 4, if the resistance value of the first resistor R1 mounted here is the first value, then the signal voltage read by the analog-to-digital conversion module 412 is the first voltage value; otherwise, if the resistance value of the first resistor R1 mounted here is The resistance value of the first resistor R1 is the second value, so the signal voltage read by the analog-to-digital conversion module 412 is the second voltage value. That is to say, by attaching the first resistors R1 with different resistance values, and then reading different voltage values through the analog-to-digital conversion module 412 , different application scenarios of the power management circuit 40 can be identified according to these voltage values.

It should also be noted that the power management circuit 40 of the embodiment of the present application realizes the combination of three pins PON, EN and RESETIN on the first power management chip 41 into one first control pin (indicated by PON). It is mainly by setting different components on the circuit board (such as the first resistor R1, the second resistor R2, the first switch S1 and the analog-to-digital conversion module 412, etc.), so that it can be identified when the state machine module 411 is initialized. According to the application scenario corresponding to the power management circuit 40, the state machine module 411 is used to assign different control logics to the first control pin to realize different control functions, so that multiple control logics can be integrated into one pin (that is, the first pin A control pin) to achieve.

Specifically, in some embodiments, the analog-to-digital conversion module 412 is configured to read the signal voltage at the first control pin after closing the first switch S1;

The state machine module 411 is used to trigger the power-on function or reset function of the first power management chip 41 through the first control pin when the signal voltage meets the first preset interval; or, when the signal voltage meets the second preset interval , the power-on function or reset function of the first power management chip 41 is triggered through the external control module and the first control pin.

Further, in some embodiments, the state machine module 411 may include a register unit (not shown in the figure); wherein,

A register unit, configured to store the signal voltage read by the analog-to-digital conversion module 412, and disconnect the first switch S1 after the storage is completed;

The state machine module 411 is specifically used to read the signal voltage from the register unit, and compare the signal voltage with the preset interval; wherein, when the signal voltage satisfies the first preset interval, trigger the first power supply through the first control pin Manage the power-on function or reset function of the chip 41; or, when the signal voltage meets the second preset interval, trigger the power-on function or reset function of the first power management chip 41 through the external control module and the first control pin.

That is to say, in the embodiment of the present application, the first switch S1 needs to be closed first, and then the signal voltage at the first control pin is read through the analog-to-digital conversion module 412; and then the signal voltage is stored in the state machine module 411 In the register unit, the first switch S1 is then opened. At this time, the state machine module 411 can read the signal voltage from the register unit, and compare it with the preset interval (including the first preset interval and/or the second preset interval, etc.); When the interval is set, this time is applied to an independent scene, and the power-on function or reset function of the first power management chip 41 is triggered through the first control pin; or, when the signal voltage meets the second preset interval, this time is applied to the combination In different scenarios, the power-on function or reset function of the first power management chip 41 is triggered by the external control module and the first control pin, so as to realize different control functions in different application scenarios.

In some embodiments, on the basis of the power management circuit 40 shown in FIG. 4, referring to FIG. 5, the first power management chip 41 may further include a first conversion circuit 413 and a second power pin; wherein,

The second power supply pin is connected to an external power supply, and is used to provide an input voltage for the first power management chip;

The first conversion circuit 413 is configured to perform voltage conversion on the input voltage to generate a supply voltage;

The first power supply pin is used to receive a power supply voltage, and supply power to the state machine module 411 according to the power supply voltage, so as to realize the initialization of the state machine module 411 and the analog-to-digital conversion module 412 .

In a specific example, the first conversion circuit 413 may be an LDO circuit.

It should be noted that, in this embodiment of the application, the external power supply can be represented by Vsys power supply, the first control pin can be represented by PON pin, the first power supply pin can be represented by VPMIC pin, and the second power supply pin can be represented by Represented by the Vsys pin.

It should also be noted that the second power supply pin is connected to the Vsys power supply. At this time, the input voltage provided for the first power management chip 41 can be represented by the Vsys voltage; and the power supply voltage generated by the first conversion circuit 413 can be represented by the VPMIC voltage. express. In this way, after the voltage of Vsys is established, the voltage of VPMIC is established, at this time, the initialization of the state machine module 411 and the initialization of the analog-to-digital conversion module 412 can be realized.

Further, in some embodiments, referring to FIG. 5 , the power management circuit 40 may further include a first capacitor C1; wherein, one end of the first capacitor C1 is connected to the first power supply pin, and the other end of the first capacitor C1 is grounded. . Here, the first capacitor C1 mainly functions to filter the VPMIC voltage at the first power supply pin.

Further, in some embodiments, referring to FIG. 5 , the first power management chip 41 may further include a second conversion circuit 414; wherein,

The state machine module 411 is further configured to generate a control power supply sequence according to the signal level state at the first control pin;

The second conversion circuit 414 is configured to perform voltage conversion on the input voltage according to the control power sequence to generate a target voltage.

In a specific example, the second converting circuit 414 may be a DC-DC circuit.

It should be noted that the first power management chip 41 may be a baseband power management chip (BB_PMIC). In this way, in the power management system, in addition to the power management circuit 40, a baseband chip (BBIC) can also be included, wherein the first power management chip 41 can supply power and power control for the baseband chip (BBIC), where the target voltage It is the power output provided by BB_PMIC to BBIC.

It should also be noted that, after the state machine module 411 and the analog-to-digital conversion module 412 are initialized, the signal voltage at the first control pin is related to the resistance value of the mounted first resistor R1. Specifically, the signal voltage can be obtained by dividing the voltage between the first resistor R1 and the second resistor R2. In some embodiments, the first resistor R1 is used to make the signal voltage read by the analog-to-digital conversion module 412 satisfy the first preset interval when the resistance value is the first value; or, when the resistance value is In the case of the second value, the signal voltage read by the analog-to-digital conversion module 412 satisfies the second preset interval.

That is to say, by attaching the first resistor R1 with different resistance values, the signal voltage read by the analog-to-digital conversion module 412 can be a different voltage value. After the signal voltage is stored in the register unit of the state machine module 411, The state machine module 411 reads the signal voltage from the register unit, and determines whether the signal voltage satisfies the first preset interval or the second preset interval, thereby identifying different application scenarios.

Exemplarily, for the first resistor R1 and the second resistor R2, it is assumed that the resistance value of the second resistor R2 can be 100K ohms (Ω), at this time, if the resistance value of the first resistor R1 is 2.2KΩ, then it can be determined The signal voltage read by the analog-to-digital conversion module 412 satisfies the first preset interval; if the resistance value of the first resistor R1 can be 4.7KΩ, then it can be determined that the signal voltage read by the analog-to-digital conversion module 412 satisfies the second preset interval interval, but without any limitation.

It can be understood that, according to application scenarios, the power management circuit 40 can be at least divided into an independent power management circuit and a combined power management circuit. In some embodiments, for the state machine module 411, it can also be used to determine that the signal voltage is applied to an independent power management circuit if the signal voltage satisfies the first preset interval; or, if the signal voltage satisfies the second preset interval, It is determined to apply to the combination power management circuit.

In the embodiment of the present application, if it is applied to an independent scene, it can be an independent power management circuit at this time, which is composed of the power management circuit 40 alone, that is, the independent power management circuit includes the first power management chip 41 and the first resistor R1 ; If it is applied to a combined scene, it can be a combined power management circuit at this time, which is composed of a power management circuit 40 and an external control module, that is, the combined power management circuit includes a first power management chip 41, a first resistor R1 and an external control module.

In some embodiments, for an independent power management circuit, referring to FIG. 6 , the independent power management circuit 60 may include a first power management chip 41 and a first resistor R1. Wherein, inside the first power management chip 41, the first switch S1 and the second resistor R2 are connected in series between the first power pin and the first control pin, and the first power pin is also connected to the state machine module 411, The first control pin is also connected to the state machine module 411 and the analog-to-digital conversion module 412 respectively; outside the first power management chip 41 , the first control pin is connected to the ground after being connected to the first resistor R1.

In this embodiment of the application, the state machine module 411 is specifically used to configure the function of the first control pin as the power key function, so that after the first switch S1 is turned off, when the signal level at the first control pin is When the state changes, the power-on function or reset function of the first power management chip 41 is triggered.

Further, in some embodiments, referring to FIG. 6 , the independent power management circuit 60 may further include a power key K1, one end of the power key K1 is connected to the first control pin, and the other end of the power key K1 is grounded; wherein,

The power key K1 is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the second level state lasts for the first time After a preset time, the power-on operation of the first power management chip 41 is triggered to realize the power-on function.

In addition, in some embodiments, when the terminal device works abnormally, for example, the software of the baseband chip runs to death, or cannot be shut down or restarted normally through the software, it is necessary to reset the first power management chip 41 at this time. in,

The power key K1 is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction, and the second level state lasts for the second time After a preset time, the power-off and restart operation of the first power management chip 41 is triggered to realize the reset function.

Wherein, the first level state is high level, and the second level state is low level.

It should be noted that the first operation instruction is generated according to the user pressing the power key for a first preset time, and the second operation instruction is generated according to the user pressing the power key for a second preset time. .

In the embodiment of the present application, the first preset time is shorter than the second preset time. Wherein, the first preset time may be represented by T1, and the second preset time may be represented by T2. In a specific example, the first preset time can be set to 1 second, and the second preset time can be set to 10 seconds.

That is to say, when the power button is pressed, the PON signal at the first control pin is pulled down, and after a duration of T1, the state machine module 411 triggers the power-on sequence, and the first power management chip 41 starts to power on, The baseband chip is powered on and started. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, it is also possible to press the power button for a long time, and after T2 time, the state machine module 411 triggers the power-off sequence, and the first power management chip 41 performs a forced reset operation. , the baseband chip is powered off and restarted.

In some embodiments, for combined power management circuits, the external control module may include a second power management chip and an application processor. 7, the combined power management circuit 70 may include a first power management chip 41, a first resistor R1, a second power management chip 71 and an application processor 72, and the second power management chip 71 may include a second control pin and a common Input and output pins, and the general input and output pins are connected to the first control pin; wherein,

The state machine module 411 is specifically used to configure the function of the first control pin to enable the reset function, so that after the first switch S1 is turned off, when the signal level state at the first control pin changes, trigger The power-on function or reset function of the first power management chip 41 .

Further, in some embodiments, referring to FIG. 7 , the combined power management circuit 70 may further include a power key K1, one end of the power key K1 is connected to the second control pin, and the other end of the power key K1 is grounded; wherein,

The power key K1 is used to control the second power management chip 71 to start powering on when receiving the third operation instruction;

The second power management chip 71 is used to control the signal level at the first control pin from the second level state to the first level state through the general-purpose input and output pins after the power-on, and trigger the first The power-on operation of the power management chip to realize the power-on function.

In addition, in some embodiments, when the terminal device works abnormally, for example, the software of the baseband chip runs to death, and cannot be shut down or restarted normally through the software, it is necessary to use the second power management chip 71 and the application processor 72 to control the first power supply. The management chip 41 is reset. in,

The application processor 72 is configured to send a reset command to the second power management chip 71;

The second power management chip 71 is also used to control the signal level at the first control pin from the first level state to the second level state through the general-purpose input and output pins according to the reset command, and trigger the first power supply The power-off operation of the management chip 41; and after the third preset time, the signal level at the first control pin is controlled again by the general-purpose input and output pins to be adjusted from the second level state to the first level state, triggering The power-on operation of the first power management chip 41 is implemented to realize the reset function.

It should be noted that the third operation instruction is generated according to the user pressing the power key. In addition, the third preset time is denoted by T3, and the value of the third preset time can be set to a millisecond level. Exemplarily, the third preset time is 20 milliseconds, but it is not limited thereto.

It should also be noted that the second control pin may also be represented by a PON pin, and the general-purpose input and output pin may be represented by a GPIO_0 pin. In the embodiment of the present application, the PON pin of the second power management chip 71 is connected to the power key, and the GPIO_01 pin of the second power management chip 71 is connected to the PON pin of the first power management chip 41 to realize the first The power-on function or reset function of the power management chip 41 .

That is to say, when the power key is pressed, the PON signal at the second control pin is pulled low, and the second power management chip 71 starts to power on, and then the PON signal at the first control pin is pulled high, so that The first power management chip 41 starts to be powered on, and the baseband chip is powered on to start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, the application processor 72 notifies the second power management chip 71 to pull down the PON signal at the first control pin, and the first power management chip 41 is powered off. After the time T3 elapses, the second power management chip 71 pulls the PON signal at the first control pin high again, and the baseband chip is powered on again.

It should also be noted that since the first resistor R1 can have multiple resistance values, multiple preset intervals can also be set correspondingly, so that more types of application scenarios can be distinguished. In other words, the embodiment of the present application is not limited to the independent power management circuit in the independent scenario and the combined power management circuit in the combined scenario, and can also correspond to other application scenarios, so that the first power management chip (that is, the baseband power management chip, uses BB_PMIC Indicates that the function is extensible.

This embodiment provides a power management circuit. The power management circuit includes a first power management chip and a first resistor. The first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, a state machine module, and a second resistor. A control pin and a first power pin; wherein, inside the first power management chip, the first switch and the second resistor are connected in series between the first power pin and the first control pin, and the first power pin It is also connected to the state machine module, and the first control pin is also connected to the state machine module and the analog-to-digital conversion module respectively; outside the first power management chip, the first resistor is connected in series between the first control pin and the ground. Like this, because three pins of PON, EN and RESETIN on the first power management chip are merged into one control pin, thereby not only can reduce chip area, save manufacturing cost; The risk of key signal being interfered can be reduced, and the system stability is improved.

In another embodiment of the present application, refer to FIG. 8 , which shows a schematic flowchart of a power control method provided in an embodiment of the present application. As shown in Figure 8, the method may include:

S801: After closing the first switch, read the signal voltage at the first control pin through the analog-to-digital conversion module.

It should be noted that this method is applied to the power management circuit 40 described in the foregoing embodiments. In the power management circuit, it may include a first power management chip and a first resistor, and the first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, a state machine module, a first control pin, and a second resistor. A power pin. Specifically, inside the first power management chip, the first switch and the second resistor are connected in series between the first power supply pin and the first control pin, the first power supply pin is also connected to the state machine module, and the first control The pins are also respectively connected to the state machine module and the analog-to-digital conversion module; outside the first power management chip, the first resistor is connected in series between the first control pin and the ground.

In this way, after the first switch is closed, the signal voltage at the first control pin can be read through the analog-to-digital conversion module according to the voltage division between the first resistor and the second resistor. In addition, since the first resistors with different resistance values are mounted, different voltage values can be read through the analog-to-digital conversion module, and different application scenarios of the power management circuit can be identified according to these voltage values.

In some embodiments, before closing the first switch, the method may further include:

Perform voltage conversion on the input voltage to generate a supply voltage;

The state machine module is powered according to the power supply voltage to realize the initialization of the state machine module and the analog-to-digital conversion module.

In this embodiment of the present application, the external power supply may be represented by a Vsys power supply. The second power supply pin is connected to the Vsys power supply. At this time, the input voltage provided for the first power management chip can be represented by the Vsys voltage; and the power supply voltage generated through voltage conversion can be represented by the VPMIC voltage. In this way, after the Vsys voltage is established, the VPMIC voltage is established, and at this time, the state machine module and the analog-to-digital conversion module can be initialized.

It should be noted that after the initialization of the state machine module and the analog-to-digital conversion module, the signal voltage at the first control pin is related to the resistance value of the mounted first resistor. In some embodiments, the method may further include: when the resistance of the first resistor is a first value, determining that the signal voltage satisfies a first preset interval; or, when the resistance of the first resistor is a second value In the case of , it is determined that the signal voltage satisfies the second preset interval.

Further, in some embodiments, after the signal voltage at the first control pin is read by the analog-to-digital conversion module, the method may further include: storing the signal voltage into a register unit in the state machine module, and storing Turn off the first switch when finished.

That is to say, by attaching the first resistors with different resistance values, the signal voltages read by the analog-to-digital conversion module can be different voltage values. After the signal voltages are stored in the register unit of the state machine module 411, the state The machine module 411 reads the signal voltage from the register unit, and determines whether the signal voltage satisfies the first preset interval or the second preset interval, and then identifies different application scenarios.

S802: Using a state machine module to compare the signal voltage with a preset interval, and determine to apply to the independent power management circuit or the combined power management circuit according to the comparison result.

It should be noted that, according to application scenarios, power management circuits can be at least divided into independent power management circuits and combined power management circuits. Specifically, after the signal voltage is compared with the preset interval by the state machine module, the determination to apply to the independent power management circuit or combined power management circuit according to the comparison result may include:

If the signal voltage satisfies the first preset interval, it is determined to be applied to an independent power management circuit; or,

If the signal voltage satisfies the second preset interval, it is determined to apply to the combined power management circuit.

Specifically, if it is applied to an independent scenario, it can be an independent power management circuit at this time, which is composed of a power management circuit alone, that is, the independent power management circuit includes a first power management chip and a first resistor; if it is applied to a combined scenario , this time may be a combined power management circuit, which is composed of a power management circuit and an external control module, that is, the combined power management circuit includes a first power management chip, a first resistor and an external control module.

S803: When it is determined to be applied to an independent power management circuit, trigger a power-on function or a reset function of the first power management chip through the first control pin.

It should be noted that the state machine module in the embodiment of the present application configures the function of the first control pin as a power button function. For S803, the triggering the power-on function or reset function of the first power management chip through the first control pin may include:

When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and after the second level state lasts for the first preset time, trigger The power-on operation of the first power management chip, so as to realize the power-on function; or,

When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and after the second level state lasts for a second preset time, trigger The power-off and restart operation of the first power management chip is implemented to realize the reset function.

In the embodiment of the present application, the first operation instruction is generated according to the user pressing the power button for a first preset time, and the second operation instruction is generated according to the user pressing the power button for a second preset time Generated.

That is to say, when the power button is pressed, the PON signal at the first control pin is pulled low, and after a duration of T1, the state machine module triggers the power-on sequence, the first power management chip starts to power on, and the baseband chip Power on and start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, you can also press the power button for a long time, and after T2 time, the state machine module triggers the power-off sequence, and the first power management chip performs a forced reset operation. The chip is powered off and restarted.

S804: When it is determined to be applied to a combined power management circuit, trigger a power-on function or a reset function of the first power management chip through the external control module and the first control pin.

It should be noted that, in the state machine module of the embodiment of the present application, the function of configuring the first control pin is to enable a reset function. For S804, the triggering the power-on function or reset function of the first power management chip through the external control module and the first control pin may include:

According to receiving the third operation instruction, after the second power management chip starts to be powered on, control the signal level at the first control pin to be adjusted from the second level state to the first level state, triggering the first power management chip The power-on operation to realize the power-on function; or,

After the second power management chip receives the reset command sent by the application processor, it controls the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the first power management chip to switch off. Electrical operation; and after the third preset time, control the signal level at the first control pin again to be adjusted from the second level state to the first level state, triggering the re-power-on operation of the first power management chip, to Realize the reset function.

In the embodiment of the present application, the external control module may include a second power management chip and an application processor. Wherein, the second control pin of the second power management chip is connected to the power key, and the general-purpose input and output pins of the second power management chip are connected to the first control pin of the first power management chip, so as to realize the first power management chip power-on function or reset function.

That is to say, when the power button is pressed, the PON signal at the second control pin is pulled low, the second power management chip starts to power on, and then the PON signal at the first control pin is pulled high, so that the first A power management chip starts to be powered on, and the baseband chip is powered on to start. If the terminal device works abnormally and cannot be shut down or restarted normally through the software, the application processor notifies the second power management chip to pull down the PON signal at the first control pin, the first power management chip is powered off, and after the third After a preset time, the second power management chip pulls up the PON signal at the first control pin, and the baseband chip is powered on again.

This embodiment provides a power control method, which is applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios. After the first switch is closed, the signal voltage at the first control pin is read through the analog-to-digital conversion module; the signal voltage is compared with the preset interval through the state machine module, and the application to the independent power supply is determined according to the comparison result management circuit or the combined power management circuit; when it is determined to be applied to the independent power management circuit, the power-on function or reset function of the first power management chip is triggered through the first control pin; when it is determined to be applied to the When the power management circuit is combined, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin. In this way, multiple pins such as PON, EN, and RESETIN are combined into one control pin, and different peripheral components are used to identify different application scenarios, and the pins are configured into corresponding functions; thus not only reducing the chip area, but also saving Manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

In yet another embodiment of the present application, refer to FIG. 9 , which shows a schematic diagram of the composition and structure of a power management system 90 provided in an embodiment of the present application. As shown in FIG. 9 , the power management system 90 may at least include any power management circuit 40 and a baseband chip 91 described in the foregoing embodiments; wherein, the power management circuit 40 may perform power-on or reset control for the baseband chip 91 .

In the embodiment of the present application, the application scenarios include at least an independent scenario and a combined scenario, and correspondingly, the power management system 90 can be at least divided into an independent power management system and a combined power management system. Wherein, the independent power management system can be regarded as composed of an independent power management circuit and a baseband chip, and the combined power management system can be regarded as composed of a combined power management circuit and a baseband chip.

The power management systems in these two application scenarios will be described in detail below.

In a possible implementation manner, when a single group of first power management chips forms a system, the power key is connected to the first control pin of the first power management chip at this time. For the first resistor R1, an appropriate resistance value is selected through calculation, so that the signal voltage divided by the first resistor R1 and the second resistor R2 conforms to the first preset range. Referring to FIG. 10 , it shows a schematic diagram of the composition and structure of an independent power management system provided by an embodiment of the present application. As shown in FIG. 10 , the independent power management system 100 may include a first power management chip 41 , a first resistor R1 , a power key K1 and a baseband chip 91 .

Here, the first power management chip 41 may be a BB_PMIC, and the baseband chip 91 may be a BBIC. Specifically, BB_PMIC may include a state machine module, a second resistor R2, a first switch S1, an analog-to-digital conversion module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second Power pin. Among them, the first control pin is represented by a PON pin, the first power supply pin is represented by a VPMIC pin, and the second power supply pin is represented by a Vsys pin, and a first resistor R1 and a power button are attached to the PON pin K1, and the other end of the first resistor R1 and the power button K1 are both connected to the ground; in addition, the first capacitor C1 can also be connected to the pin of the VPMIC for filtering.

In another possible implementation, when the first power management chip and the external control module form a system together, the power key is connected to the second control pin of the second power management chip, and the general input of the second power management chip The output pin is connected to the first control pin of the first power management chip. For the first resistor R1, an appropriate resistance value is selected through calculation, so that the signal voltage divided by the first resistor R1 and the second resistor R2 conforms to the second preset range. Referring to FIG. 11 , it shows a schematic diagram of the composition and structure of a combined power management system provided by an embodiment of the present application. As shown in FIG. 11 , the combined power management system 110 may include a first power management chip 41 , a second power management chip 111 , an application processor 112 , a first resistor R1 , a power key K1 and a baseband chip 91 .

Here, the first power management chip 41 may be a BB_PMIC, the second power management chip 111 may be a Main_PMIC, the application processor 112 may be an AP, and the baseband chip 91 may be a BBIC. Specifically, BB_PMIC may include a state machine module, a second resistor R2, a first switch S1, an analog-to-digital conversion module, a first conversion circuit, a second conversion circuit, a first control pin, a first power supply pin, and a second The power supply pins, Main_PMIC may include second control pins and general input and output pins. Wherein, the first control pin of BB_PMIC is represented by a PON pin, the first power supply pin is represented by a VPMIC pin, and the second power supply pin is represented by a Vsys pin; the second control pin of Main_PMIC is represented by a PON pin, The general-purpose input and output pins are represented by GPIO_01 pins; and the PON pin of Main_PMIC is connected to the power button K1, the GPIO_01 pin of Main_PMIC is connected to the PON pin of BB_PMIC, and the first resistor R1 is attached to the PON pin of BB_PMIC . In addition, the first capacitor C1 can also be connected to the VPMIC pin of the BB_PMIC for filtering.

Referring to FIG. 10 and FIG. 11 , refer to FIG. 12 , which shows a detailed flowchart of a power control method provided by an embodiment of the present application. As shown in Figure 12, the detailed process may include:

S1201: Vsys voltage is established.

S1202: VPMIC voltage is established, and the state machine module and the analog-to-digital conversion module are initialized.

S1203: Turn on the first switch S1, and the analog-to-digital conversion module reads the signal voltage at the first control pin PON; and after the signal voltage is stored in the register unit, turn off the first switch S1.

S1204: The state machine module reads the signal voltage from the register unit.

S1205: If the signal voltage satisfies the first preset interval, the state machine module configures the function of the first control pin as a power key function.

S1206: After pressing the power button for T1 time, the BB_PMIC starts to be powered on, and the BBIC is powered on and started.

S1207: After pressing the power button for T2, the BB_PMIC is reset, and the BBIC is powered off and restarted.

S1208: If the signal voltage satisfies the second preset interval, the state machine module configures the function of the first control pin to enable the reset function.

S1209: Press the power button, after the Main_PMIC starts to be powered on, pull up the signal level at the first control pin, the BB_PMIC starts to be powered on, and the BBIC starts to be powered on.

S1210: AP sends a reset command to Main_PMIC, Main_PMIC pulls down the signal level at the first control pin, and powers off BBIC; after T3 time, Main_PMIC pulls up the signal level at the first control pin, and BBIC restarts electricity.

S1211: If the signal voltage satisfies the third preset range, the state machine module configures the function of the first control pin as other function options.

It should be noted that the technical solution of the embodiment of the present application is to combine the PON, EN and RESETIN pins in the related art into one control pin, and the signal voltage at the first control pin (PON pin) is at the BB_PMIC The inside of the chip is pulled up to the VPMIC voltage through the second resistor R2 and the first switch S1, and the signal voltage is connected to the ADC module inside the BB_PMIC chip. The first control pin (PON pin) is pulled down to ground after being connected to the first resistor R1 outside the BB_PMIC chip. After closing the first switch S1, the signal voltage at the first control pin (PON pin) can be obtained by dividing the voltage between the first resistor R1 and the second resistor R2. By mounting the first resistor R1 with different resistance values, the ADC module Different voltage values will be read to identify different application scenarios, thereby configuring the PON pins to corresponding functions.

When BBIC constitutes a system alone, the system block diagram is shown in Figure 10 for details. At this time, the power button is connected to the PON pin of BB_PMIC, and the first resistor R1 with a suitable resistance value is calculated and selected, so that the first resistor R1 and the second resistor R2 are voltage-divided. The signal voltage at the PON pin conforms to the first preset range.

For the independent power management system 100 shown in FIG. 10 , the boot process is as follows:

In the first step, the Vsys voltage is established;

In the second step, the VPMIC voltage is established, the state machine module is initialized, and the ADC module is initialized;

In the third step, the first switch S1 is closed, and the ADC module reads the signal voltage at the PON pin; and after the signal voltage is stored in the register unit of the state machine module, the first switch S1 is opened.

In the fourth step, the state machine module reads the signal voltage from the register unit, and compares the signal voltage with the preset interval; the preset interval here is a preset voltage interval, and the embodiment of the present application may refer to the first preset interval. Set interval, second preset interval, third preset interval and so on.

The fifth step, the state machine module configures the PON pin function as the power key function: when the signal at the PON pin is pulled down for a period of time (such as T1 time), the state machine module will trigger the power-on sequence and control the second conversion Power on the circuit;

Step 6, BB_PMIC waits for the power button to be pressed. When the power button is pressed, the signal at the PON pin is pulled down, and after a period of time (such as T1 time), BB_PMIC starts the power-on process, and BBIC is powered on and started;

Step 7: When the terminal device is working abnormally, such as the BBIC software running dead, unable to shut down or restart normally through the software, you can press and hold the power button for a period of time (such as T2 time), and the state machine module will trigger the power-off sequence. Control the second conversion circuit to be powered off, the BB_PMIC performs a reset operation, and the BBIC is powered off and restarted.

In this embodiment of the application, both the T1 time and the T2 time can be configured according to product requirements. Generally, T1 is less than T2. Exemplarily, T1 is set to 1 second, and T2 is set to 10 seconds, but this is not specifically limited.

When BBIC and AP form a system together, the system block diagram is shown in Figure 11. At this time, the power button is connected to the PON pin of Main_PMIC, the GPIO_01 pin of Main_PMIC is connected to the PON pin of BB_PMIC, and the first resistor R1 with an appropriate resistance value is calculated and selected. , so that the signal voltage at the PON pin divided by the first resistor R1 and the second resistor R2 conforms to the second preset range.

For the combined power management system 110 shown in FIG. 11 , the boot process is as follows:

In the first step, the Vsys voltage is established;

In the fifth step, the state machine module configures the function of the PON pin to enable the reset function: when the signal at the PON pin is pulled up from the low level, the state machine module will trigger the power-on sequence to control the second conversion circuit. When the signal at the PON pin is pulled down from high level, the state machine module will trigger the power-off sequence to control the power-off of the second conversion circuit;

Step 6, BB_PMIC waits for the PON pin to be pulled high by Main_PMIC. After Main_PMIC starts to be powered on, pull the PON pin of BB_PMIC high, BB_PMIC starts the power-on process, and BBIC is powered on to start;

Step 7: When the terminal equipment works abnormally, such as the BBIC software running dead, the AP can notify Main_PMIC to pull down the PON pin of BB_PMIC, BBIC powers off and resets, and after a period of time (such as T3 time), Main_PMIC will pull the PON pin of BB_PMIC again. The pin is pulled high, and the BBIC is powered on again.

In addition, the embodiment of the present application may also be applied to other scenarios. Specifically, as long as the resistance values of multiple first resistors R1 are reasonably calculated and distributed, and multiple voltage intervals are preset, more scene distinctions can be realized, that is, the technical solutions of the embodiments of the present application are not limited to the above two Application scenarios make the BB_PMIC function scalable.

In short, in the embodiment of this application, multiple control pins (such as PON, EN and RESETIN pins) can be combined into one control pin, and then different peripheral circuits are used to identify different application scenarios, and the The control pins are configured with corresponding functions. Here, when distinguishing different resistance values of the first resistor, the ADC module may not be used, but a pure hardware method may be used. For example, multiple voltage comparators can be set up to determine which preset voltage range the signal voltage falls in, and then make subsequent judgments. It should be noted that the advantage of using a comparator is that the judgment speed is faster than the reading speed of the ADC, which is more advantageous in scenarios with strict timing requirements; the disadvantage is that the identifiable application scenarios are limited by the number of comparators, and Not as much as ADC.

The embodiment of the present application provides a power management system. According to different resistance values of the mounted first resistor R1, it can be determined whether it is applied to an independent power management system or a combined power management system. Moreover, whether it is an independent power management system or a combined power management system, BB_PMIC has reduced two pins, which can reduce the chip area of BB_PMIC and save manufacturing costs; in addition, it also reduces the control signals on the circuit board and reduces the number of key signals. The risk of being disturbed improves the system stability.

The above are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

It should be noted that in this application, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above embodiments of the present application are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in this application can be combined arbitrarily to obtain new method embodiments under the condition of no conflict.

The features disclosed in several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Industrial Applicability

In the embodiment of the present application, the power management circuit includes a first power management chip and a first resistor, and the first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, a state machine module, a first control pin and The first power supply pin; wherein, inside the first power management chip, the first switch and the second resistor are connected in series between the first power supply pin and the first control pin, and the first power supply pin is connected to the state machine module , the first control pin is respectively connected to the state machine module and the analog-to-digital conversion module; outside the first power management chip, the first resistor is connected in series between the first control pin and the ground. In this way, since the three pins of the power key signal pin (PON), the enable signal pin (EN) and the reset signal pin (RESETIN) in BB_PMIC are combined into one control pin, it is not only possible to reduce the BB_PMIC The chip area saves manufacturing cost; and because the control signals on the circuit board are reduced, the risk of key signals being interfered can be reduced, and the system stability is improved.

Claims

A power management circuit, the power management circuit includes a first power management chip and a first resistor, the first power management chip includes a second resistor, a first switch, an analog-to-digital conversion module, a state machine module, a first control pin and the first power supply pin; where,

Inside the first power management chip, the first switch and the second resistor are connected in series between the first power supply pin and the first control pin, and the first power supply pin is also Connected to the state machine module, the first control pin is also connected to the state machine module and the analog-to-digital conversion module respectively;

Outside the first power management chip, the first resistor is connected in series between the first control pin and ground.
The power management circuit according to claim 1, wherein,

The analog-to-digital conversion module is configured to read the signal voltage at the first control pin after closing the first switch;

The state machine module is configured to trigger the power-on function or reset function of the first power management chip through the first control pin when the signal voltage satisfies a first preset interval; or, in the When the signal voltage satisfies the second preset interval, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.
The power management circuit according to claim 2, wherein the state machine module comprises a register unit; wherein,

The register unit is configured to store the signal voltage read by the analog-to-digital conversion module, and disconnect the first switch after the storage is completed;

The state machine module is specifically configured to read the signal voltage from the register unit, and compare the signal voltage with a preset interval; wherein, when the signal voltage satisfies the first preset interval , triggering the power-on function or reset function of the first power management chip through the first control pin; or, when the signal voltage satisfies the second preset range, through the external control module and the second A control pin triggers a power-on function or a reset function of the first power management chip.
The power management circuit according to claim 2 or 3, wherein,

The first resistor is used to make the signal voltage read by the analog-to-digital conversion module satisfy the first preset interval when the resistance value is a first value; or,

When the resistance value is the second value, the signal voltage read by the analog-to-digital conversion module satisfies the second preset interval.
The power management circuit according to claim 1, wherein the first power management chip further includes a first conversion circuit and a second power pin, and the second power pin is connected to an external power supply; wherein,

The second power supply pin is used to provide an input voltage for the first power management chip;

The first conversion circuit is configured to perform voltage conversion on the input voltage to generate a supply voltage;

The first power supply pin is specifically used to receive the power supply voltage, and supply power to the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module and the analog-to-digital conversion module.
The power management circuit according to claim 5, wherein the first conversion circuit is a low dropout linear regulator LDO circuit.
The power management circuit according to claim 4, wherein the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; wherein,

The state machine module is further configured to determine to apply to the independent power management circuit if the signal voltage satisfies the first preset interval; or, if the signal voltage satisfies the second preset interval, Then it is determined to be applied to the combined power management circuit;

Wherein, the independent power management circuit is composed of the power management circuit alone, and the combined power management circuit is composed of the power management circuit and an external control module.
The power management circuit according to claim 7, wherein the independent power management circuit comprises the first power management chip and the first resistor; wherein,

The state machine module is specifically configured to configure the function of the first control pin as a power button function, so that after the first switch is turned off, when the signal level state at the first control pin is When a change occurs, the power-on function or reset function of the first power management chip is triggered.
The power management circuit according to claim 8, wherein the independent power management circuit further includes a power key, one end of the power key is connected to the first control pin, and the other end of the power key is grounded; wherein ,

The power button is used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the first operation instruction, and the second power level After the flat state lasts for a first preset time, a power-on operation of the first power management chip is triggered to realize the power-on function.
The power management circuit according to claim 9, wherein,

The power key is also used to control the signal level at the first control pin to be adjusted from the first level state to the second level state when receiving the second operation instruction, and After the second level state lasts for a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.
The power management circuit according to claim 10, wherein the first preset time is shorter than the second preset time.
The power management circuit according to claim 7, wherein the combined power management circuit comprises the first power management chip, the first resistor and the external control module, and the external control module comprises a second power management A chip and an application processor, the second power management chip includes a second control pin and a general-purpose input and output pin, and the general-purpose input and output pin is connected to the first control pin; wherein,

The state machine module is specifically configured to configure the function of the first control pin to enable a reset function, so that after the first switch is turned off, when the signal level at the first control pin is When the state changes, the power-on function or reset function of the first power management chip is triggered.
The power management circuit according to claim 12, wherein the combined power management circuit further comprises a power key, one end of the power key is connected to the second control pin, and the other end of the power key is grounded; wherein ,

The power key is used to control the second power management chip to start powering on when receiving the third operation instruction;

The second power management chip is configured to control the signal level at the first control pin to be adjusted from the second level state to the first level through the general-purpose input and output pin after the power-on state, triggering a power-on operation of the first power management chip, so as to realize the power-on function.
The power management circuit of claim 13, wherein,

The application processor is configured to send a reset command to the second power management chip;

The second power management chip is further configured to control the signal level at the first control pin to be adjusted from the first level state to the The second level state triggers the power-off operation of the first power management chip; and after the third preset time, controls the signal level at the first control pin again through the general-purpose input and output pin Adjusting from the second level state to the first level state triggers a power-on operation of the first power management chip to realize the reset function.
The power management circuit according to any one of claims 9, 10, 13 and 14, wherein the first level state is high level, and the second level state is low level.
A power control method, applied to a power management circuit, and the power management circuit is at least divided into an independent power management circuit and a combined power management circuit according to application scenarios; the method includes:

After closing the first switch, reading the signal voltage at the first control pin through the analog-to-digital conversion module;

Comparing the signal voltage with a preset interval through a state machine module, and determining whether to apply to the independent power management circuit or the combined power management circuit according to the comparison result;

When it is determined to be applied to the independent power management circuit, triggering the power-on function or reset function of the first power management chip through the first control pin;

When it is determined to be applied to the combined power management circuit, the power-on function or reset function of the first power management chip is triggered through the external control module and the first control pin.
The method according to claim 16, wherein, after reading the signal voltage at the first control pin through the analog-to-digital conversion module, the method further comprises:

storing the signal voltage to a register unit in the state machine module, and turning off the first switch after the storage is completed.
The method according to claim 17, wherein the determining to apply to the independent power management circuit or the combined power management circuit according to the comparison result comprises:

If the signal voltage satisfies the first preset interval, determine to apply to the independent power management circuit; or,

If the signal voltage satisfies the second preset interval, it is determined to be applied to the combined power management circuit.
The method according to claim 18, wherein said method further comprises:

When the resistance value of the first resistor is the first value, it is determined that the signal voltage satisfies the first preset interval; or,

When the resistance of the first resistor is the second value, it is determined that the signal voltage satisfies the second preset interval.
The method of claim 16, prior to closing the first switch, the method further comprising:

receiving an input voltage provided by an external power supply for the first power management chip;

performing voltage conversion on the input voltage to generate a supply voltage;

Powering the state machine module according to the power supply voltage, so as to realize the initialization of the state machine module and the analog-to-digital conversion module.
The method according to any one of claims 16 to 20, wherein when it is determined to be applied to the independent power management circuit, the power-on function of the first power management chip is triggered through the first control pin or reset functions, including:

When the first operation instruction is received, the signal level at the first control pin is controlled to be adjusted from the first level state to the second level state, and the second level state lasts for the first preset After a period of time, trigger the power-on operation of the first power management chip to realize the power-on function; or,

When receiving the second operation instruction, control the signal level at the first control pin to be adjusted from the first level state to the second level state, and continue in the second level state After a second preset time, a power-off and restart operation of the first power management chip is triggered to realize the reset function.
The method of claim 21, wherein the first predetermined time is less than the second predetermined time.
The method according to any one of claims 16 to 20, wherein when it is determined to be applied to the combined power management circuit, the first power management chip is triggered by the external control module and the first control pin The power-on function or reset function, including:

According to receiving the third operation instruction, after the second power management chip starts to be powered on, the signal level at the first control pin is controlled to be adjusted from the second level state to the first level state, triggering the second power management chip. A power-on operation of a power management chip to realize the power-on function; or,

After the second power management chip receives the reset command sent by the application processor, control the signal level at the first control pin to be adjusted from the first level state to the second level state, triggering the power-off operation of the first power management chip; and controlling the signal level at the first control pin to be adjusted from the second level state to the first power level state again after a third preset time In the flat state, trigger the power-on operation of the first power management chip to realize the reset function.
A power management system, the power management system at least comprising a power management circuit and a baseband chip according to any one of claims 1 to 15; wherein the power management circuit performs power-on or reset control for the baseband chip .