CN101666838B - Chip system and mode control method thereof - Google Patents
Chip system and mode control method thereof Download PDFInfo
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- CN101666838B CN101666838B CN2009100927064A CN200910092706A CN101666838B CN 101666838 B CN101666838 B CN 101666838B CN 2009100927064 A CN2009100927064 A CN 2009100927064A CN 200910092706 A CN200910092706 A CN 200910092706A CN 101666838 B CN101666838 B CN 101666838B
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- reset signal
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- logical value
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Abstract
The invention provides a chip system and a mode control method thereof. The method comprises the following steps: establishing a corresponding relationship between a logical value of a chip pin and an operating mode of a chip; generating a corresponding power-on electric reset signal and an internal reset signal according to an external reset signal, and releasing the internal reset signal after at least two clock cycles after the release of the power-on electric reset signal; configuring the attribute of the chip pin into input before releasing the internal rest signal, and configuring the attribute of the chip pin into input or output after releasing the internal reset signal; latching the logical value of the chip pin after releasing the power-on reset signal and before releasing the internal reset signal; and searching the operating mode from the corresponding relationship according to the latched logical value after releasing the internal reset signal, and controlling the chip system to enter in the searched operating mode. According to the chip system and the mode control method thereof, the control to the operating mode of the chip system can be realized without setting a special mode to control the pin.
Description
Technical field
The invention belongs to microelectronics technology, particularly a kind of chip system and mode control method thereof.
Background technology
Can there be a plurality of mode of operations in many chip systems, for example be useful on the different operating mode mode of operation 1, mode of operation 2 ... mode of operation N, be used for the every performance of test chip test pattern 1, test pattern 2 ... test pattern N.The pattern control pin that so common needs are provided with one group of special use is controlled the conversion between each pattern, utilizes the process of dedicated pin configuring chip pattern to comprise: at first, to define the corresponding relation of the logical value and the chip operation pattern of dedicated pin as required; Then, utilize drop-down control on chip exterior is carried out dedicated pin, reach the purpose of configuring chip mode of operation.The weak point of this kind mode is, pattern control pin need be set separately, so can increase area of chip, thereby directly cause chip cost significantly to increase, and increase the complicacy of system, has reduced the stability of system.
Summary of the invention
Technical matters to be solved by this invention provides a kind of chip system and mode control method thereof, does not need special pattern control pin is set, and just can realize the control to the mode of operation of chip system.
For solving the problems of the technologies described above, it is as follows to the invention provides technical scheme:
A kind of mode control method of chip system, the chip system that is applied to have at least two mode of operations comprises:
Set up the corresponding relation of the logical value and the chip operation pattern of chip pin;
Produce corresponding power-on reset signal and internal reset signal according to external reset signal, wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least;
The attribute configuration of chip pin was input before internal reset signal discharged, and the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged;
After power-on reset signal discharges, before internal reset signal discharges, the logical value of chip pin is latched;
After internal reset signal discharged, according to the logical value that latchs searching work pattern from described corresponding relation, and the control chip system entered the mode of operation that finds.
Above-mentioned mode control method, wherein, the logical value of described chip pin is: external system is by going up the logical value that drop-down control is imported to chip pin.
A kind of chip system has at least two mode of operations, comprises the pattern configurations module that is connected with at least one chip pin in the described chip system, comprises in the described pattern configurations module:
Corresponding relation is set up the unit, is used to set up the corresponding relation of the logical value and the chip operation pattern of chip pin;
The electrification reset control module is used for producing corresponding power-on reset signal and internal reset signal according to external reset signal, and wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least;
Input and output property control unit, the attribute configuration of chip pin is input to be used for discharging internal reset signal before, the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged;
Latch units is used for after power-on reset signal discharges, before internal reset signal discharges, and the logical value of chip pin is latched;
The pattern control module is used for after internal reset signal discharges, the logical value searching work pattern from described corresponding relation that latchs according to latch units, and the control chip system enters the mode of operation that finds.
Above-mentioned chip system, wherein, the logical value that described latch units latchs is: external system is by going up the logical value that drop-down control is imported to chip pin.
The embodiment of the invention utilizes the electrification reset process to carry out multiplexing to chip pin, thereby realize configuration to the chip operation pattern, owing to do not need special pattern control pin is set, thereby reduced total pin number of chip, and can save the chip production cost.
Description of drawings
Fig. 1 is the structural representation of the chip system of the embodiment of the invention;
Fig. 2 is the inside sequential chart of said chip system;
Fig. 3 is the mode control method process flow diagram of the chip system of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
The key of the embodiment of the invention is, utilize the electrification reset process to carry out multiplexing to chip pin, thereby realize configuration to the chip operation pattern, promptly, in the electrification reset process, the common pin of chip is used as pattern control pin, after electrification reset finishes, original function that inputs or outputs of the common pin that recovery is re-used.
With reference to Fig. 1, chip system for the embodiment of the invention, it has at least two mode of operations, comprise the pattern configurations module that is connected with at least one chip pin in the described chip system, comprise in the described pattern configurations module: corresponding relation is set up unit, electrification reset control module, input and output property control unit, latch units and pattern control module.
Corresponding relation is set up the unit, is used to set up the corresponding relation of the logical value and the chip operation pattern of chip pin.Among the present invention, need multiplexing chip pin to count the quantity M decision of N, and follow N=ceil (Log by the mode of operation that chip system had
2M), wherein, ceil () expression rounds up.So-called multiplexing, be meant in the electrification reset process, the common pin of chip is controlled pin as pattern use, after electrification reset finishes, original function that inputs or outputs of the common pin that recovery is re-used.Such as, chip system has 2 mode of operations, then needs a multiplexing chip pin, and sets up following mapping table:
| The chip pin logical value | Mode state |
| 0 | Mode of operation 1 |
| 1 | Mode of operation 2 |
Table 1
Again such as, chip system has 6 mode of operations, then needs multiplexing three chip pins, when multiplexing three chip pins, described pattern configurations module then is connected with these three chip pins.For example, can set up following mapping table:
| The chip pin logical value | Mode value |
| 000 | Mode of operation 1 |
| 001 | Mode of operation 2 |
| 010 | Mode of operation 3 |
| 011 | Mode of operation 4 |
| 100 | Mode of operation 5 |
| 101 | Mode of operation 6 |
Table 2
The electrification reset control module is used for producing corresponding power-on reset signal and internal reset signal according to external reset signal, and wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least.
Input and output property control unit, the attribute configuration of chip pin is input to be used for discharging internal reset signal before, the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged.Among Fig. 1, the triangle symbol on top represents that with the input that enables the triangle symbol of bottom is represented output.Before internal reset signal discharges, the attribute configuration of chip pin for input, so can be received the input of external system to the chip system pattern information; After internal reset signal discharges, with the attribute configuration of chip pin for inputing or outputing, original function of the pin that is re-used of recovery like this.
Latch units is used for after power-on reset signal discharges, before internal reset signal discharges, and the logical value of chip pin is latched.For the logical value of avoiding chip pin plays pendulum, external system is imported different logical values by chip pin being gone up drop-down control, and among Fig. 1, switch closure draws on being, is input as logical one, and switch open is drop-down, is input as logical zero.In the latch units a plurality of registers can be set, each register correspondence is used for the logical value of respective chip pin is latched in a chip input pin.
The pattern control module is used for after internal reset signal discharges, the logical value searching work pattern from described corresponding relation that latchs according to latch units, and the control chip system enters the mode of operation that finds.Have 2 mode of operations such as chip system, then comprise a register in the latch units, according to above-mentioned table 1, if the value of register is 0, then the control chip system enters mode of operation 1, if the value of register is 1, then the control chip system enters mode of operation 2.Have 6 mode of operations such as chip system again, then comprise three registers in the latch units, if the value of register is respectively 0,1,0, then according to above-mentioned table 2, the control chip system enters mode of operation 3.
Introduce the mode control method of the chip system of the embodiment of the invention below in conjunction with Fig. 2 and Fig. 3.Described mode control method is applied to have the chip system of at least two mode of operations, and it comprises the steps:
Step 301: the corresponding relation of setting up the logical value and the chip operation pattern of chip pin;
Among the present invention, need multiplexing chip pin to count the quantity M decision of N, and follow N=ceil (Log by the mode of operation that chip system had
2M), wherein, ceil () expression rounds up.So-called multiplexing, be meant in the electrification reset process, the common pin of chip is controlled pin as pattern use, after electrification reset finishes, original function that inputs or outputs of the common pin that recovery is re-used.Such as, chip system has 2 mode of operations, then needs a multiplexing chip pin, and the corresponding relation of foundation is as above shown in the table 1; Again such as, chip system has 6 mode of operations, then needs multiplexing three chip pins, the corresponding relation of foundation is as above shown in the table 2.
Step 302: produce corresponding power-on reset signal and internal reset signal according to external reset signal, wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least;
Referring to Fig. 2, in the present embodiment, internal reset signal discharged after 5 clock period after power-on reset signal discharges.
Step 303: the attribute configuration of chip pin was input before internal reset signal discharged, and the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged;
Before internal reset signal discharges, the attribute configuration of chip pin for input, so can be received the input of external system to the chip system pattern information; After internal reset signal discharges, with the attribute configuration of chip pin for inputing or outputing, original function of the pin that is re-used of recovery like this.
Step 304: after power-on reset signal discharges, before internal reset signal discharges, the logical value of chip pin is latched;
For the logical value of avoiding chip pin plays pendulum, external system is imported different logical values by chip pin being gone up drop-down control, for example, draws on chip pin carried out, and then is input as logical one; Chip pin is carried out drop-down, then be input as logical zero.A plurality of registers can be set in chip system, and each register correspondence is used for the logical value of respective chip pin is latched in a chip input pin.
Step 305: after internal reset signal discharged, according to the logical value that latchs searching work pattern from described corresponding relation, and the control chip system entered the mode of operation that finds.
Have 2 mode of operations such as chip system, then be provided with a register in the system, according to above-mentioned table 1, if the value of register is 0, then the control chip system enters mode of operation 1, if the value of register is 1, then the control chip system enters mode of operation 2.Have 6 mode of operations such as chip system again, then be provided with three registers in the system, if the value of register is respectively 0,1,0, then according to above-mentioned table 2, the control chip system enters mode of operation 3.
Should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spiritual scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (4)
1. the mode control method of a chip system, the chip system that is applied to have at least two mode of operations is characterized in that, comprising:
Set up the corresponding relation of the logical value and the chip operation pattern of chip pin;
Produce corresponding power-on reset signal and internal reset signal according to external reset signal, wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least;
The attribute configuration of chip pin was input before internal reset signal discharged, and the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged;
After power-on reset signal discharges, before internal reset signal discharges, the logical value of chip pin is latched;
After internal reset signal discharged, according to the logical value that latchs searching work pattern from described corresponding relation, and the control chip system entered the mode of operation that finds.
2. mode control method as claimed in claim 1 is characterized in that:
The logical value of described chip pin is: the logical value of external system by drawing control or drop-down control to import on chip pin is carried out.
3. a chip system has at least two mode of operations, it is characterized in that, comprises the pattern configurations module that is connected with at least one chip pin in the described chip system, comprises in the described pattern configurations module:
Corresponding relation is set up the unit, is used to set up the corresponding relation of the logical value and the chip operation pattern of chip pin;
The electrification reset control module is used for producing corresponding power-on reset signal and internal reset signal according to external reset signal, and wherein, internal reset signal discharges after two clock period after power-on reset signal discharges at least;
Input and output property control unit, the attribute configuration of chip pin is input to be used for discharging internal reset signal before, the attribute configuration of chip pin was for inputing or outputing after internal reset signal was discharged;
Latch units is used for after power-on reset signal discharges, before internal reset signal discharges, and the logical value of chip pin is latched;
The pattern control module is used for after internal reset signal discharges, the logical value searching work pattern from described corresponding relation that latchs according to latch units, and the control chip system enters the mode of operation that finds.
4. chip system as claimed in claim 3 is characterized in that:
The logical value that described latch units latchs is: the logical value of external system by drawing control or drop-down control to import on chip pin is carried out.
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| CN2009100927064A CN101666838B (en) | 2009-09-15 | 2009-09-15 | Chip system and mode control method thereof |
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| CN2009100927064A CN101666838B (en) | 2009-09-15 | 2009-09-15 | Chip system and mode control method thereof |
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| CN101666838A CN101666838A (en) | 2010-03-10 |
| CN101666838B true CN101666838B (en) | 2011-09-28 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236066B (en) * | 2010-04-22 | 2015-07-01 | 上海华虹集成电路有限责任公司 | Method for realizing rapid debugging and locating of chip functional fault and debugging circuit |
| CN102236065B (en) * | 2010-04-22 | 2015-07-01 | 上海华虹集成电路有限责任公司 | Method for rapidly debugging and locating chip functional fault and debugging circuit |
| CN101957803B (en) * | 2010-09-21 | 2012-12-26 | 昆山芯视讯电子科技有限公司 | Automatic synchronization and phase shifting method for multiple chips |
| CN102622070A (en) * | 2012-02-28 | 2012-08-01 | 广州市广晟微电子有限公司 | Method and device for chip reset reconfiguration |
| CN102801405A (en) * | 2012-06-26 | 2012-11-28 | 深圳市芯海科技有限公司 | Method and device for switching chip mode |
| CN103401574B (en) * | 2013-08-08 | 2016-08-24 | 昆腾微电子股份有限公司 | FM receives demodulation modes conversion equipment and the method for chip |
| CN104270127A (en) * | 2014-09-16 | 2015-01-07 | 四川和芯微电子股份有限公司 | Pin multiplexing circuit of SOC |
| CN105988548B (en) * | 2015-02-05 | 2020-04-17 | 恩智浦美国有限公司 | Initial operating mode for an integrated circuit |
| CN109074338B (en) * | 2016-10-05 | 2021-11-09 | 富士电机株式会社 | Integrated circuit device |
| CN113138330A (en) * | 2020-12-29 | 2021-07-20 | 苏州裕太微电子有限公司 | Method and system for preventing chip from entering test mode by mistake |
| CN113726126B (en) * | 2021-08-25 | 2023-04-14 | Oppo广东移动通信有限公司 | Power management circuit and control method and system thereof |
| CN114020682A (en) * | 2021-10-18 | 2022-02-08 | 爱芯元智半导体(上海)有限公司 | Chip working mode control method and device, chip and storage medium |
| CN114264867B (en) * | 2021-12-15 | 2024-01-19 | 江苏纵帆微电子有限公司 | Method for switching operation mode and production test mode of electronic equipment |
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