CN102938642A - Reset method of internal memory of chip based on scan chain - Google Patents
Reset method of internal memory of chip based on scan chain Download PDFInfo
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- CN102938642A CN102938642A CN2012104937866A CN201210493786A CN102938642A CN 102938642 A CN102938642 A CN 102938642A CN 2012104937866 A CN2012104937866 A CN 2012104937866A CN 201210493786 A CN201210493786 A CN 201210493786A CN 102938642 A CN102938642 A CN 102938642A
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Abstract
The invention discloses a reset method of an internal memory of a chip based on a scan chain. The reset method comprises the implementation steps of: 1) constructing at least one scan chain for a register chain in the chip design stage, and determining the connection relation between a register and a previous register in the scan chain according to a reset value of the register; and 2) in the chip using stage, enabling scan enable signals of every register in the chip to be effective, providing a reset clock, controlling every scan chain to enter a reset scanning state, inputting the reset value of the register of a chain tag of the scan chain into the chain tag of the scan chain, orderly resetting the next register in the scan chain by each register of the scan chain under the control of the reset clock according to the connection relation between the register and the next register in the scan chain, and exiting the reset scanning state after the register at the tail of the scan chain is reset. According to the invention, a reset tree structure required by the conventional synchronous reset method or the conventional asynchronous reset method, and the reset method has the advantages of simplicity in realization and small performance cost.
Description
Technical field
The present invention relates to the digital integrated circuit field, be specifically related to a kind of repositioning method of the chip internal register based on scan chain.
Background technology
In digital integrated circuit, need to register be resetted by certain method, make it that definite initial condition (0 or 1) be arranged, thereby guarantee that digital integrated circuit can work.Register repositioning method commonly used comprises synchronous reset and asynchronous reset.In the synchronous reset structure, when reset signal is effective, register does not reset immediately, but, when effective saltus step occurs the clock of register, just register is reset to fixing initial value.In the synchronous reset structure, reset signal is used as data-signal, participates in the combinational logic operation of register data input, and this has increased the combinational logic progression between register, and the performance of digital integrated circuit is had a certain impact.In the asynchronous reset structure, when reset signal is effective, whether no matter effective clock saltus step arranged, register will be reset to fixing initial value at once.The independent input of asynchronous reset register using reset signal as register, so reset signal do not participate in the combinational logic operation of register data input as data-signal, but the circuit stability of asynchronous reset structure is not as the synchronous reset circuit.When normal operation, any burr in asynchronous reset circuit on reset signal all will cause register to be resetted mistakenly, unless and in the synchronous reset circuit, the burr on reset signal occurs in effective hopping edge of clock just, otherwise can not cause register to be resetted mistakenly.Synchronous reset and asynchronous reset all need the reseting signal line of an overall situation.In the situation that the digital integrated circuit scale constantly enlarges, no matter be synchronous reset or asynchronous reset, all face the wiring problem of overall signal's line.Along with improving constantly of integrated circuit technology, the scale of digital integrated circuit constantly enlarges, and register number integrated in one single chip is more and more.No matter be to adopt synchronous reset or asynchronous reset, all need to give by global reset signal the register that each need to reset, this will cause the load of global reset signal line very large.And register spreads all over each corner of chip, reset signal need to be walked very long path could arrive register, and this causes very large holding wire to postpone.General way is to adopt the tree structure that resets at present, by multi-buffer, single global reset signal is done to tree-like scattering, and guarantees that the holding wire from root node to all leaf nodes postpones identical.This has not only expended a large amount of hardware resources, has brought certain tree power consumption expense that resets, and, along with the continuous expansion of digital integrated circuit scale, the tree that resets will constantly promote chip physical Design complexity, and the design of chip is realized causing great difficulty.
In sum, existing digital integrated circuit synchronous reset structure, have a certain impact to the performance of chip.And the asynchronous reset structure has potential stability problem.And no matter be synchronous reset structure or asynchronous reset structure, all need design to realize the tree structure that resets of the overall situation, not only bring extra power consumption expense, also to chip, physics realization brings great difficulty.Therefore, along with the continuous increase with integrated level that improves constantly of integrated circuit technology, be badly in need of a kind of effective digital integrated circuit register repositioning method, to solve the general existing variety of problems of synchronous and asynchronous repositioning method at present.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind ofly can cancel existing synchronous reset or the required tree structure that resets of asynchronous reset method, does not affect the repositioning method of chip performance, good stability, realization is simple, performance cost the is little chip internal register based on scan chain.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
A kind of repositioning method of the chip internal register based on scan chain, implementation step is as follows:
1) in chip design stage, the register catena that needs are resetted is configured at least one scan chain, and determines the annexation between a upper register in this register and scan chain according to the reset values of scan chain begin chain register and the reset values of each register while building scan chain; If the reset values of scan chain begin chain register is 1 o'clock, by 1 scan input end that is connected to this register; If the reset values of scan chain begin chain register is 0 o'clock, by 0 scan input end that is connected to this register; If register is identical with the reset values of a upper register in scan chain, the scan input end of this register is connected with the forward output of a upper register in scan chain; If register is different from the reset values of a upper register in scan chain, the scan input end of this register is connected with the inverse output terminal of a upper register in scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, if if the reset values of begin chain register is 0 reset values at this begin chain input 0 begin chain register be 1 in this begin chain input 1, and provide reset clock, control each scan chain and enter the scanning mode that resets, each register under the control of input reset clock, reset values being write to scan chain successively, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, exit the scanning mode that resets, complete chip reset.
The present invention has following advantage:
1, the present invention utilizes the existing scan chain architecture for test in chip, determine in this register and scan chain the annexation between a upper register and build scan chain according to the reset values of the reset values of scan chain begin chain register and each register, needs are reset to 0 and be reset to 1 register line and staff control on one or more scan chain, enter scanning mode by repositioning control device gated sweep chain when resetting, and in the input of the begin chain of scan chain fixing 0 or 1, by the annexation between register in scan chain, register is reset to 0 or 1, can cancel existing synchronous reset or the required tree structure that resets of asynchronous reset method, be easy to realize, without extra performance cost, solved the chip performance that affects of synchronously existing or the existence of asynchronous reset technology, poor stability, the problem of physics realization difficulty, have and do not affect chip performance, good stability, realize simple, the advantage that performance cost is little.
2, the present invention takes full advantage of the existing scan chain architecture for test in chip, and realizing except repositioning control device, not increasing extra logic to the resetting of register, and having does not affect that data path performance, stability are high, the simple advantage of physics realization.
3, the present invention is by the catena method based on reset values, realizes resetting flexibly of register on chain, the register on chain can be reset to 0 or 1 flexibly, has advantages of that flexibility is high.
The accompanying drawing explanation
The basic procedure schematic diagram that Fig. 1 is the embodiment of the present invention.
Fig. 2 determines the detailed process schematic diagram of register annexation in the embodiment of the present invention.
Fig. 3 is schematic diagram and the input and output truth table of the chip internal register of the application embodiment of the present invention.
The circuit theory schematic diagram that Fig. 4 is the scan chain that builds in the embodiment of the present invention.
The circuit theory schematic diagram that Fig. 5 is repositioning control device in the embodiment of the present invention.
Marginal data: 101, test enable end; 102, reset signal input; 103, test scan enable signal input; 104, work clock input; 105, reset clock input; 106, test clock input; 107, test data input; 1, scan chain enables control unit; 11, state controller; 12, enable signal selector; 2, scan chain clock control module; 21, one-level clock selector; 22, secondary clock selector; 3, input data selector.
Embodiment
As shown in Figure 1, the implementation step of the repositioning method of the chip internal register of the present embodiment based on scan chain is as follows:
1) in chip design stage, the register catena that need to reset is configured at least one scan chain, and determines the annexation between a upper register in this register and scan chain according to the reset values of scan chain begin chain register and the reset values of each register while building scan chain; If the reset values of scan chain begin chain register is 1 o'clock, by 1 scan input end that is connected to this register; If the reset values of scan chain begin chain register is 0 o'clock, by 0 scan input end that is connected to this register; If register is identical with the reset values of a upper register in scan chain, the scan input end of this register is connected with the forward output of a upper register in scan chain; If register is different from the reset values of a upper register in scan chain, the scan input end of this register is connected with the inverse output terminal of a upper register in scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, if if the reset values of begin chain register is 0 reset values at this begin chain input 0 begin chain register be 1 in this begin chain input 1, and provide reset clock, control each scan chain and enter the scanning mode that resets, each register under the control of input reset clock, reset values being write to scan chain successively, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, exit the scanning mode that resets, complete chip reset.
Determine that according to the reset values of scan chain begin chain register and the reset values of each register the detailed step of the annexation between a upper register in this register and scan chain is as follows while as shown in Figure 2, in the present embodiment step 1), building scan chain:
1.1) process the register of scan chain begin chain, if the reset values of scan chain begin chain register is 0 reset values 0 is connected to the scan input end of scan chain begin chain register in when scanning of resetting, otherwise reset values 1 is connected to the scan input end of scan chain begin chain register when resetting scanning;
1.2) using the next register in scan chain as current register, redirect execution step 1.3) processed;
1.3) judge that whether the reset values of current register is identical with the reset values of a upper register, if the same the forward output of a upper register is connected to the scan input end of current register, otherwise the inverse output terminal of a upper register is connected to the scan input end of current register, then the redirect execution step 1.4);
1.4) judge whether to arrive the scanning last-of-chain, if do not arrive return to execution step 1.2), otherwise having completed the annexation between register in definite current scan chain, representative processes.
As shown in Figure 3, adopt typically the register with scan function in the chip of the present embodiment, this register with scan function has five input ports and two delivery outlets, input port is respectively data input pin D(D end), scan input end SI(SI end), scan enable end SE and clock end CK, delivery outlet is respectively forward output Q(Q end) and inverse output terminal
(
End).At the rising edge of clock end CK, if scan enable end SE is 0, Q holds sampling D end data; If scan enable end SE is 1, Q holds sampling SI end data.In other cases, no matter CK be 0 or 1, Q end all remain unchanged.And under any circumstance,
The output of end and Q end is contrary.While while building scan chain in step 1), according to the reset values of the reset values of scan chain begin chain register and each register, determining in this register and scan chain the annexation between a upper register, if register is in the scan chain begin chain: if this register need to be reset to 0, when resetting scanning, by 0, receive its SI end; If this register need to be reset to 1, when resetting scanning, by 1, receive its SI end; If register is not in the scan chain begin chain: if the reset values of this register is identical with the reset values of a upper register on chain, the Q of upper register end is connected to the SI end of this register; If the reset values of this register is not identical with the reset values of a upper register on chain, by a upper register
End is connected to the SI end of this register.Therefore, when building scan chain, at first the register of scan chain begin chain is processed, if this register resets to 0, when resetting scanning, 0 SI that receives this register is held; Otherwise, when resetting scanning, 1 SI that receives this register is held.Next next register on processing chain, if this register is identical with a upper register reset values on chain, terminate to the Q of a upper register SI end of this register; Otherwise by a upper register
Terminate to the SI end of this register.If the register-bit of just processing current, in last-of-chain, completes processing; Otherwise continuing to get next register on chain is processed.
The present embodiment utilizes digital integrated circuit to test necessary scan chain architecture and the reset values based on register is carried out the scan chain tissue, when carrying out catena, need to be reset to 0 and can mix arbitrarily string on one or more scan chain with the register that need to be reset to 1; Control for signal specifically realizes by a repositioning control device that is integrated in chip internal, when resetting, by repositioning control device gated sweep chain, enters scanning mode, thereby realizes resetting of register.When resetting, repositioning control device is set to the scan enable signals of register effectively, and scan clock is provided, the gated sweep chain enters scanning mode, and after the scanning by certain hour, it is invalid that the scan enable signals of register is set to, exit scanning mode, complete and reset.
As shown in Figure 4, be the multi-strip scanning chain by the register string in full chip in the present embodiment, and be reset to 0 and be reset to 1 register line and staff control on a scan chain.Have scan chain 0, scan chain 1 ..., scan chain i amounts to i+1 bar scan chain, the begin chain of all scan chains is all controlled by repositioning control device, the clock end CK of all registers and scan enable end SE are also controlled by repositioning control device.
As shown in Figure 5, the embodiment of the present invention comprises that for the register repositioning control device of digital integrated circuit scan chain enables control unit 1, scan chain clock control module 2 and respectively to the input data selector 3 of scan chain begin chain output test signal or reset values, the input port of repositioning control device comprises test enable end 101, reset signal input 102, test scan enable signal input 103, work clock input 104, reset clock input 105, test clock input 106 and a plurality of test data input 107, scan chain enables control unit 1 and forms by state controller 11 with for the enable signal selector 12 of selecting output scanning chain enable signal, state controller 11 is connected with reset signal input 102, and control reset mode according to the value of reset signal input 102, an input of enable signal selector 12 is connected with state controller 11, another input of scan chain enable signal selector 12 is connected with test scan enable signal input 103, scan chain clock control module 2 forms by the one-level clock selector 21 of cascade with for the secondary clock selector 22 to integrated circuit output clock signal, the input of one-level clock selector 21 is connected with work clock input 104, reset clock input 105 respectively, the control end of one-level clock selector 21 is connected with the output of state controller 11, an input of secondary clock selector 22 is connected with test clock input 106, and another input of secondary clock selector 22 is connected with the output of one-level clock selector 21, input data selector 3 is corresponding one by one with test data input 107, and an input of input data selector 3 is connected with corresponding test data input 107, another input of input data selector 3 is prefabricated reset values, and the selection control end of enable signal selector 12, secondary clock selector 22 and each input data selector 3 all is connected with test enable end 101.
The input port of the register repositioning control device of the present embodiment is as follows: test enable end 101 is for input test enable signal DFT_EN, reset signal input 102 is for inputting reset signal RST, test scan enable signal input 103 is scan chain enable signal T_SE during for input test, work clock input 104 is for input service clock signal F_CK, reset clock input 105 is for inputting reset clock signal R_CK, test clock input 106 is for input test clock signal T_CK, test data input 107 is respectively used to input scan test data T_SI
0T_SI
i.The output port of the register repositioning control device of the present embodiment is as follows: the output of enable signal selector 12 is for output scanning chain enable signal SE when testing or resetting; The output of secondary clock selector 22 for when test output test clock signals T_CK, while resetting output reset clock signal R_CK and resetting after output services clock signal F_CK; The output of input data selector 3 for exporting reset values or outputing test data when testing when resetting.
The course of work of register repositioning control device is as follows:
1, test enable signal DFT_EN is that 1(is effective) time, the gated sweep chain enters test pattern, and now the register repositioning control device of the present embodiment can be for realizing the test of digital integrated circuit.When now, enable signal selector 12 is selected test, scan chain enable signal T_SE is scan chain enable signal SE; Secondary clock selector 22 is selected the clock signal of test clock signals T_CK as output; Input data selector 3 is selected respectively input scan test data SI
0SI
iInput each scan chain begin chain as scan test data.
2, test enable signal DFT_EN is that 0(is invalid) time, if reset signal RST is effective, now the register repositioning control device of the present embodiment can reset for the register of realizing digital integrated circuit.
Now, by state controller 11 output scanning enable signals, and selected as scan chain enable signal SE by enable signal selector 12; State controller 11 is controlled one-level clock selector 21 and is selected reset clock signal R_CK and export as clock signal C K by secondary clock selector 22; Input data selector 3 selects prefabricated reset values as scan chain begin chain input data, if the register of this scan chain begin chain need to be reset to 0, selects 0 as the output of scan chain begin chain input data; If the register of this scan chain begin chain need to be reset to 1, select 1 as the output of scan chain begin chain input data.After entering the scanning mode that resets, reset signal RST is revocable, and it is invalid to become.After this within the regular hour, state controller 11 is by the hold reset scanning mode, so that all scan chains have all completed the scanning that resets, also all register has all completed and resetted.After the register by all scanning last-of-chains writes reset values, it is invalid that state controller 11 is set to scan chain enable signal SE, and clock signal F_CK exporting as clock signal C K by secondary clock selector 22 when controlling one-level clock selector 21 and selecting work, thereby the gated sweep chain exits the scanning mode that resets, and enters operating state.So far, all registers all are reset to the initial value of hope by scan chain.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (1)
1. the repositioning method of the chip internal register based on scan chain is characterized in that implementation step is as follows:
1) in chip design stage, the register catena that needs are resetted is configured at least one scan chain, and determines the annexation between a upper register in this register and scan chain according to the reset values of scan chain begin chain register and the reset values of each register while building scan chain; If the reset values of scan chain begin chain register is 1 o'clock, by 1 scan input end that is connected to this register; If the reset values of scan chain begin chain register is 0 o'clock, by 0 scan input end that is connected to this register; If register is identical with the reset values of a upper register in scan chain, the scan input end of this register is connected with the forward output of a upper register in scan chain; If register is different from the reset values of a upper register in scan chain, the scan input end of this register is connected with the inverse output terminal of a upper register in scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, if if the reset values of begin chain register is 0 reset values at this begin chain input 0 begin chain register be 1 in this begin chain input 1, and provide reset clock, control each scan chain and enter the scanning mode that resets, each register under the control of input reset clock, reset values being write to scan chain successively, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, exit the scanning mode that resets, complete chip reset.
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| CN2012104937866A CN102938642A (en) | 2012-11-28 | 2012-11-28 | Reset method of internal memory of chip based on scan chain |
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| CN2012104937866A CN102938642A (en) | 2012-11-28 | 2012-11-28 | Reset method of internal memory of chip based on scan chain |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104462698A (en) * | 2014-12-16 | 2015-03-25 | 浪潮电子信息产业股份有限公司 | Designing method for improving access reliability of chipset register of ASIC (application specific integrated circuit) |
| CN111103959A (en) * | 2019-12-20 | 2020-05-05 | 展讯通信（上海）有限公司 | Register resetting system and chip |
| CN112684327A (en) * | 2020-11-30 | 2021-04-20 | 海光信息技术股份有限公司 | Scan chain and design method thereof and serial scan reset method based on scan chain |
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| CN102495356A (en) * | 2011-11-30 | 2012-06-13 | 福州大学 | Processing method of reset port of scan chain asynchronous reset register |
| CN102495360A (en) * | 2011-12-16 | 2012-06-13 | 浙江大学 | Safety scanning register, safety scan chain and scanning method of safety scan chain |
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| US5163155A (en) * | 1988-06-07 | 1992-11-10 | Mitsubishi Denki Kabushiki Kaisha | System for resetting a series of latches to varying data patterns |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104462698A (en) * | 2014-12-16 | 2015-03-25 | 浪潮电子信息产业股份有限公司 | Designing method for improving access reliability of chipset register of ASIC (application specific integrated circuit) |
| CN111103959A (en) * | 2019-12-20 | 2020-05-05 | 展讯通信（上海）有限公司 | Register resetting system and chip |
| CN111103959B (en) * | 2019-12-20 | 2021-05-18 | 展讯通信（上海）有限公司 | Register resetting system and chip |
| CN112684327A (en) * | 2020-11-30 | 2021-04-20 | 海光信息技术股份有限公司 | Scan chain and design method thereof and serial scan reset method based on scan chain |
| CN112684327B (en) * | 2020-11-30 | 2023-09-05 | 海光信息技术股份有限公司 | Scan chain, design method thereof and serial scanning resetting method based on scan chain |
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Application publication date: 20130220 |