WO2023024573A1 - 电子设备及芯片封装方法 - Google Patents

电子设备及芯片封装方法 Download PDF

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Publication number
WO2023024573A1
WO2023024573A1 PCT/CN2022/091534 CN2022091534W WO2023024573A1 WO 2023024573 A1 WO2023024573 A1 WO 2023024573A1 CN 2022091534 W CN2022091534 W CN 2022091534W WO 2023024573 A1 WO2023024573 A1 WO 2023024573A1
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Prior art keywords
substrate
shielding
metal
shielding metal
crystal device
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PCT/CN2022/091534
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English (en)
French (fr)
Inventor
郭学平
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荣耀终端有限公司
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Publication date
Application filed by 荣耀终端有限公司 filed Critical 荣耀终端有限公司
Priority to JP2023552101A priority Critical patent/JP2024508134A/ja
Priority to US17/924,814 priority patent/US20240234334A9/en
Priority to EP22797241.1A priority patent/EP4163969A4/en
Publication of WO2023024573A1 publication Critical patent/WO2023024573A1/zh

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present application relates to the field of chip packaging, in particular to an electronic device and a chip packaging method.
  • a wireless headset is paired and connected to a mobile phone through the Bluetooth function.
  • the electronic device is provided with an antenna, and the antenna and other components are packaged together in the same package structure.
  • the antenna will generate electromagnetic waves, and in a narrow space, the antenna will cause electromagnetic wave interference to other components, which will degrade the working performance of other components. In such a working state for a long time, the device is prone to damage, which in turn causes damage to the electronic equipment.
  • Embodiments of the present application provide an electronic device and a chip packaging method, which can ensure a shielding effect between devices and avoid mutual influence between devices.
  • the embodiment of the present application provides an electronic device, including: a casing; a substrate is arranged inside the casing; a first crystal device and an adapter plate are arranged side by side on one side of the substrate, and the adapter plate includes a first ground solder plate; the first grounding pad is arranged on the surface of the adapter plate facing the substrate, and the adapter plate is electrically connected to the substrate through the first grounding pad, so that the adapter plate is grounded; the first plastic sealing layer, the surface of the first crystal device is set There is a first part of the first plastic sealing layer, and a second part of the first plastic sealing layer is arranged between the adapter board and the substrate. The first part and the second part are integrated; the surface of the first part is covered with the first shielding metal, and the first shielding metal The metal is electrically connected to the first ground pad to ground the first shield metal.
  • the first part is arranged outside the first crystal device, and by grounding the first part, a closed Faraday cage can be formed to separate the first crystal device from the adapter plate to realize the first crystal device Mutual shielding with the adapter board.
  • a closed Faraday cage can be formed to separate the first crystal device from the adapter plate to realize the first crystal device Mutual shielding with the adapter board.
  • the adapter board further includes an interconnection via hole, one end of the interconnection via hole is connected to the first ground pad, and the other end penetrates through the surface of the adapter board facing away from the substrate; A part of the surface extends to the surface of the adapter board facing away from the substrate, and is connected to the interconnection via hole, so that the first shielding metal is connected to the first ground pad through the interconnection via hole.
  • the first shielding metal can be grounded by covering the interconnection via holes, and the grounding of the first shielding metal can be realized without adding components, and the process is simple and the integration degree is high.
  • the adapter board further includes an interconnection via hole and a second ground pad; the second ground pad is arranged on the surface of the adapter board facing away from the substrate, and the two ends of the interconnection via hole are respectively A grounding pad and a second grounding pad are connected; the first shielding metal extends from the surface of the first part to the surface of the adapter board facing away from the substrate, and is connected to the second grounding pad so that the first shielding metal passes through the second The ground pad and the interconnection via are connected to the first ground pad. In this way, the first shielding metal can be grounded through the second ground pad, the interconnection via, and the first ground pad.
  • the second shielding metal includes a first shielding section and a second shielding section; the first shielding section is arranged on the side of the adapter board facing the first crystal device, and the first shielding section is away from One end of the substrate is connected to the first shielding metal; the second shielding section is arranged on the surface of the adapter board facing the substrate, one end of the second shielding section is connected to the first shielding section, and the other end is connected to the first ground pad.
  • the first shielding metal can be connected to the first ground pad through the second shielding segment and the first shielding segment, thereby realizing grounding.
  • the second shielding metal further includes a third shielding section, the third shielding section is arranged on the surface of the adapter plate facing away from the substrate, one end of the third shielding section is connected to the first shielding section, and the other end is connected to the first shielding section. A certain distance is extended in a direction close to the second grounding pad, and the third shielding segment is connected to the first shielding metal.
  • a third grounding pad is provided where the first shielding metal contacts the substrate, and the first shielding metal is connected to the third grounding pad to ground the first shielding metal. In this way, the end of the first shielding metal away from the adapter board can be grounded.
  • the adapter boards are distributed on the edge of the substrate.
  • a second crystal device is provided on the other surface of the substrate; a second plastic sealing layer is arranged on the surface of the second crystal device; the surface of the second plastic sealing layer and the side surface of the substrate are covered There is a third shielding metal; there is a grounding metal layer inside the substrate, and the grounding metal layer extends from the inside of the substrate to the side of the substrate to connect with the third shielding metal.
  • the third shielding metal also covers the side of the second part facing away from the first crystal device, and also covers the side of the adapter board facing away from the first crystal device.
  • the first crystal device includes: one of a nor-type flash memory, a mos tube, a SoC chip, a decoding circuit, a charging chip, an RLC device, a crystal, a bluetooth chip, a radio frequency chip, a WiFi chip, an NFC chip, and a sensor. species or several.
  • the second crystal device includes: one of a nor-type flash memory, a mos tube, a SoC chip, a decoding circuit, a charging chip, an RLC device, a crystal, a bluetooth chip, a radio frequency chip, a WiFi chip, an NFC chip, and a sensor. species or several.
  • the first shielding metal, the second shielding metal and the third shielding metal are formed by spraying or sputtering.
  • the embodiment of the present application also provides a chip packaging method, including: setting a substrate inside the casing; bonding or soldering the first crystal device to one side surface of the substrate, and preparing the first ground solder on the adapter plate
  • the adapter plate is welded to one side surface of the substrate through the first grounding pad, the first grounding pad is arranged on the surface of the adapter plate facing the substrate, and the first crystal device is arranged side by side with the adapter plate; the adapter plate
  • the first grounding pad is electrically connected to the substrate to ground the adapter plate; the surface of the first crystal device is coated with a plastic encapsulant to form the first part; the plastic encapsulant is coated between the adapter plate and the substrate to form the second part; the first part and the second part form the first plastic sealing layer, and the first part and the second part have an integrated structure; after the first part is cured, the surface of the first part is covered with metal to form the first shielding metal, and the first shielding metal and the second part A ground pad is electrical
  • the first part is arranged outside the first crystal device, and by grounding the first part, a closed Faraday cage can be formed to separate the first crystal device from the adapter board, and the first crystal device has been realized Mutual shielding with the adapter board.
  • the shielding effect is obvious.
  • an interconnection via hole is prepared on the adapter board, one end of the interconnection via hole is connected to the first ground pad, and the other end penetrates the surface of the adapter board facing away from the substrate; the first shielding The metal extends from the surface of the first part to the surface of the interposer board facing away from the substrate, and is connected with the interconnection via, so that the first shielding metal is connected with the first ground pad through the interconnection via.
  • the first shielding metal can be grounded by covering the interconnection via holes, and the grounding of the first shielding metal can be realized without adding components, and the process is simple and the integration degree is high.
  • the interconnection via hole and the second ground pad are prepared on the adapter board; the second ground pad is arranged on the surface of the adapter board facing away from the substrate, and the two ends of the interconnection via hole are respectively connected to the The first grounding pad and the second grounding pad are connected; the first shielding metal extends from the surface of the first part to the surface of the adapter board facing away from the substrate, and is connected to the second grounding pad so that the first shielding metal passes through The second ground pad and the interconnection via are connected to the first ground pad. In this way, the first shielding metal can be grounded through the second ground pad, the interconnection via, and the first ground pad.
  • the side of the adapter plate facing the first crystal device is covered with metal to form a first shielding section, and the end of the first shielding section away from the substrate is connected to the first shielding metal; on the side of the adapter plate facing the substrate The surface is covered with metal to form a second shielding section, one end of the second shielding section is connected to the first shielding section, and the other end is connected to the first ground pad; the first shielding section and the second shielding section form a second shielding metal.
  • the first shielding metal can be connected to the first ground pad through the second shielding segment and the first shielding segment, thereby realizing grounding.
  • the surface of the adapter plate facing away from the substrate is covered with metal to form a third shielding section, one end of the third shielding section is connected to the first shielding section, and the other end faces toward the second grounding pad Extending for a certain distance, the third shielding section is connected to the first shielding metal; the first shielding section, the second shielding section and the third shielding section form a second shielding metal.
  • a third grounding pad is prepared at the place where the first shielding metal contacts the substrate, and the first shielding metal is connected to the third grounding pad so that the first shielding metal is grounded. In this way, the end of the first shielding metal away from the adapter board can be grounded.
  • the adapter board is soldered to one side surface of the substrate through the first ground pad, and the adapter board is distributed on the edge of the substrate.
  • the second crystal device is welded or bonded on the other surface of the substrate; the surface of the second crystal device is coated with a molding compound to form a second plastic sealing layer; after the second plastic sealing layer is solidified, the The surface of the second plastic packaging layer and the side of the substrate are covered with metal to form a third shielding metal; a grounding metal layer is prepared inside the substrate, and the grounding metal layer extends from the inside of the substrate to the side of the substrate to connect with the third shielding metal.
  • the double-sided packaging of the substrate can be realized, and the first crystal device on one side of the substrate and the adapter plate can be shielded from each other, and the second crystal device on the other side of the substrate can also be separated from the outside world. Open to avoid leakage of electromagnetic signals.
  • the side of the second part facing away from the first crystal device and the side of the adapter plate facing away from the first crystal device are covered with metal to form a third shielding metal.
  • one or more of nor-type flash memory, mos tube, SoC chip, decoding circuit, charging chip, RLC device, crystal, bluetooth chip, radio frequency chip, WiFi chip, NFC chip and sensor are included in one implementation.
  • one or more of nor-type flash memory, mos tube, SoC chip, decoding circuit, charging chip, RLC device, crystal, bluetooth chip, radio frequency chip, WiFi chip, NFC chip and sensor are included in one implementation.
  • the first shielding metal, the second shielding metal and the third shielding metal are formed by spraying or sputtering.
  • Fig. 1 is a schematic diagram of connection between a wireless earphone and a mobile phone
  • FIG. 2 is a schematic diagram of a current electronic device
  • FIG. 3 is a first structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • Fig. 4 is a schematic diagram of the first Faraday cage of the electronic device provided by the embodiment of the present application.
  • Fig. 5 is a second structural schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a second Faraday cage of an electronic device provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a third structure of an electronic device provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a third Faraday cage of an electronic device provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a fourth structure of an electronic device provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a fourth Faraday cage of an electronic device provided by an embodiment of the present application.
  • Fig. 11 is a schematic diagram of packaging of peripheral components provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a fifth structure of an electronic device provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a fifth Faraday cage of an electronic device provided by an embodiment of the present application.
  • Fig. 14 is a schematic diagram of the grounding of the first shielding metal provided by the embodiment of the present application.
  • Fig. 15 is a schematic structural diagram of a TWS earphone provided by an embodiment of the present application.
  • FIG. 16 is a schematic flow chart of a chip packaging method provided by an embodiment of the present application.
  • Fig. 17 is an exploded view of a chip packaging method provided by an embodiment of the present application.
  • Fig. 18 is an exploded view of another first shielding metal package provided by the embodiment of the present application.
  • Fig. 19 is an exploded view of another first shielding metal package provided by the embodiment of the present application.
  • Fig. 20 is an exploded view of another first shielding metal package provided by the embodiment of the present application.
  • Fig. 21 is a schematic flow chart of another chip packaging method provided by the embodiment of the present application.
  • Fig. 22 is an exploded view of another chip packaging method provided by the embodiment of the present application.
  • Fig. 23 is a schematic structural diagram of a casing of an electronic device provided by an embodiment of the present application.
  • Reflow soldering (reflow soldering), heating air or nitrogen to a high enough temperature and blowing it to the circuit board where the components have been pasted, so that the solder on both sides of the component melts and bonds with the circuit board.
  • True wireless (true wireless stereo, TWS) earphones that is, true wireless stereo earphones, can be connected to mobile phones and other devices through Bluetooth.
  • TWS earphones can process Bluetooth signals into left and right channels wirelessly, and the left and right earphones can be used independently. It has the characteristics of low delay, fast Bluetooth connection, fast transmission speed and low energy consumption.
  • the wireless earphone and the mobile phone are paired and connected through the bluetooth function.
  • the electronic device is provided with an antenna, and the antenna and other components are packaged together in the same package structure.
  • the antenna will generate electromagnetic waves, and in a narrow space, the antenna will cause electromagnetic wave interference to other components, which will degrade the working performance of other components. In such a working state for a long time, the device is prone to damage, which in turn causes damage to the electronic equipment.
  • FIG. 2 it is a schematic diagram of a current electronic device.
  • the electronic device may include: a substrate 01 , an adapter board 02 welded on one side of the substrate 01 , and a first component 03 .
  • the adapter board 02 is a circuit board capable of transmitting signals, and generates electromagnetic waves during operation. Since the adapter board 02 and the first component 03 are arranged side by side on one side of the substrate 01 , the electromagnetic waves generated by the adapter board 02 during operation will directly cause electromagnetic wave interference to the first component 03 .
  • an embodiment of the present application provides an electronic device.
  • FIG. 3 it is a schematic diagram of a first structure of an electronic device provided by an embodiment of the present application.
  • FIG. 23 it is a schematic structural diagram of a casing of an electronic device provided by an embodiment of the present application. It can be seen from Fig. 3 and Fig. 23 that the electronic device may include: a housing 13, a substrate 1, a first crystal device 2, an adapter board 3, a first plastic sealing layer 4, and a first shielding metal 6, the first crystal device 2 and a transfer board.
  • the connecting boards 3 are juxtaposed on one side surface of the substrate 1 .
  • the substrate 1 is disposed inside the casing 13 .
  • a ground layer is provided inside the substrate 1 , so that components electrically connected to the substrate 1 can be grounded.
  • the first crystal device 2 can be fixed on the substrate 1 by welding or bonding.
  • the adapter plate 3 may include a first ground pad 31, the first ground pad 31 is disposed on the surface of the adapter plate 3 facing the substrate 1, the adapter plate 3 may be electrically connected to the substrate 1 through the first ground pad 31, In order to ground the adapter board 3 .
  • the way that the adapter board 3 is packaged on the substrate 1 can be a ball grid array (ball grid array, BGA) package, and BGA solder balls can be formed between the first ground pad 31 and the substrate 1, and the second A ground pad 31 provides an attachment site for BGA solder balls.
  • BGA ball grid array
  • the riser board 3 can be packaged on the substrate 1 , and the riser board 3 is electrically connected to the substrate 1 through the first ground pad 31 and the BGA solder ball.
  • the first plastic encapsulation layer 4 may include a first portion 41 and a second portion 42 , the first portion 41 may be disposed on the surface of the first crystal device 2 , and the second portion 42 may be disposed between the interposer 3 and the substrate 1 .
  • the first part 41 can achieve the effect of wrapping the first crystal device 2, and the second part 42 can achieve the effect of filling between the adapter plate 3 and the substrate 1, so as to play the role of insulation, heat dissipation and dustproof, and at the same time prevent the first A crystal device 2 and the adapter plate 3 are displaced or damaged when subjected to external force.
  • the first part 41 and the second part 42 can be formed by molding compound, and are shaped by a molding jig.
  • first part 41 and the second part 42 are integrally structured.
  • the first shielding metal 6 may cover the surface of the first portion 41 , and the first shielding metal 6 is electrically connected to the first ground pad 31 to ground the first shielding metal 6 .
  • the first shielding metal 6 can be formed on the surface of the first part 41 by spraying or sputtering, and the thickness of the first shielding metal 6 can be designed according to actual conditions.
  • the electronic device provided by the embodiment of the present application can also be provided with a third ground pad 8, and the third ground pad 8 is provided at the place where the first shielding metal 6 contacts the substrate 1, and the first shielding metal 6 It is connected to the third ground pad 8 so that the first shielding metal 6 is grounded through the substrate 1 .
  • the third ground pad 8 may be pre-prepared on the substrate 1 .
  • FIG. 3 also specifically shows a grounding method of the first shielding metal 6.
  • the adapter plate 3 includes interconnection vias 32, and one end of the interconnection vias 32 is connected to the first grounding pad. 31 connection, and the other end penetrates the surface of the adapter board 3 facing away from the substrate 1 .
  • the first shielding metal 6 extends from the surface of the first part 41 to the surface of the adapter plate 3 facing away from the substrate 1, and is connected to the interconnection via hole 32, so that the first shielding metal 6 is connected to the first ground through the interconnection via hole 32. Pad 31 is connected.
  • the interconnection via hole 32 can play the role of electrical connection. After the first shielding metal 6 covers one side surface of the interconnection via hole 32, it can pass through the interconnection via hole 32 and connect with the other side surface of the interconnection via hole 32.
  • the first ground pad 31 is electrically connected. In this way, the ground layer of the substrate, the first shielding metal 6 , the interconnection vias 32 , the first ground pad 31 and the BGA solder balls form a closed space, that is, a "Faraday cage".
  • FIG. 4 it is a schematic diagram of the first type of Faraday cage of the electronic device provided by the embodiment of the present application, and the part indicated by the dotted line box in FIG. 4 can be regarded as a "Faraday cage".
  • the "Faraday cage” can play a role of shielding, which can ensure that the first crystal device 2 inside it is free from electromagnetic interference of the adapter board 3, and can also ensure that the first crystal device 2 is free from electromagnetic interference from the external environment.
  • the adapter plate 3 outside the “Faraday cage” is protected from the interference of the first crystal device 2 .
  • the diameter of the interconnection via hole 32 can be designed according to actual needs, and is not specifically limited in this application.
  • the shielding film can be covered on the position of the adapter board 3 except for the interconnection via hole 32, so as to play a role of shielding.
  • FIG. 5 it is a schematic diagram of a second structure of an electronic device provided by an embodiment of the present application. It can be seen from Fig. 5 that the grounding method of the first shielding metal 6 can also be realized by the following components:
  • the adapter board 3 also includes a second ground pad 33, the second ground pad 33 is arranged on the surface of the adapter board 3 facing away from the substrate 1, and the two ends of the interconnection via hole 32 are connected with the first ground pad 31 and the first ground pad 31 respectively.
  • the second ground pad 33 is connected.
  • the first shielding metal 6 extends from the surface of the first part 41 to the surface of the adapter board facing away from the substrate 1, and is connected to the second ground pad 33, so that the first shielding metal 6 is interconnected through the second ground pad 33
  • the via hole 32 is connected to the first ground pad 31 .
  • FIG. 6 it is a schematic diagram of a second type of Faraday cage for an electronic device provided in the embodiment of the present application.
  • the part indicated by the dashed box in FIG. 6 can be regarded as a "Faraday cage”.
  • the effects that the "Faraday cage” can achieve have been explained in the previous description, so I won't repeat them here.
  • the transfer Other components of the board 3 may be affected, and the shielding film may be covered on the position of the adapter board 3 except the second grounding pad 33 to play a role of shielding.
  • FIG. 7 it is a schematic diagram of a third structure of an electronic device provided by an embodiment of the present application.
  • the second shielding metal 7 may also be provided outside the adapter plate 3 by spraying or sputtering.
  • the second shielding metal 7 may include a first shielding segment 71 and a second shielding segment 72 .
  • the first shielding section 71 is arranged on the side of the adapter plate 3 facing the first crystal device 2 , and the end of the first shielding section 71 away from the substrate 1 is connected to the first shielding metal 6 .
  • One end of the second shielding segment 72 is connected to the first shielding segment 71 , and the other end is connected to the first ground pad 31 .
  • the first shielding metal 6 After the first shielding metal 6 is connected to the first shielding segment 71 , it can be connected to the first ground pad 31 through the first shielding segment 71 and the second shielding segment 72 , so as to realize grounding.
  • FIG. 8 it is a schematic diagram of a Faraday cage of the third structure of the electronic device provided by the embodiment of the present application.
  • the part shown in the dotted box in FIG. 8 can be regarded as a "Faraday cage”.
  • the effects that the "Faraday cage” can achieve have been explained in the previous description, so I won't repeat them here.
  • the shielding film can be covered on the surface of the adapter board 3 facing away from the substrate 1 to play a shielding role.
  • FIG. 9 it is a schematic diagram of a fourth structure of an electronic device provided by an embodiment of the present application.
  • the second shielding metal 7 may also be provided outside the adapter plate 3 by spraying or sputtering.
  • the second shielding metal 7 also includes a third shielding section 73 .
  • the first shielding section 71 is arranged on the side of the adapter plate 3 facing the first crystal device 2 , and the end of the first shielding section 71 away from the substrate 1 is connected to the first shielding metal 6 .
  • One end of the second shielding segment 72 is connected to the first shielding segment 71 , and the other end is connected to the first ground pad 31 .
  • the third shielding section 73 is disposed on the surface of the adapter board 3 facing away from the substrate 1 , one end of the third shielding section 73 is connected to the first shielding section 71 , and the other end extends a certain distance away from the first crystal device 2 .
  • the first shielding metal 6 may extend in a direction facing away from the first crystal device 2 to completely cover the third shielding segment 73 .
  • the first shielding metal 6 After the first shielding metal 6 is in contact with the third shielding segment 73 , it is connected to the first ground pad 31 through the third shielding segment 73 , the first shielding segment 71 and the second shielding segment 72 , thereby realizing grounding.
  • FIG. 10 it is a schematic diagram of the fourth Faraday cage of the electronic device provided by the embodiment of the present application. The part shown in the dotted line box in FIG. It has already been explained in the description and will not be repeated here.
  • a shielding film can be provided on the surface of the adapter board 3 facing away from the substrate 1, and it must be ensured that the shielding film does not cover the third shielding section 73, so as to play a shielding role.
  • the adapter plate 3 prepared with the second shielding metal 7 may also include a first ground pad 31, an interconnection via hole 32, a second ground pad 33, etc., and the first ground pad 31 may
  • the BGA solder balls are electrically connected to the substrate 1 , and the surface of the second ground pad 33 can be tinned.
  • the second ground pad 33 can be connected to other external devices by soldering, so that other external devices can be connected to the first ground pad 31 through the second ground pad 33 and the interconnection via hole 32 .
  • the number of the first ground pad 31, the interconnection via hole 32 and the second ground pad 33 included in the adapter board 3 can also be planned according to actual needs, and is not limited to including only one first ground pad 31, one interconnect A via hole 32 and a second ground pad 33 .
  • the first crystal device 2 may be packaged on the substrate 1 by welding or bonding.
  • the first crystal device 2a is packaged on the substrate 1 by bonding, and is electrically connected to the substrate 1 by bonding (bonding), and the first crystal device 2b is directly welded on the substrate 1. superior.
  • the first crystal device 2 can also adopt other achievable packaging methods, which are not limited in this embodiment of the present application.
  • the electronic device provided in the embodiments of the present application further includes peripheral components.
  • FIG. 11 it is a schematic diagram of packaging of peripheral components provided by the embodiment of the present application.
  • Figure 11(a) shows the peripheral components of the electronic device of Figure 3
  • Figure 11(b) shows the peripheral components of the electronic device of Figure 5
  • Figure 11(c) shows the peripheral components of the electronic device of Figure 7
  • Encapsulation is performed by soldering or bonding.
  • the peripheral components may be gravity sensors or other devices that are not easily affected by electromagnetic signal interference.
  • the electronic device provided by the embodiment of the present application may include one or more riser boards 3 , and multiple riser boards 3 may be arranged along the edge of the substrate 1 .
  • the number and specific arrangement positions of the adapter plates 3 can be designed according to the actual situation, and are not specifically limited in this application.
  • FIG. 12 it is a schematic diagram of a fifth structure of an electronic device provided by an embodiment of the present application. It can be seen from FIG. 12 that the adapter boards 3 provided in the embodiment of the present application are distributed on the edge of the substrate 1 . Since FIG. 12 is a schematic diagram formed by vertically slicing the electronic device, in FIG. 12 , a plurality of adapter plates 3 are distributed on both sides of the first crystal device 2 .
  • the packaging form of the first crystal device 2 shown in FIG. 12 is only an example, and does not constitute a specific limitation on the packaging form of the first crystal device 2.
  • the first crystal device 2c can be soldered by BGA solder balls. Electrically connected to the substrate 1 , the first crystal device 2 d can be directly soldered on the substrate 1 .
  • FIG. 13 it is a schematic diagram of the fifth Faraday cage of the electronic device provided by the embodiment of the present application.
  • the part shown in the dotted line box in FIG. When the number of 3 is two, both ends of the first shielding metal 6 are respectively connected to the first grounding pad 31 through the third shielding segment 73 , the first shielding segment 71 and the second shielding segment 72 to achieve grounding.
  • the substrate ground layer, the first shielding metal 6, the two third shielding sections 73, the two first shielding sections 71, the two first grounding pads 31 and the BGA solder balls form a similar closed space, namely "Faraday cage".
  • the grounding method of the first shielding metal 6 is not limited to the way of cooperating with the third shielding section 73, the first shielding section 71 and the second shielding section 72, It is also possible to interconnect via holes 32 and the like, for details, refer to FIG. 14 , which will not be described in detail here.
  • the components are generally packaged in a stacked manner.
  • the electronic equipment provided in the embodiment of the present application as an example, except for the components on one side of the substrate 1,
  • the other side of the substrate 1 may also be provided with components, therefore, the shielding of the components on the other side of the substrate 1 should also be ensured during packaging.
  • the electronic device provided by the embodiment of the present application further includes a second crystal device 9 , a second plastic encapsulation layer 10 , a third shielding metal 11 and a grounding metal layer 12 .
  • the second crystal device 9 is disposed on the other surface of the substrate 1 , and the second plastic encapsulation layer 10 is disposed on the surface of the second crystal device 9 .
  • the second crystal device 9 may be packaged on the substrate 1 by welding or bonding.
  • the second plastic encapsulation layer 10 can achieve the effect of wrapping the second crystal device 9 to play the role of insulation, heat dissipation and dustproof, and at the same time prevent the second crystal device 9 from being displaced or damaged when subjected to external force.
  • the second plastic sealing layer 10 can be formed of a plastic sealing compound, and is shaped by a plastic sealing jig.
  • the third shielding metal 11 covers the surface of the second plastic encapsulation layer 10 and the side of the substrate 1 .
  • the grounding metal layer 12 is located inside the substrate 1 and extends from the inside of the substrate 1 to the side of the substrate 1 to connect with the third shielding metal 11 .
  • the third shielding metal 11 can be prepared and formed on the surface of the second plastic encapsulation layer 10 and the side of the substrate 1 by spraying or sputtering, and the thickness of the third shielding metal 11 can be designed according to the actual situation.
  • the third shielding metal 11 covers the second plastic encapsulation layer 10 and the surface and the sides of the substrate 1 , it forms a complete package for the second crystal device 9 and isolates the second crystal device 9 from other devices.
  • the third shielding metal 11 can be grounded through the grounding metal layer 12 extending from the inside of the substrate 1, so as to achieve the shielding effect on the second crystal device 9, avoid mutual interference between the second crystal device 9 and other devices, and prevent the second crystal device 9 from interfering with other devices.
  • the device 9 is subject to electromagnetic interference from the external environment, and at the same time, it can also prevent the second crystal device 9 from interfering with the outside world.
  • the third shielding metal 11 can also cover the side of the second part 42 facing away from the first crystal device 2 , and can also cover the surface of the adapter plate 3 facing away from the first crystal device 2 .
  • a complete shielding layer can be formed by covering the third shielding metal 11 to separate the substrate 1 and the second crystal device 9 from the outside world, making the shielding effect more remarkable.
  • the first crystal device 2 on one side of the substrate 1 and the adapter plate 3 can be shielded from each other, and the second crystal device 9 on the other side of the substrate 1 can also be separated from the outside world Come.
  • the first crystal device 2 may include: nor type flash memory (nor flash), mos tube, SoC chip, decoding circuit (codec IC), charging chip (charger), RLC (resistance, inductance, capacitance ) devices, crystals, bluetooth chips, radio frequency chips, WiFi chips, NFC chips and sensors.
  • the second crystal device 9 may include: nor type flash memory (nor flash), mos tube, SoC chip, decoding circuit (codec IC), charging chip (charger), RLC device, crystal, bluetooth chip, radio frequency chip, WiFi chip One or more of NFC chips and sensors.
  • the first crystal device 2 and the second crystal device 9 may also be other types of chips, which are not specifically limited in this application.
  • the electronic device provided by the embodiment of the present application further includes a solder resist layer 5 , and the solder resist layer 5 covers the surface of the interposer 3 facing away from the substrate 1 .
  • the position where the solder resist layer 5 is provided can be guaranteed not to be soldered. cover.
  • the electronic device provided in the embodiment of the present application may be a TWS earphone.
  • FIG. 15 it is a schematic structural diagram of a TWS earphone provided by an embodiment of the present application.
  • the TWS earphone package may include: a substrate 1 , a first crystal device 2 and an adapter board 3 arranged side by side on the surface of the substrate 1 .
  • the number of adapter boards 3 included in the TWS earphone package can be one, the adapter board 3 includes a first ground pad 31, the first ground pad 31 is arranged on the surface of the adapter board 3 facing the substrate 1, and the adapter board 3 includes a first ground pad 31.
  • the board 3 is electrically connected to the substrate 1 through the first ground pad 31 so as to ground the interposer board 3 .
  • the adapter board 3 may be packaged on the substrate 1 through BGA solder balls.
  • the adapter board 3 may further include interconnect via holes 32 and a second ground pad 32 , and the second ground pad 32 may be tin-plated.
  • a first part 41 is provided on the surface of the first crystal device 2
  • a second part 42 is provided between the adapter board 3 and the first ground pad 31, the first part 41 and the second part 42 are integrally structured, the first part 41 and the second part
  • the two parts 42 form the first plastic encapsulation layer 4 .
  • a second shielding metal 7 is also included, and the second shielding metal 7 includes a first shielding segment 71 , a second shielding segment 72 and a third shielding segment 73 .
  • the first shielding section 71 is disposed on the side of the adapter plate 3 facing the first crystal device 2 , and the end of the first shielding section 71 away from the substrate 1 is connected to the first shielding metal 6 .
  • One end of the second shielding segment 72 is connected to the first shielding segment 71 , and the other end is connected to the first ground pad 31 .
  • the third shielding section 73 is arranged on the surface of the adapter board 3 facing away from the substrate 1, one end of the third shielding section 73 is connected to the first shielding section 71, and the other end extends for a certain distance in the direction facing away from the first crystal device 2.
  • the three shielding segments 73 are connected to the first shielding metal 6 .
  • the substrate 1 is further provided with a third grounding pad 8 , the third grounding pad 8 is disposed at the contact between the first shielding metal 6 and the substrate 1 , and the first shielding metal 6 is connected to the third grounding pad 8 . In this way, the first shielding metal 6 is grounded through the third grounding pad 8 and the second shielding metal 7 , and the substrate 1 is pre-prepared with a grounding layer.
  • the TWS package also includes a second crystal device 9, a second plastic sealing layer 10, a third shielding metal 11, and a ground metal layer 12.
  • the second crystal device 9 is arranged on the other side surface of the substrate 1, and the second plastic sealing layer 10 is arranged on the second The surface of the second crystal device 9 .
  • the third shielding metal 11 is covered on the surface of the second plastic encapsulation layer 10 and the side of the substrate 1, and the third shielding metal 11 is also covered on the side of the second part 42 facing away from the first crystal device 2, and is also covered on the adapter plate. 3 on the side facing away from the first crystal device 2.
  • the ground metal layer 12 is located inside the substrate 1 , extends from the inside of the substrate 1 to the side of the substrate 1 , and is connected to the third shielding metal 11 .
  • the first crystal device 2 can be specifically a nor flash memory (nor flash), an SoC chip, and a crystal
  • the second crystal device 9 can be specifically a charging chip (charger), a decoding circuit (codec IC), a sensor, an RLC device, and a crystal.
  • MOS tube, etc., and the peripheral components can be specific gravity sensors.
  • the first shielding metal 6 may also include other grounding methods, which can be referred to above for details, and will not be described in detail here.
  • the embodiment of the present application also provides a chip packaging method, which can be applied to the packaging field of electronic equipment, especially electronic equipment with a circuit board that transmits signals.
  • FIG. 16 is a schematic flowchart of a chip packaging method provided by an embodiment of the present application.
  • FIG. 17 is an exploded view of a chip packaging method provided by an embodiment of the present application.
  • the method may include the following steps:
  • the substrate 1 may be a circuit board on which ground layer wiring has been carried out and pads are arranged, and specifically may be a printed circuit board (printed circuit board, PCB) or a flexible circuit board (flexible printed circuit board, FPC).
  • PCB printed circuit board
  • FPC flexible printed circuit board
  • the substrate 1 Since the substrate 1 is corroded by moisture and the like during storage, the substrate 1 with high humidity is prone to bursting during packaging.
  • the substrate 1 is baked before the encapsulation operation.
  • the baking temperature and duration can be: 120°C for 8 hours, 150°C for 4-6 hours, or 125°C for 24 hours, etc.
  • the exact baking temperature and duration can be selected according to the actual situation.
  • a third grounding pad 8 is also provided to facilitate the subsequent grounding of the first shielding metal 6 .
  • the specific preparation position of the third ground pad 8 will be described in detail below.
  • solder When soldering and packaging devices, solder can play a role in soldering.
  • S104 bonding or soldering the first crystal device 2 on one side surface of the substrate 1, preparing the first ground pad 31 on the adapter plate 3, and soldering the adapter plate 3 to the substrate 1 through the first ground pad 31
  • the first ground pad 31 is arranged on the surface of the adapter plate 3 facing the substrate 1, and the first crystal device 2 is arranged side by side with the adapter plate 3; the adapter plate 3 is connected to the substrate through the first ground pad 31. 1 is electrically connected so that the adapter plate 3 is grounded.
  • the adapter board 3 may be prepared in advance with the first ground pad 31 , and after the first ground pad 31 is prepared, the adapter board 3 is soldered to the substrate 1 .
  • Bonding the first crystal device 2 may specifically include the following steps:
  • S1041 Perform plasma cleaning on one surface of the substrate 1 .
  • the plasma cleaning step can remove excess flux, oil stains, etc. on the surface of the substrate 1 to prepare for bonding.
  • S1042 Dispensing glue on one side of the substrate 1 .
  • the dispensing operation is performed at the position where the first crystal device 2 needs to be bonded.
  • S1044 Make a bonding wire between the first crystal device 2 and the substrate 1 .
  • Bonding is a way to realize electrical connection. After the bonding wire is bonded between the first crystal device 2 and the substrate 1 , the first crystal device 2 is electrically connected to the substrate 1 .
  • the chip packaging method provided by the embodiment of the present application further includes:
  • the first part 41 and the second part 42 need to be cured for a period of time. After curing, the first part 41 can achieve the effect of wrapping the first crystal device 2, and the second part 42 can achieve the effect of filling between the adapter plate 3 and the substrate 1 effect, so as to play the role of insulation, heat dissipation and dustproof, and at the same time, it can prevent the first crystal device 2 and the adapter plate 3 from being displaced or damaged when subjected to external force.
  • the first part 41 and the second part 42 are formed by means of a plastic sealing jig.
  • the molding compound may include epoxy resin and silicone resin materials and the like.
  • the coating height of the first part 41 can be flush with the height of the adapter plate 3 to ensure a good flatness of the packaged electronic device and provide a flat plane for the subsequent preparation of shielding metal.
  • the coating position of the first part 41 at the end far away from the first crystal device 2 may be flush with the edge of the third ground pad 8 , so as to facilitate subsequent preparation of the first shielding metal 6 .
  • the substrate 1 Before preparing the first part 41 and the second part 42 , the substrate 1 may also be plasma cleaned to remove residual glue and the like on the surface of the substrate 1 .
  • the covering method of the first shielding metal 6 may adopt a process of spraying or sputtering. Due to the spraying or sputtering process in the implementation process, it has a wide coverage. When the first part 41 is sprayed or sputtered, it may affect the surface of the adapter plate 3 facing away from the substrate 1, so it is necessary to cover the surface of the adapter plate 3 facing away from the substrate 1 with a shielding film to play a shielding role. role.
  • the specific coverage range of the shielding film is related to the extension distance of the first shielding metal 6 on the surface of the interposer 3 facing away from the substrate 1 , which will be described in detail below.
  • the chip packaging method provided by the embodiment of the present application may also include packaging some peripheral components.
  • the peripheral components may be arranged on one side of the substrate 1, specifically on the first shielding metal 6
  • the side away from the first crystal device 2 may be packaged by welding or bonding.
  • Peripheral components can be gravity sensors and the like. The specific preparation steps are: first apply solder paste on the surface of the substrate 1 for which peripheral components need to be prepared, and then use reflow soldering technology to solder the peripheral components at corresponding positions.
  • the position of the substrate 1 used to package peripheral components is also covered with a shielding film, so as to avoid the influence of spraying or sputtering the first shielding metal 6 on the encapsulation of subsequent peripheral components .
  • S107 Prepare a third grounding pad 8 where the first shielding metal 6 is in contact with the substrate 1, and connect the first shielding metal 6 to the third grounding pad 8, so as to ground the first shielding metal 6.
  • the first shielding metal 6 may cover part of the third ground pad 8 to ensure that the first shielding metal 8 can be connected to the ground layer of the substrate 1 through the third ground pad 8 .
  • the end of the first shielding metal 6 far away from the adapter plate 3 is grounded by means of the third ground pad 8, and the grounding of the side of the first shielding metal 6 close to the adapter plate 3 can be realized through the following S107 and S108 .
  • this step can be completed before performing S104 , that is, the preparation of the adapter plate 3 is completed before the adapter plate 3 is welded on the substrate 1 .
  • S109 Extend the first shielding metal 6 from the surface of the first part 41 to the surface of the adapter plate 3 facing away from the substrate 1, and connect to the interconnection via hole 32, so that the first shielding metal 6 passes through the interconnection via hole 32 and The first ground pad 31 is connected.
  • S109 may be performed at the same time, so as to realize the grounding of the first shielding metal 6 .
  • the position of the adapter board 3 except the interconnection via hole 32 can be covered with a shielding film to play a role of shielding.
  • the specific covering position of the shielding film can be referred to FIG. 17 .
  • the end of the first shielding metal 6 away from the adapter plate 3 is grounded by means of the third ground pad 8, and the grounding of the side of the first shielding metal 6 close to the adapter plate 3 can also be done through the following S110 and S111 accomplish.
  • FIG. 18 it is an exploded view of another first shielding metal package provided by the embodiment of the present application.
  • this step can be completed before performing S103 , that is, the preparation of the adapter plate 3 is completed before the adapter plate 3 is welded on the substrate 1 .
  • S111 Extend the first shielding metal 6 from the surface of the first part 41 to the surface of the adapter board 3 facing away from the substrate 1, and connect to the second ground pad 33, so that the first shielding metal 6 passes through the second ground pad 33.
  • the interconnection via hole 32 is connected to the first ground pad 31 .
  • S111 may be performed at the same time, so as to realize the grounding of the first shielding metal 6 .
  • the first shielding metal 6 when preparing the first shielding metal 6, on the surface of the adapter plate 3 facing away from the substrate 1, since the first shielding metal 6 only covers the second ground pad 33, in order to avoid spraying or sputtering The process method affects other parts of the adapter board 3 , and the position of the adapter board 3 except the second grounding pad 33 can be covered with a shielding film to play a shielding role.
  • the end of the first shielding metal 6 away from the adapter plate 3 is grounded by means of the third ground pad 8, and the grounding of the side of the first shielding metal 6 close to the adapter plate 3 can also be done through the following S112 and S113 accomplish.
  • FIG. 19 it is an exploded view of another first shielding metal package provided by the embodiment of the present application.
  • S112 Cover the side of the adapter plate 3 facing the first crystal device 2 with metal to form a first shielding section 71 , and an end of the first shielding section 71 away from the substrate 1 is connected to the first shielding metal 6 .
  • S113 Cover the surface of the adapter board 3 facing the substrate 1 with metal to form a second shielding section 72, one end of the second shielding section 72 is connected to the first shielding section 71, and the other end is connected to the first ground pad 31;
  • the first shielding segment 71 and the second shielding segment 72 form the second shielding metal 6 .
  • the step of forming the second shielding metal 6 is completed before performing S104 , that is, the preparation of the interposer 3 is completed before the interposer 3 is soldered on the substrate 1 .
  • the end of the first shielding metal 6 away from the adapter plate 3 is grounded by means of the third ground pad 8 , and the grounding of the side of the first shielding metal 6 close to the adapter plate 3 can also be realized through the following S113 .
  • the second shielding metal 7 may include not only the first shielding section 71 and the second shielding section 72 , but also a third shielding section 73 to realize the grounding of the first shielding metal 6 .
  • FIG. 20 it is an exploded view of another first shielding metal package provided by the embodiment of the present application. specific:
  • S114 Cover the surface of the adapter board 3 facing away from the substrate 1 with metal to form a third shielding section 73, one end of the third shielding section 73 is connected to the first shielding section 71, and the other end is connected to the second grounding pad 33 The direction extends for a certain distance, and the third shielding section 73 is connected to the first shielding metal 6;
  • the first shielding segment 71 , the second shielding segment 72 and the third shielding segment 73 form the second shielding metal 7 .
  • the step of forming the second shielding metal 6 is completed before performing S104 , that is, the preparation of the interposer 3 is completed before the interposer 3 is soldered on the substrate 1 .
  • a shielding film can be provided on the surface of the adapter board 3 facing away from the substrate 1 , and the shielding film does not cover the third shielding section 73 to play a shielding role.
  • the number of adapter boards 3 may be one or multiple, and the packaging method of the adapter board 3 may also be:
  • adapter plates 3 can be welded on the basis of S104, and the specific welding method can refer to the description of S104.
  • a plurality of adapter plates 3 can be arranged along the edge of the substrate 1 , and the number and specific arrangement positions of the adapter plates 3 can be designed according to actual conditions, which are not specifically limited in this application.
  • FIG. 21 is a schematic flowchart of another chip packaging method provided by the embodiment of the present application.
  • FIG. 22 it is an exploded view of another chip packaging method provided by the embodiment of the present application.
  • a specific encapsulation method may include the following steps:
  • the substrate 1 may be pre-baked before printing the solder paste.
  • solder When soldering and packaging devices, solder can play a role in soldering.
  • the second crystal device 9 may be disposed on the surface of the substrate 1 by welding, and may be directly welded on the substrate 1, such as the second crystal device 9a. It can also be soldered on the substrate 1 through BGA solder balls, such as the second crystal device 9b.
  • the second crystal device 9 can also be arranged on the surface of the substrate 1 by bonding, such as the second crystal device 9c, at this time, a bonding wire (bonding) can be made between the second crystal device 9c and the substrate 1 to The second crystal device 9 c is electrically connected to the substrate 1 .
  • the second crystal device 9 a and the second crystal device 9 b to be soldered can be soldered on the substrate 1 by a reflow soldering process, and then plasma cleaning is performed to remove residual solder paste on the surface of the substrate 1 .
  • Glue is dispensed on the position where the second crystal device 9c is packaged, and then the third crystal device 9c is glued on the substrate 1, and then bonding is performed.
  • plasma cleaning should be performed to remove residual glue and the like on the surface of the substrate 1 .
  • the second plastic sealing layer 10 needs to be cured for a period of time. After curing, the second plastic sealing layer 10 can achieve the effect of wrapping the second crystal device 9, so as to play the role of insulation, heat dissipation and dustproof, and can prevent the second crystal device 9 from The device 9 is displaced or damaged when subjected to an external force.
  • the second plastic sealing layer 10 can be formed of a plastic sealing compound, and is shaped by a plastic sealing jig.
  • the molding compound may include epoxy resin and silicone resin materials and the like.
  • the first crystal device 2 when double-sided packaging is performed, after the second crystal device 9 and the second plastic encapsulation layer 10 are prepared, the first crystal device 2, the first part 41, the second part 42 and the first shielding metal
  • the specific preparation operations can refer to S102, S103, S104, S105 and S106.
  • solder resist layer 5 should also be prepared on the surface of the second ground pad 33 .
  • the covering method of the third shielding metal 11 may adopt a process of spraying or sputtering.
  • tinning can also be performed on the second ground pad 33 of the adapter board 3 .
  • S120 Prepare the ground metal layer 12 inside the substrate 1, and the ground metal layer 12 extends from the inside of the substrate 1 to the side of the substrate 1, and is connected to the third shielding metal 11.
  • this step can be performed simultaneously when preparing the substrate 1 .
  • the third shielding metal 11 can also cover the side of the second part 42 facing away from the first crystal device 9 and the side of the adapter plate 1 facing away from the first crystal device 9.
  • the specific packaging steps are as follows:
  • two or more chips when the electronic device is packaged by the chip packaging method provided in the embodiment of the present application, two or more chips can be packaged at one time to form a whole of two or more chips, while ensuring the performance and quality of the chips Under the premise, two or more chips are cut into single pieces to form a single chip.
  • the single cutting operation may be performed before S119 .
  • the electronic devices provided in the embodiments of the present application may be some miniaturized devices, such as earphones, smart bracelets, and smart watches.
  • the technical solutions provided by the embodiments of the present application can realize mutual shielding between components without increasing the layout space, and can also prevent leakage of electromagnetic signals and the like.
  • the technical solution provided by this application can also realize the shielding of electromagnetic signals.
  • the process is simple, and the integration degree is high.

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Abstract

本申请提供一种电子设备及芯片封装方法。该电子设备包括：壳体，壳体内设置有基板；基板一侧表面并列设置有第一晶体器件和转接板，转接板包括第一接地焊盘；第一接地焊盘设置在转接板的面向基板的表面，转接板通过第一接地焊盘与基板电连接，以使转接板接地；第一晶体器件表面设置有第一塑封层的第一部分，转接板与基板之间设置有第一塑封层的第二部分，第一部分和第二部分为一体结构；第一部分表面的覆盖有第一屏蔽金属，第一屏蔽金属与第一接地焊盘电连接，以使第一屏蔽金属接地。本申请的技术方案，可以在不增加布局空间的前提下，实现元器件之间的相互屏蔽，无需增加其他元器件，工艺简单，集成度高。

Description

电子设备及芯片封装方法
本申请要求于2021年8月23日提交到国家知识产权局、申请号为202110968469.4、发明名称为“电子设备及芯片封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装领域，尤其涉及一种电子设备及芯片封装方法。
背景技术
电子设备一直保持着小型化的发展趋势，目前，出现了体积较小的智能手表、智能手环以及无线耳机等。随着电子设备的体积逐渐减小，功能逐渐多样化，用于实现功能的元器件数量也逐渐增多，这也导致了电子设备的元器件的密度逐渐增大。因此，对电子设备的封装工艺提出了更高的要求。
对于具有蓝牙、WiFi或者其他数据传输功能的电子设备来说，例如，参见图1，无线耳机与手机通过蓝牙功能配对连接。为了实现蓝牙、WiFi或者其他数据传输，电子设备设置了天线，天线及其他元器件共同封装在同一封装结构内。但是，在电子设备工作过程中，天线会产生电磁波，在狭小的空间内，天线会对其他部件造成电磁波干扰，使得其他部件的工作性能下降。长期处于这样的工作状态中，器件容易发生损坏，进而造成电子设备的损坏。
发明内容
本申请实施例提供了一种电子设备及芯片封装方法，能够保证器件之间的屏蔽效果，避免器件之间相互影响。
为达到上述目的，本申请实施例提供了以下技术方案：
第一方面，本申请实施例提供了一种电子设备，包括：壳体；壳体内设置有基板；基板一侧表面并列设置有第一晶体器件和转接板，转接板包括第一接地焊盘；第一接地焊盘设置在转接板的面向基板的表面，转接板通过第一接地焊盘与基板电连接，以使转接板接地；第一塑封层，第一晶体器件表面设置有第一塑封层的第一部分，转接板与基板之间设置有第一塑封层的第二部分，第一部分和第二部分为一体结构；第一部分表面覆盖有第一屏蔽金属，第一屏蔽金属与第一接地焊盘电连接，以使第一屏蔽金属接地。
由以上技术方案可知，第一部分设置在第一晶体器件的外侧，通过第一部分的接地，可以形成封闭的法拉第笼，将第一晶体器件与转接板分隔开来，以实现第一晶体器件与转接板之间的相互屏蔽。在实现屏蔽过程中，不需要增加布局空间，屏蔽效果明显。
在一种实现方式中，转接板还包括互连过孔，互连过孔一端与第一接地焊盘连接，另一端贯穿于转接板的背对基板的表面；第一屏蔽金属从第一部分的表面延伸至转接板的背对基板的表面，与互连过孔连接，以使第一屏蔽金属通过互连过孔与第一接地焊盘连接。这样，第一屏蔽金属可以通过覆盖互连过孔的方式进行接地，能够在不增加元器件的情形下实现第一屏蔽金属的接地，工艺简单，集成度高。
在一种实现方式中，转接板还包括互连过孔和第二接地焊盘；第二接地焊盘设置在转接板的背对基板的表面，互连过孔的两端分别与第一接地焊盘以及第二接地焊盘连接；第一屏蔽金属从第一部分的表面延伸至转接板的背对基板的表面，与第二接地焊盘连接，以使第一屏蔽金属通过第二接地焊盘、互连过孔与第一接地焊盘连接。这样，第一屏蔽金属能够通过第二接地焊盘、互连过孔以及第一接地焊盘进行接地。
在一种实现方式中，第二屏蔽金属，第二屏蔽金属包括第一屏蔽段和第二屏蔽段；第一屏蔽段设置在转接板面向第一晶体器件的侧面，第一屏蔽段的远离基板的一端与第一屏蔽金属连接；第二屏蔽段设置在转接板面向基板的表面，第二屏蔽段一端与第一屏蔽段连接，另一端与第一接地焊盘连接。这样，第一屏蔽金属能够通过第二屏蔽段以及第一屏蔽段与第一接地焊盘连接，进而实现接地。
在一种实现方式中，第二屏蔽金属还包括第三屏蔽段，第三屏蔽段设置于转接板的背对基板的表面，第三屏蔽段的一端与第一屏蔽段连接，另一端向靠近第二接地焊盘的方向延伸一定距离，第三屏蔽段与第一屏蔽金属连接。
在一种实现方式中，第一屏蔽金属与基板相接触处设置有第三接地焊盘，第一屏蔽金属与第三接地焊盘连接，以使第一屏蔽金属接地。这样，第一屏蔽金属远离转接板的一端即可实现接地。
在一种实现方式中，转接板分布在基板的边缘。
在一种实现方式中，还包括：基板的另一表面设置有第二晶体器件；第二塑封层，第二塑封层设置在第二晶体器件表面；第二塑封层的表面和基板的侧面覆盖有第三屏蔽金属；基板内部有接地金属层，并且接地金属层从基板内部延伸至基板的侧面，与第三屏蔽金属连接。这样，即可实现对基板的双面封装，且处于基板一侧表面的第一晶体器件与转接板之间可以相互屏蔽，处于基板另一侧表面的第二晶体器件也能够与外界分隔开来，避免电磁信号泄露。
在一种实现方式中，第三屏蔽金属还覆盖在第二部分的背对第一晶体器件的侧面，以及还覆盖在转接板的背对第一晶体器件的侧面。
在一种实现方式中，第一晶体器件包括：nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
在一种实现方式中，第二晶体器件包括：nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
在一种实现方式中，第一屏蔽金属、第二屏蔽金属以及第三屏蔽金属通过喷涂或者溅射的工艺形成。
第二方面，本申请实施例还提供一种芯片封装方法，包括：在壳体内部设置基板；第一晶体器件粘接或者焊接在基板的一侧表面，在转接板上制备第一接地焊盘，将转接板通过第一接地焊盘焊接在基板的一侧表面，第一接地焊盘设置在转接板的面向基板的表面，第一晶体器件与转接板并列设置；转接板通过第一接地焊盘与基板电连接，以使转接板接地；在第一晶体器件的表面涂布塑封料，形成第一部分；在转接板与基板之间涂布塑封料，形成第二部分；第一部分和第二部分形成第一塑封层，第一部分和第二部分为一体结构；待第一部分固化后，在第一部分的表面覆盖金属，形成第一屏蔽金属， 第一屏蔽金属与第一接地焊盘电连接，以使第一屏蔽金属接地。
由以上技术方案可知，第一部分设置在第一晶体器件的外侧，通过第一部分的接地，可以形成封闭的法拉第笼，将第一晶体器件与转接板分隔开来，已实现第一晶体器件与转接板之间的相互屏蔽。在实现屏蔽过程中，不需要增加布局空间，屏蔽效果明显。
在一种实现方式中，在转接板上制备互连过孔，互连过孔的一端与第一接地焊盘连接，另一端贯穿于转接板的背对基板的表面；将第一屏蔽金属从第一部分的表面延伸至转接板的背对基板的表面，与互连过孔连接，以使第一屏蔽金属通过互连过孔与第一接地焊盘连接。这样，第一屏蔽金属可以通过覆盖互连过孔的方式进行接地，能够在不增加元器件的情形下实现第一屏蔽金属的接地，工艺简单，集成度高。
在一种实现方式中，在转接板上制备互连过孔和第二接地焊盘；第二接地焊盘设置在转接板的背对基板的表面，互连过孔的两端分别与第一接地焊盘以及第二接地焊盘连接；将第一屏蔽金属从第一部分的表面延伸至转接板的背对基板的表面，与第二接地焊盘连接，以使第一屏蔽金属通过第二接地焊盘、互连过孔与第一接地焊盘连接。这样，第一屏蔽金属能够通过第二接地焊盘、互连过孔以及第一接地焊盘进行接地。
在一种实现方式中，在转接板面向第一晶体器件的侧面覆盖金属，形成第一屏蔽段，第一屏蔽段的远离基板的一端与第一屏蔽金属连接；在转接板面向基板的表面覆盖金属，形成第二屏蔽段，第二屏蔽段一端与第一屏蔽段连接，另一端与第一接地焊盘连接；第一屏蔽段和第二屏蔽段形成第二屏蔽金属。这样，第一屏蔽金属能够通过第二屏蔽段以及第一屏蔽段与第一接地焊盘连接，进而实现接地。
在一种实现方式中，在转接板的背对基板的表面覆盖金属，形成第三屏蔽段，第三屏蔽段的一端与第一屏蔽段连接，另一端向靠近第二接地焊盘的方向延伸一定距离，第三屏蔽段与第一屏蔽金属连接；第一屏蔽段、第二屏蔽段以及第三屏蔽段形成第二屏蔽金属。
在一种实现方式中，在第一屏蔽金属与基板相接触处制备第三接地焊盘，第一屏蔽金属与第三接地焊盘连接，以使第一屏蔽金属接地。这样，第一屏蔽金属远离转接板的一端即可实现接地。
在一种实现方式中，将转接板通过第一接地焊盘焊接在基板的一侧表面，转接板分布在基板的边缘。
在一种实现方式中，将第二晶体器件焊接或者粘接在基板的另一表面；在第二晶体器件的表面涂布塑封料，形成第二塑封层；待第二塑封层固化后，在第二塑封层的表面以及基板的侧面覆盖金属，形成第三屏蔽金属；在基板内部制备接地金属层，并且接地金属层从基板内部延伸至基板的侧面，与第三屏蔽金属连接。这样，即可实现对基板的双面封装，且处于基板一侧表面的第一晶体器件与转接板之间可以相互屏蔽，处于基板另一侧表面的第二晶体器件也能够与外界分隔开来，避免电磁信号泄露。
在一种实现方式中，在第二部分的背对第一晶体器件的侧面、转接板的背对第一晶体器件的侧面覆盖金属，形成第三屏蔽金属。
在一种实现方式中，nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
在一种实现方式中，nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
在一种实现方式中，第一屏蔽金属、第二屏蔽金属以及第三屏蔽金属通过喷涂或者溅射的工艺形成。
附图说明
图1是一种无线耳机与手机的连接示意图；
图2是目前一种电子设备的示意图；
图3是本申请实施例提供的电子设备的第一种结构示意图；
图4是本申请实施例提供的电子设备的第一种法拉第笼示意图；
图5是本申请实施例提供的电子设备的第二种结构示意图；
图6是本申请实施例提供的电子设备的第二种法拉第笼示意图；
图7是本申请实施例提供的电子设备的第三种结构示意图；
图8是本申请实施例提供的电子设备的第三种法拉第笼示意图；
图9是本申请实施例提供的电子设备的第四种结构示意图；
图10是本申请实施例提供的电子设备的第四种法拉第笼示意图；
图11是本申请实施例提供的外围元器件的封装示意图；
图12是本申请实施例提供的电子设备的第五种结构示意图；
图13是本申请实施例提供的电子设备的第五种法拉第笼示意图；
图14是本申请实施例提供的第一屏蔽金属接地示意图；
图15是本申请实施例提供的一种TWS耳机结构示意图；
图16是本申请实施例提供的一种芯片封装方法的流程示意图；
图17是本申请实施例提供的一种芯片封装方法的分解图；
图18是本申请实施例提供的又一种第一屏蔽金属封装分解图；
图19是本申请实施例提供的又一种第一屏蔽金属封装分解图；
图20是本申请实施例提供的又一种第一屏蔽金属封装分解图；
图21是本申请实施例提供的又一种芯片封装方法流程示意图；
图22是本申请实施例提供的又一种芯片封装方法的分解图；
图23是本申请实施例提供的一种电子设备的壳体的结构示意图。
具体实施方式
为便于理解本申请实施例的技术方案，在对本申请实施例的具体实施方式进行阐述说明之前，首先对本申请实施例所属技术领域的一些技术术语进行简单解释说明。其中：
回流焊接(reflow soldering)，将空气或氮气加热到足够高的温度后吹向已经贴好元件的线路板，让元件两侧的焊料融化后与线路板粘结。
真无线(true wireless stereo，TWS)耳机，即真实无线立体声耳机，可以通过蓝牙与手机等设备进行连接。TWS耳机能够将蓝牙信号处理为左右声道无线分离，左右耳机可独立使用，具有延迟低、蓝牙连接快、传输速度快以及能耗低等特点。
电子设备一直保持着小型化的发展趋势，目前，出现了体积较小的智能手表、智能手环以及无线耳机等。随着电子设备的体积逐渐减小，功能逐渐多样化，用于实现功能的元器件数量也逐渐增多，这也导致了电子设备的元器件的密度逐渐增大。因此，对电子设备的封装工艺提出了更高的要求。
对于具有蓝牙、WiFi或者其他数据传输功能的电子设备来说，例如，参见图1，无 线耳机与手机通过蓝牙功能配对连接。为了实现蓝牙、WiFi或者其他数据传输，电子设备设置了天线，天线及其他元器件共同封装在同一封装结构内。但是，在电子设备工作过程中，天线会产生电磁波，在狭小的空间内，天线会对其他部件造成电磁波干扰，使得其他部件的工作性能下降。长期处于这样的工作状态中，器件容易发生损坏，进而造成电子设备的损坏。
参见图2，为目前一种电子设备的示意图。
如图2所示，该电子设备可以包括：基板01、焊接在基板01一侧的转接板02以及第一元器件03。转接板02是能够传递信号的电路板，在工作时会产生电磁波。由于转接板02与第一元器件03并列设置在基板01的一侧，因此，转接板02在工作时产生的电磁波，会直接对第一元器件03造成电磁波干扰。
为了解决上述问题，本申请实施例提供一种电子设备。
参见图3，为本申请实施例提供的电子设备的第一种结构示意图。参见图23，为本申请实施例提供的一种电子设备的壳体的结构示意图。由图3及图23可知，电子设备可以包括：壳体13、基板1、第一晶体器件2、转接板3、第一塑封层4以及第一屏蔽金属6，第一晶体器件2以及转接板3并列设置在基板1的一侧表面。
具体实现中，基板1设置在壳体13内部。基板1的内部设置有接地层，以使与基板1电连接的部件能够实现接地。第一晶体器件2可以通过焊接或者粘接的方式固定在基板1上。
转接板3可以包括第一接地焊盘31，第一接地焊盘31设置在转接板3的面向基板1的表面，转接板3可以通过第一接地焊盘31与基板1电连接，以使转接板3接地。
在一些实现方式中，转接板3封装在基板1上的方式可以为球栅阵列(ball grid array，BGA)封装，第一接地焊盘31与基板1之间可以形成有BGA焊球，第一接地焊盘31提供了BGA焊球的附着位置。这样，转接板3能够封装在基板1上，并且转接板3通过第一接地焊盘31以及BGA焊球与基板1之间形成电连接。
第一塑封层4可以包括第一部分41以及第二部分42，第一部分41可以设置在第一晶体器件2的表面，第二部分42可以设置在转接板3和基板1之间。第一部分41可以达到包裹第一晶体器件2的效果，第二部分42可以达到填充在转接板3和基板1之间的效果，以起到绝缘、散热及防尘等作用，同时能够防止第一晶体器件2以及转接板3在受到外力作用时发生移位或者受损。
第一部分41和第二部分42可以由塑封料形成，并且依靠塑封治具来成型。
应当理解的是，对第一部分41以及第二部分42进行划分只是为了便于描述，而非物理意义的划分，即第一部分41和第二部分42为一体结构。
第一屏蔽金属6可以覆盖在第一部分41的表面，第一屏蔽金属6与第一接地焊盘31电连接，以使第一屏蔽金属6接地。第一屏蔽金属6可以采用喷涂或者溅射的方式在第一部分41的表面制备形成，第一屏蔽金属6的厚度可以根据实际情况进行设计。
从图3中可以看出，第一屏蔽金属6通过第一接地焊盘31接地后，可以形成一个封闭的空间，这个空间可以将第一晶体器件2隔离起来，这样，可以达到第一晶体器件2和转接板3之间互相屏蔽的作用，使得第一晶体器件2和转接板3不会互相干扰。
在一种实现方式中，本申请实施例提供的电子设备还可以设置第三接地焊盘8，第三接地焊盘8设置在第一屏蔽金属6与基板1相接触处，第一屏蔽金属6与第三接地焊盘8 连接，使第一屏蔽金属6通过基板1接地。第三接地焊盘8可以预先制备在基板1上。
图3中还具体示出了一种第一屏蔽金属6的接地方式，由图3可以看出，转接板3包括互连过孔32，互连过孔32的一端与第一接地焊盘31连接，另一端贯穿于转接板3的背对基板1的表面。第一屏蔽金属6从第一部分41的表面延伸至转接板3的背对基板1的表面，与互连过孔32连接，以使第一屏蔽金属6通过互连过孔32与第一接地焊盘31连接。
互连过孔32可以起到电气连接的作用，第一屏蔽金属6覆盖互连过孔32的一侧表面后，即可通过该互连过孔32，与互连过孔32另一侧表面的第一接地焊盘31电连接。这样，基板接地层、第一屏蔽金属6、互连过孔32、第一接地焊盘31以及BGA焊球即形成了类封闭的空间，即形成了“法拉第笼”。参见图4，为本申请实施例提供的电子设备的第一种法拉第笼示意图，图4中虚线框示出的部位即可视为“法拉第笼”。“法拉第笼”可以起到屏蔽的作用，能够保证其内部的第一晶体器件2免受转接板3电磁干扰，也能够保证第一晶体器件2免受外界环境的电磁干扰，同时也能使得“法拉第笼”外部的转接板3免受第一晶体器件2的干扰。
互连过孔32的孔径可以根据实际需要进行设计，本申请不作具体限定。
在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖互连过孔32，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3除互连过孔32的位置，覆盖屏蔽膜，以起到遮挡的作用。
参见图5，为本申请实施例提供的电子设备的第二种结构示意图。由图5可知，第一屏蔽金属6的接地方式还可以通过以下部件实现：
转接板3还包括第二接地焊盘33，第二接地焊盘33设置在转接板3的背对基板1的表面，互连过孔32的两端分别与第一接地焊盘31以及第二接地焊盘33连接。第一屏蔽金属6从第一部分41的表面延伸至转接板的背对基板1的表面，与第二接地焊盘33连接，以使第一屏蔽金属6通过第二接地焊盘33、互连过孔32与第一接地焊盘31连接。
这样，基板接地层、第一屏蔽金属6、第二接地焊盘33、互连过孔32、第一接地焊盘31以及BGA焊球即形成了类封闭的空间，即“法拉第笼”。参见图6，为本申请实施例提供的电子设备的第二种法拉第笼示意图，图6中虚线框示出的部位即可视为“法拉第笼”。“法拉第笼”可以达到的效果在之前的叙述中已经说明，在此不再赘述。
在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第二接地焊盘33，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3除第二接地焊盘33的位置，覆盖屏蔽膜，以起到遮挡的作用。
参见图7，为本申请实施例提供的电子设备的第三种结构示意图。为了实现第一屏蔽金属6的接地，还可以在转接板3外部以喷涂或者溅射的方式设置第二屏蔽金属7。
第二屏蔽金属7可以包括第一屏蔽段71以及第二屏蔽段72。第一屏蔽段71设置在转接板3面向第一晶体器件2的侧面，第一屏蔽段71的远离基板1的一端与第一屏蔽金属6连接。第二屏蔽段72一端与第一屏蔽段71连接，另一端与第一接地焊盘31连接。
第一屏蔽金属6与第一屏蔽段71连接后，可以通过第一屏蔽段71以及第二屏蔽段72与第一接地焊盘31连接，进而实现接地。
这样，基板接地层、第一屏蔽金属6、第一屏蔽段71、第二屏蔽段72、第一接地焊盘31以及BGA焊球即形成了类封闭的空间，即“法拉第笼”。参见图8，为本申请实施 例提供的电子设备的第三种结构法拉第笼示意图，图8中虚线框示出的部位即可视为“法拉第笼”。“法拉第笼”可以达到的效果在之前的叙述中已经说明，在此不再赘述。
在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第一屏蔽段71，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3背对基板1的表面上覆盖屏蔽膜，以起到遮挡作用。
参见图9，为本申请实施例提供的电子设备的第四种结构示意图。由图9可知，为了实现第一屏蔽金属6的接地，还可以在转接板3外部以喷涂或者溅射的方式设置第二屏蔽金属7。第二屏蔽金属7除了包括第一屏蔽段71以及第二屏蔽段72外，还包括有第三屏蔽段73。
第一屏蔽段71设置在转接板3面向第一晶体器件2的侧面，第一屏蔽段71的远离基板1的一端与第一屏蔽金属6连接。第二屏蔽段72一端与第一屏蔽段71连接，另一端与第一接地焊盘31连接。第三屏蔽段73设置于转接板3的背向基板1的表面，第三屏蔽段73的一端与第一屏蔽段71连接，另一端向背对第一晶体器件2的方向延伸一定距离。
由图9可以看出，第三屏蔽段73在向靠近第二接地焊盘33的方向上延伸时，第三屏蔽段73不与第二接地焊盘33相接触。
第一屏蔽金属6可以在背对第一晶体器件2的方向上延伸，至完全覆盖第三屏蔽段73。
第一屏蔽金属6与第三屏蔽段73接触后，通过第三屏蔽段73、第一屏蔽段71以及第二屏蔽段72与第一接地焊盘31连接，进而实现接地。
这样，基板接地层、第一屏蔽金属6、第三屏蔽段73、第一屏蔽段71、第二屏蔽段72、第一接地焊盘31以及BGA焊球即形成了类封闭的空间，即“法拉第笼”。参见图10，为本申请实施例提供的电子设备的第四种法拉第笼示意图，图10中虚线框示出的部位即可视为“法拉第笼”，“法拉第笼”可以达到的效果在之前的叙述中已经说明，在此不再赘述。
在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第三屏蔽段73，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3背对基板1的表面上设置屏蔽膜，且保证屏蔽膜不覆盖第三屏蔽段73，以起到遮挡作用。
在一些实现方式中，制备有第二屏蔽金属7的转接板3，也可以包括第一接地焊盘31、互连过孔32以及第二接地焊盘33等，第一接地焊盘31可以通过BGA焊球与基板1电连接，第二接地焊盘33表面可以镀锡。第二接地焊盘33可以通过焊接的方式与其他外部器件连接，以使其他外部器件通过第二接地焊盘33、互连过孔32与第一接地焊盘31连接。转接板3包括的第一接地焊盘31、互连过孔32以及第二接地焊盘33的数量也可以根据实际需要进行规划，不限于只包括一个第一接地焊盘31、一个互连过孔32以及一个第二接地焊盘33。
本申请实施例中，第一晶体器件2可以通过焊接或者粘接的方式封装在基板1上。例如，参见图9，第一晶体器件2a以粘接的方式封装在基板1上，并通过打绑定线(bonding)的方式与基板1实现电连接，第一晶体器件2b直接焊接在基板1上。可以理解的是，第一晶体器件2除图9中示出的封装方式外，还可以采用其他可实现的封装方式，本申请 实施例对此不做限定。
在一些实现方式中，本申请实施例提供的电子设备还包括外围元器件。参见图11，为本申请实施例提供的外围元器件的封装示意图。图11(a)示出了图3电子设备的外围元器件，图11(b)示出了图5电子设备的外围元器件，图11(c)示出了图7电子设备的外围元器件，图11(d)示出了图9电子设备的外围元器件，外围元器件可以设置在基板1的一侧表面，具体设置在第一屏蔽金属6远离第一晶体器件2的一侧，可以通过焊接或者粘接的工艺进行封装。外围元器件可以为重力传感器或者其他不容易受电磁信号干扰影响的器件等。
在一些实现方式中，本申请实施例提供的电子设备，包括的转接板3的数量可以为一个，也可以为多个，多个转接板3可以沿着基板1的边缘排布。转接板3的数量以及具体排布位置可以根据实际情况进行设计，本申请不做具体限定。
参见图12，为本申请实施例提供的电子设备的第五种结构示意图。通过图12可以看出，本申请实施例提供的转接板3分布在基板1的边缘。由于图12是对电子设备进行垂直切片后形成的示意图，因此在图12中，多个转接板3分布在第一晶体器件2的两侧。
可以理解的是，图12中示出的第一晶体器件2的封装形式仅作为示例，不构成对第一晶体器件2的封装形式的具体限定，例如：第一晶体器件2c可以通过BGA焊球与基板1电连接，第一晶体器件2d可以直接焊接在基板1上。
参见图13，为本申请实施例提供的电子设备的第五种法拉第笼示意图，图13中虚线框示出的部位即可视为“法拉第笼”，通过图13可以看出，在转接板3的数量为两个的情况下，第一屏蔽金属6的两端分别通过第三屏蔽段73、第一屏蔽段71以及第二屏蔽段72与第一接地焊盘31连接，以实现接地。此时，基板接地层、第一屏蔽金属6、两个第三屏蔽段73、两个第一屏蔽段71、两个第一接地焊盘31以及BGA焊球即形成了类封闭的空间，即“法拉第笼”。
在一些实现方式中，转接板3的数量为多个情况下，第一屏蔽金属6的接地方式不限于通过第三屏蔽段73、第一屏蔽段71以及第二屏蔽段72配合的方式，还可以通过互连过孔32等，具体可以参见图14，此处不再详述。
对于元器件较多的电子设备，在保证小型化的前提下，一般采用堆叠的方式对元器件进行封装，以本申请实施例提供的电子设备为例，除基板1一侧设置有元器件，基板1的另一侧也可能设置有元器件，因此，封装时也应保证基板1另一侧的元器件的屏蔽性。
继续参见图12，本申请实施例提供的电子设备还包括第二晶体器件9、第二塑封层10、第三屏蔽金属11以及接地金属层12。
第二晶体器件9设置在基板1的另一表面，第二塑封层10设置在第二晶体器件9的表面。
具体实现中，第二晶体器件9可以通过焊接或者粘接的工艺方法封装在基板1上。
第二塑封层10可以达到包裹第二晶体器件9的效果，以起到绝缘、散热及防尘等作用，同时能够防止第二晶体器件9在受到外力作用时发生移位或者受损。第二塑封层10可以由塑封料形成，并且依靠塑封治具来成型。
第三屏蔽金属11覆盖在第二塑封层10的表面和基板1的侧面，接地金属层12位于基板1内部，并且从基板1内部延伸至基板1的侧面，与第三屏蔽金属11连接。
具体实现中，第三屏蔽金属11可以采用喷涂或者溅射的方式在第二塑封层10的表 面和基板1的侧面制备形成，第三屏蔽金属11的厚度可以根据实际情况进行设计。
第三屏蔽金属11覆盖在第二塑封层10和表面和基板1的侧面后，形成了对第二晶体器件9的完全包裹，将第二晶体器件9与其他器件隔离开来。第三屏蔽金属11可以通过从基板1内部延伸出的接地金属层12接地，以达到对第二晶体器件9的屏蔽作用，避免第二晶体器件9与其他器件之间相互干扰，避免第二晶体器件9受到外界环境的电磁干扰，同时也能避免第二晶体器件9对外界产生干扰。
第三屏蔽金属11还可以覆盖在第二部分42的背对第一晶体器件2的侧面，以及还可以覆盖在转接板3的背对第一晶体器件2的表面。
从图12中可以看出，通过第三屏蔽金属11的覆盖，可以形成完整的屏蔽层，将基板1以及第二晶体器件9等与外界分隔开来，使得屏蔽效果更加显著。
双面封装完成后，处于基板1一侧的第一晶体器件2与转接板3之间能够相互屏蔽，并且，处于基板1另一侧表面的第二晶体器件9也能与外界分隔开来。
在一些实现方式中，所述第一晶体器件2可以包括：nor型闪存(nor flash)、mos管、SoC芯片、解码电路(codec IC)、充电芯片(charger)、RLC(电阻、电感、电容)器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。所述第二晶体器件9可以包括：nor型闪存(nor flash)、mos管、SoC芯片、解码电路(codec IC)、充电芯片(charger)、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。第一晶体器件2和第二晶体器件9还可以为其他类型的芯片，本申请不做具体限定。
在一些实现方式中，通过图12可以看出，本申请实施例提供的电子设备还包括阻焊层5，阻焊层5覆盖在转接板3背对基板1的表面上。在将转接板3使用回流焊接技术焊接至基板1上，以及在转接板3的第二接地焊盘33上镀锡等操作中，设置有阻焊层5的位置，可以保证不被焊锡覆盖。
在一些实现方式中，本申请实施例提供的电子设备可以为TWS耳机。参见图15，为本申请实施例提供的一种TWS耳机结构示意图。由图15可知，TWS耳机封装可以包括：基板1、并列设置在基板1一侧表面的第一晶体器件2和转接板3。TWS耳机在封装时包括的转接板3的数量可以为一个，转接板3包括第一接地焊盘31，第一接地焊盘31设置在转接板3的面向基板1的表面，转接板3通过第一接地焊盘31与基板1电连接，以使转接板3接地。转接板3具体可以通过BGA焊球封装在基板1上。转接板3还可以包括互连过孔32以及第二接地焊盘32，第二接地焊盘32上可以镀锡处理。第一晶体器件2的表面设置有第一部分41，转接板3与第一接地焊盘31之间设置有第二部分42，第一部分41和第二部分42为一体结构，第一部分41和第二部分42形成第一塑封层4。还包括第二屏蔽金属7，第二屏蔽金属7包括第一屏蔽段71、第二屏蔽段72以及第三屏蔽段73。第一屏蔽段71设置在转接板3面向第一晶体器件2的侧面，第一屏蔽段71远离基板1的一端与第一屏蔽金属6连接。第二屏蔽段72一端与第一屏蔽段71连接，另一端与第一接地焊盘31连接。第三屏蔽段73设置于转接板3的背对基板1的表面，第三屏蔽段73的一端与第一屏蔽段71连接，另一端向背对第一晶体器件2的方向延伸一定距离，第三屏蔽段73与第一屏蔽金属6连接。基板1上还设置有第三接地焊盘8，第三接地焊盘8设置在第一屏蔽金属6与基板1相接触处，第一屏蔽金属6与第三接地焊盘8连接。这样，第一屏蔽金属6就通过第三接地焊盘8以及第二屏蔽金属7接地，基板1 预先制备有接地层。
TWS封装还包括第二晶体器件9、第二塑封层10、第三屏蔽金属11以及接地金属层12，第二晶体器件9设置在基板1的另一侧表面，第二塑封层10设置在第二晶体器件9的表面。第三屏蔽金属11覆盖在第二塑封层10的表面和基板1的侧面，第三屏蔽金属11还覆盖在第二部分42的背对第一晶体器件2的侧面，以及还覆盖在转接板3的背对第一晶体器件2的侧面。接地金属层12位于基板1内部，并且从基板1内部延伸至基板1的侧面，与第三屏蔽金属11连接。
具体的，第一晶体器件2可以具体为nor型闪存(nor flash)、SoC芯片以及晶体，第二晶体器件9可以具体为充电芯片(charger)、解码电路(codec IC)、传感器、RLC器件以及mos管等，外围元器件可以具体为重力传感器。
可以理解的是，TWS耳机在封装时，第一屏蔽金属6还可以包括其他接地方式，可具体参见上文叙述，此处不再详述。
本申请实施例还提供了一种芯片封装方法，该方法可以应用至电子设备的封装领域，尤其是带有传递信号功能的电路板的电子设备。
图16为本申请实施例提供的一种芯片封装方法的流程示意图。图17为本申请实施例提供的一种芯片封装方法的分解图。
下面对本申请实施例提供的方法进行具体说明，如图16所示，该方法可以包括以下步骤：
S101：烘烤基板1。
其中，基板1可以是已进行接地层布线的、布置焊盘的电路板，具体可以为印制电路板(printed circuit board，PCB)或者柔性电路板(flexible printed circuit board，FPC)。
由于基板1在存储过程中，会受到湿气等的侵蚀，湿气较大的基板1在进行封装时容易出现爆裂的情况。为了保证基板1的封装效果，在进行封装操作前，对基板1进行烘烤。烘烤的温度及时长可以为：120℃烘烤8小时，150℃烘烤4-6小时，或者125℃烘烤24小时等，确切的烘烤温度及时长可以根据实际情况进行选择。
基板1在制备过程中，还设置有第三接地焊盘8，便于后续第一屏蔽金属6的接地。第三接地焊盘8的具体制备位置将在下文详述。
S102：在基板1的一侧表面印刷锡膏。
在对器件进行焊接封装时，焊锡可以起到助焊的作用。
S103：在壳体13内部设置基板1；
S104：将第一晶体器件2粘接或者焊接在基板1的一侧表面，在转接板3上制备第一接地焊盘31，将转接板3通过第一接地焊盘31焊接在基板1的一侧表面，第一接地焊盘31设置在转接板3的面向基板1的表面，第一晶体器件2与转接板3并列设置；转接板3通过第一接地焊盘31与基板1电连接，以使转接板3接地。
具体实现中，转接板3可以预先进行第一接地焊盘31的制备，制备有第一接地焊盘31后再将转接板3焊接至基板1上。
对第一晶体器件2进行粘接可以具体包括以下步骤：
S1041：对基板1的一侧表面进行等离子清洗。
等离子清洗的步骤可以去除基板1表面多余的助焊剂、油渍等，为粘接做准备。
S1042：在基板1一侧表面进行点胶。
具体表现为：在需要粘接第一晶体器件2的位置进行点胶操作。
S1043：在基板1的一侧表面对第一晶体器件2进行粘接。
S1044：在第一晶体器件2与基板1之间打绑定线。
打绑定线(bonding)是一种实现电连接的方式，在第一晶体器件2与基板1之间打绑定线后，第一晶体器件2即与基板1之间实现了电连接。
继续参见图16，本申请实施例提供的芯片封装方法还包括：
S105：在第一晶体器件2的表面涂布塑封料，形成第一部分41；在转接板3与基板1之间涂布塑封料，形成第二部分42；第一部分41和第二部分42形成第一塑封层4，第一部分41和第二部分42为一体结构。
第一部分41以及第二部分42需要经过一段时间的固化，在固化后，第一部分41可以达到包裹第一晶体器件2的效果，第二部分42可以达到填充在转接板3和基板1之间的效果，以起到绝缘、散热及防尘等作用，同时能够防止第一晶体器件2以及转接板3在受到外力作用时发生移位或者受损。
第一部分41和第二部分42的并且依靠塑封治具来成型。塑封料可以包括环氧树脂和有机硅树脂材料等。
第一部分41的涂布高度可以与转接板3的高度齐平，以保证封装后的电子器件具有一个良好的平整度，并且为后续制备屏蔽金属提供平整的平面。同时，第一部分41在远离第一晶体器件2的一端的涂布位置，可以与第三接地焊盘8的边缘平齐，以便于后续第一屏蔽金属6的制备。
在进行第一部分41以及第二部分42制备之前，还可以对基板1进行等离子清洗，以去除基板1表面残留的胶水等。
S106：待第一部分41固化后，在第一部分41的表面覆盖金属，形成第一屏蔽金属6，第一屏蔽金属6与第一接地焊盘31电连接，以使第一屏蔽金属6接地。
具体实现中，第一屏蔽金属6的覆盖方式可以采用喷涂或者溅射的工艺。由于喷涂或者溅射工艺在实施过程中，具有广泛的覆盖性。在对第一部分41进行喷涂或者溅射时，可能会影响到转接板3的背对基板1的表面，因此需要在转接板3的背对基板1的表面覆盖屏蔽膜，以起到遮挡的作用。屏蔽膜具体覆盖的范围与第一屏蔽金属6在转接板3的背对基板1的表面的延伸距离有关，这部分内容将在下文进行详述。
在一些实现方式中，由图11可知，本申请实施例提供的芯片封装方法还可以包括封装一些外围的元器件，外围元器件可以设置在基板1的一侧表面，具体设置在第一屏蔽金属6远离第一晶体器件2的一侧，可以通过焊接或者粘接的工艺进行封装。外围元器件可以为重力传感器等。具体制备步骤为：先在需要制备外围元器件的基板1的表面点锡膏，再采用回流焊接的技术将外围元器件焊接在相应的位置。在对转接板3进行屏蔽膜的覆盖时，基板1用于封装外围元器件的位置也覆盖有屏蔽膜，以避免在喷涂或者溅射第一屏蔽金属6对后续外围元器件的封装产生影响。
本申请实施例提供的芯片封装方法还包括以下步骤：
S107：在第一屏蔽金属6与基板1相接触处制备第三接地焊盘8，第一屏蔽金属6与第三接地焊盘8连接，以使第一屏蔽金属6接地。
具体实现中，第一屏蔽金属6可以覆盖部分第三接地焊盘8，以保证第一屏蔽金属8 能够通过第三接地焊盘8与基板1的接地层连接。
在一种实现方式中，第一屏蔽金属6远离转接板3的一端依靠第三接地焊盘8接地，第一屏蔽金属6靠近转接板3的一侧的接地可以通过以下S107及S108实现。
继续参见图17。
S108：在转接板3上制备互连过孔32，互连过孔32的一端与第一接地焊盘31连接，另一端贯穿于转接板3的背对基板1的表面。
具体实现中，这一步骤可以在进行S104之前完成，即，在将转接板3焊接在基板1上之前完成转接板3的制备。
S109：将第一屏蔽金属6从第一部分41的表面延伸至转接板3的背对基板1的表面，与互连过孔32连接，以使第一屏蔽金属6通过互连过孔32与第一接地焊盘31连接。
具体实现中，在S106制备第一屏蔽金属6时，可以同时进行S109，以实现第一屏蔽金属6的接地。
需要说明的是，在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖互连过孔32，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3除互连过孔32的位置，覆盖屏蔽膜，以起到遮挡的作用。屏蔽膜的具体覆盖位置可以参见图17。
在一种实现方式中，第一屏蔽金属6远离转接板3的一端依靠第三接地焊盘8接地，第一屏蔽金属6靠近转接板3的一侧的接地还可以通过以下S110及S111实现。
参见图18，为本申请实施例提供的又一种第一屏蔽金属封装分解图。
S110：在转接板3上制备互连过孔32以及第二接地焊盘33；第二接地焊盘33设置在转接板3的背对基板1的表面，互连过孔32的两端分别与第一接地焊盘31以及第二接地焊盘33连接。
具体实现中，这一步骤可以在进行S103之前完成，即，在将转接板3焊接在基板1上之前完成转接板3的制备。
S111：将第一屏蔽金属6从第一部分41的表面延伸至转接板3的背对基板1的表面，与第二接地焊盘33连接，以使第一屏蔽金属6通过第二接地焊盘33、互连过孔32与第一接地焊盘31连接。
具体实现中，在S106制备第一屏蔽金属6时，可以同时进行S111，以实现第一屏蔽金属6的接地。
需要说明的是，在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第二接地焊盘33，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3除第二接地焊盘33的位置，覆盖屏蔽膜，以起到遮挡的作用。
在一种实现方式中，第一屏蔽金属6远离转接板3的一端依靠第三接地焊盘8接地，第一屏蔽金属6靠近转接板3的一侧的接地还可以通过以下S112及S113实现。
参见图19，为本申请实施例提供的又一种第一屏蔽金属封装分解图。
S112：在转接板3面向第一晶体器件2的侧面覆盖金属，形成第一屏蔽段71，第一屏蔽段71的远离基板1的一端与第一屏蔽金属6连接。
S113：在转接板3面向基板1的表面覆盖金属，形成第二屏蔽段72，第二屏蔽段72一端与第一屏蔽段71连接，另一端与第一接地焊盘31连接；
第一屏蔽段71和第二屏蔽段72形成第二屏蔽金属6。
具体实现中，形成第二屏蔽金属6的步骤在进行S104之前完成，即，在将转接板3焊接在基板1上之前完成转接板3的制备。
需要说明的是，在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第一屏蔽段71，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3背对基板1的表面上覆盖屏蔽膜，以起到遮挡作用。
在一种实现方式中，第一屏蔽金属6远离转接板3的一端依靠第三接地焊盘8接地，第一屏蔽金属6靠近转接板3的一侧的接地还可以通过以下S113实现。
第二屏蔽金属7不仅可以包括第一屏蔽段71以及第二屏蔽段72，还可以包括第三屏蔽段73，以实现第一屏蔽金属6的接地。参见图20，为本申请实施例提供的又一种第一屏蔽金属封装分解图。具体的：
S114：在转接板3的背对基板1的表面覆盖金属，形成第三屏蔽段73，第三屏蔽段73的一端与第一屏蔽段71连接，另一端向靠近第二接地焊盘33的方向延伸一定距离，第三屏蔽段73与第一屏蔽金属6连接；
第一屏蔽段71、第二屏蔽段72以及第三屏蔽段73形成第二屏蔽金属7。
具体实现中，形成第二屏蔽金属6的步骤在进行S104之前完成，即，在将转接板3焊接在基板1上之前完成转接板3的制备。
需要说明的是，在制备第一屏蔽金属6时，在转接板3的背对基板1的表面上，由于第一屏蔽金属6只覆盖第三屏蔽段73，为了避免喷涂或者溅射的工艺方法对转接板3的其他部件产生影响，可以在转接板3背对基板1的表面上设置屏蔽膜，且保证屏蔽膜不覆盖第三屏蔽段73，以起到遮挡作用。
在一些实现方式中，转接板3的数量可以为一个，也可以为多个，转接板3的封装方法还可以为：
S115：将转接板3通过第一接地焊盘31焊接在基板1的一侧表面，转接板3分布在基板1的边缘。
多个转接板3可以在S104的基础上进行焊接，具体焊接方式可以参照S104的叙述。多个转接板3可以沿着基板1的边缘排布，转接板3的数量以及具体排布位置可以根据实际情况进行设计，本申请不做具体限定。
在一些实现方式中，针对需要在基板1的两面都进行封装的情形中，参见图21，为本申请实施例提供的又一种芯片封装方法流程示意图。参见图22，为本申请实施例提供的又一种芯片封装方法的分解图。具体的封装方法可以包括以下步骤：
S116：在基板1的另一侧表面印刷锡膏。
具体实现中，可以在印刷锡膏之前预先对基板1进行烘烤。
在对器件进行焊接封装时，焊锡可以起到助焊的作用。
S117：将第二晶体器件9焊接或者粘接在基板1的另一表面。
从图12中可以看出，第二晶体器件9可以通过焊接的方式设置在基板1的表面，可以直接焊接在基板1上，例如第二晶体器件9a。也可以通过BGA焊球焊接在基板1上，例如第二晶体器件9b。第二晶体器件9还可以通过粘接的方式设置在基板1的表面，例如第二晶体器件9c，此时，可以在第二晶体器件9c与基板1之间打绑定线(bonding)， 以使第二晶体器件9c与基板1电连接。
具体实现中，可以先将需要焊接的第二晶体器件9a以及第二晶体器件9b以回流焊接的工艺焊接在基板1上，然后进行等离子清洗，去除基板1表面残留的锡膏等。在封装第二晶体器件9c的位置上点胶，之后将第三晶体器件9c粘接在基板1上，然后打绑定线(bonding)。
S118：在第二晶体器件9的表面涂布塑封料，形成第二塑封层10。
具体实现中，在进行第二塑封层10的制备之前，还应当进行等离子清洗，以去除基板1表面残留的胶水等。
第二塑封层10需要经过一段时间的固化，在固化后，第二塑封层10可以达到包裹第二晶体器件9的效果，以起到绝缘、散热及防尘等作用，同时能够防止第二晶体器件9在受到外力作用时发生移位或者受损。第二塑封层10可以由塑封料形成，并且依靠塑封治具来成型。塑封料可以包括环氧树脂和有机硅树脂材料等。
在一些实现方式中，在进行双面封装时，完成第二晶体器件9以及第二塑封层10的制备后，可以进行第一晶体器件2、第一部分41、第二部分42以及第一屏蔽金属6的制备，具体制备操作可以参照S102、S103、S104、S105以及S106。
继续参见图21，在焊接转接板3之前，除在转接板3上制备第二屏蔽金属7外，还应当在第二接地焊盘33表面制备阻焊层5。
S119：待第二塑封层10固化后，在第二塑封层10的表面以及基板1的侧面覆盖金属，形成第三屏蔽金属11。
具体实现中，第三屏蔽金属11的覆盖方式可以采用喷涂或者溅射的工艺。
在进行第三屏蔽金属11的制备前，还可以在转接板3的第二接地焊盘33上进行镀锡的操作。
S120：在基板1内部制备接地金属层12，并且接地金属层12从基板1内部延伸至基板1的侧面，与第三屏蔽金属11连接。
具体实现中，这一步骤可以在制备基板1时同时进行。
在一些实现方式中，第三屏蔽金属11还可以覆盖在第二部分42的背对第一晶体器件9的侧面、转接板1的背对第一晶体器件9的侧面，具体封装步骤如下：
S121：在第二部分42的背对第一晶体器件9的侧面、转接板3的背对第一晶体器件2的侧面覆盖金属，形成第三屏蔽金属11。
在一些实现方式中，通过本申请实施例提供的芯片封装方法对电子设备进行封装时，可以一次性封装两个或多个芯片，形成两个或者多个芯片的整体，在保证芯片性能和质量的前提下，将两个或多个芯片整体切单，形成单个芯片。比如，图22示出的分解步骤中，可以在S119之前进行切单操作。
应当理解的是，图22中仅示出了第一屏蔽金属6通过第一屏蔽段71、第二屏蔽段72以及第三屏蔽段73接地的情形，第一屏蔽金属6通过其他器件进行接地的情形在此不再详述。
在一些实施例中，本申请实施例提供的电子设备可以是一些小型化设备，比如耳机、智能手环以及智能手表等。
本申请实施例提供的技术方案，能够在不增加布局空间的前提下，实现元器件之间的相互屏蔽，也能防止电磁信号等发生泄漏。同时，在芯片需要双面封装时，本申请提 供的技术方案也能实现电磁信号的屏蔽。在实现屏蔽性能时，无需增加其他元器件，工艺简单，集成度高。
以上的具体实施方式，对本申请实施例的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上仅为本申请实施例的具体实施方式而已，并不用于限定本申请实施例的保护范围，凡在本申请实施例的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请实施例的保护范围之内。

Claims (17)

  1. 一种电子设备，其特征在于，包括：壳体；
    所述壳体内设置有基板：
    所述基板一侧表面并列设置有第一晶体器件和转接板，所述转接板包括第一接地焊盘；所述第一接地焊盘设置在所述转接板的面向所述基板的表面，所述转接板通过所述第一接地焊盘与所述基板电连接，以使所述转接板接地；
    所述第一晶体器件表面设置有第一塑封层的第一部分，所述转接板与所述基板之间设置有所述第一塑封层的第二部分，所述第一部分和第二部分为一体结构；
    所述第一部分表面覆盖有第一屏蔽金属，所述第一屏蔽金属与所述第一接地焊盘电连接，以使所述第一屏蔽金属接地。
  2. 根据权利要求1所述电子设备，其特征在于，
    所述转接板还包括互连过孔，所述互连过孔一端与所述第一接地焊盘连接，另一端贯穿于所述转接板的背对所述基板的表面；
    所述第一屏蔽金属从所述第一部分的表面延伸至所述转接板的背对所述基板的表面，与所述互连过孔连接，以使所述第一屏蔽金属通过所述互连过孔与所述第一接地焊盘连接。
  3. 根据权利要求1所述电子设备，其特征在于，
    所述转接板还包括互连过孔和第二接地焊盘；
    所述第二接地焊盘设置在所述转接板的背对所述基板的表面，所述互连过孔的两端分别与所述第一接地焊盘以及所述第二接地焊盘连接；
    所述第一屏蔽金属从所述第一部分的表面延伸至所述转接板的背对所述基板的表面，与所述第二接地焊盘连接，以使所述第一屏蔽金属通过所述第二接地焊盘、所述互连过孔与所述第一接地焊盘连接。
  4. 根据权利要求3所述电子设备，其特征在于，还包括：
    第二屏蔽金属，所述第二屏蔽金属包括第一屏蔽段和第二屏蔽段；
    所述第一屏蔽段设置在所述转接板面向所述第一晶体器件的侧面，所述第一屏蔽段的远离所述基板的一端与所述第一屏蔽金属连接；
    所述第二屏蔽段设置在所述转接板面向所述基板的表面，所述第二屏蔽段一端与所述第一屏蔽段连接，另一端与所述第一接地焊盘连接。
  5. 根据权利要求4所述电子设备，其特征在于，
    所述第二屏蔽金属还包括第三屏蔽段，所述第三屏蔽段设置于所述转接板的背对所述基板的表面，所述第三屏蔽段的一端与所述第一屏蔽段连接，另一端向靠近所述第二接地焊盘的方向延伸一定距离，所述第三屏蔽段与所述第一屏蔽金属连接。
  6. 根据权利要求3-5任一项所述电子设备，其特征在于，还包括：
    第三接地焊盘，所述第三接地焊盘设置在所述第一屏蔽金属与所述基板相接触处，所述第一屏蔽金属与所述第三接地焊盘连接，以使所述第一屏蔽金属接地。
  7. 根据权利要求3-6任一项所述电子设备，其特征在于，所述转接板分布在所述基板的边缘。
  8. 根据权利要求7所述电子设备，其特征在于，还包括：
    第二晶体器件，所述第二晶体器件设置在所述基板的另一表面；
    第二塑封层，所述第二塑封层设置在所述第二晶体器件表面；
    第三屏蔽金属，所述第三屏蔽金属覆盖在所述第二塑封层的表面和所述基板的侧面；
    接地金属层，所述接地金属层位于所述基板内部，并且从所述基板内部延伸至所述基板的侧面，与所述第三屏蔽金属连接。
  9. 根据权利要求8所述电子设备，其特征在于，
    所述第三屏蔽金属还覆盖在所述第二部分的背对所述第一晶体器件的侧面，以及还覆盖在所述转接板的背对所述第一晶体器件的侧面。
  10. 根据权利要求1-9任一项所述电子设备，其特征在于，所述第一晶体器件包括：
    nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
  11. 根据权利要求8-9任一项所述电子设备，其特征在于，所述第二晶体器件包括：
    nor型闪存、mos管、SoC芯片、解码电路、充电芯片、RLC器件、晶体、蓝牙芯片、射频芯片、WiFi芯片、NFC芯片以及传感器中的一种或几种。
  12. 根据权利要求5所述电子设备，其特征在于，所述第一屏蔽金属、所述第二屏蔽金属以及所述第三屏蔽金属通过喷涂或者溅射的工艺形成。
  13. 一种芯片封装方法，其特征在于，包括：
    在壳体内部设置基板；
    将第一晶体器件粘接或者焊接在基板的一侧表面，在转接板上制备第一接地焊盘，将所述转接板通过所述第一接地焊盘焊接在所述基板的一侧表面，所述第一接地焊盘设置在所述转接板的面向基板的表面，所述第一晶体器件与所述转接板并列设置；所述转接板通过所述第一接地焊盘与所述基板电连接，以使所述转接板接地；
    在所述第一晶体器件的表面涂布塑封料，形成第一部分；在所述转接板与所述基板之间涂布塑封料，形成第二部分；所述第一部分和所述第二部分形成第一塑封层，所述第一部分和第二部分为一体结构；
    待第一部分固化后，在第一部分的表面覆盖金属，形成第一屏蔽金属，所述第一屏蔽金属与所述第一接地焊盘电连接，以使所述第一屏蔽金属接地。
  14. 根据权利要求13所述的芯片封装方法，其特征在于，
    在所述转接板上制备互连过孔，所述互连过孔的一端与所述第一接地焊盘连接，另一端贯穿于所述转接板的背对所述基板的表面；
    将所述第一屏蔽金属从所述第一部分的表面延伸至所述转接板的背对所述基板的表面，与所述互连过孔连接，以使所述第一屏蔽金属通过所述互连过孔与所述第一接地焊盘连接。
  15. 根据权利要求14所述的芯片封装方法，其特征在于，还包括：
    在所述转接板面向所述第一晶体器件的侧面覆盖金属，形成第一屏蔽段，所述第一屏蔽段的远离所述基板的一端与所述第一屏蔽金属连接；
    在所述转接板面向所述基板的表面覆盖金属，形成第二屏蔽段，所述第二屏蔽段一端与所述第一屏蔽段连接，另一端与所述第一接地焊盘连接；
    所述第一屏蔽段和所述第二屏蔽段形成第二屏蔽金属。
  16. 根据权利要求15所述的芯片封装方法，其特征在于，
    将转接板通过所述第一接地焊盘焊接在所述基板的一侧表面，所述转接板分布在所述基板的边缘。
  17. 根据权利要求16所述的芯片封装方法，其特征在于，
    将第二晶体器件焊接或者粘接在所述基板的另一表面；
    在所述第二晶体器件的表面涂布塑封料，形成第二塑封层；
    待第二塑封层固化后，在第二塑封层的表面以及所述基板的侧面覆盖金属，形成第三屏蔽金属；
    在所述基板内部制备接地金属层，并且所述接地金属层从所述基板内部延伸至所述基板的侧面，与所述第三屏蔽金属连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170179039A1 (en) * 2015-12-21 2017-06-22 Apple Inc. Vertical interconnects for self shielded system in package (sip) modules
US20180019216A1 (en) * 2016-07-18 2018-01-18 Atmel Corporation Antenna on integrated circuit package
CN107768349A (zh) * 2017-09-25 2018-03-06 江苏长电科技股份有限公司 双面SiP三维封装结构
CN107978580A (zh) * 2016-10-25 2018-05-01 日月光半导体制造股份有限公司 半导体器件封装及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102530753B1 (ko) * 2017-08-11 2023-05-10 삼성전자주식회사 전자기파를 차폐하는 반도체 패키지 및 이를 포함하는 전자 시스템
CN112242360B (zh) * 2019-07-19 2022-08-26 江苏长电科技股份有限公司 fcBGA封装结构及其制备方法
CN112563249A (zh) * 2019-09-25 2021-03-26 江苏长电科技股份有限公司 集成封装结构
CN113140538A (zh) * 2021-04-21 2021-07-20 上海闻泰信息技术有限公司 转接板、封装结构及转接板的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170179039A1 (en) * 2015-12-21 2017-06-22 Apple Inc. Vertical interconnects for self shielded system in package (sip) modules
US20180019216A1 (en) * 2016-07-18 2018-01-18 Atmel Corporation Antenna on integrated circuit package
CN107978580A (zh) * 2016-10-25 2018-05-01 日月光半导体制造股份有限公司 半导体器件封装及其制造方法
CN107768349A (zh) * 2017-09-25 2018-03-06 江苏长电科技股份有限公司 双面SiP三维封装结构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4163969A4 *

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