WO2023023972A1 - 半导体结构及半导体结构的形成方法 - Google Patents

半导体结构及半导体结构的形成方法 Download PDF

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Publication number
WO2023023972A1
WO2023023972A1 PCT/CN2021/114493 CN2021114493W WO2023023972A1 WO 2023023972 A1 WO2023023972 A1 WO 2023023972A1 CN 2021114493 W CN2021114493 W CN 2021114493W WO 2023023972 A1 WO2023023972 A1 WO 2023023972A1
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Prior art keywords
conductive layer
region
layer
metal layer
active region
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Ceased
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PCT/CN2021/114493
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English (en)
French (fr)
Inventor
苏巴什·库查努里
王俊
郁扬
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202180099126.7A priority Critical patent/CN117678070A/zh
Priority to PCT/CN2021/114493 priority patent/WO2023023972A1/zh
Priority to US18/686,422 priority patent/US20240387622A1/en
Publication of WO2023023972A1 publication Critical patent/WO2023023972A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a method for forming the semiconductor structure.
  • the technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, which can reduce the size of circuit devices to improve integration.
  • the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes at least one unit region, the unit region includes adjacent first regions and second regions, and the first A region and a second region are arranged along a first direction, the first region includes a first active region, a first isolation region and a second active region arranged along a second direction, the first active region and The second active region is located on both sides of the first isolation region, the second region includes a third active region, a second isolation region and a fourth active region arranged along the second direction, the third active region and The fourth active region is located on both sides of the second isolation region, the central axis of the first isolation region parallel to the first direction does not coincide with the central axis of the second isolation region parallel to the first direction, and the first direction and the first direction do not coincide.
  • the two directions are parallel to the surface of the substrate, and the first direction and the second direction are perpendicular to each other; the first gate structure located on the first region, the first gate structure straddles the first active region, The first isolation region and the second active region, and the first metal layer and the second metal layer respectively located on both sides of the first gate structure, the first gate structure, the first metal layer and the second metal layer
  • the layer is parallel to the second direction; the second gate structure located on the second region, the second gate structure straddles the third active region, the second isolation region and the fourth active region, and respectively located The third metal layer and the fourth metal layer on both sides of the second gate structure, the second gate structure, the third metal layer and the fourth metal layer are parallel to the second direction; an isolation structure, the first isolation structure penetrates the first metal layer and the second metal layer along a first direction, the first gate structure is located on the first isolation structure; the second isolation area located on the second isolation region structure, the second isolation structure penetrates through the third metal layer and the fourth metal layer along the first direction, and
  • the first isolation region is adjacent to the first active region and the second active region; the second isolation region is adjacent to the third active region and the fourth active region.
  • the conductivity type of the device on the first active region is opposite to that of the device on the second active region, and the conductivity type of the device on the third active region is the same as that of the device on the fourth active region.
  • the conductivity type is reversed.
  • the first active region is adjacent to the third active region, and the second active region is adjacent to the fourth active region; the conductivity type of the device on the first active region and the second active region
  • the conductivity type of the device on the three active regions is the same, and the conductivity type of the device is N type; the conductivity type of the device on the second active region is the same as that of the device on the fourth active region, and the conductivity type of the device is It is P type.
  • a fifth metal layer located on the first region, the fifth metal layer is located between the second metal layer and the third metal layer, the fifth metal layer is parallel to the second direction, the The first isolation structure also penetrates the fifth metal layer along the first direction.
  • it also includes: several dummy gate structures on the substrate, several dummy gate structures are arranged in parallel, and the dummy gate structures are parallel to the second direction; the first metal layer is located on the dummy gate structure and the first gate structure, the second metal layer is located between the dummy gate structure and the first gate structure, the third metal layer is located between the dummy gate structure and the second gate structure, The fourth metal layer is located between the dummy gate structure and the second gate structure, and the fifth metal layer is located between adjacent dummy gate structures.
  • a first connection layer parallel to the first direction the first connection layer electrically connects the second metal layer on the first active region and the third active region, the fifth metal layer and the The third metal layer; the second connection layer parallel to the first direction, the second connection layer electrically connects the second metal layer and the fifth metal layer on the second active region; the first conductive layer parallel to the first direction layer, the first conductive layer spans the first active region and the third active region, and the first conductive layer is electrically connected to the first metal layer on the first active region and the third active region
  • a fourth conductive layer parallel to the first direction the fourth conductive layer is electrically connected to the second gate structure, the fourth conductive layer straddles the first active region and Second Quarantine.
  • the first conductive layer, the fourth conductive layer, the second conductive layer and the third conductive layer are arranged in parallel at equal intervals in sequence.
  • a fifth conductive layer parallel to the first direction the fifth conductive layer is located on the first isolation region, the fifth conductive layer is electrically connected to the first gate structure, and the fifth conductive layer is The central axis of the fifth conductive layer in the first direction coincides with the central axis of the second conductive layer in the first direction.
  • it also includes: a power supply voltage line electrically connected to the fifth metal layer on the first active area; a ground voltage line electrically connected to the fifth metal layer on the second active area, and the power supply voltage line and the ground voltage line parallel to the first direction.
  • the plurality of unit areas include a first unit area and a second unit area, the units of the first unit area and the second unit area are arranged along the first direction, and the second area of the first unit area and the second unit area
  • the first area of the two unit areas is adjacent; the first active area of the second unit area is adjacent to the third active area of the first unit area, and the second active area of the second unit area is adjacent to the third active area of the first unit area.
  • the first unit area is adjacent to the fourth active area.
  • a first connection layer parallel to the first direction the first connection layer is electrically connected to the second metal layer on the first active region and on the third active region of the first cell region, The fifth metal layer and the third metal layer; the second connection layer parallel to the first direction, the second connection layer electrically connects the second metal layer and the fifth metal layer on the second active region of the first cell region ; a third connection layer parallel to the first direction, the central axis of the third connection layer in the first direction coincides with the central axis of the first connection layer in the first direction, and the third connection layer is electrically connected to the first The second metal layer and the fifth metal layer on the first active area of the two-cell area; the fourth connection layer parallel to the first direction, the central axis of the fourth connection layer in the first direction is connected to the second The central axes of the layers coincide in the first direction, and the fourth connection layer is electrically connected to the second metal layer and the fifth metal layer on the second active area of the second cell area.
  • the second gate structure, the fourth conductive layer straddles the first active region and the second isolation region of the first cell region; the fifth conductive layer on the first cell region, the fifth conductive layer layers parallel to the first direction, the fifth conductive layer is located on the first isolation region, the fifth conductive layer is electrically connected to the first gate structure of the first cell region, and the fifth conductive layer is on the first
  • the central axis in the direction coincides with the central axis of the second conductive layer in the first direction.
  • the first conductive layer, the fourth conductive layer, the second conductive layer and the third conductive layer are arranged in parallel at equal intervals in sequence.
  • a sixth conductive layer located on the first active region of the second cell region, the sixth conductive layer is parallel to the first direction, and the sixth conductive layer is electrically connected to the The first metal layer on the first active region; the seventh conductive layer on the third active region of the second cell region, the seventh conductive layer is parallel to the first direction, and the seventh conductive layer is electrically connected The third metal layer and the fourth metal layer on the third active area of the second unit area; the eighth conductive layer on the second active area of the second unit area, the eighth conductive layer is parallel to In the first direction, the eighth conductive layer is electrically connected to the first metal layer on the second active area of the second unit area; the ninth conductive layer located on the fourth active area of the second unit area, the first The nine conductive layers are parallel to the first direction, and the ninth conductive layer is electrically connected to the third metal layer and the fourth metal layer on the fourth active area of the second cell area; the first conductive layer, the sixth conductive layer The central axes in the first direction of the
  • a first electrical output layer parallel to the second direction the first electrical output layer is electrically connected to the first conductive layer and the second conductive layer on the first unit area; direction of the second electrical output layer, the second electrical output layer is electrically connected to the sixth conductive layer and the eighth conductive layer on the second unit area.
  • it also includes: a power supply voltage line electrically connected to the fifth metal layer on the first active area of the first cell area and the fifth metal layer on the first active area of the second cell area;
  • the fifth metal layer on the second active area of the region and the fifth metal layer on the second active area of the second cell area are electrically connected to a ground voltage line, and the power supply voltage line and the ground voltage line are parallel to the first direction.
  • the plurality of unit areas include a first unit area, a second unit area, a third unit area and a fourth unit area; the first unit area and the second unit area are arranged along a first The second area of the first unit area is adjacent to the first area of the second unit area; the third unit area and the fourth unit area are arranged along a first direction parallel to the substrate surface, so The second area of the third unit area is adjacent to the first area of the fourth unit area; the first unit area and the fourth unit area are arranged along a second direction parallel to the surface of the substrate, and the first unit area The first area of the area is adjacent to the second area of the fourth unit area, and the second area of the first unit area is adjacent to the first area of the fourth unit area; the second unit area and the third The unit regions are arranged along a second direction parallel to the substrate surface, the second region of the second unit region is adjacent to the first region of the third unit region, the first region of the second unit region is adjacent to the third The second regions of the unit regions are contiguous.
  • a first connection layer parallel to the first direction the first connection layer electrically connecting the second metal layer and the fifth metal layer on the first active region
  • the second connection layer parallel to the first direction Two connection layers, the second connection layer is electrically connected to the second metal layer and the fifth metal layer on the second active region
  • the first conductive layer parallel to the first direction the first conductive layer and the first active layer
  • the first metal layer on the source region is electrically connected
  • the second conductive layer parallel to the first direction is electrically connected to the first gate structure, and the second conductive layer straddles the first active a source region and a second isolation region
  • a third conductive layer parallel to the first direction said third conductive layer being electrically connected to the first metal layer on the second active region
  • an electrical output layer parallel to the second direction The electrical output layer is electrically connected to the first conductive layer and the third conductive layer.
  • a fourth conductive layer parallel to the first direction the fourth conductive layer is electrically connected to the third metal layer on the third active region and the fourth metal layer, the fourth conductive layer
  • the central axis of the layer in the first direction coincides with the central axis of the first conductive layer in the first direction
  • a fifth conductive layer parallel to the first direction the fifth conductive layer is electrically connected to the fourth active region
  • the central axis of the fifth conductive layer in the first direction coincides with the central axis of the third conductive layer in the first direction.
  • the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes at least one unit region, and the unit region includes an adjacent first region and a second region, so The first region and the second region are arranged along a first direction, the first direction is parallel to the substrate surface, the first region includes a first isolation region, the second region includes a second isolation region, the The central axis of the first isolation region parallel to the first direction does not coincide with the central axis of the second isolation region parallel to the first direction; a first gate structure is formed on the first region and located on both sides of the first gate structure respectively The first metal layer and the second metal layer, the first gate structure, the first metal layer and the second metal layer are parallel to the second direction, and the second direction is parallel to the substrate surface and perpendicular to the first direction ; forming a second gate structure on the second region, and a third metal layer and a fourth metal layer respectively located on both sides of the second gate structure, the second gate structure, the third
  • the substrate includes at least one unit area, and the unit area includes adjacent first areas and second areas, and the first area and the second area are parallel to the substrate along the Adjacent in the first direction of the surface, the first area includes a first isolation area, the second area includes a second isolation area, and the central axis of the first isolation area in the first direction is the same as that of the second isolation area The central axes in the first direction do not coincide.
  • the conductive layer parallel to the first direction is subsequently formed, under the predetermined conductive layer design rules, the conductive layer can be combined with the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the The position of electrical connection of the first gate structure or the second gate structure is increased, so that a complex circuit can be formed by using a smaller area of the semiconductor structure unit area, thereby saving the area, increasing the flexibility of the rear-end wiring, and improving the integration degree.
  • the substrate includes a first region and a second region, the first region and the second region are adjacent along a first direction parallel to the surface of the substrate, the first region includes a first isolation region, The second area includes a second isolation area, and the central axis of the first isolation area in the first direction does not coincide with the central axis of the second isolation area in the first direction. Therefore, the second conductive layer can form an active gate contact electrically connected to the first gate structure on the first active region, thereby saving area and increasing wiring flexibility.
  • FIG. 1 is a schematic diagram of a semiconductor structural unit in an embodiment
  • FIG. 2 is a schematic diagram of a semiconductor structure formation process in an embodiment of the present invention.
  • 3 to 5 are schematic diagrams of the process of forming a semiconductor structure in another embodiment of the present invention.
  • 6 to 8 are schematic diagrams of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a semiconductor structure formation process in another embodiment of the present invention.
  • 10 to 12 are schematic views of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a semiconductor structural unit in an embodiment.
  • the semiconductor structure unit includes: a substrate 100, the substrate 100 includes a first region I, an isolation region III and a second region II arranged along a second direction Y parallel to the substrate;
  • the first gate structure 101, the second gate structure 102 and the dummy gate structure 103 in two directions Y, the first gate structure 101, the second gate structure 102 and the dummy gate structure 103 are arranged at equal intervals;
  • the metal layer 104 on both sides of the first gate structure 101, on both sides of the second gate structure 102 and between adjacent dummy gate structures 103; the isolation structure 105 parallel to the first direction X, the isolation structure 105 is located in the isolation On region III and through the metal layer 104, the first direction X is perpendicular to the second direction Y;
  • the isolation region III is located between the first region I and the second region II, so that only one first conductive layer 106 can be formed on the first region I under a predetermined design rule, Only one second conductive layer 107 can be formed on the first region II, so that the metal layer 104, the first gate structure 101 and the second gate structure 102 respectively located on the first region I and the second region II It can only be connected through a conductive layer, and the selection space is small. If a more complex circuit structure is to be formed, it needs to be formed by integrating multiple semiconductor structural units, and the formed semiconductor structure has a large area.
  • the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, which can form a complex circuit by using a smaller area of the semiconductor structure unit area, thereby saving the area, increasing the flexibility of the rear wiring, and improving the degree of integration.
  • FIG. 2 is a schematic diagram of a process of forming a semiconductor structure in an embodiment of the present invention.
  • a substrate 200 is provided, the substrate 200 includes at least one unit area, the unit area includes adjacent first area I and second area II, and the first area I and second area II Arranged along the first direction X, the first direction X is parallel to the surface of the substrate 200, the first region I includes a first isolation region B1, the second region II includes a second isolation region B2, and the second region II includes a second isolation region B2.
  • the central axis of an isolation region B1 parallel to the first direction X does not coincide with the central axis of the second isolation region B2 parallel to the first direction X.
  • the first region I further includes a first active region A1 and a second active region A2, the first isolation region B1 is located between the first active region A1 and the second active region A2, and the first active region B1 is located between the first active region A1 and the second active region A2, and the first An isolation region B1 is adjacent to the first active region A1 and the second active region A2, and the first active region A1, the second active region A2 and the first isolation region B1 are arranged along the second direction Y ;
  • the second region II also includes a third active region A3 and a fourth active region A4, the second isolation region B2 is located between the third active region A3 and the fourth active region A4, and the The second isolation region B2 is adjacent to the third active region A3 and the fourth active region A4, and the third active region A3, the fourth active region A4 and the second isolation region B2 are along the second direction Y arrangement.
  • the conductivity type of the device on the first active region A1 is opposite to that of the device on the second active region A2, and the conductivity type of the device on the third active region A3 is the same as that of the device on the fourth active region A4. The conductivity type is reversed.
  • the first active region A1 is adjacent to the third active region A3, and the second active region A2 is adjacent to the fourth active region A4; the first active region A1
  • the conductivity type of the device on the third active region A3 is the same as the conductivity type of the device on the third active region A3, and the conductivity type of the device is N type; the conductivity type of the device on the second active region A2 is the same as that of the device on the fourth active region A4
  • the conductivity types of the devices are the same, and the conductivity type of the devices is P type.
  • a first gate structure 207, a first isolation structure 209, and a first metal layer 201 and a second metal layer 202 respectively located on both sides of the first gate structure 207 are formed on the first region I,
  • the first gate structure 207 straddles the first active region A1, the first isolation region B1 and the second active region A2, and the first isolation structure 209 penetrates the first metal layer 201, a second metal layer 202 and a fifth metal layer 205
  • the first gate structure 207 is located on the first isolation structure 209
  • the first isolation structure 209 is located on the first isolation region B1
  • the first The gate structure 207 , the first metal layer 201 and the second metal layer 202 are parallel to the second direction Y, which is parallel to the surface of the substrate 200 and perpendicular to the first direction X.
  • a second gate structure 208 , a second isolation structure 210 , and a third metal layer 203 and a fourth metal layer 204 located on both sides of the second gate structure 208 are formed on the second region II,
  • the second gate structure 208 spans the third active region A3, the second isolation region B2 and the fourth active region A4, the second gate structure 208 is located on the second isolation structure 210, the The second isolation structure 210 is located on the second isolation region B2, the second isolation structure 210 penetrates the third metal layer 203 and the fourth metal layer 204 along the first direction X, the second gate structure 208, the first The third metal layer 203 and the fourth metal layer 204 are parallel to the second direction Y.
  • the first metal layer 201 , the second metal layer 202 , the third metal layer 203 and the fourth metal layer 204 are formed simultaneously, and the first gate structure 207 and the second gate structure 208 are formed simultaneously.
  • a fifth metal layer 205 is also formed on the first region I, the The fifth metal layer 205 is located between the second metal layer 202 and the third metal layer 203 , and the fifth metal layer 205 is parallel to the second direction Y.
  • the dummy gate structures 206 are also formed on the substrate, and the several dummy gate structures 206 are arranged in parallel, The dummy gate structure 206 is parallel to the second direction Y.
  • the first metal layer 201 is located between the dummy gate structure 206 and the first gate structure 207
  • the second metal layer 202 is located between the dummy gate structure 206 and the first gate structure 207
  • the third metal layer 203 is located between the dummy gate structure 206 and the second gate structure 208
  • the fourth metal layer 204 is located between the dummy gate structure 206 and the second gate structure 208
  • the fifth metal layer 205 is located between adjacent dummy gate structures 206 .
  • the dummy gate structure 206 is used to improve the process uniformity of forming the first gate structure 207 and the second gate structure 208 .
  • the central axis of the first isolation region B1 in the first direction X does not coincide with the central axis of the second isolation region B2 in the first direction X. Therefore, when the conductive layer parallel to the first direction Y is subsequently formed, under the predetermined conductive layer design rule, the conductive layer can be connected with the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer.
  • the positions of the metal layer 204, the fifth metal layer 205, the first gate structure 207 or the second gate structure 208 are increased, so that a smaller area of the semiconductor structure unit area can be used to form a complex circuit, thereby saving the area, Increase the flexibility of rear-end wiring and improve integration.
  • it also includes: forming a first dielectric layer (not shown) on the substrate 200, the first metal layer 201, the second metal layer 202, the third metal layer 203, and the fourth metal layer 204 , the fifth metal layer 205 , the dummy gate structure 206 , the first gate structure 207 and the second gate structure 208 are located in the first dielectric layer.
  • the embodiment of the present invention also provides a semiconductor structure, please continue to refer to FIG. 2, including:
  • a substrate 200 includes at least one unit area, the unit area includes an adjacent first area I and a second area II, and the first area I and the second area II are arranged along a first direction X
  • the first direction X is parallel to the surface of the substrate 200
  • the first region I includes a first isolation region B1
  • the second region II includes a second isolation region B2
  • the first isolation region B1 is parallel to
  • the central axis of the first direction X does not coincide with the central axis of the second isolation zone B2 parallel to the first direction X;
  • the layer 201 and the second metal layer 202 are parallel to a second direction Y, the second direction Y is parallel to the surface of the substrate 200 and perpendicular to the first direction X;
  • the second gate structure 208 located on the second region II, and the third metal layer 203 and the fourth metal layer 204 respectively located on both sides of the second gate structure 208, the second gate structure 208, the third metal layer Layer 203 and fourth metal layer 204 are parallel to the second direction Y;
  • the second isolation structure 210 located on the second isolation region B2 the second isolation structure 210 penetrates the third metal layer 203 and the fourth metal layer 204 along the first direction X, and the second gate structure 208 is located on the second isolation structure 210 .
  • the first region I further includes a first active region A1 and a second active region A2, and the first isolation region B1 is located between the first active region A1 and the second active region A2 between, and the first isolation region B1 is adjacent to the first active region A1 and the second active region A2, the first active region A1, the second active region A2 and the first isolation region B1 Arranged along the second direction Y;
  • the second region II also includes a third active region A3 and a fourth active region A4, and the second isolation region B2 is located in the third active region A3 and the fourth active region A4 between, and the second isolation region B2 is adjacent to the third active region A3 and the fourth active region A4, the third active region A3, the fourth active region A4 and the second isolation region B2 is arranged along the second direction Y.
  • the conductivity type of the device on the first active region A1 is opposite to the conductivity type of the device on the second active region A2, and the conductivity type of the device on the third active region A3 is opposite to that of the fourth active region A3.
  • the conductivity type of the device on the source region A4 is reversed.
  • the first active region A1 is adjacent to the third active region A3, and the second active region A2 is adjacent to the fourth active region A4; the first active region A1
  • the conductivity type of the device on the third active region A3 is the same as the conductivity type of the device on the third active region A3, and the conductivity type of the device is N type; the conductivity type of the device on the second active region A2 is the same as that of the device on the fourth active region A4
  • the conductivity types of the devices are the same, and the conductivity type of the devices is P type.
  • it further includes: a fifth metal layer 205 located on the first region I, the fifth metal layer 205 is located between the second metal layer 202 and the third metal layer 203, the fifth metal layer 205 is parallel to the second direction Y.
  • it also includes: several dummy gate structures 206 on the substrate, the several dummy gate structures 206 are arranged in parallel, and the dummy gate structures 206 are parallel to the second direction Y; the first The metal layer 201 is located between the dummy gate structure 206 and the first gate structure 207, the second metal layer 202 is located between the dummy gate structure 206 and the first gate structure 207, and the third metal layer 203 is located Between the dummy gate structure 206 and the second gate structure 208, the fourth metal layer 204 is located between the dummy gate structure 206 and the second gate structure 208, and the fifth metal layer 205 is located in the adjacent dummy gate structure 208. between the gate structures 206 .
  • 3 to 5 are schematic views of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 3 is a schematic diagram based on FIG. 2.
  • a first connection layer 211 parallel to the first direction X is formed on the substrate 200, and the first connection layer 211 is electrically connected to the first active region A1. and the second metal layer 202, the fifth metal layer 205, and the third metal layer 203 on the third active region A3;
  • a second connection layer 212 parallel to the first direction X is formed on the substrate 200, and the first The second connection layer 212 is electrically connected to the second metal layer 202 and the fifth metal layer 205 on the second active area A2.
  • first connection layer 211 and the second connection layer 212 Before forming the first connection layer 211 and the second connection layer 212, it also includes: forming a second dielectric layer (not shown) on the first dielectric layer, the first connection layer 211 and the second connection layer 212 are located at the in the second dielectric layer.
  • the first connection layer 211 is electrically connected to the second metal layer 202, the fifth metal layer 205, and the third metal layer 203 on the first active area A1 and the third active area A3, so that the subsequent second The metal layer 202, the fifth metal layer 205 and the third metal layer 203 can be at the same voltage level; the second connection layer 212 is electrically connected to the second metal layer 202 and the fifth metal layer 205 on the second active area A2, Thus, the second metal layer 202 and the fifth metal layer 205 can be at the same voltage level.
  • a first conductive layer 213 parallel to the first direction X is formed on the second dielectric layer, the first conductive layer 213 straddles the first active region A1 and the third active region A3,
  • the first conductive layer 213 is electrically connected to the first metal layer 201 on the first active area A1 and the fourth metal layer 204 on the third active area A3;
  • the second conductive layer 214, the second conductive layer 214 is electrically connected to the third metal layer 203 on the fourth active region A4, the second conductive layer 214 is located on the fourth active region A4;
  • a third conductive layer 215 parallel to the first direction X is formed on the second dielectric layer, the third conductive layer 215 straddles the second active region A2 and the fourth active region A4, and the third conductive layer 215
  • the first metal layer 201 on the second active area A2 is electrically connected to the fourth metal layer 204 on the fourth active area A4.
  • FIG. 4 further comprising: forming a fourth conductive layer 216 parallel to the first direction X on the second dielectric layer, the fourth conductive layer 216 is electrically connected to the second gate structure 208, and the first The four conductive layers 216 straddle the first active region A1 and the second isolation region B1.
  • the first conductive layer 213 , the fourth conductive layer 216 , the second conductive layer 214 and the third conductive layer 215 are arranged in parallel at equal intervals in sequence.
  • a fifth conductive layer 217 parallel to the first direction X on the second dielectric layer the fifth conductive layer 217 is located on the first isolation region B1, and the fifth conductive layer 217 is electrically connected to the first gate structure 207 , and the central axis of the fifth conductive layer 217 in the first direction X coincides with the central axis of the second conductive layer 214 in the first direction X.
  • the central axis of the first isolation region B1 in the first direction X does not coincide with the central axis of the second isolation region B2 in the first direction X. Therefore, when the first conductive layer 213, the fourth conductive layer 216, the second conductive layer 214 and the third conductive layer 215 are formed parallel to the first direction Y, under the established conductive layer design rule, the first conductive layer The layer 213, the fourth conductive layer 216, the second conductive layer 214 or the third conductive layer 215 can be combined with the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer 204, the fifth metal layer 205. The electrical connection positions of the first gate structure 207 or the second gate structure 208 are increased, so that a complex circuit can be formed by using a smaller area of the semiconductor structure unit area, thereby saving the area and increasing the flexibility of the subsequent wiring, Improved integration.
  • FIG. 4 also includes: forming on the second dielectric layer a power supply voltage line 218 electrically connected to the fifth metal layer 205 on the first active region A1;
  • the fifth metal layer 205 on the area A2 is electrically connected to the ground voltage line 219 , and the power supply voltage line 218 and the ground voltage line 219 are parallel to the first direction X.
  • it also includes: forming a third dielectric layer (not shown) on the second dielectric layer, the first conductive layer 213, the fourth conductive layer 216, the second conductive layer 214, the third conductive layer 215 , the fifth conductive layer 217 , the power supply voltage line 218 and the ground voltage line 219 are located in the third dielectric layer.
  • an electrical output layer 220 parallel to the second direction Y is formed on the third dielectric layer, and the electrical output layer 220 is electrically connected to the first conductive layer 213 and the second conductive layer 214 .
  • an embodiment of the present invention also provides a semiconductor structure. Please continue to refer to FIG. 5 .
  • the structure in FIG. 5 also includes:
  • connection layer 212 parallel to the first direction X, the second connection layer 212 electrically connects the second metal layer 202 and the fifth metal layer 205 on the second active region A2;
  • the first conductive layer 213, the fourth conductive layer 216, the second conductive layer 214 and the third conductive layer 215 are arranged in parallel at equal intervals in sequence;
  • a power supply voltage line 218 electrically connected to the fifth metal layer 205 on the first active area A1; a ground voltage line 219 electrically connected to the fifth metal layer 205 on the second active area A2 formed on the second dielectric layer , the power supply voltage line 218 and the ground voltage line 219 are parallel to the first direction X.
  • 6 to 8 are schematic views of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram based on FIG. 2.
  • a plurality of unit areas include a first unit area and a second unit area, and the first unit area and the second unit area are arranged along the first direction X Arranged, the second area II of the first unit area is adjacent to the first area I of the second unit area; the first active area A1 of the second unit area and the third active area of the first unit area The area A3 is adjacent, and the second active area A2 of the second unit area is adjacent to the fourth active area A4 of the first unit area.
  • a first connection layer 311 parallel to the first direction X is formed on the first dielectric layer, and the first connection layer 311 is electrically connected to the first active region A1 of the first cell region and the third The second metal layer 202, the fifth metal layer 205, and the third metal layer 203 on the active area A3; a second connection layer 312 parallel to the first direction X is formed on the first dielectric layer, and the second connection layer 312 electrically connects the second metal layer 202 and the fifth metal layer 205 on the second active area A2 of the first cell area; a third connection layer 313 parallel to the first direction X is formed on the first dielectric layer, the The central axis of the third connection layer 313 in the first direction X coincides with the central axis of the first connection layer 311 in the first direction X, and the third connection layer 313 is electrically connected to the first active region of the second cell region The second metal layer 202 and the fifth metal layer 205 on A1; the fourth connection layer 314 parallel to
  • the first connection layer 311 , the second connection layer 312 , the third connection layer 313 and the fourth connection layer 314 are formed simultaneously.
  • the first connection layer 311 is used to make the second metal layer 202, the fifth metal layer 205 and the third metal layer 203 on the first active region A1 and on the third active region A3 be at the same voltage level;
  • the second connection layer 312 is used to make the second metal layer 202 and the fifth metal layer 205 on the second active area A2 of the first cell area be at the same voltage level;
  • the third connection layer 313 is used to make the second cell The second metal layer 202 and the fifth metal layer 205 on the first active area A1 of the cell area are at the same voltage level;
  • the fourth connection layer 314 is used to make the second metal layer 202 on the second active area A2 of the second cell area
  • the second metal layer 202 and the fifth metal layer 205 are at the same voltage level.
  • it also includes: forming a second dielectric layer (not shown) on the first dielectric layer, the first connection layer 311, the second connection layer 312, the third connection layer 313 and the fourth connection layer 314 is located in the second dielectric layer.
  • a first conductive layer 315 located on the first unit area is formed on the second dielectric layer, the first conductive layer 315 is parallel to the first direction X, and the first conductive layer 315 straddles the The first active region A1 and the third active region A3 of the first unit region, the first conductive layer 315 is electrically connected to the first metal layer 201 and the third active region A1 on the first unit region.
  • a second conductive layer 316 on the fourth active region A4 of the first cell region and on the first isolation region B1 of the second cell region is formed on the second dielectric layer, and the second conductive layer 316 is parallel to the first In the direction X, the second conductive layer 316 is electrically connected to the fourth metal layer 204 on the fourth active area A4 of the first cell area and the first gate structure 207 of the second cell area.
  • a third conductive layer 317 is formed on the first cell area on the second dielectric layer, the third conductive layer 317 is parallel to the first direction X, and the third conductive layer 317 spans the first cell area
  • the second active region A2 and the fourth active region A4 the third conductive layer 317 is electrically connected to the first metal layer 201 on the second active region A2 of the first unit region and the metal layer on the fourth active region A4.
  • the third metal layer 203 is formed on the first cell area on the second dielectric layer, the third conductive layer 317 is parallel to the first direction X, and the third conductive layer 317 spans the first cell area
  • the second active region A2 and the fourth active region A4 the third conductive layer 317 is electrically connected to the first metal layer 201 on the second active region A2 of the first unit region and the metal layer on the fourth active region A4.
  • the third metal layer 203 is formed on the first cell area on the second dielectric layer, the third conductive layer 317 is parallel to the first direction X, and
  • a fourth conductive layer 318 located on the first unit area is formed on the second dielectric layer, the fourth conductive layer 318 is parallel to the first direction X, and the fourth conductive layer 318 is electrically connected to the first unit area.
  • the fourth conductive layer 318 straddles the first active region A1 and the second isolation region B2 of the first cell region.
  • a fifth conductive layer 319 located on the first cell region is formed on the second dielectric layer, the fifth conductive layer 319 is parallel to the first direction X, and the fifth conductive layer 319 is located on the first isolation region B1, so The fifth conductive layer 319 is electrically connected to the first gate structure 207 of the first cell region, and the central axis of the fifth conductive layer 319 in the first direction X is the same as that of the second conductive layer 316 in the first direction X. The central axis coincides.
  • the first conductive layer 315 , the fourth conductive layer 318 , the second conductive layer 316 and the third conductive layer 317 are arranged in parallel at equal intervals in sequence.
  • the conductive layer 315, the fourth conductive layer 318, the second conductive layer 316 and the third conductive layer 317 parallel to the first direction X under the established conductive layer design rules, the conductive layer
  • the positions that can be electrically connected to the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer 204, the first gate structure 207 or the second gate structure 208 are increased, so that two The smaller area of the semiconductor structure unit area forms a complex circuit, thereby saving the area, increasing the flexibility of the rear-end wiring, and improving the integration level.
  • FIG. 7 further comprising: forming a sixth conductive layer 320 on the first active region A1 of the second cell region on the second dielectric layer, the sixth conductive layer 320 is parallel to the first direction X, The sixth conductive layer 320 is electrically connected to the first metal layer 201 on the first active area A1 of the second cell area.
  • a seventh conductive layer 321 located on the third active area A3 of the second unit area is formed on the second dielectric layer, the seventh conductive layer 321 is parallel to the first direction X, and the seventh conductive layer 321 is connected to The third metal layer 203 and the fourth metal layer 204 on the third active area A3 of the second cell area.
  • An eighth conductive layer 322 located on the second active area A2 of the second cell area is formed on the second dielectric layer, the eighth conductive layer 322 is parallel to the first direction X, and the eighth conductive layer 322 is electrically connected to The first metal layer 201 on the second active area A2 of the second cell area.
  • a ninth conductive layer 323 located on the fourth active area A4 of the second cell area is formed on the second dielectric layer, the ninth conductive layer 323 is parallel to the first direction X, and the ninth conductive layer 323 is electrically connected to The third metal layer 203 and the fourth metal layer 204 are on the fourth active area A4 of the second cell area.
  • the central axes of the first conductive layer 315, the sixth conductive layer 320 and the seventh conductive layer 321 in the first direction X coincide; the third conductive layer 317, the eighth conductive layer 322 and the seventh conductive layer
  • the central axes of the nine conductive layers 323 in the first direction coincide.
  • the first conductive layer 315, the fourth conductive layer 318, the second conductive layer 316, the third conductive layer 317, the fifth conductive layer 319, the sixth conductive layer 320, the seventh conductive layer 321, the eighth conductive layer 322 and The ninth conductive layer 323 is formed simultaneously. In this embodiment, it also includes forming a third dielectric layer (not shown) on the second dielectric layer, the first conductive layer 315, the fourth conductive layer 318, the second conductive layer 316, the third conductive layer 317 , the fifth conductive layer 319 , the sixth conductive layer 320 , the seventh conductive layer 321 , the eighth conductive layer 322 and the ninth conductive layer 323 are located in the third dielectric layer.
  • FIG. 7 further includes: forming the fifth metal layer 205 on the first active region A1 of the first unit region and the fifth metal layer 205 on the first active region A1 of the second unit region in the third dielectric layer
  • the power supply voltage line 324 electrically connected to the layer 205; the fifth metal layer 205 on the second active area A2 of the first unit area and the fifth metal layer 205 on the second active area A2 of the second unit area are formed in the third dielectric layer.
  • the metal layer 205 is electrically connected to the ground voltage line 325 , and the power supply voltage line 324 and the ground voltage line 325 are parallel to the first direction.
  • FIG. 8 it also includes: forming a first electrical output layer 326 parallel to the second direction Y on the third dielectric layer, the first electrical output layer 326 is electrically connected to the first conductive layer on the first unit area layer 315 and the second conductive layer 316; on the third dielectric layer, a second electrical output layer 327 parallel to the second direction Y is formed, and the second electrical output layer 327 is electrically connected to the sixth The conductive layer 320 and the eighth conductive layer 322 .
  • an embodiment of the present invention also provides a semiconductor structure. Please continue to refer to FIG. 8 .
  • the structure in FIG. 8 also includes:
  • the plurality of unit areas include a first unit area and a second unit area, the units of the first unit area and the second unit area are arranged along the first direction X, and the second unit area of the first unit area Region II is adjacent to the first region I of the second cell region; the first active region A1 of the second cell region is adjacent to the third active region A3 of the first cell region, and the second cell region The second active region A2 of the first cell region is adjacent to the fourth active region A4 of the first cell region.
  • it further includes: a first connection layer 311 parallel to the first direction X, and the first connection layer 311 electrically connects the first active region A1 of the first cell region and the third active region A3 the second metal layer 202, the fifth metal layer 205 and the third metal layer 203; the second connection layer 312 parallel to the first direction X, the second connection layer 312 is electrically connected to the second active The second metal layer 202 and the fifth metal layer 205 on the source region A2; the third connection layer 313 parallel to the first direction X, the central axis of the third connection layer 313 in the first direction X is connected to the first The central axis of the layer 311 in the first direction X coincides, and the third connection layer 313 electrically connects the second metal layer 202 and the fifth metal layer 205 on the first active area A1 of the second cell area; parallel to the first A fourth connection layer 314 in a direction X, the central axis of the fourth connection layer 314 in the first direction X coincides with the central
  • it further includes: a first conductive layer 315 located on the first cell area, the first conductive layer 315 is parallel to the first direction X, and the first conductive layer 315 straddles the first cell
  • the first conductive layer 315 is electrically connected to the first metal layer 201 on the first active region A1 of the first cell region and the third active region A3 the fourth metal layer 204 above
  • the second conductive layer 316 located on the fourth active region A4 of the first cell region and the first isolation region B1 of the second cell region, the second conductive layer 316 is parallel to the first In one direction X
  • the second conductive layer 316 is electrically connected to the fourth metal layer 204 on the fourth active area A4 of the first cell area and the first gate structure 207 of the second cell area
  • region, the third conductive layer 317 is parallel to the first direction X, and the third conductive layer 317 straddles the second active region A2 and the fourth active region A2 of the
  • the first conductive layer 315 , the fourth conductive layer 318 , the second conductive layer 316 and the third conductive layer 317 are arranged in parallel at equal intervals in sequence.
  • it further includes: a sixth conductive layer 320 located on the first active region A1 of the second cell region, the sixth conductive layer 320 is parallel to the first direction X, and the sixth conductive layer 320 Electrically connect the first metal layer 201 on the first active area A1 of the second unit area; the seventh conductive layer 321 located on the third active area A3 of the second unit area, the seventh conductive layer 321 is parallel to In the first direction X, the seventh conductive layer 321 connects the third metal layer 203 and the fourth metal layer 204 on the third active area A3 of the second cell area; The eighth conductive layer 322 on the source region A2, the eighth conductive layer 322 is parallel to the first direction X, and the eighth conductive layer 322 is electrically connected to the first metal layer on the second active region A2 of the second cell region layer 201; the ninth conductive layer 323 located on the fourth active area A4 of the second unit area, the ninth conductive layer 323 is parallel to the first direction X, and the ninth conductive layer 3
  • the central axes of the first conductive layer 315, the sixth conductive layer 320 and the seventh conductive layer 321 in the first direction X coincide; the third conductive layer 317, the eighth conductive layer 322 and the seventh conductive layer Central axes in the first direction of the nine conductive layers 323 are coincident.
  • it also includes: a power supply voltage electrically connected to the fifth metal layer 205 on the first active area A1 of the first cell area and the fifth metal layer 205 on the first active area A1 of the second cell area line 324; a ground voltage line 325 electrically connected to the fifth metal layer 205 on the second active area A2 of the first cell area and the fifth metal layer 205 on the second active area A2 of the second cell area, the power supply The voltage line 324 and the ground voltage line 325 are parallel to the first direction.
  • it further includes: a first electrical output layer 326 parallel to the second direction Y, and the first electrical output layer 326 is electrically connected to the first conductive layer 315 and the second conductive layer 315 on the first unit area.
  • layer 316 the second electrical output layer 327 parallel to the second direction Y, the second electrical output layer 327 is electrically connected to the sixth conductive layer 320 and the eighth conductive layer 322 on the second unit area.
  • FIG. 9 is a schematic diagram of a semiconductor structure in another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram based on FIG. 2 , the plurality of unit areas include a first unit area, a second unit area, a third unit area and a fourth unit area.
  • the first unit area and the second unit area are arranged along a first direction X parallel to the surface of the substrate 200, and the second area II of the first unit area is adjacent to the first area I of the second unit area;
  • the third unit area and the fourth unit area are arranged along a first direction X parallel to the surface of the substrate 200, and the second area II of the third unit area is adjacent to the first area I of the fourth unit area;
  • the first unit area and the fourth unit area are arranged along a second direction Y parallel to the surface of the substrate, the first area I of the first unit area is adjacent to the second area II of the fourth unit area, and the The second area II of the first unit area is adjacent to the first area I of the fourth unit area;
  • the second unit area and the third unit area are arranged along a second direction Y parallel to the surface of the substrate 200, so The second area II of the second unit area is adjacent to the first area I of the third unit area, and the first area I of the second unit area is adjacent to the second area II of the third unit area
  • the conductive layer parallel to the first direction X is subsequently formed, under the predetermined conductive layer design rule, the conductive layer can be connected with the first metal layer 201, the second metal layer 202, the third metal layer 203, the fourth metal layer
  • the positions for electrical connection of the metal layer 204, the first gate structure 207 or the second gate structure 208 are increased, so that four or several semiconductor structure unit regions with a smaller area can be used to form a complex circuit, thereby saving area and increasing
  • the flexibility of the back-end wiring improves the integration level.
  • 10 to 12 are schematic views of the formation process of the semiconductor structure in another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram based on FIG. 2.
  • a first connection layer 511 parallel to the first direction X is formed on the first dielectric layer.
  • a second connection layer 512 parallel to the first direction X is formed on the first dielectric layer, and the second connection layer 512 is electrically connected to the second active region The second metal layer 202 and the fifth metal layer 205 on A2.
  • it further includes: forming a second dielectric layer (not shown) on the first dielectric layer, and the first connection layer 511 and the second connection layer 512 are located in the second dielectric layer.
  • the first connection layer 511 is used to make the second metal layer 202 and the fifth metal layer 205 on the first active region A1 at the same voltage level; the second connection layer 512 is used to make the second active region A1
  • the second metal layer 202 and the fifth metal layer 205 on the area A2 are at the same voltage level.
  • a first conductive layer 513 parallel to the first direction X is formed on the second dielectric layer, and the first conductive layer 513 is electrically connected to the first metal layer 201 on the first active region A1;
  • a second conductive layer 514 parallel to the first direction X is formed on the second dielectric layer, the second conductive layer 514 is electrically connected to the first gate structure 207, and the second conductive layer 514 straddles the first gate structure.
  • Source region A1 and second isolation region B2; a third conductive layer 515 parallel to the first direction X is formed on the second dielectric layer, and the third conductive layer 515 is connected with the first metal layer on the second active region A2 201 is electrically connected.
  • the central axis of the first isolation region B1 in the first direction X is in the same direction as the second isolation region B2.
  • the central axes in the first direction X do not coincide. Therefore, the second conductive layer 514 can form an active gate contact electrically connected to the first gate structure 207 on the first active region A1 , thereby saving area and increasing wiring flexibility.
  • a fourth conductive layer 516 parallel to the first direction X on the second dielectric layer further comprising: forming a fourth conductive layer 516 parallel to the first direction X on the second dielectric layer, and the fourth conductive layer 516 is electrically connected to the third active area A3 on the third The metal layer 203 and the fourth metal layer 204, the central axis of the fourth conductive layer 516 in the first direction X coincides with the central axis of the first conductive layer 513 in the first direction X; formed on the second dielectric layer A fifth conductive layer 517 parallel to the first direction X, the fifth conductive layer 517 is electrically connected to the third metal layer 203 and the fourth metal layer 204 on the fourth active area A4, the fifth conductive layer
  • the central axis of 517 in the first direction X coincides with the central axis of the third conductive layer 515 in the first direction X; a sixth conductive layer 518 parallel to the first direction X is formed on the second dielectric layer, and the first The six
  • the fourth conductive layer 516 is electrically connected to the third metal layer 203 and the fourth metal layer 204 on the third active area A3, for making the second gate structure 208 on the third active area A3 Failure; the fifth conductive layer 517 is electrically connected to the third metal layer 203 and the fourth metal layer 204 on the fourth active region A4, for making the second gate on the fourth active region A4 Structure 208 fails.
  • the first conductive layer 513 , the second conductive layer 514 , the sixth conductive layer 518 and the third conductive layer 515 are arranged in parallel at equal intervals in sequence.
  • FIG. 11 further comprising: forming a power supply voltage line 519 parallel to the first direction X on the second dielectric layer, and the power supply voltage line 519 is electrically connected to the fifth metal layer 205 on the first active region A1 ; Form a ground voltage line 520 parallel to the first direction X on the second dielectric layer, and the ground voltage line 520 is electrically connected to the fifth metal layer 205 on the second active area A2.
  • it also includes: forming a third dielectric layer (not shown) on the second dielectric layer, the first conductive layer 513, the second conductive layer 514, the sixth conductive layer 518, the third conductive layer 515 , the fourth conductive layer 516 , the fifth conductive layer 517 , the power supply voltage line 519 and the ground voltage line 520 are located in the third dielectric layer.
  • an electrical output layer 521 parallel to the second direction Y is formed on the third dielectric layer, and the electrical output layer 521 is electrically connected to the first conductive layer 513 and the third conductive layer 515 .
  • the embodiment of the present invention also provides a semiconductor structure. Please continue to refer to FIG. 12.
  • the structure in FIG. 12 also includes:
  • first connection layer 511 parallel to the first direction X, the first connection layer 511 electrically connects the second metal layer 202 and the fifth metal layer 205 on the first active region A1;
  • connection layer 512 parallel to the first direction X, the second connection layer 512 electrically connects the second metal layer 202 and the fifth metal layer 205 on the second active region A2;
  • first conductive layer 513 parallel to the first direction X, the first conductive layer 513 is electrically connected to the first metal layer 201 on the first active region A1;
  • the central axis of 516 in the first direction X coincides with the central axis of the first conductive layer 513 in the first direction X;
  • the central axis of 517 in the first direction X coincides with the central axis of the third conductive layer 515 in the first direction X;
  • ground voltage line 520 parallel to the first direction X, the ground voltage line 520 is electrically connected to the fifth metal layer 205 on the second active area A2;
  • the electrical output layer 521 parallel to the second direction Y is electrically connected to the first conductive layer 513 and the third conductive layer 515 .

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Abstract

半导体结构及其形成方法，结构包括：衬底，衬底包括至少一个单元区，单元区包括沿第一方向排布的相邻的第一区和第二区，第一区包括第一隔离区，第二区包括第二隔离区，第一隔离区平行于第一方向的中轴线与第二隔离区的中轴线不重合；位于第一区上的第一栅极结构、分别位于第一栅极结构两侧的第一金属层和第二金属层；位于第二区上的第二栅极结构、分别位于第二栅极结构两侧的第三金属层和第四金属层，第一栅极结构、第一金属层、第二金属层、第二栅极结构、第三金属层和第四金属层平行于第二方向；位于第一隔离区上沿第一方向贯穿第一金属层和第二金属层的第一隔离结构；位于第二隔离区上沿第一方向贯穿第三金属层和第四金属层的第二隔离结构。

Description

半导体结构及半导体结构的形成方法 技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及半导体结构的形成方法。
背景技术
随着半导体技术的不断发展，集成电路性能的提高主要是通过不断缩小集成电路器件的尺寸以提高它的速度来实现的。目前，由于高器件密度、高性能和低成本的需求，半导体工业已经进步到纳米技术工艺节点。
然而，缩小电路器件的尺寸以提升集成度是持续需要解决的问题。
发明内容
本发明解决的技术问题是提供一种半导体结构及半导体结构的形成方法，缩小电路器件的尺寸以提升集成度。
为解决上述技术问题，本发明技术方案提供一种半导体结构，包括：衬底，所述衬底包括至少一个单元区，所述单元区包括相邻的第一区和第二区，所述第一区和第二区沿第一方向排布，所述第一区包括沿第二方向排列的第一有源区、第一隔离区和第二有源区，所述第一有源区和第二有源区位于第一隔离区两侧，所述第二区包括沿第二方向排列的第三有源区、第二隔离区和第四有源区，所述第三有源区和第四有源区位于第二隔离区两侧，所述第一隔离区平行于第一方向的中轴线与第二隔离区平行于第一方向的中轴线不重合，所述第一方向和第二方向平行于衬底表面，且所述第一方向和第二方向相互垂直；位于第一区上的第一栅极结构，所述第一栅极结构横跨所述第一有源区、第一隔离区和第二有源区，以及分别位于所述第一栅极结构 两侧的第一金属层和第二金属层，所述第一栅极结构、第一金属层和第二金属层平行于第二方向；位于第二区上的第二栅极结构，所述第二栅极结构横跨所述第三有源区、第二隔离区和第四有源区，以及分别位于第二栅极结构两侧的第三金属层和第四金属层，所述第二栅极结构、第三金属层和第四金属层平行于第二方向；位于第一隔离区上的第一隔离结构，所述第一隔离结构沿第一方向贯穿所述第一金属层和第二金属层，所述第一栅极结构位于第一隔离结构上；位于第二隔离区上的第二隔离结构，所述第二隔离结构沿第一方向贯穿所述第三金属层和第四金属层，所述第二栅极结构位于第二隔离结构上。
可选的，所述第一隔离区与所述第一有源区和第二有源区相邻；所述第二隔离区与所述第三有源区和第四有源区相邻。
可选的，所述第一有源区上的器件导电类型与第二有源区上的器件导电类型相反，所述第三有源区上的器件导电类型与第四有源区上的器件导电类型相反。
可选的，所述第一有源区和第三有源区相邻，所述第二有源区和第四有源区相邻；所述第一有源区上的器件导电类型和第三有源区上的器件导电类型相同，所述器件导电类型为N型；所述第二有源区上的器件导电类型和第四有源区上的器件导电类型相同，所述器件导电类型为P型。
可选的，还包括：位于第一区上的第五金属层，所述第五金属层位于第二金属层和第三金属层之间，所述第五金属层平行于第二方向，所述第一隔离结构还沿第一方向贯穿所述第五金属层。
可选的，还包括：位于衬底上的若干伪栅极结构，若干所述伪栅极结构平行排列，所述伪栅极结构平行于第二方向；所述第一金属层位于伪栅极结构和第一栅极结构之间，所述第二金属层位于伪栅极结构和第一栅极结构之间，所述第三金属层位于伪栅极结构和第二栅极结构之间，所述第四金属层位于伪栅极结构和第二栅极结构之间，所述第五金属层位于相邻的伪栅极结构之间。
可选的，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一有源区上和第三有源区上的第二金属层、第五金属层和第三金属层；平行于第一方向的第二连接层，所述第二连接层电连接第二有源区上的第二金属层和第五金属层；平行于第一方向的第一导电层，所述第一导电层横跨所述第一有源区和第三有源区，所述第一导电层电连接第一有源区上的第一金属层和第三有源区上的第四金属层；平行于第一方向的第二导电层，所述第二导电层电连接所述第四有源区上的第三金属层，所述第二导电层位于第四有源区上；平行于第一方向的第三导电层，所述第三导电层横跨所述第二有源区和第四有源区，所述第三导电层电连接第二有源区上的第一金属层和第四有源区上的第四金属层；平行于第二方向的电输出层，所述电输出层电连接所述第一导电层和第二导电层。
可选的，还包括：平行于第一方向的第四导电层，所述第四导电层电连接所述第二栅极结构，所述第四导电层横跨所述第一有源区和第二隔离区。
可选的，所述第一导电层、第四导电层、第二导电层和第三导电层依次等间距平行排列。
可选的，还包括：平行于第一方向的第五导电层，所述第五导电层位于第一隔离区上，所述第五导电层电连接所述第一栅极结构，所述第五导电层在第一方向上的中轴线与第二导电层在第一方向上的中轴线重合。
可选的，还包括：与第一有源区上的第五金属层电连接的电源电压线；与第二有源区上的第五金属层电连接的接地电压线，所述电源电压线和接地电压线平行于第一方向。
可选的，多个单元区中包括第一单元区和第二单元区，所述第一单元区和第二单元区单元沿第一方向排列，所述第一单元区的第二区与第二单元区的第一区相邻接；所述第二单元区的第一有源区和第一单元区的第三有源区相邻，所述第二单元区的第二有源区和第一单元 区第四有源区相邻。
可选的，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一单元区的第一有源区上和第三有源区上的第二金属层、第五金属层和第三金属层；平行于第一方向的第二连接层，所述第二连接层电连接第一单元区的第二有源区上的第二金属层和第五金属层；平行于第一方向的第三连接层，所述第三连接层在第一方向上的中轴线与第一连接层在第一方向上的中轴线重合，所述第三连接层电连接第二单元区的第一有源区上的第二金属层和第五金属层；平行于第一方向的第四连接层，所述第四连接层在第一方向上的中轴线与第二连接层在第一方向上的中轴线重合，所述第四连接层电连接第二单元区的第二有源区上的第二金属层和第五金属层。
可选的，还包括：位于第一单元区上的第一导电层，所述第一导电层平行于第一方向，所述第一导电层横跨所述第一单元区的第一有源区和第三有源区，所述第一导电层电连接第一单元区的第一有源区上的第一金属层和第三有源区上的第四金属层；位于第一单元区的第四有源区上和第二单元区的第一隔离区上的第二导电层，所述第二导电层平行于第一方向，所述第二导电层电连接所述第一单元区的第四有源区上的第四金属层和第二单元区的第一栅极结构；位于第一单元区上的第三导电层，所述第三导电层平行于第一方向，所述第三导电层横跨所述第一单元区的第二有源区和第四有源区，所述第三导电层电连接第一单元区的第二有源区上的第一金属层和第四有源区上的第三金属层；位于第一单元区上的第四导电层，所述第四导电层平行于第一方向，所述第四导电层电连接所述第一单元区的第二栅极结构，所述第四导电层横跨所述第一单元区的第一有源区和第二隔离区；位于第一单元区上的第五导电层，所述第五导电层平行于第一方向，所述第五导电层位于第一隔离区上，所述第五导电层电连接所述第一单元区的第一栅极结构，所述第五导电层在第一方向上的中轴线与第二导电层在第一方向上的中轴线重合。
可选的，所述第一导电层、第四导电层、第二导电层和第三导电层依次等间距平行排列。
可选的，还包括：位于第二单元区的第一有源区上的第六导电层，所述第六导电层平行于第一方向，所述第六导电层电连接第二单元区的第一有源区上的第一金属层；位于第二单元区的第三有源区上的第七导电层，所述第七导电层平行于第一方向，所述第七导电层电连接所述第二单元区的第三有源区上的第三金属层和第四金属层；位于第二单元区的第二有源区上的第八导电层，所述第八导电层平行于第一方向，所述第八导电层电连接第二单元区的第二有源区上的第一金属层；位于第二单元区的第四有源区上的第九导电层，所述第九导电层平行于第一方向，所述第九导电层电连接所述第二单元区的第四有源区上第三金属层和第四金属层；所述第一导电层、第六导电层和第七导电层第一方向上的中轴线重合；所述第三导电层、第八导电层和第九导电层第一方向上的中轴线重合。
可选的，还包括：平行于第二方向的第一电输出层，所述第一电输出层电连接所述第一单元区上的第一导电层和第二导电层；平行于第二方向的第二电输出层，所述第二电输出层电连接所述第二单元区上的第六导电层和第八导电层。
可选的，还包括：与第一单元区第一有源区上的第五金属层以及第二单元区第一有源区上的第五金属层电连接的电源电压线；与第一单元区第二有源区上的第五金属层以及第二单元区第二有源区上的第五金属层电连接的接地电压线，所述电源电压线和接地电压线平行于第一方向。
可选的，多个单元区中包括第一单元区、第二单元区、第三单元区和第四单元区；所述第一单元区和第二单元区沿平行于衬底表面的第一方向排列，所述第一单元区的第二区与第二单元区的第一区相邻接；所述第三单元区和第四单元区沿平行于衬底表面的第一方向排列，所述第三单元区的第二区与第四单元区的第一区相邻接；所述第 一单元区和第四单元区沿平行于衬底表面的第二方向排列，所述第一单元区的第一区与第四单元区的第二区相邻接，所述第一单元区的第二区与第四单元区的第一区相邻接；所述第二单元区和第三单元区沿平行于衬底表面的第二方向排列，所述第二单元区的第二区与第三单元区的第一区相邻接，所述第二单元区的第一区与第三单元区的第二区相邻接。
可选的，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一有源区上的第二金属层和第五金属层；平行于第一方向的第二连接层，所述第二连接层电连接第二有源区上的第二金属层和第五金属层；平行于第一方向的第一导电层，所述第一导电层与第一有源区上的第一金属层电连接；平行于第一方向的第二导电层，所述第二导电层与第一栅极结构电连接，所述第二导电层横跨所述第一有源区和第二隔离区；平行于第一方向的第三导电层，所述第三导电层与第二有源区上的第一金属层电连接；平行于第二方向的电输出层，所述电输出层电连接所述第一导电层和第三导电层。
可选的，还包括：平行于第一方向的第四导电层，所述第四导电层电连接所述第三有源区上的第三金属层和第四金属层，所述第四导电层在第一方向上的中轴线与第一导电层在第一方向上的中轴线重合；平行于第一方向的第五导电层，所述第五导电层电连接所述第四有源区上的第三金属层和第四金属层，所述第五导电层在第一方向上的中轴线与第三导电层在第一方向上的中轴线重合。
可选的，还包括：平行于第一方向的第六导电层，所述第六导电层横跨所述第一隔离区和第四有源区；所述第一导电层、第二导电层、第六导电层和第三导电层依次等间距平行排列；平行于第一方向的电源电压线，所述电源电压线与第一有源区上的第五金属层电连接；平行于第一方向的接地电压线，所述接地电压线与第二有源区上的第五金属层电连接。
相应地，本发明技术方案还提供一种半导体结构的形成方法，包 括：提供衬底，所述衬底包括至少一个单元区，所述单元区包括相邻的第一区和第二区，所述第一区和第二区沿第一方向排布，所述第一方向平行于衬底表面，所述第一区包括第一隔离区，所述第二区包括第二隔离区，所述第一隔离区平行于第一方向的中轴线与第二隔离区平行于第一方向的中轴线不重合；在第一区上形成第一栅极结构、以及分别位于第一栅极结构两侧的第一金属层和第二金属层，所述第一栅极结构、第一金属层和第二金属层平行于第二方向，所述第二方向平行于衬底表面且与第一方向垂直；在第二区上形成第二栅极结构、以及分别位于第二栅极结构两侧的第三金属层和第四金属层，所述第二栅极结构、第三金属层和第四金属层平行于第二方向；在第一隔离区上形成第一隔离结构，所述第一隔离结构沿第一方向贯穿所述第一金属层和第二金属层；在第二隔离区上形成第二隔离结构，所述第二隔离结构沿第一方向贯穿所述第三金属层和第四金属层。
本发明技术方案中的半导体结构，所述衬底包括至少一个单元区，所述单元区包括相邻的第一区和第二区，所述第一区和第二区在沿平行于衬底表面的第一方向上相邻，所述第一区包括第一隔离区，所述第二区包括第二隔离区，所述第一隔离区在第一方向上的中轴线与第二隔离区在第一方向上的中轴线不重合。从而使得后续形成平行于第一方向的导电层时，在既定的导电层设计规则下，所述导电层可与第一金属层、第二金属层、第三金属层、第四金属层、第一栅极结构或第二栅极结构电连接的位置增加，从而能够利用较小面积的半导体结构单元区形成复杂的电路，从而节省了面积，增加后段布线的灵活性，提高了集成度。
进一步，所述衬底包括第一区和第二区，所述第一区和第二区在沿平行于衬底表面的第一方向上相邻，所述第一区包括第一隔离区，所述第二区包括第二隔离区，所述第一隔离区在第一方向上的中轴线与第二隔离区在第一方向上的中轴线不重合。从而所述第二导电层能够在第一有源区上形成与第一栅极结构电连接的有源栅接触，从而能够节省面积，增加布线的灵活性。
附图说明
图1为一实施例中半导体结构单元的示意图；
图2为本发明一实施例中半导体结构形成过程的示意图；
图3至图5为本发明另一实施例中半导体结构形成过程的示意图；
图6至图8为本发明另一实施例中半导体结构形成过程的示意图；
图9为本发明另一实施例中半导体结构形成过程的示意图；
图10至图12为本发明另一实施例中半导体结构形成过程的示意图。
具体实施方式
如背景技术所述，缩小电路器件的尺寸以提升集成度是持续需要解决的问题。现结合具体的实施例进行分析说明。
图1为一实施例中半导体结构单元的示意图。
请参考图1，所述半导体结构单元包括：衬底100，所述衬底100包括沿平行于衬底第二方向Y排列的第一区I、隔离区III和第二区II；平行于第二方向Y的第一栅极结构101、第二栅极结构102和伪栅极结构103，所述第一栅极结构101、第二栅极结构102和伪栅极结构103等间距排列；位于第一栅极结构101两侧、第二栅极结构102两侧以及相邻伪栅极结构103之间的金属层104；平行于第一方向X的隔离结构105，所述隔离结构105位于隔离区III上且贯穿所述金属层104，所述第一方向X与第二方向Y垂直；平行于第一方向X的第一导电层106和第二导电层107，所述第一导电层106横跨所述第一区I，所述第二导电层107横跨所述第二区II。
所述半导体结构单元中，所述隔离区III位于第一区I和第二区II之间，从而在既定的设计规则下，所述第一区I上只能形成一条第 一导电层106，所述第一区II上只能形成一条第二导电层107，从而分别位于第一区I和第二区II上的所述金属层104、第一栅极结构101和第二栅极结构102只能通过一条导电层连出，选择空间小，如果要形成较为复杂的电路结构，则需要多个半导体结构单元集成才能形成，形成的半导体结构面积较大。
为了解决上述问题，本发明技术方案提供一种半导体结构及半导体结构的形成方法，能够利用较小面积的半导体结构单元区形成复杂的电路，从而节省了面积，增加后段布线的灵活性，提高了集成度。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2为本发明一实施例中半导体结构形成过程的示意图。
请参考图2，提供衬底200，所述衬底200包括至少一个单元区，所述单元区包括相邻的第一区I和第二区II，所述第一区I和第二区II沿第一方向X排布，所述第一方向X平行于衬底200表面，所述第一区I包括第一隔离区B1，所述第二区II包括第二隔离区B2，所述第一隔离区B1平行于第一方向X的中轴线与第二隔离区B2平行于第一方向X的中轴线不重合。
所述第一区I还包括第一有源区A1和第二有源区A2，所述第一隔离区B1位于第一有源区A1和第二有源区A2之间，且所述第一隔离区B1与所述第一有源区A1和第二有源区A2相邻，所述第一有源区A1、第二有源区A2和第一隔离区B1沿第二方向Y排列；所述第二区II还包括第三有源区A3和第四有源区A4，所述第二隔离区B2位于第三有源区A3和第四有源区A4之间，且所述第二隔离区B2与所述第三有源区A3和第四有源区A4相邻，所述第三有源区A3、第四有源区A4和第二隔离区B2沿第二方向Y排列。
所述第一有源区A1上的器件导电类型与第二有源区A2上的器件导电类型相反，所述第三有源区A3上的器件导电类型与第四有源区A4上的器件导电类型相反。
在本实施例中，所述第一有源区A1和第三有源区A3相邻，所述第二有源区A2和第四有源区A4相邻；所述第一有源区A1上的器件导电类型和第三有源区A3上的器件导电类型相同，所述器件导电类型为N型；所述第二有源区A2上的器件导电类型和第四有源区A4上的器件导电类型相同，所述器件导电类型为P型。
请继续参考图2，在第一区I上形成第一栅极结构207、第一隔离结构209、以及分别位于第一栅极结构207两侧的第一金属层201和第二金属层202，所述第一栅极结构207横跨所述第一有源区A1、第一隔离区B1和第二有源区A2，所述第一隔离结构209沿第一方向X贯穿所述第一金属层201、第二金属层202和第五金属层205，所述第一栅极结构207位于第一隔离结构209上，所述第一隔离结构209位于第一隔离区B1上，所述第一栅极结构207、第一金属层201和第二金属层202平行于第二方向Y，所述第二方向Y平行于衬底200表面且与第一方向X垂直。
请继续参考图2，在第二区II上形成第二栅极结构208、第二隔离结构210、以及分别位于第二栅极结构208两侧的第三金属层203和第四金属层204，所述第二栅极结构208横跨所述第三有源区A3、第二隔离区B2和第四有源区A4，所述第二栅极结构208位于第二隔离结构210上，所述第二隔离结构210位于第二隔离区B2上，所述第二隔离结构210沿第一方向X贯穿所述第三金属层203和第四金属层204，所述第二栅极结构208、第三金属层203和第四金属层204平行于第二方向Y。
所述第一金属层201、第二金属层202、第三金属层203和第四金属层204同时形成，所述第一栅极结构207和第二栅极结构208同时形成。
在本实施例中，在形成第一金属层201、第二金属层202、第三金属层203和第四金属层204的同时，还在第一区I上形成第五金属层205，所述第五金属层205位于第二金属层202和第三金属层203之间，所述第五金属层205平行于第二方向Y。
在本实施例中，在形成所述第一栅极结构207和第二栅极结构208的同时，还在衬底上形成若干伪栅极结构206，若干所述伪栅极结构206平行排列，所述伪栅极结构206平行于第二方向Y。
所述第一金属层201位于伪栅极结构206和第一栅极结构207之间，所述第二金属层202位于伪栅极结构206和第一栅极结构207之间，所述第三金属层203位于伪栅极结构206和第二栅极结构208之间，所述第四金属层204位于伪栅极结构206和第二栅极结构208之间，所述第五金属层205位于相邻的伪栅极结构206之间。
所述伪栅极结构206用于提升形成第一栅极结构207和第二栅极结构208的工艺均匀性。
所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合。从而使得后续形成平行于第一方向Y的导电层时，在既定的导电层设计规则下，所述导电层可与第一金属层201、第二金属层202、第三金属层203、第四金属层204、第五金属层205、第一栅极结构207或第二栅极结构208电连接的位置增加，从而能够利用较小面积的半导体结构单元区形成复杂的电路，从而节省了面积，增加后段布线的灵活性，提高了集成度。
在本实施例中，还包括：在衬底200上形成第一介质层(未图示)，所述第一金属层201、第二金属层202、第三金属层203、第四金属层204、第五金属层205、伪栅极结构206、第一栅极结构207和第二栅极结构208位于所述第一介质层内。
相应地，本发明实施例还提供一种半导体结构，请继续参考图2，包括：
衬底200，所述衬底200包括至少一个单元区，所述单元区包括相邻的第一区I和第二区II，所述第一区I和第二区II沿第一方向X排布，所述第一方向X平行于衬底200表面，所述第一区I包括第一隔离区B1，所述第二区II包括第二隔离区B2，所述第一隔离区B1平行于第一方向X的中轴线与第二隔离区B2平行于第一方向X的中轴线不重合；
位于第一区I上的第一栅极结构207、以及分别位于第一栅极结构207两侧的第一金属层201和第二金属层202，所述第一栅极结构207、第一金属层201和第二金属层202平行于第二方向Y，所述第二方向Y平行于衬底200表面且与第一方向X垂直；
位于第二区II上的第二栅极结构208、以及分别位于第二栅极结构208两侧的第三金属层203和第四金属层204，所述第二栅极结构208、第三金属层203和第四金属层204平行于第二方向Y；
位于第一隔离区B1上的第一隔离结构209，所述第一隔离结构209沿第一方向X贯穿所述第一金属层201、第二金属层202和第五金属层205，所述第一栅极结构207位于第一隔离结构209上；
位于第二隔离区B2上的第二隔离结构210，所述第二隔离结构210沿第一方向X贯穿所述第三金属层203和第四金属层204，所述第二栅极结构208位于第二隔离结构210上。
在本实施例中，所述第一区I还包括第一有源区A1和第二有源区A2，所述第一隔离区B1位于第一有源区A1和第二有源区A2之间，且所述第一隔离区B1与所述第一有源区A1和第二有源区A2相邻，所述第一有源区A1、第二有源区A2和第一隔离区B1沿第二方向Y排列；所述第二区II还包括第三有源区A3和第四有源区A4，所述第二隔离区B2位于第三有源区A3和第四有源区A4之间，且所述第二隔离区B2与所述第三有源区A3和第四有源区A4相邻，所述第三有源区A3、第四有源区A4和第二隔离区B2沿第二方向Y排列。
在本实施例中，所述第一有源区A1上的器件导电类型与第二有源区A2上的器件导电类型相反，所述第三有源区A3上的器件导电类型与第四有源区A4上的器件导电类型相反。
在本实施例中，所述第一有源区A1和第三有源区A3相邻，所述第二有源区A2和第四有源区A4相邻；所述第一有源区A1上的器件导电类型和第三有源区A3上的器件导电类型相同，所述器件导电类型为N型；所述第二有源区A2上的器件导电类型和第四有源区 A4上的器件导电类型相同，所述器件导电类型为P型。
在本实施例中，还包括：位于第一区I上的第五金属层205，所述第五金属层205位于第二金属层202和第三金属层203之间，所述第五金属层205平行于第二方向Y。
在本实施例中，还包括：位于衬底上的若干伪栅极结构206，若干所述伪栅极结构206平行排列，所述伪栅极结构206平行于第二方向Y；所述第一金属层201位于伪栅极结构206和第一栅极结构207之间，所述第二金属层202位于伪栅极结构206和第一栅极结构207之间，所述第三金属层203位于伪栅极结构206和第二栅极结构208之间，所述第四金属层204位于伪栅极结构206和第二栅极结构208之间，所述第五金属层205位于相邻的伪栅极结构206之间。
图3至图5为本发明另一实施例中半导体结构形成过程的示意图。
请参考图3，图3为在图2基础上的示意图，在衬底200上形成平行于第一方向X的第一连接层211，所述第一连接层211电连接第一有源区A1上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203；在衬底200上形成平行于第一方向X的第二连接层212，所述第二连接层212电连接第二有源区A2上的第二金属层202和第五金属层205。
在形成第一连接层211和第二连接层212之前，还包括：在第一介质层上形成第二介质层(未图示)，所述第一连接层211和第二连接层212位于所述第二介质层内。
所述第一连接层211电连接第一有源区A1上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203，从而使得后续所述第二金属层202、第五金属层205和第三金属层203能够处于同一电压水平；所述第二连接层212电连接第二有源区A2上的第二金属层202和第五金属层205，从而使得所述第二金属层202和第五金属层205能够处于同一电压水平。
请参考图4，在第二介质层上形成平行于第一方向X的第一导电层213，所述第一导电层213横跨所述第一有源区A1和第三有源区A3，所述第一导电层213电连接第一有源区A1上的第一金属层201和第三有源区A3上的第四金属层204；在第二介质层上形成平行于第一方向X的第二导电层214，所述第二导电层214电连接所述第四有源区A4上的第三金属层203，所述第二导电层214位于第四有源区A4上；在第二介质层上形成平行于第一方向X的第三导电层215，所述第三导电层215横跨所述第二有源区A2和第四有源区A4，所述第三导电层215电连接第二有源区A2上的第一金属层201和第四有源区A4上的第四金属层204。
请继续参考图4，还包括：在第二介质层上形成平行于第一方向X的第四导电层216，所述第四导电层216电连接所述第二栅极结构208，所述第四导电层216横跨所述第一有源区A1和第二隔离区B1。
所述第一导电层213、第四导电层216、第二导电层214和第三导电层215依次等间距平行排列。
请继续参考图4，还包括：在第二介质层上形成平行于第一方向X的第五导电层217，所述第五导电层217位于第一隔离区B1上，所述第五导电层217电连接所述第一栅极结构207，所述第五导电层217在第一方向X上的中轴线与第二导电层214在第一方向X上的中轴线重合。
由于所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合。从而使得形成的平行于第一方向Y的第一导电层213、第四导电层216、第二导电层214和第三导电层215时，在既定的导电层设计规则下，所述第一导电层213、第四导电层216、第二导电层214或第三导电层215可与第一金属层201、第二金属层202、第三金属层203、第四金属层204、第五金属层205、第一栅极结构207或第二栅极结构208电连接的位置增加，从而能够利用较小面积的半导体结构单元区形成复杂的电路，从而节 省了面积，增加后段布线的灵活性，提高了集成度。
请继续参考图4，还包括：在第二介质层上形成与第一有源区A1上的第五金属层205电连接的电源电压线218；在第二介质层上形成与第二有源区A2上的第五金属层205电连接的接地电压线219，所述电源电压线218和接地电压线219平行于第一方向X。
在本实施例中，还包括：在第二介质层上形成第三介质层(未图示)，所述第一导电层213、第四导电层216、第二导电层214、第三导电层215、第五导电层217、电源电压线218和接地电压线219位于第三介质层内。
请参考图5，在第三介质层上形成平行于第二方向Y的电输出层220，所述电输出层220电连接所述第一导电层213和第二导电层214。
相应地，本发明实施例还提供一种半导体结构，请继续参考图5，图5的结构在图2的结构的基础上还包括：
平行于第一方向X的第一连接层211，所述第一连接层211电连接第一有源区A1上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203；
平行于第一方向X的第二连接层212，所述第二连接层212电连接第二有源区A2上的第二金属层202和第五金属层205；
平行于第一方向X的第一导电层213，所述第一导电层213横跨所述第一有源区A1和第三有源区A3，所述第一导电层213电连接第一有源区A1上的第一金属层201和第三有源区A3上的第四金属层204；
平行于第一方向X的第二导电层214，所述第二导电层214电连接所述第四有源区A4上的第三金属层203，所述第二导电层214位于第四有源区A4上；
平行于第一方向X的第三导电层215，所述第三导电层215横跨所述第二有源区A2和第四有源区A4，所述第三导电层215电连接 第二有源区A2上的第一金属层201和第四有源区A4上的第四金属层204；
平行于第二方向Y的电输出层220，所述电输出层220电连接所述第一导电层213和第二导电层214；
平行于第一方向X的第四导电层216，所述第四导电层216电连接所述第二栅极结构208，所述第四导电层216横跨所述第一有源区A1和第二隔离区B1；
所述第一导电层213、第四导电层216、第二导电层214和第三导电层215依次等间距平行排列；
平行于第一方向X的第五导电层217，所述第五导电层217位于第一隔离区B1上，所述第五导电层217电连接所述第一栅极结构207，所述第五导电层217在第一方向X上的中轴线与第二导电层214在第一方向X上的中轴线重合；
与第一有源区A1上的第五金属层205电连接的电源电压线218；在第二介质层上形成与第二有源区A2上的第五金属层205电连接的接地电压线219，所述电源电压线218和接地电压线219平行于第一方向X。
图6至图8为本发明另一实施例中半导体结构形成过程的示意图。
请参考图6，图6为在图2基础上的结构示意图，多个单元区中包括第一单元区和第二单元区，所述第一单元区和第二单元区单元沿第一方向X排列，所述第一单元区的第二区II与第二单元区的第一区I相邻接；所述第二单元区的第一有源区A1和第一单元区的第三有源区A3相邻，所述第二单元区的第二有源区A2和第一单元区第四有源区A4相邻。
请继续参考图6，在第一介质层上形成平行于第一方向X的第一连接层311，所述第一连接层311电连接第一单元区的第一有源区A1 上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203；在第一介质层上形成平行于第一方向X的第二连接层312，所述第二连接层312电连接第一单元区的第二有源区A2上的第二金属层202和第五金属层205；在第一介质层上形成平行于第一方向X的第三连接层313，所述第三连接层313在第一方向X上的中轴线与第一连接层311在第一方向X上的中轴线重合，所述第三连接层313电连接第二单元区的第一有源区A1上的第二金属层202和第五金属层205；在第一介质层上形成平行于第一方向X的第四连接层314，所述第四连接层314在第一方向X上的中轴线与第二连接层312在第一方向X上的中轴线重合，所述第四连接层314电连接第二单元区的第二有源区A2上的第二金属层202和第五金属层205。
所述第一连接层311、第二连接层312、第三连接层313和第四连接层314同时形成。
所述第一连接层311用于使第一有源区A1上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203处于同一电压水平；所述第二连接层312用于使第一单元区的第二有源区A2上的第二金属层202和第五金属层205处于同一电压水平；所述第三连接层313用于使第二单元区的第一有源区A1上的第二金属层202和第五金属层205处于同一电压水平；所述第四连接层314用于使第二单元区的第二有源区A2上的第二金属层202和第五金属层205处于同一电压水平。
在本实施例中，还包括：在第一介质层上形成第二介质层(未图示)，所述第一连接层311、第二连接层312、第三连接层313和第四连接层314位于所述第二介质层内。
请参考图7，在第二介质层上形成位于第一单元区上的第一导电层315，所述第一导电层315平行于第一方向X，所述第一导电层315横跨所述第一单元区的第一有源区A1和第三有源区A3，所述第一导电层315电连接第一单元区的第一有源区A1上的第一金属层201 和第三有源区A3上的第四金属层204。
在第二介质层上形成位于第一单元区的第四有源区A4上和第二单元区的第一隔离区B1上的第二导电层316，所述第二导电层316平行于第一方向X，所述第二导电层316电连接所述第一单元区的第四有源区A4上的第四金属层204和第二单元区的第一栅极结构207。
在第二介质层上形成位于第一单元区上的第三导电层317，所述第三导电层317平行于第一方向X，所述第三导电层317横跨所述第一单元区的第二有源区A2和第四有源区A4，所述第三导电层317电连接第一单元区的第二有源区A2上的第一金属层201和第四有源区A4上的第三金属层203。
在第二介质层上形成位于第一单元区上的第四导电层318，所述第四导电层318平行于第一方向X，所述第四导电层318电连接所述第一单元区的第二栅极结构208，所述第四导电层318横跨所述第一单元区的第一有源区A1和第二隔离区B2。
在第二介质层上形成位于第一单元区上的第五导电层319，所述第五导电层319平行于第一方向X，所述第五导电层319位于第一隔离区B1上，所述第五导电层319电连接所述第一单元区的第一栅极结构207，所述第五导电层319在第一方向X上的中轴线与第二导电层316在第一方向X上的中轴线重合。
在本实施例中，所述第一导电层315、第四导电层318、第二导电层316和第三导电层317依次等间距平行排列。
由于所述第一单元区的所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合，所述第二单元区的所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合。从而在形成平行于第一方向X的所述第一导电层315、第四导电层318、第二导电层316和第三导电层317时，在既定的导电层设计规则下，所述导电层可与第一金属层201、第二金属层202、第三金属层203、第四金属层204、第一栅 极结构207或第二栅极结构208电连接的位置增加，从而能够利用两个较小面积的半导体结构单元区形成复杂的电路，从而节省了面积，增加后段布线的灵活性，提高了集成度。
请继续参考图7，还包括：在第二介质层上形成位于第二单元区的第一有源区A1上的第六导电层320，所述第六导电层320平行于第一方向X，所述第六导电层320电连接第二单元区的第一有源区A1上的第一金属层201。
在第二介质层上形成位于第二单元区的第三有源区A3上的第七导电层321，所述第七导电层321平行于第一方向X，所述第七导电层电321连接所述第二单元区的第三有源区A3上的第三金属层203和第四金属层204。
在第二介质层上形成位于第二单元区的第二有源区A2上的第八导电层322，所述第八导电层322平行于第一方向X，所述第八导电层322电连接第二单元区的第二有源区A2上的第一金属层201。
在第二介质层上形成位于第二单元区的第四有源区A4上的第九导电层323，所述第九导电层323平行于第一方向X，所述第九导电层323电连接所述第二单元区的第四有源区A4上第三金属层203和第四金属层204。
在本实施例中，所述第一导电层315、第六导电层320和第七导电层321第一方向X上的中轴线重合；所述第三导电层317、第八导电层322和第九导电层323第一方向上的中轴线重合。
所述第一导电层315、第四导电层318、第二导电层316、第三导电层317、第五导电层319、第六导电层320、第七导电层321、第八导电层322和第九导电层323同时形成。在本实施例中，还包括，在第二介质层上形成第三介质层(未图示)，所述第一导电层315、第四导电层318、第二导电层316、第三导电层317、第五导电层319、第六导电层320、第七导电层321、第八导电层322和第九导电层323位于第三介质层内。
请继续参考图7，还包括：在第三介质层内形成与第一单元区第一有源区A1上的第五金属层205以及第二单元区第一有源区A1上的第五金属层205电连接的电源电压线324；在第三介质层内形成与第一单元区第二有源区A2上的第五金属层205以及第二单元区第二有源区A2上的第五金属层205电连接的接地电压线325，所述电源电压线324和接地电压线325平行于第一方向。
请参考图8，还包括：在第三介质层上形成平行于第二方向Y的第一电输出层326，所述第一电输出层326电连接所述第一单元区上的第一导电层315和第二导电层316；在第三介质层上形成平行于第二方向Y的第二电输出层327，所述第二电输出层327电连接所述第二单元区上的第六导电层320和第八导电层322。
相应地，本发明实施例还提供一种半导体结构，请继续参考图8，图8的结构在图2的结构的基础上还包括：
在本实施例中，多个单元区中包括第一单元区和第二单元区，所述第一单元区和第二单元区单元沿第一方向X排列，所述第一单元区的第二区II与第二单元区的第一区I相邻接；所述第二单元区的第一有源区A1和第一单元区的第三有源区A3相邻，所述第二单元区的第二有源区A2和第一单元区第四有源区A4相邻。
在本实施例中，还包括：平行于第一方向X的第一连接层311，所述第一连接层311电连接第一单元区的第一有源区A1上和第三有源区A3上的第二金属层202、第五金属层205和第三金属层203；平行于第一方向X的第二连接层312，所述第二连接层312电连接第一单元区的第二有源区A2上的第二金属层202和第五金属层205；平行于第一方向X的第三连接层313，所述第三连接层313在第一方向X上的中轴线与第一连接层311在第一方向X上的中轴线重合，所述第三连接层313电连接第二单元区的第一有源区A1上的第二金属层202和第五金属层205；平行于第一方向X的第四连接层314，所述第四连接层314在第一方向X上的中轴线与第二连接层312在第一方向X上的中轴线重合，所述第四连接层314电连接第二单元 区的第二有源区A2上的第二金属层202和第五金属层205。
在本实施例中，还包括：位于第一单元区上的第一导电层315，所述第一导电层315平行于第一方向X，所述第一导电层315横跨所述第一单元区的第一有源区A1和第三有源区A3，所述第一导电层315电连接第一单元区的第一有源区A1上的第一金属层201和第三有源区A3上的第四金属层204；位于第一单元区的第四有源区A4上和第二单元区的第一隔离区B1上的第二导电层316，所述第二导电层316平行于第一方向X，所述第二导电层316电连接所述第一单元区的第四有源区A4上的第四金属层204和第二单元区的第一栅极结构207；位于第一单元区上的第三导电层317，所述第三导电层317平行于第一方向X，所述第三导电层317横跨所述第一单元区的第二有源区A2和第四有源区A4，所述第三导电层317电连接第一单元区的第二有源区A2上的第一金属层201和第四有源区A4上的第三金属层203；位于第一单元区上的第四导电层318，所述第四导电层318平行于第一方向X，所述第四导电层318电连接所述第一单元区的第二栅极结构208，所述第四导电层318横跨所述第一单元区的第一有源区A1和第二隔离区B2；位于第一单元区上的第五导电层319，所述第五导电层319平行于第一方向X，所述第五导电层319位于第一隔离区B1上，所述第五导电层319电连接所述第一单元区的第一栅极结构207，所述第五导电层319在第一方向X上的中轴线与第二导电层316在第一方向X上的中轴线重合。
在本实施例中，所述第一导电层315、第四导电层318、第二导电层316和第三导电层317依次等间距平行排列。
在本实施例中，还包括：位于第二单元区的第一有源区A1上的第六导电层320，所述第六导电层320平行于第一方向X，所述第六导电层320电连接第二单元区的第一有源区A1上的第一金属层201；位于第二单元区的第三有源区A3上的第七导电层321，所述第七导电层321平行于第一方向X，所述第七导电层电321连接所述第二单元区的第三有源区A3上的第三金属层203和第四金属层204；位于 第二单元区的第二有源区A2上的第八导电层322，所述第八导电层322平行于第一方向X，所述第八导电层322电连接第二单元区的第二有源区A2上的第一金属层201；位于第二单元区的第四有源区A4上的第九导电层323，所述第九导电层323平行于第一方向X，所述第九导电层323电连接所述第二单元区的第四有源区A4上第三金属层203和第四金属层204。
在本实施例中，所述第一导电层315、第六导电层320和第七导电层321第一方向X上的中轴线重合；所述第三导电层317、第八导电层322和第九导电层323第一方向上的中轴线重合。
在本实施例中，还包括：与第一单元区第一有源区A1上的第五金属层205以及第二单元区第一有源区A1上的第五金属层205电连接的电源电压线324；与第一单元区第二有源区A2上的第五金属层205以及第二单元区第二有源区A2上的第五金属层205电连接的接地电压线325，所述电源电压线324和接地电压线325平行于第一方向。
在本实施例中，还包括：平行于第二方向Y的第一电输出层326，所述第一电输出层326电连接所述第一单元区上的第一导电层315和第二导电层316；平行于第二方向Y的第二电输出层327，所述第二电输出层327电连接所述第二单元区上的第六导电层320和第八导电层322。
图9为本发明另一实施例中半导体结构的示意图。
请参考图9，图9为在图2基础上的结构示意图，多个单元区中包括第一单元区、第二单元区、第三单元区和第四单元区。
所述第一单元区和第二单元区沿平行于衬底200表面的第一方向X排列，所述第一单元区的第二区II与第二单元区的第一区I相邻接；所述第三单元区和第四单元区沿平行于衬底200表面的第一方向X排列，所述第三单元区的第二区II与第四单元区的第一区I相邻接；所述第一单元区和第四单元区沿平行于衬底表面的第二方向Y 排列，所述第一单元区的第一区I与第四单元区的第二区II相邻接，所述第一单元区的第二区II与第四单元区的第一区I相邻接；所述第二单元区和第三单元区沿平行于衬底200表面的第二方向Y排列，所述第二单元区的第二区II与第三单元区的第一区I相邻接，所述第二单元区的第一区I与第三单元区的第二区II相邻接。
由于所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合。从而使得后续形成平行于第一方向X的导电层时，在既定的导电层设计规则下，所述导电层可与第一金属层201、第二金属层202、第三金属层203、第四金属层204、第一栅极结构207或第二栅极结构208电连接的位置增加，从而能够利用较小面积的四个或若干个半导体结构单元区形成复杂的电路，从而节省了面积，增加后段布线的灵活性，提高了集成度。
图10至图12为本发明另一实施例中半导体结构形成过程的示意图。
请参考图10，图10为在图2基础上的结构示意图，在第一介质层上形成平行于第一方向X的第一连接层511，所述第一连接层511电连接第一有源区A1上的第二金属层202和第五金属层205；在第一介质层上形成平行于第一方向X的第二连接层512，所述第二连接层512电连接第二有源区A2上的第二金属层202和第五金属层205。
在本实施例中，还包括：在第一介质层上形成第二介质层(未图示)，所述第一连接层511和第二连接层512位于所述第二介质层内。
所述第一连接层511用于使所述第一有源区A1上的第二金属层202和第五金属层205位于同一电压水平；所述第二连接层512用于使第二有源区A2上的第二金属层202和第五金属层205位于同一电压水平。
请参考图11，在第二介质层上形成平行于第一方向X的第一导电层513，所述第一导电层513与第一有源区A1上的第一金属层201电连接；在第二介质层上形成平行于第一方向X的第二导电层514， 所述第二导电层514与第一栅极结构207电连接，所述第二导电层514横跨所述第一有源区A1和第二隔离区B2；在第二介质层上形成平行于第一方向X的第三导电层515，所述第三导电层515与第二有源区A2上的第一金属层201电连接。
由于所述第一区I包括第一隔离区B1，所述第二区II包括第二隔离区B2，所述第一隔离区B1在第一方向X上的中轴线与第二隔离区B2在第一方向X上的中轴线不重合。从而所述第二导电层514能够在第一有源区A1上形成与第一栅极结构207电连接的有源栅接触，从而能够节省面积，增加布线的灵活性。
请继续参考图11，还包括：在第二介质层上形成平行于第一方向X的第四导电层516，所述第四导电层516电连接所述第三有源区A3上的第三金属层203和第四金属层204，所述第四导电层516在第一方向X上的中轴线与第一导电层513在第一方向X上的中轴线重合；在第二介质层上形成平行于第一方向X的第五导电层517，所述第五导电层517电连接所述第四有源区A4上的第三金属层203和第四金属层204，所述第五导电层517在第一方向X上的中轴线与第三导电层515在第一方向X上的中轴线重合；在第二介质层上形成平行于第一方向X的第六导电层518，所述第六导电层518横跨所述第一隔离区B1和第四有源区A4。
所述第四导电层516电连接所述第三有源区A3上的第三金属层203和第四金属层204，用于使所述第三有源区A3上的第二栅极结构208失效；所述第五导电层517电连接所述第四有源区A4上的第三金属层203和第四金属层204，用于使所述第四有源区A4上的第二栅极结构208失效。
在本实施例中，所述第一导电层513、第二导电层514、第六导电层518和第三导电层515依次等间距平行排列。
请继续参考图11，还包括：在第二介质层上形成平行于第一方向X的电源电压线519，所述电源电压线519与第一有源区A1上的第五金属层205电连接；在第二介质层上形成平行于第一方向X的 接地电压线520，所述接地电压线520与第二有源区A2上的第五金属层205电连接。
在本实施例中，还包括：在第二介质层上形成第三介质层(未图示)，所述第一导电层513、第二导电层514、第六导电层518、第三导电层515、第四导电层516、第五导电层517、电源电压线519和接地电压线520位于所述第三介质层内。
请参考图12，在第三介质层上形成平行于第二方向Y的电输出层521，所述电输出层521电连接所述第一导电层513和第三导电层515。
相应地，本发明实施例还提供一种半导体结构，请继续参考图12，图12的结构在图2的结构的基础上还包括：
平行于第一方向X的第一连接层511，所述第一连接层511电连接第一有源区A1上的第二金属层202和第五金属层205；
平行于第一方向X的第二连接层512，所述第二连接层512电连接第二有源区A2上的第二金属层202和第五金属层205；
平行于第一方向X的第一导电层513，所述第一导电层513与第一有源区A1上的第一金属层201电连接；
平行于第一方向X的第二导电层514，所述第二导电层514与第一栅极结构207电连接，所述第二导电层514横跨所述第一有源区A1和第二隔离区B2；
平行于第一方向X的第三导电层515，所述第三导电层515与第二有源区A2上的第一金属层201电连接；
平行于第一方向X的第四导电层516，所述第四导电层516电连接所述第三有源区A3上的第三金属层203和第四金属层204，所述第四导电层516在第一方向X上的中轴线与第一导电层513在第一方向X上的中轴线重合；
平行于第一方向X的第五导电层517，所述第五导电层517电连接所述第四有源区A4上的第三金属层203和第四金属层204，所述 第五导电层517在第一方向X上的中轴线与第三导电层515在第一方向X上的中轴线重合；
平行于第一方向X的第六导电层518，所述第六导电层518横跨所述第一隔离区B1和第四有源区A4；
平行于第一方向X的电源电压线519，所述电源电压线519与第一有源区A1上的第五金属层205电连接；
平行于第一方向X的接地电压线520，所述接地电压线520与第二有源区A2上的第五金属层205电连接；
平行于第二方向Y的电输出层521，所述电输出层521电连接所述第一导电层513和第三导电层515。

Claims (23)

  1. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底包括至少一个单元区，所述单元区包括相邻的第一区和第二区，所述第一区和第二区沿第一方向排布，所述第一区包括沿第二方向排列的第一有源区、第一隔离区和第二有源区，所述第一有源区和第二有源区位于第一隔离区两侧，所述第二区包括沿第二方向排列的第三有源区、第二隔离区和第四有源区，所述第三有源区和第四有源区位于第二隔离区两侧，所述第一隔离区平行于第一方向的中轴线与第二隔离区平行于第一方向的中轴线不重合，所述第一方向和第二方向平行于衬底表面，且所述第一方向和第二方向相互垂直；
    位于第一区上的第一栅极结构，所述第一栅极结构横跨所述第一有源区、第一隔离区和第二有源区，以及分别位于所述第一栅极结构两侧的第一金属层和第二金属层，所述第一栅极结构、第一金属层和第二金属层平行于第二方向；
    位于第二区上的第二栅极结构，所述第二栅极结构横跨所述第三有源区、第二隔离区和第四有源区，以及分别位于第二栅极结构两侧的第三金属层和第四金属层，所述第二栅极结构、第三金属层和第四金属层平行于第二方向；
    位于第一隔离区上的第一隔离结构，所述第一隔离结构沿第一方向贯穿所述第一金属层和第二金属层，所述第一栅极结构位于第一隔离结构上；
    位于第二隔离区上的第二隔离结构，所述第二隔离结构沿第一方向贯穿所述第三金属层和第四金属层，所述第二栅极结构位于第二隔离结构上。
  2. 如权利要求1所述的半导体结构，其特征在于，所述第一隔离区与所述第一有源区和第二有源区相邻；所述第二隔离区与所述第三有源区和第四有源区相邻。
  3. 如权利要求2所述的半导体结构，其特征在于，所述第一有源区 上的器件导电类型与第二有源区上的器件导电类型相反，所述第三有源区上的器件导电类型与第四有源区上的器件导电类型相反。
  4. 如权利要求3所述的半导体结构，其特征在于，所述第一有源区和第三有源区相邻，所述第二有源区和第四有源区相邻；所述第一有源区上的器件导电类型和第三有源区上的器件导电类型相同，所述器件导电类型为N型；所述第二有源区上的器件导电类型和第四有源区上的器件导电类型相同，所述器件导电类型为P型。
  5. 如权利要求2所述的半导体结构，其特征在于，还包括：位于第一区上的第五金属层，所述第五金属层位于第二金属层和第三金属层之间，所述第五金属层平行于第二方向，所述第一隔离结构还沿第一方向贯穿所述第五金属层。
  6. 如权利要求5所述的半导体结构，其特征在于，还包括：位于衬底上的若干伪栅极结构，若干所述伪栅极结构平行排列，所述伪栅极结构平行于第二方向；所述第一金属层位于伪栅极结构和第一栅极结构之间，所述第二金属层位于伪栅极结构和第一栅极结构之间，所述第三金属层位于伪栅极结构和第二栅极结构之间，所述第四金属层位于伪栅极结构和第二栅极结构之间，所述第五金属层位于相邻的伪栅极结构之间。
  7. 如权利要求6所述的半导体结构，其特征在于，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一有源区上和第三有源区上的第二金属层、第五金属层和第三金属层；平行于第一方向的第二连接层，所述第二连接层电连接第二有源区上的第二金属层和第五金属层；平行于第一方向的第一导电层，所述第一导电层横跨所述第一有源区和第三有源区，所述第一导电层电连接第一有源区上的第一金属层和第三有源区上的第四金属层；平行于第一方向的第二导电层，所述第二导电层电连接所述第四有源区上的第三金属层，所述第二导电层位于第四有源区上； 平行于第一方向的第三导电层，所述第三导电层横跨所述第二有源区和第四有源区，所述第三导电层电连接第二有源区上的第一金属层和第四有源区上的第四金属层；平行于第二方向的电输出层，所述电输出层电连接所述第一导电层和第二导电层。
  8. 如权利要求7所述的半导体结构，其特征在于，还包括：平行于第一方向的第四导电层，所述第四导电层电连接所述第二栅极结构，所述第四导电层横跨所述第一有源区和第二隔离区。
  9. 如权利要求8所述的半导体结构，其特征在于，所述第一导电层、第四导电层、第二导电层和第三导电层依次等间距平行排列。
  10. 如权利要求8所述的半导体结构，其特征在于，还包括：平行于第一方向的第五导电层，所述第五导电层位于第一隔离区上，所述第五导电层电连接所述第一栅极结构，所述第五导电层在第一方向上的中轴线与第二导电层在第一方向上的中轴线重合。
  11. 如权利要求7所述的半导体结构，其特征在于，还包括：与第一有源区上的第五金属层电连接的电源电压线；与第二有源区上的第五金属层电连接的接地电压线，所述电源电压线和接地电压线平行于第一方向。
  12. 如权利要求6所述的半导体结构，其特征在于，多个单元区中包括第一单元区和第二单元区，所述第一单元区和第二单元区单元沿第一方向排列，所述第一单元区的第二区与第二单元区的第一区相邻接；所述第二单元区的第一有源区和第一单元区的第三有源区相邻，所述第二单元区的第二有源区和第一单元区第四有源区相邻。
  13. 如权利要求12所述的半导体结构，其特征在于，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一单元区的第一有源区上和第三有源区上的第二金属层、第五金属层和第三金属层；平行于第一方向的第二连接层，所述第二连接层电连接第一单元区的第二有源区上的第二金属层和第五金属层；平行于第一方向的第三连接层，所述第三连接层在第一方向上的中轴线与 第一连接层在第一方向上的中轴线重合，所述第三连接层电连接第二单元区的第一有源区上的第二金属层和第五金属层；平行于第一方向的第四连接层，所述第四连接层在第一方向上的中轴线与第二连接层在第一方向上的中轴线重合，所述第四连接层电连接第二单元区的第二有源区上的第二金属层和第五金属层。
  14. 如权利要求13所述的半导体结构，其特征在于，还包括：位于第一单元区上的第一导电层，所述第一导电层平行于第一方向，所述第一导电层横跨所述第一单元区的第一有源区和第三有源区，所述第一导电层电连接第一单元区的第一有源区上的第一金属层和第三有源区上的第四金属层；位于第一单元区的第四有源区上和第二单元区的第一隔离区上的第二导电层，所述第二导电层平行于第一方向，所述第二导电层电连接所述第一单元区的第四有源区上的第四金属层和第二单元区的第一栅极结构；位于第一单元区上的第三导电层，所述第三导电层平行于第一方向，所述第三导电层横跨所述第一单元区的第二有源区和第四有源区，所述第三导电层电连接第一单元区的第二有源区上的第一金属层和第四有源区上的第三金属层；位于第一单元区上的第四导电层，所述第四导电层平行于第一方向，所述第四导电层电连接所述第一单元区的第二栅极结构，所述第四导电层横跨所述第一单元区的第一有源区和第二隔离区；位于第一单元区上的第五导电层，所述第五导电层平行于第一方向，所述第五导电层位于第一隔离区上，所述第五导电层电连接所述第一单元区的第一栅极结构，所述第五导电层在第一方向上的中轴线与第二导电层在第一方向上的中轴线重合。
  15. 如权利要求14所述的半导体结构，其特征在于，所述第一导电层、第四导电层、第二导电层和第三导电层依次等间距平行排列。
  16. 如权利要求14所述的半导体结构，其特征在于，还包括：位于第二单元区的第一有源区上的第六导电层，所述第六导电层平行于第一方向，所述第六导电层电连接第二单元区的第一有源区上的 第一金属层；位于第二单元区的第三有源区上的第七导电层，所述第七导电层平行于第一方向，所述第七导电层电连接所述第二单元区的第三有源区上的第三金属层和第四金属层；位于第二单元区的第二有源区上的第八导电层，所述第八导电层平行于第一方向，所述第八导电层电连接第二单元区的第二有源区上的第一金属层；位于第二单元区的第四有源区上的第九导电层，所述第九导电层平行于第一方向，所述第九导电层电连接所述第二单元区的第四有源区上第三金属层和第四金属层；所述第一导电层、第六导电层和第七导电层第一方向上的中轴线重合；所述第三导电层、第八导电层和第九导电层第一方向上的中轴线重合。
  17. 如权利要求16所述的半导体结构，其特征在于，还包括：平行于第二方向的第一电输出层，所述第一电输出层电连接所述第一单元区上的第一导电层和第二导电层；平行于第二方向的第二电输出层，所述第二电输出层电连接所述第二单元区上的第六导电层和第八导电层。
  18. 如权利要求17所述的半导体结构，其特征在于，还包括：与第一单元区第一有源区上的第五金属层以及第二单元区第一有源区上的第五金属层电连接的电源电压线；与第一单元区第二有源区上的第五金属层以及第二单元区第二有源区上的第五金属层电连接的接地电压线，所述电源电压线和接地电压线平行于第一方向。
  19. 如权利要求6所述的半导体结构，其特征在于，多个单元区中包括第一单元区、第二单元区、第三单元区和第四单元区；所述第一单元区和第二单元区沿平行于衬底表面的第一方向排列，所述第一单元区的第二区与第二单元区的第一区相邻接；所述第三单元区和第四单元区沿平行于衬底表面的第一方向排列，所述第三单元区的第二区与第四单元区的第一区相邻接；所述第一单元区和第四单元区沿平行于衬底表面的第二方向排列，所述第一单元区的第一区与第四单元区的第二区相邻接，所述第一单元区的第二区与第四单元区的第一区相邻接；所述第二单元区和第三单元 区沿平行于衬底表面的第二方向排列，所述第二单元区的第二区与第三单元区的第一区相邻接，所述第二单元区的第一区与第三单元区的第二区相邻接。
  20. 如权利要求6所述的半导体结构，其特征在于，还包括：平行于第一方向的第一连接层，所述第一连接层电连接第一有源区上的第二金属层和第五金属层；平行于第一方向的第二连接层，所述第二连接层电连接第二有源区上的第二金属层和第五金属层；平行于第一方向的第一导电层，所述第一导电层与第一有源区上的第一金属层电连接；平行于第一方向的第二导电层，所述第二导电层与第一栅极结构电连接，所述第二导电层横跨所述第一有源区和第二隔离区；平行于第一方向的第三导电层，所述第三导电层与第二有源区上的第一金属层电连接；平行于第二方向的电输出层，所述电输出层电连接所述第一导电层和第三导电层。
  21. 如权利要求20所述的半导体结构，其特征在于，还包括：平行于第一方向的第四导电层，所述第四导电层电连接所述第三有源区上的第三金属层和第四金属层，所述第四导电层在第一方向上的中轴线与第一导电层在第一方向上的中轴线重合；平行于第一方向的第五导电层，所述第五导电层电连接所述第四有源区上的第三金属层和第四金属层，所述第五导电层在第一方向上的中轴线与第三导电层在第一方向上的中轴线重合。
  22. 如权利要求21所述的半导体结构，其特征在于，还包括：平行于第一方向的第六导电层，所述第六导电层横跨所述第一隔离区和第四有源区；所述第一导电层、第二导电层、第六导电层和第三导电层依次等间距平行排列；平行于第一方向的电源电压线，所述电源电压线与第一有源区上的第五金属层电连接；平行于第一方向的接地电压线，所述接地电压线与第二有源区上的第五金属层电连接。
  23. 一种半导体结构的形成方法，其特征在于，包括：
    提供衬底，所述衬底包括至少一个单元区，所述单元区包括相邻 的第一区和第二区，所述第一区和第二区沿第一方向排布，所述第一区包括沿第二方向排列的第一有源区、第一隔离区和第二有源区，所述第一有源区和第二有源区位于第一隔离区两侧，所述第二区包括沿第二方向排列的第三有源区、第二隔离区和第四有源区，所述第三有源区和第四有源区位于第二隔离区两侧，所述第一隔离区平行于第一方向的中轴线与第二隔离区平行于第一方向的中轴线不重合，所述第一方向和第二方向平行于衬底表面，且所述第一方向和第二方向相互垂直；
    在第一区上形成第一栅极结构，所述第一栅极结构横跨所述第一有源区、第一隔离区和第二有源区，以及形成分别位于第一栅极结构两侧的第一金属层和第二金属层，所述第一栅极结构、第一金属层和第二金属层平行于第二方向；
    在第二区上形成第二栅极结构，所述第二栅极结构横跨所述第三有源区、第二隔离区和第四有源区，以及形成分别位于第二栅极结构两侧的第三金属层和第四金属层，所述第二栅极结构、第三金属层和第四金属层平行于第二方向；
    在第一隔离区上形成第一隔离结构，所述第一隔离结构沿第一方向贯穿所述第一金属层和第二金属层，所述第一栅极结构位于第一隔离结构上；
    在第二隔离区上形成第二隔离结构，所述第二隔离结构沿第一方向贯穿所述第三金属层和第四金属层，所述第二栅极结构位于第二隔离结构上。
PCT/CN2021/114493 2021-08-25 2021-08-25 半导体结构及半导体结构的形成方法 Ceased WO2023023972A1 (zh)

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CN106610562A (zh) * 2015-10-26 2017-05-03 中芯国际集成电路制造(上海)有限公司 掩膜版版图以及形成半导体结构的方法
CN107731921A (zh) * 2016-08-11 2018-02-23 三星电子株式会社 包含接触结构的半导体装置
CN113140566A (zh) * 2021-05-08 2021-07-20 英诺赛科（珠海）科技有限公司 具有隔离结构的集成式芯片及其制作方法

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CN106610562A (zh) * 2015-10-26 2017-05-03 中芯国际集成电路制造(上海)有限公司 掩膜版版图以及形成半导体结构的方法
CN107731921A (zh) * 2016-08-11 2018-02-23 三星电子株式会社 包含接触结构的半导体装置
CN113140566A (zh) * 2021-05-08 2021-07-20 英诺赛科（珠海）科技有限公司 具有隔离结构的集成式芯片及其制作方法

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