WO2023023950A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023023950A1
WO2023023950A1 PCT/CN2021/114352 CN2021114352W WO2023023950A1 WO 2023023950 A1 WO2023023950 A1 WO 2023023950A1 CN 2021114352 W CN2021114352 W CN 2021114352W WO 2023023950 A1 WO2023023950 A1 WO 2023023950A1
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Prior art keywords
layer
channel
work function
forming
gate
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French (fr)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to PCT/CN2021/114352 priority Critical patent/WO2023023950A1/zh
Priority to US18/684,575 priority patent/US20250374662A1/en
Priority to CN202180099973.3A priority patent/CN117581381A/zh
Publication of WO2023023950A1 publication Critical patent/WO2023023950A1/zh
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/832—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
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    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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    • H10D84/83135—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different gate conductor materials or different gate conductor implants
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/851—Complementary IGFETs, e.g. CMOS comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels

Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • the semiconductor process has gradually begun to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as Gate-all-around (GAA) transistors.
  • GAA Gate-all-around
  • the gate surrounds the area where the channel is located.
  • the gate of a fully surrounded gate transistor has a stronger ability to control the channel and can better suppress the short channel effect. .
  • the problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to reduce the leakage current of the device.
  • an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate-surrounding transistor located on the substrate, and the gate-surrounding transistor includes: a raised portion separated from the substrate and connected to the gate
  • the protrusions are spaced apart from the channel structure layer suspended in the air, the channel structure layer includes a plurality of channel layers arranged at intervals in sequence, the channel layers are vertically stacked along the direction perpendicular to the substrate surface, and vertically stacked along the vertical direction In the direction of the substrate surface, the distance between the raised portion and the channel layer adjacent to the raised portion is greater than the distance between the adjacent channel layers;
  • the gate structure spans The channel structure layer surrounds each of the channel layers in the channel structure layer;
  • the gate structure includes a work function layer surrounding the surface of the channel layer, and the work function layer is filled in the channel layer Between the raised portion and the channel layer adjacent to the raised portion, and between the adjacent channel layers; wherein, when forming an NMOS transistor, the material of the work function layer is
  • an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate for forming a MOS transistor, the substrate including a substrate, a raised portion separated from the substrate, and a raised portion located on the raised portion a plurality of stacked channel stacks on the portion, each of the channel stacks includes a sacrificial layer and a channel layer on the sacrificial layer; The sacrificial layer between the channel layers is used as a first sacrificial layer, the sacrificial layer in the channel stack above the first sacrificial layer is used as a second sacrificial layer, and the first sacrificial layer The thickness is greater than the thickness of the second sacrificial layer; a dummy gate structure across the channel stack is formed; source and drain doped regions are formed in the channel stack on both sides of the dummy gate structure, and the source The doped drain region is in contact with the end of each channel layer in the channel stack along the extension direction;
  • the work function layer surrounds the surface of the channel layer, and when an NMOS transistor is formed, the work function layer
  • the material is a P-type work function material, thereby increasing the threshold voltage of the NMOS device
  • the material of the work function layer is an N-type work function material, thereby increasing the threshold voltage of the PMOS device
  • the distance between the raised portion and the channel layer adjacent to the raised portion is greater than the distance between the adjacent channel layers, and accordingly, the The thickness of the work function layer between the protrusion and the channel layer adjacent to the protrusion is greater than the thickness of the work function layer filled between the adjacent channel layers.
  • the work function layer In the case where the material of the function layer is the same, the thicker the work function layer is, the more obvious the adjustment effect on the threshold voltage of the device is, and the work function between the protrusion and the channel layer adjacent to the protrusion
  • the layer is thicker than the work function layer located between the adjacent channel layers, so that the threshold voltage of the parasitic device corresponding to the protrusion is higher than that of the device corresponding to the channel layer, the The more difficult it is for the parasitic device to be turned on, it is beneficial to reduce the bottom leakage current generated in the raised portion and improve the performance of the semiconductor structure.
  • the thickness of the first sacrificial layer is greater than the thickness of the second sacrificial layer, and the first through groove is formed by removing the first sacrificial layer, and the second through groove is formed by removing the second sacrificial layer.
  • the height of the first through groove is correspondingly greater than the height of the second through groove; in the step of forming the gate structure, the work function layer surrounds the surface of the channel layer and fills the through groove , when forming an NMOS transistor, the material of the work function layer is a P-type work function material, thereby increasing the threshold voltage of the NMOS device; when forming a PMOS, the material of the work function layer is an N-type work function material, thereby increasing The threshold voltage of the PMOS device; and, because the height of the first through groove is greater than the height of the second through groove, correspondingly, the thickness of the work function layer filled in the first through groove is greater than the work function layer filled in the second through groove.
  • the work function layer in the second through groove is thicker, so that compared with the device corresponding to the channel layer, the threshold voltage of the parasitic device corresponding to the raised part is higher, and the parasitic device is less likely to be turned on, and then It is beneficial to reduce the bottom leakage current generated in the raised portion, and improves the performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure.
  • FIGS. 2 to 3 are structural schematic diagrams of an embodiment of the semiconductor structure of the present invention.
  • 4 to 16 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • FIG. 1 is a schematic diagram of a semiconductor structure.
  • the semiconductor structure includes: a base, including a substrate 1, a raised portion 2 separated on the substrate 1, and the raised portion 2
  • the channel structure layer 4 suspended at intervals, the channel structure layer 4 includes a plurality of channel layers 3 arranged at intervals in sequence; the gate structure 5 spans the channel structure layer 4 and surrounds the channel layer 3.
  • the gate dielectric layer 6 is located between the gate structure 5 and the channel layer 1, and between the gate structure 5 and the raised portion 2; the source-drain doped region 7 is located in the The protrusions 2 on both sides of the gate structure 5 are in contact with the ends of the channel structure layer 4 along the extending direction.
  • the semiconductor structure generally further includes an isolation layer 8 on the substrate 1 and surrounding the raised portion 2 .
  • one method is to implant dopant ions into the isolation layer 8 during the formation of the semiconductor structure, the doping type of the dopant ions is the same as that of the source-drain doped region 7 are of different doping types, and the dopant ions are diffused into the raised portion 2, so that the raised portion 2 is doped with dopant ions different from the doping type of the source-drain doped region 7 , so as to increase the difficulty of opening the channel in the raised portion 2, thereby reducing the leakage current in the raised portion 2.
  • ion implantation causes random dopant fluctuations (random dopant fluctuation); moreover, in the formation process of the semiconductor structure, before forming the gate structure, there are usually formed between adjacent channel layers 3 and between the channel layer 3 and the raised portion 2 Sacrificial layer, the sacrificial layer is used to occupy a space position for forming the gate structure, and when the dopant ions also diffuse into the sacrificial layer, it will also affect the removal of the sacrificial layer in subsequent process steps.
  • an embodiment of the present invention provides a semiconductor structure, the work function layer surrounds the surface of the channel layer, and when an NMOS transistor is formed, the material of the work function layer is a P-type work function material, thereby increasing the size of the NMOS transistor.
  • the threshold voltage of the device when forming PMOS, the material of the work function layer is an N-type work function material, thereby increasing the threshold voltage of the PMOS device; and, along the direction perpendicular to the substrate surface, the raised portion and The distance between the channel layers adjacent to the raised portion is greater than the distance between the adjacent channel layers, correspondingly, the The thickness of the work function layer between the channel layers is greater than the thickness of the work function layer filled between the adjacent channel layers.
  • the work function layer In the field of semiconductors, in the case of the same work function layer material, the work function layer is usually The thicker the function layer, the more obvious the adjustment effect on the threshold voltage of the device, and the work function layer between the raised part and the channel layer adjacent to the raised part is more than the adjacent channel layer.
  • the work function layer between the layers is thicker, so that the threshold voltage of the parasitic device corresponding to the raised portion is higher than that of the device corresponding to the channel layer, and the parasitic device is less likely to be turned on, which in turn facilitates The bottom leakage current generated in the raised portion is reduced, improving the performance of the semiconductor structure.
  • an embodiment of the present invention also provides a method for forming a semiconductor structure, the thickness of the first sacrificial layer is greater than the thickness of the second sacrificial layer, and the first through groove is formed after removing the first sacrificial layer 1.
  • the height of the first through groove is correspondingly greater than the height of the second through groove; in the step of forming the gate structure, the work function layer surrounds the channel layer Surface and filled in the through groove, when forming an NMOS transistor, the material of the work function layer is a P-type work function material, thereby increasing the threshold voltage of the NMOS device; when forming a PMOS, the material of the work function layer is N type work function material, thereby increasing the threshold voltage of the PMOS device; and, since the height of the first through groove is greater than the height of the second through groove, correspondingly, the thickness of the work function layer filled in the first through groove is greater than that of filling
  • the thickness of the work function layer in the second through slot in the field of semiconductors, in the case of the same work function layer material, usually the thicker the work function layer, the more obvious the adjustment effect on the threshold voltage of the device.
  • the work function layer in the groove is thicker than the work function layer in the second through groove, so that the threshold voltage of the parasitic device corresponding to the protrusion is higher than that of the device corresponding to the channel layer, the The more difficult it is for the parasitic device to be turned on, it is beneficial to reduce the bottom leakage current generated in the raised portion and improve the performance of the semiconductor structure.
  • FIG. 1 and FIG. 2 a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
  • 2 is a cross-sectional view at the position of the gate structure along a direction perpendicular to the extension of the channel layer
  • FIG. 3 is a cross-sectional view along the direction A-A1 of FIG. 2 .
  • the semiconductor structure includes: a substrate 100 ;
  • the direction of the surface of the substrate 100 is stacked vertically, and along the direction perpendicular to the surface of the substrate 100, the distance between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is greater than that of the adjacent channel layer 40.
  • the substrate 100 , the raised portion 110 separated on the substrate 100 , and the channel structure layer 200 spaced apart from the raised portion 110 constitute the base 10 .
  • the substrate 100 is used to provide a process operation platform for the formation of semiconductor structures.
  • the substrate 100 is used to provide a process platform for forming a gate all around (GAA) transistor (ie, the gate around transistor).
  • GAA gate all around
  • the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon.
  • the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium, and the substrate can also be silicon-on-insulator Substrates or other types of substrates such as germanium-on-insulator substrates.
  • the protruding portion 110 and the substrate 100 are of an integrated structure, and the material of the protruding portion 110 and the substrate 100 is the same, both being silicon.
  • the material of the raised portion may be different from that of the substrate, and the material of the raised portion may be other suitable materials, such as germanium, silicon germanium, silicon carbide, gallium nitride, One or more of gallium arsenide and gallium indium.
  • the semiconductor structure further includes: an isolation layer 115 located on the substrate 100 and surrounding the protrusion 110 .
  • the isolation layer 115 exposes the channel structure layer 200 .
  • the isolation layer 115 is used for isolating adjacent protrusions 110 , and is also used for isolating the substrate 100 and the gate structure 230 .
  • the material of the isolation layer 115 is silicon oxide.
  • the material of the isolation layer 115 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium oxide.
  • the top surface of the isolation layer 115 is lower than the top surface of the protrusion 110 .
  • the top surface of the isolation layer may also be flush with the top surface of the protrusion.
  • the channel structure layer 200 is used to provide a conduction channel of a field effect transistor.
  • the channel layer 40 provides a conduction channel of a field effect transistor.
  • the stacking direction of the channel layer 40 is perpendicular to the surface of the substrate 100 .
  • the material of the channel layer 40 is the same as that of the protruding portion 110 . More specifically, the material of the channel layer 40 is Si, which is beneficial to improve the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology may be used, and the material of the channel layer is SiGe.
  • the material of the channel layer 40 is the same as that of the protruding portion 110 . In other embodiments, the material of the channel layer and the protrusion part may also be different.
  • the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.
  • the number of the channel layers 40 is three. In other embodiments, there may be other numbers of channel layers, for example: two, four, five, and so on.
  • the distance between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is greater than the distance between adjacent channel layers 40 , so that the thickness of the work function layer 210 filled between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is greater than the thickness of the work function layer 210 filled between the adjacent channel layers 40 The thickness of the work function layer 210.
  • the work function layer 210 In the field of semiconductors, when the work function layer 210 is made of the same material, generally the thicker the work function layer 210 is, the more obvious the adjustment effect on the threshold voltage of the device is.
  • the work function layer 210 between the adjacent channel layers 40 is thicker than the work function layer 210 between the adjacent channel layers 40, so that compared with the device corresponding to the channel layer 40,
  • the threshold voltage of the parasitic device corresponding to the raised portion 110 is higher, and the parasitic device is less likely to be turned on, thereby reducing the bottom leakage current generated in the raised portion 110 and improving the performance of the semiconductor structure.
  • the distance between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is the first distance D1
  • the adjacent channel layers 40 is the second distance D2.
  • the difference between the first distance D1 and the second distance D2 should not be too small, otherwise, the gap between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 will be filled.
  • the thickness difference between the work function layer 210 and the work function layer 210 filled between the adjacent channel layers 40 is not obvious, and the threshold voltage adjustment effect of the work function layer 210 on the parasitic device corresponding to the raised portion 110 is not obvious, and is not obvious. It is beneficial to make the threshold voltage of the parasitic device significantly higher than the threshold voltage of the device corresponding to the channel layer 40 , and the effect of reducing the leakage current of the device is correspondingly insignificant. Therefore, in this embodiment, the first distance D1 is greater than or equal to 1.2 times the second distance D2.
  • the first distance D1 should not be too large.
  • the material of the work function layer 210 that is farther away from the raised portion 110 has a greater influence on the channel of the parasitic device. If the first distance D1 is too large, the work function layer 10 is not easy to fill the raised portion 110 and the space between the raised portion 110 , and the height of the device is likely to be too large.
  • the first distance D1 is less than or equal to three times the second distance D2. That is, the first distance D1 is greater than or equal to 1.2 times the second distance D2 and less than or equal to 3 times the second distance D2.
  • the distance between the channel structure layer 200 and the channel structure layer 200 is greater than that between the channel layer 40 and the channel layer 40 in the channel structure layer 200 distance. That is to say, the distance between adjacent channel structure layers 200 is greater than the distance between adjacent channel layers 40 in the channel structure layers 200 .
  • the gate structure 230 is used to control the turn-on and turn-off of the conductive channel.
  • the gate structure 230 is a metal gate structure.
  • the gate structure 230 is located on the isolation layer 115 and crosses the channel structure layer 200 .
  • the work function layer 210 is used to adjust the work function of the gate structure 230 , thereby adjusting the threshold voltage of the field effect transistor.
  • the material of the work function layer 210 is a P-type work function material. That is, the work function of the material of the work function layer 210 is closer to the top of the valence band of the material of the protrusion 110 and the channel layer 40 , thereby increasing the threshold voltage of the NMOS device.
  • the material of the work function layer is an N-type work function material. That is, the work function of the material of the work function layer 210 is closer to the conduction band bottom of the material of the protrusion 110 and the channel layer 40 , thereby increasing the threshold voltage of the PMOS device.
  • the distance between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is greater than the distance between adjacent channel layers 40 distance, so that the thickness of the work function layer 210 filled between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is greater than the thickness of the work function layer 210 filled between the adjacent channel layers 40
  • the thickness of the work function layer 210 in the field of semiconductors, in the case of the same material of the work function layer 210, usually the thicker the work function layer 210, the more obvious the adjustment effect on the threshold voltage of the device, filling the raised portion 110 and the work function layer 210 between the channel layer 40 adjacent to the protruding part 110 is thicker than the work function layer 210 filled between the adjacent channel layers 40, so as to be consistent with the Compared with the device corresponding to the channel layer 40, the threshold voltage of the parasitic device corresponding to the raised portion 110 is higher, and the parasitic device is less likely to be turned on, which is beneficial to reduce the bottom leakage generated in the raised portion 110
  • the material of the protruding portion 110 and the channel layer 40 includes silicon; when an NMOS transistor is formed, the work function of the material of the work function layer 210 is 4.5 eV to 5.5 eV. Specifically, when forming an NMOS transistor, the material of the work function layer 210 includes one or more of TiN, TaC, MoN, Ta, TaN, TaSiN and TiSiN.
  • the work function layer of the material of the work function layer 210 is 3.9 eV to 4.3 eV.
  • the material of the work function layer 210 includes one or more of TiAl, Al, TaAlN, TiAlN, TaCN and AlN.
  • the gate structure 230 further includes: a gate electrode layer 220 located on the work function layer 210 .
  • the gate electrode layer 220 is used as an external electrode to realize electrical connection between the gate structure 230 and external circuits or other interconnection structures.
  • the gate electrode layer 220 is a metal gate electrode, and the material of the gate electrode layer 220 is a metal material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
  • the gate structure 230 may further include: a cover layer (not shown in the figure), located between the work function layer 210 and the gate dielectric layer 240; a barrier layer (not shown in the figure) shown), located on the work function layer 210.
  • the gate electrode layer 220 is correspondingly located on the barrier layer.
  • the gate structure may not include the covering layer and the blocking layer.
  • the gate dielectric layer 240 is used to realize electrical isolation between the gate structure 230 and the conductive channel. More specifically, in this embodiment, the gate dielectric layer 240 is used to realize electrical isolation between the work function layer 210 and the conductive channel.
  • the material of the gate dielectric layer 240 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 and Al 2 O 3 .
  • the gate dielectric layer 240 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material.
  • the material of the high-k gate dielectric layer can be selected from ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 .
  • the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.
  • the portion of the gate structure 230 located between adjacent channel layers 40 and between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is defined as a first portion 230(1), the The portion of the gate structure 230 across the channel structure layer 200 serves as the second portion 230(2); along the extending direction of the channel structure layer 200, the first portion 230(1) and the second portion 230( 2) the sidewall is indented relative to the end of the channel layer 40 .
  • the semiconductor structure further includes: an inner wall 150 located on the sidewall of the first portion 230 ( 1 ) and exposing the end of the channel structure layer 200 along the extending direction.
  • the inner wall 150 is used to realize the isolation between the source-drain doped region 140 and the gate structure 230, and also increases the distance between the gate structure 230 and the source-drain doped region 140, which is beneficial to reduce the gate The parasitic capacitance between the structure 230 and the source-drain doped region 140 .
  • the material of the inner wall 150 is an insulating material, so as to realize the isolation between the gate structure 230 and the source-drain doped region 140 .
  • the material of the inner wall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
  • the material of the inner wall 150 is silicon nitride.
  • the semiconductor structure further includes: a gate spacer 165 located on the sidewall of the second portion 230 ( 2 ) and exposing the end of the channel structure layer 200 along the extending direction.
  • the gate spacer 165 is used to define the formation position of the source-drain doped region, and the gate spacer 165 is also used to protect the sidewall of the gate structure 230 .
  • the material of the gate spacer 165 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate spacer 165 is a single layer or stacked layers structure.
  • the gate spacer 165 is a single-layer structure, and the material of the gate spacer 165 is silicon nitride.
  • the source-drain doped region 140 is used as the source or drain of the field effect transistor, and the source-drain doped region 140 is used to provide a carrier source when the field effect transistor is working.
  • the source-drain doped region 140 is located on two sides of the gate structure 230 , the gate spacer 165 and the inner wall 150 .
  • the source-drain doped region 140 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, thereby increasing the mobility of carriers.
  • the source-drain doped region 140 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when a PMOS transistor is formed, the source-drain doped region 140 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe.
  • the semiconductor structure further includes: an interlayer dielectric layer 120 located on the isolation layer 115 at the side of the gate structure 230 .
  • the interlayer dielectric layer 120 covers the sidewalls of the gate spacer 165 and the source-drain doped region 140 .
  • the interlayer dielectric layer 120 is used to isolate adjacent devices.
  • the material of the interlayer dielectric layer 120 is silicon oxide.
  • the material of the interlayer dielectric layer 120 may also be other insulating materials.
  • the present invention also provides a method for forming a semiconductor structure.
  • 4 to 16 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • Fig. 4 is a sectional view along the direction perpendicular to the extension of the channel layer
  • Fig. 5 is a sectional view along the A-A1 direction of Fig. 4, providing a substrate 10 for forming a MOS transistor, the substrate 10 Comprising a substrate 100, a raised portion 110 separated on the substrate 100, and a plurality of stacked channel stacks 130 on the raised portion 110, each of the channel stacks 130 includes a sacrificial layer 30 and The channel layer 40 on the sacrificial layer 30; the sacrificial layer 30 between the raised portion 110 and the channel layer 40 adjacent to the raised portion 110 is used as the first sacrificial layer 30 ( 1), the sacrificial layer 30 in the channel stack 130 above the first sacrificial layer 30(1) is used as the second sacrificial layer 30(2), and the first sacrificial layer 30(1) The thickness is greater than the thickness of the second sacrificial layer 30(2).
  • the substrate 10 is used to provide a process platform for subsequent processes.
  • the substrate 10 is used to provide a process platform for forming a gate all around (GAA) transistor (ie, a gate around transistor).
  • GAA gate all around
  • the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon.
  • the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium, and the substrate can also be silicon-on-insulator Substrates or other types of substrates such as germanium-on-insulator substrates.
  • the protruding portion 110 and the substrate 100 are of an integrated structure, and the material of the protruding portion 110 and the substrate 100 is the same, both being silicon.
  • the material of the raised portion may be different from that of the substrate, and the material of the raised portion may be other suitable materials, such as germanium, silicon germanium, silicon carbide, gallium nitride, One or more of gallium arsenide and gallium indium.
  • the channel stack 210 provides a process basis for the subsequent formation of the channel layer 40 disposed in suspension spaces.
  • the channel layer 40 is used to provide the conduction channel of the field effect transistor, and the sacrificial layer 30 is used to support the channel layer 40, so as to provide a process basis for the subsequent realization of the gap setting of the channel layer 40.
  • Layer 30 also serves to occupy a spatial location for subsequent formation of gate structures.
  • the substrate 10 is used to form an NMOS transistor, the material of the channel layer 40 is Si, and the material of the sacrificial layer 30 is SiGe.
  • the etching options of SiGe and Si are relatively high, so by setting the material of the sacrificial layer 30 to SiGe and the material of the channel layer 40 to Si, the sacrificial layer can be effectively reduced. 30 on the channel layer 40, thereby improving the quality of the channel layer 40, which is beneficial to improving device performance.
  • the material of the channel layer 40 is the same as that of the protruding portion 110 . In other embodiments, the material of the channel layer and the raised portion may also be different.
  • the material of the channel layer is SiGe
  • the material of the sacrificial layer is Si.
  • the material of the channel layer may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium.
  • the stacking direction of the multiple channel stacks 130 is perpendicular to the surface of the substrate 100 .
  • the number of the channel stacks 130 is three. In other embodiments, there may be other numbers of channel stacks, for example: two, four, five and so on.
  • the thickness of the first sacrificial layer 30(1) is greater than the thickness of the second sacrificial layer 30(2), so that in the subsequent step of removing the sacrificial layer 30 to form the through groove, the first sacrificial layer 30(1) is removed to form The first through groove, removing the second sacrificial layer 30(2) to form the second through groove, the height of the first through groove is correspondingly greater than the height of the second through groove, so that the subsequent formation of the work function layer filled in the through groove In the step, the thickness of the work function layer filled in the first through groove is greater than the thickness of the work function layer filled in the second through groove.
  • the thickness of the first sacrificial layer 30(1) is greater than the thickness of the second sacrificial layer 30(2), and the first sacrificial layer 30(1) and the second sacrificial layer 30(2)
  • the thickness difference should not be too small, otherwise the height difference between the subsequent first through groove and the second through groove is too small, correspondingly, the work function layer filled in the first through groove and the work function layer filled in the second through groove
  • the thickness difference of the work function layer is not obvious, and the threshold voltage adjustment effect of the work function layer on the parasitic device corresponding to the raised part is not obvious, which is not conducive to making the threshold voltage of the parasitic device significantly greater than that of the device corresponding to the channel layer. threshold voltage, the effect of reducing the leakage current of the device is correspondingly insignificant. Therefore, in this embodiment, the thickness of the first sacrificial layer 30(1) is greater than 1.2 times the thickness of the second sacrificial layer 30(2).
  • the thickness of the first sacrificial layer 30(1) should not be too large.
  • the first sacrificial layer 30(1) is too thick, the subsequent formation of the second through groove , and when forming the work function layer filled in the second through-groove, the material of the work-function layer farther away from the protrusion 110 has a weaker influence on the channel of the parasitic device, and also causes the height of the second through-groove to be too large , the work function layer is not easy to fill the second through groove, and it is easy to cause the height of the device to be too large.
  • the thickness of the first sacrificial layer 30(1) is less than or equal to three times the thickness of the second sacrificial layer 30(2). That is, the thickness of the first sacrificial layer 30(1) is greater than 1.2 times the thickness of the second sacrificial layer 30(2), and less than or equal to 3 times the thickness of the second sacrificial layer 30(2) thickness of.
  • the material of the sacrificial layer 30 includes SiGe, and the germanium concentration in the second sacrificial layer 30(2) is greater than the germanium concentration in the first sacrificial layer 30(1). .
  • the second sacrificial layer 30(2) is thinner, and the subsequent removal of the second sacrificial layer 30(2) is more difficult than removing the first sacrificial layer 30(2).
  • Layer 30(1) is more difficult, by making the germanium concentration in the second sacrificial layer 30(2) greater than the germanium concentration in the first sacrificial layer 30(1), the second sacrificial layer 30( 2) The removal rate during the subsequent removal of the sacrificial layer 30 .
  • the method for forming the semiconductor structure further includes: forming on the substrate 100 surrounding the raised portion 110 The isolation layer 115 , the isolation layer 115 exposes the channel stack 130 .
  • the isolation layer 115 is used for isolating adjacent raised portions 110 and is also used for isolating the substrate 100 and the gate structure.
  • the material of the isolation layer 115 is silicon oxide.
  • the material of the isolation layer 115 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium oxide.
  • the top surface of the isolation layer 115 is lower than the top surface of the protrusion 110 .
  • the top surface of the isolation layer may also be flush with the top surface of the protrusion.
  • FIG. 6 is a cross-sectional view based on FIG. 4
  • FIG. 7 is a cross-sectional view along the A-A1 direction of FIG. 5 , forming a dummy gate structure 160 across the channel stack 130 .
  • the dummy gate structure 160 is formed on the isolation layer 110 and across the channel stack 130 ; the dummy gate structure 160 covers part of the top and part of the sidewall of the channel stack 130 .
  • the extending direction of the dummy gate structure 160 is perpendicular to the extending direction of the channel stack.
  • the dummy gate structure 160 is used to pre-occupy a space position for subsequent formation of a gate structure.
  • the dummy gate structure 160 may be a stacked structure or a single layer structure.
  • the dummy gate structure 160 is a stacked structure, including a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) on the dummy gate oxide layer.
  • the dummy gate structure 160 is a polysilicon gate structure, the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the dummy gate layer may be polysilicon.
  • the method for forming the semiconductor structure further includes: forming gate spacers 165 on sidewalls of the dummy gate structure 160 .
  • the gate spacer 165 is used together with the dummy gate structure 160 as an etching mask for the subsequent etching process to form a groove, so as to define the formation position of the source-drain doped region, and the gate spacer 165 is also used to protect The dummy gate structure 160 and the sidewalls of subsequent gate structures.
  • the material of the gate spacer 165 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate spacer 165 has a single-layer or stacked structure.
  • the gate spacer 165 is a single-layer structure
  • the material of the gate spacer 165 is silicon nitride.
  • the method for forming the semiconductor structure further includes: channel stacks 130 on both sides of the dummy gate structure 160 A source-drain doped region 140 is formed in the center, and the source-drain doped region 140 is in contact with the end of each channel layer 40 in the channel stack 130 along the extending direction.
  • the source-drain doped region 140 is used as the source or drain of the field effect transistor, and the source-drain doped region 140 is used to provide a carrier source when the field effect transistor is working.
  • the source-drain doped region 140 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, thereby increasing the mobility of carriers.
  • the source-drain doped region 140 when forming an NMOS transistor, the source-drain doped region 140 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source-drain doped region 140 includes doped There is a stress layer with P-type ions, and the material of the stress layer is Si or SiGe.
  • an interlayer dielectric layer 120 is formed on the isolation layer 115 exposed by the dummy gate structure 160 .
  • the interlayer dielectric layer 120 covers the sidewalls of the gate spacer 165 and the source-drain doped region 140 .
  • the interlayer dielectric layer 120 is used to isolate adjacent devices.
  • the material of the interlayer dielectric layer 120 is silicon oxide.
  • the material of the interlayer dielectric layer 120 may also be other insulating materials.
  • FIG. 9 is a schematic cross-sectional view at the position of the gate opening along the direction perpendicular to the extension of the channel stack 130
  • FIG. 10 is a cross-sectional view along the direction A-A1 of FIG. , forming a gate opening 170 to expose the channel stack 130 .
  • the gate opening 170 is used to provide a space for forming a gate structure.
  • the gate opening 170 exposes the channel stack 130 so that the sacrificial layer 30 in the channel stack 130 can be subsequently removed through the gate opening 170 .
  • the bottom of the gate opening 170 also exposes the isolation layer 115 .
  • the gate opening 170 is formed in the interlayer dielectric layer 120 .
  • FIG. 11 is a cross-sectional view based on FIG. 9, and FIG. 12 is a cross-sectional view along the A-A1 direction of FIG.
  • the through groove 180 includes a first through groove 180(1) formed by removing the first sacrificial layer 30(1), and a first through groove 180(1) formed by removing the second sacrificial layer 30(2) The second through groove 180(2) is formed.
  • the thickness of the first sacrificial layer 30(1) is greater than the thickness of the second sacrificial layer 30(2), and the first through groove 180(1) is formed after removing the first sacrificial layer 30(1). 1.
  • the height of the first through-groove 180(1) is correspondingly greater than the height of the second through-groove 180(2).
  • the channel layer 40 is spaced from the protruding portion 110 , and adjacent channel layers 40 are spaced apart.
  • the plurality of channel layers 40 arranged at intervals are used to form the channel structure layer 200 .
  • the material of the sacrificial layer 30 includes SiGe
  • the process of removing the sacrificial layer 30 includes a wet etching process.
  • the wet etching process has the characteristics of isotropic etching, which facilitates the removal of each sacrificial layer 30 .
  • the second sacrificial layer 30(2) is thinner, and the difficulty of removing the second sacrificial layer 30(2) is compared to removing the first sacrificial layer 30(1). ) is more difficult.
  • the germanium concentration in the second sacrificial layer 30(2) is greater than the germanium concentration in the first sacrificial layer 30(1), thereby improving the second sacrificial layer 30( 2)
  • the removal rate during the process of removing the sacrificial layer 30 which is beneficial to reduce the probability of the second sacrificial layer 30 ( 2 ) remaining.
  • the etching solution or etching vapor of the wet etching process is HCl.
  • FIG. 13 to FIG. 15 show schematic cross-sectional views
  • FIG. 16 is a cross-sectional view along the direction A-A1 of FIG.
  • the gate structure 230 includes a work function layer 210 that surrounds the surface of the channel layer 40 and fills the through groove 180 .
  • the gate structure 230 is used to control the turn-on and turn-off of the conductive channel.
  • the gate structure 230 is a metal gate structure.
  • the work function layer 210 is used to adjust the work function of the gate structure 230 , thereby adjusting the threshold voltage of the field effect transistor.
  • the material of the work function layer 210 is a P-type work function material. That is, the work function of the material of the work function layer 210 is closer to the top of the valence band of the material of the protrusion 110 and the channel layer 40 , thereby increasing the threshold voltage of the NMOS device.
  • the material of the work function layer 210 is an N-type work function material. That is, the work function of the material of the work function layer 210 is closer to the conduction band bottom of the material of the protrusion 110 and the channel layer 40 , thereby increasing the threshold voltage of the PMOS device.
  • the thickness of the work function layer 210 filled in the first through-slot 180(1) greater than the thickness of the work function layer 210 filled in the second through-groove 180(2).
  • the thicker the work function layer 210 In the field of semiconductors, in the case of the same material of the work function layer 210, generally the thicker the work function layer 210, the greater the effect on the threshold voltage of the device.
  • the work function layer 210 located in the first through groove 180(1) is thicker than the work function layer 210 located in the second through groove 180(2), so as to correspond to the channel layer 40
  • the threshold voltage of the parasitic device corresponding to the protruding part 110 is higher, and the parasitic device is less likely to be turned on, which in turn helps to reduce the bottom leakage current generated in the protruding part 110 and improves the reliability of the semiconductor structure. performance.
  • the material of the protruding portion 110 and the channel layer 40 includes silicon; when an NMOS transistor is formed, the work function of the material of the work function layer 210 is 4.5 eV to 5.5 eV.
  • the material of the work function layer 210 includes one or more of TiN, TaC, MoN, Ta, TaN, TaSiN and TiSiN.
  • the work function layer of the material of the work function layer 210 is 3.9 eV to 4.3 eV.
  • the material of the work function layer 210 includes one or more of TiAl, Al, TaAlN, TiAlN, TaCN and AlN.
  • the step of forming the work function layer 210 includes: as shown in FIG. 13 , forming a work function film 201 surrounding the surface of the channel layer 40 exposed by the gate opening 170 and the through groove 180, the The work function film 201 is filled in the through-groove 180; as shown in FIG. 14 , a portion of the thickness on the sidewall of the channel layer 40 exposed by the gate opening 170 and on the top of the channel layer 40 farthest from the substrate 100 is removed.
  • the work function film 201 and the rest of the work function film 201 are used as the work function layer 210 .
  • the work function film 201 filling the through groove 180, and then forming the work function film on the side wall of the channel layer 40 exposed by the gate opening 170 and on the top of the channel layer 40 farthest from the substrate 100 201 is etched to ensure that the work function layer 210 can fill the first through-groove 180(1) and the second through-groove 180(2), and it is also beneficial to ensure that the channel layer 40 side exposed by the gate opening 170
  • the thickness of the work function layer 210 on the wall and on the top of the channel layer 40 farthest from the substrate 100 satisfies the process requirements.
  • the process of forming the work function film 201 includes an atomic layer deposition process.
  • the atomic layer deposition process has strong gap-filling ability and conformal covering ability, which is beneficial to the filling of the work function film 201 in the through groove 180 and is also beneficial to improving the formation quality of the work function film 201 .
  • an isotropic etching process is used to remove the part of the work function located on the sidewall of the channel layer 40 exposed by the gate opening 170 and on the top of the channel layer 40 farthest from the substrate 100.
  • Film 201 The isotropic etching process has the characteristics of isotropic etching, so that the work function on the sidewall of the channel layer 40 exposed by the gate opening 170 and the top of the channel layer 40 farthest from the substrate 100 can be adjusted.
  • the film 201 is etched to reduce the thickness of the work function film 201 at the position.
  • the gate structure 230 further includes a gate electrode layer 220 located on the work function layer 210 and filling the gate opening 170 .
  • the gate electrode layer 220 is used as an external electrode to realize electrical connection between the gate structure 230 and external circuits or other interconnection structures.
  • the gate electrode layer 220 is a metal gate electrode, and the material of the gate electrode layer 220 is a metal material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
  • the gate electrode layer 220 filling the gate opening 170 is formed on the work function layer 210 .
  • the method for forming the semiconductor structure further includes: after forming the gate opening 170 and the through groove 180 and before forming the gate structure 230, the trenches exposed by the gate opening 170 and the through groove 180 A gate dielectric layer 240 is formed on the surface of the track layer 40 .
  • the gate dielectric layer 240 is used to realize electrical isolation between the gate structure 230 and the conductive channel. More specifically, in this embodiment, the gate dielectric layer 240 is used to realize electrical isolation between the work function layer 210 and the conductive channel.
  • the material of the gate dielectric layer 240 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 and Al 2 O 3 .
  • the gate dielectric layer 240 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material.
  • the material of the high-k gate dielectric layer can be selected from ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 .
  • the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer.
  • the gate structure 230 may further include: a capping layer (not shown in the figure), located between the work function layer 210 and the gate dielectric layer 240; not shown), located on the work function layer 210.
  • the gate electrode layer 220 is correspondingly located on the barrier layer.
  • the gate structure may not include the covering layer and the blocking layer.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体结构及其形成方法，半导体结构包括：衬底；位于所述衬底上的围栅晶体管，所述围栅晶体管包括：分立于衬底上的凸起部以及与所述凸起部间隔悬空设置的沟道结构层，所述沟道结构层包括多个依次间隔设置的沟道层，沟道层沿垂直于衬底表面的方向竖直堆叠，且沿垂直于衬底表面的方向，凸起部和与凸起部相邻的沟道层之间的距离，大于相邻的沟道层之间的距离；栅极结构，包括包围于沟道层表面的功函数层，功函数层填充于凸起部和与凸起部相邻的沟道层之间、以及相邻的沟道层之间；当形成NMOS晶体管时，功函数层的材料为P型功函数材料；当形成PMOS晶体管时，功函数层的材料为N型功函数材料。本发明实施例有利于降低器件的漏电流。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高集成度的方向发展，半导体工艺节点遵循摩尔定律的发展趋势不断减小。晶体管作为最基本的半导体器件目前正被广泛应用，因此随着半导体器件的元件密度和集成度的提高，为了适应工艺节点的减小，不得不断缩短晶体管的沟道长度。
为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面晶体管向具有更高功效的三维立体式的晶体管过渡，如全包围栅极（Gate-all-around，GAA）晶体管。全包围栅极晶体管中，栅极从四周包围沟道所在的区域，与平面晶体管相比，全包围栅极晶体管的栅极对沟道的控制能力更强，能够更好的抑制短沟道效应。
但是，目前器件的漏电流问题仍待改善。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，有利于降低器件的漏电流。
 技术解决方案
为解决上述问题，本发明实施例提供一种半导体结构，包括：衬底；位于所述衬底上的围栅晶体管，所述围栅晶体管包括：分立于衬底上的凸起部以及与所述凸起部间隔悬空设置的沟道结构层，所述沟道结构层包括多个依次间隔设置的沟道层，所述沟道层沿垂直于衬底表面的方向竖直堆叠，且沿垂直于衬底表面的方向，所述凸起部和与所述凸起部相邻的沟道层之间的距离，大于相邻的所述沟道层之间的距离；栅极结构，横跨所述沟道结构层且包围所述沟道结构层中每一个所述沟道层；所述栅极结构包括包围于所述沟道层表面的功函数层，所述功函数层填充于所述凸起部和与所述凸起部相邻的沟道层之间、以及相邻的所述沟道层之间；其中，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料；当形成PMOS晶体管时，所述功函数层的材料为N型功函数材料；栅介质层，位于所述栅极结构与所述沟道层之间、以及所述栅极结构与所述凸起部之间；源漏掺杂区，位于所述栅极结构两侧的凸起部上且与所述沟道结构层中的每一个沟道层沿延伸方向的端部相接触。
相应的，本发明实施例还提供一种半导体结构的形成方法，包括：提供基底，用于形成MOS晶体管，所述基底包括衬底、分立于衬底上的凸起部以及位于所述凸起部上的多个堆叠的沟道叠层，每个所述沟道叠层包括牺牲层和位于所述牺牲层上的沟道层；位于所述凸起部和与凸起部相邻的所述沟道层之间的牺牲层用于作为第一牺牲层，位于所述第一牺牲层上方的所述沟道叠层中的牺牲层用于作为第二牺牲层，所述第一牺牲层的厚度大于所述第二牺牲层的厚度；形成横跨所述沟道叠层的伪栅结构；在所述伪栅结构两侧的沟道叠层中形成源漏掺杂区，所述源漏掺杂区与所述沟道叠层中的每一个沟道层沿延伸方向的端部相接触；在形成所述源漏掺杂区后，去除所述伪栅结构，形成栅极开口，暴露出所述沟道叠层；去除所述沟道叠层中的牺牲层，形成通槽，与所述栅极开口相连通，所述通槽包括去除所述第一牺牲层形成的第一通槽、以及去除所述第二牺牲层形成的第二通槽；在所述栅极开口和通槽内形成栅极结构，所述栅极结构包括包围于所述沟道层的表面且填充于所述通槽内的功函数层；其中，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料；当形成PMOS晶体管时，所述功函数层的材料为N型功函数材料。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的半导体结构中，所述功函数层包围于沟道层表面，当形成NMOS晶体管时，功函数层的材料为P型功函数材料，从而增大NMOS器件的阈值电压；当形成PMOS时，所述功函数层的材料为N型功函数材料，从而增大PMOS器件的阈值电压；并且，沿垂直于衬底表面的方向，所述凸起部和与所述凸起部相邻的沟道层之间的距离，大于相邻的所述沟道层之间的距离，相应地，填充于所述凸起部和与所述凸起部相邻的沟道层之间的功函数层厚度，大于填充于相邻的所述沟道层之间的功函数层厚度，在半导体领域中，在功函数层材料相同的情况下，通常功函数层越厚，对器件的阈值电压的调节效果越明显，位于所述凸起部和与所述凸起部相邻的沟道层之间的功函数层比位于相邻的所述沟道层之间的功函数层更厚，从而和与所述沟道层对应的器件相比，与凸起部对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部中产生的底部漏电流，提升了半导体结构的性能。
本发明实施例提供的半导体结构的形成方法中，所述第一牺牲层的厚度大于所述第二牺牲层的厚度，在去除第一牺牲层形成第一通槽、去除第二牺牲层形成第二通槽的步骤中，所述第一通槽的高度相应大于第二通槽的高度；在形成栅极结构的步骤中，所述功函数层包围沟道层表面且填充于所述通槽，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料，从而增大NMOS器件的阈值电压；当形成PMOS时，功函数层的材料为N型功函数材料，从而增大PMOS器件的阈值电压；并且，由于第一通槽的高度大于第二通槽的高度，相应地，填充于第一通槽内的功函数层的厚度，大于填充于第二通槽内的功函数层的厚度，在半导体领域中，在功函数层材料相同的情况下，通常功函数层越厚，对器件的阈值电压的调节效果越明显，位于第一通槽内的功函数层比位于第二通槽内的功函数层更厚，从而和与所述沟道层对应的器件相比，与凸起部对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部中产生的底部漏电流，提升了半导体结构的性能。
 附图说明
图1是一种半导体结构的结构示意图。
图2至图3是本发明半导体结构一实施例的结构示意图。
图4至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，目前器件的漏电流问题仍待改善。以下结合一种半导体结构，分析器件的漏电流问题仍待改善的原因。图1是一种半导体结构的示意图。
参考图1，以半导体结构为全包围栅极晶体管为示例进行说明，所述半导体结构包括：基底，包括衬底1、分立于衬底1上的凸起部2以及与所述凸起部2间隔悬空设置的沟道结构层4，所述沟道结构层4包括多个依次间隔设置的沟道层3；栅极结构5，横跨所述沟道结构层4且包围所述沟道层3；栅介质层6，位于所述栅极结构5与所述沟道层1之间、以及所述栅极结构5与所述凸起部2之间；源漏掺杂区7，位于所述栅极结构5两侧的凸起部2上且与所述沟道结构层4沿延伸方向的端部相接触。
半导体结构中通常还包括位于所述衬底1上且围绕所述凸起部2的隔离层8。
所述半导体结构中，由于栅极结构5对凸起部2的控制能力相较于对沟道层3的控制能力更弱，在所述凸起部2中容易产生漏电流。
为了减小凸起部2中产生的漏电流，一种方法是在半导体结构的形成过程中，在隔离层8中注入掺杂离子，所述掺杂离子的掺杂类型与源漏掺杂区7的掺杂类型不同，并使所述掺杂离子向所述凸起部2中扩散，以使凸起部2中掺杂有与源漏掺杂区7的掺杂类型不同的掺杂离子，以增大凸起部2中的沟道开启的难度，从而减小凸起部2中的漏电流。
但是，上述方法中，难以对所述隔离层8中的掺杂离子的扩散进行控制，因此为了使凸起部2中能够扩散有足够的掺杂离子以起到减小漏电流的效果，在隔离层8中注入掺杂离子的过程中，所需的注入剂量通常较大。但是离子注入会引起随机掺杂剂波动（random dopant fluctuation）；而且，在半导体结构的形成过程中，在形成栅极结构之前，相邻的沟道层3之间以及所述沟道层3与所述凸起部2之间通常还形成有牺牲层，牺牲层用于为形成栅极结构占据空间位置，当所述掺杂离子还扩散至牺牲层中时，还会影响牺牲层在后续工艺步骤中的去除。
为了解决所述技术问题，本发明实施例提供一种半导体结构，所述功函数层包围沟道层表面，当形成NMOS晶体管时，功函数层的材料为P型功函数材料，从而增大NMOS器件的阈值电压；当形成PMOS时，所述功函数层的材料为N型功函数材料，从而增大PMOS器件的阈值电压；并且，沿垂直于衬底表面的方向，所述凸起部和与所述凸起部相邻的沟道层之间的距离，大于相邻的所述沟道层之间的距离，相应地，填充于所述凸起部和与所述凸起部相邻的沟道层之间的功函数层的厚度，大于填充于相邻的所述沟道层之间的功函数层的厚度，在半导体领域中，在功函数层材料相同的情况下，通常功函数层越厚，对器件的阈值电压的调节效果越明显，位于所述凸起部和与所述凸起部相邻的沟道层之间的功函数层比位于相邻的所述沟道层之间的功函数层更厚，从而和与所述沟道层对应的器件相比，与凸起部对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部中产生的底部漏电流，提升了半导体结构的性能。
为了解决所述技术问题，本发明实施例还提供一种半导体结构的形成方法，所述第一牺牲层的厚度大于所述第二牺牲层的厚度，在去除第一牺牲层形成第一通槽、去除第二牺牲层形成第二通槽的步骤中，所述第一通槽的高度相应大于第二通槽的高度；在形成栅极结构的步骤中，所述功函数层包围沟道层表面且填充于所述通槽，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料，从而增大NMOS器件的阈值电压；当形成PMOS时，功函数层的材料为N型功函数材料，从而增大PMOS器件的阈值电压；并且，由于第一通槽的高度大于第二通槽的高度，相应地，填充于第一通槽内的功函数层的厚度，大于填充于第二通槽内的功函数层的厚度，在半导体领域中，在功函数层材料相同的情况下，通常功函数层越厚，对器件的阈值电压的调节效果越明显，位于第一通槽内的功函数层比位于第二通槽内的功函数层更厚，从而和与所述沟道层对应的器件相比，与凸起部对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部中产生的底部漏电流，提升了半导体结构的性能。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。参考图1和图2，示出了本发明半导体结构一实施例的结构示意图。其中，图2是在栅极结构位置处沿垂直于沟道层延伸方向的剖面图，图3是图2沿A-A1方向的剖视图。
如图2和图3所示，本实施例中，所述半导体结构包括：衬底100；位于所述衬底100上的围栅晶体管，所述围栅晶体管包括：分立于衬底100上的凸起部110以及与所述凸起部110间隔悬空设置的沟道结构层200，所述沟道结构层200包括多个依次间隔设置的沟道层40，所述沟道层40沿垂直于衬底100表面的方向竖直堆叠，且沿垂直于衬底100表面的方向，所述凸起部110和与所述凸起部110相邻的沟道层40之间的距离，大于相邻的所述沟道层40之间的距离；栅极结构230，横跨所述沟道结构层200且包围所述沟道结构层200中每一个所述沟道层40；所述栅极结构230包括包围于所述沟道层40表面的功函数层210，所述功函数层210填充于所述凸起部110和与所述凸起部110相邻的沟道层40之间、以及相邻的所述沟道层40之间；其中，当形成NMOS晶体管时，功函数层的材料为P型功函数材料；当形成PMOS晶体管时，所述功函数层的材料为N型功函数材料；栅介质层240，位于所述栅极结构230与所述沟道层40之间、以及所述栅极结构230与所述凸起部110之间；源漏掺杂区140，位于所述栅极结构230两侧的凸起部110上且与所述沟道结构层200中的每一个沟道层40沿延伸方向的端部相接触。
其中，衬底100、分立于衬底100上的凸起部110以及与所述凸起部110间隔悬空设置的沟道结构层200构成基底10。
所述衬底100用于为半导体结构的形成提供工艺操作平台。本实施例中，所述衬底100用于为形成全包围栅极（GAA）晶体管（即所述围栅晶体管）提供工艺平台。
本实施例中，衬底100为硅衬底，即衬底100的材料为单晶硅。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种，衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
本实施例中，凸起部110与衬底100为一体型结构，所述凸起部110与衬底100的材料相同，均为硅。在其他实施例中，所述凸起部的材料可以与衬底的材料不同，所述凸起部的材料可以是其他适宜的材料，例如：锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。
所述半导体结构还包括：隔离层115，位于所述衬底100上且围绕所述凸起部110。所述隔离层115暴露出所述沟道结构层200。
隔离层115用于隔离相邻的凸起部110，还用于隔离衬底100与栅极结构230。本实施例中，隔离层115的材料为氧化硅。隔离层115的材料还可以是其他的绝缘材料，例如：氧化硅、氮化硅、氮氧化硅和氧化锗硅中的一种或多种。
作为一示例，所述隔离层115的顶面低于所述凸起部110的顶面。在其他实施例中，所述隔离层的顶面还可以与所述凸起部的顶面相齐平。
所述沟道结构层200用于提供场效应晶体管的导电沟道。具体地，所述沟道层40提供场效应晶体管的导电沟道。
本实施例中，所述沟道层40的堆叠方向垂直于衬底100表面。
本实施例中，所述沟道层40的材料与所述凸起部110的材料相同。更具体地，沟道层40的材料为Si，有利于提高NMOS晶体管的性能。其他实施例中，当半导体结构为PMOS晶体管时，为提升PMOS晶体管的性能，可采用SiGe沟道技术，沟道层的材料为SiGe。
本实施例中，所述沟道层40与所述凸起部110的材料相同。在其他实施例中，沟道层与凸起部的材料还可以不同。
另一些实施例中，沟道层的材料还可以为锗、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。
作为一种示例，所述沟道结构层200中，所述沟道层40的数量为三个。在其他实施例中，沟道层还可以为其他数量，例如：两个、四个、五个等。
沿垂直于衬底100表面的方向，所述凸起部110和与所述凸起部110相邻的沟道层40之间的距离，大于相邻的所述沟道层40之间的距离，以便使得填充于所述凸起部110和与所述凸起部110相邻的沟道层40之间的功函数层210的厚度，大于填充于相邻的所述沟道层40之间的功函数层210的厚度。
在半导体领域中，在功函数层210材料相同的情况下，通常功函数层210越厚，对器件的阈值电压的调节效果越明显，位于所述凸起部110和与所述凸起部110相邻的沟道层40之间的功函数层210比位于相邻的所述沟道层40之间的功函数层210更厚，从而和与所述沟道层40对应的器件相比，与凸起部110对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部110中产生的底部漏电流，提升了半导体结构的性能。
本实施例中，沿垂直于衬底100表面的方向，所述凸起部110和与所述凸起部110相邻的沟道层40之间的距离为第一距离D1，相邻的所述沟道层40之间的距离为第二距离D2。
需要说明的是，所述第一距离D1与第二距离D2的差值不宜过小，否则，填充于所述凸起部110和与所述凸起部110相邻的沟道层40之间的功函数层210与填充于相邻沟道层40之间的功函数层210的厚度差异不明显，功函数层210对凸起部110所对应的寄生器件的阈值电压调节效果不明显，不利于使得所述寄生器件的阈值电压显著地大于与沟道层40对应的器件的阈值电压，对器件的漏电流的减小效果相应也不明显。为此，本实施例中，所述第一距离D1大于或等于1.2倍的所述第二距离D2。
与第二距离D2相比，所述第一距离D1也不宜过大，当第一距离D1过大时，距离凸起部110较远的功函数层210材料对寄生器件的沟道的影响越弱，并且第一距离D1过大还容易导致功函数层10不易填充满所述凸起部110和与凸起部110之间的空间，而且还容易导致器件的高度过大。
为此，本实施例中，所述第一距离D1小于或等于3倍的所述第二距离D2。也即，所述第一距离D1大于或等于1.2倍的所述第二距离D2，且小于或等于3倍的所述第二距离D2。
还需要说明的是，本实施例中，所述沟道结构层200与沟道结构层200之间的距离，大于所述沟道结构层200中的沟道层40与沟道层40之间的距离。也就是说，相邻的沟道结构层200之间的距离，大于沟道结构层200中的相邻沟道层40之间的距离。
在器件工作时，栅极结构230用于控制导电沟道的开启和关断。本实施例中，所述栅极结构230为金属栅极结构。
本实施例中，所述栅极结构230位于所述隔离层115上且横跨所述沟道结构层200。
功函数层210用于调节栅极结构230的功函数，进而调节场效应晶体管的阈值电压。
其中，当形成NMOS晶体管时，功函数层210的材料为P型功函数材料。也即功函数层210材料的功函数更靠近凸起部110和沟道层40材料的价带顶，从而增大NMOS器件的阈值电压。
当形成PMOS时，功函数层的材料为N型功函数材料。也即功函数层210材料的功函数更靠近凸起部110和沟道层40材料的导带底，从而增大PMOS器件的阈值电压。
并且，由于在每一个围栅晶体管中，所述凸起部110和与所述凸起部110相邻的沟道层40之间的距离，大于相邻的所述沟道层40之间的距离，使得填充于所述凸起部110和与所述凸起部110相邻的沟道层40之间的功函数层210的厚度，大于填充于相邻的所述沟道层40之间的功函数层210的厚度，在半导体领域中，在功函数层210材料相同的情况下，通常功函数层210越厚，对器件的阈值电压的调节效果越明显，填充于所述凸起部110和与所述凸起部110相邻的沟道层40之间的功函数层210，比填充于相邻的所述沟道层40之间的功函数层210更厚，从而和与所述沟道层40对应的器件相比，与凸起部110对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部110中产生的底部漏电流，提升了半导体结构的性能。
本实施例中，所述凸起部110和沟道层40的材料包括硅；当形成NMOS晶体管时，所述功函数层210材料的功函数为4.5eV至5.5eV。具体地，当形成NMOS晶体管时，所述功函数层210的材料包括TiN、TaC、MoN、Ta、TaN、TaSiN和TiSiN中的一种或多种。
本实施例中，当形成PMOS晶体管时，所述功函数层210材料的功函数层为3.9eV至4.3eV。具体地，当形成PMOS晶体管时，所述功函数层210的材料包括TiAl、Al、TaAlN、TiAlN、TaCN和AlN中的一种或多种。
本实施例中，所述栅极结构230还包括：栅电极层220，位于所述功函数层210上。
栅电极层220用于作为外接电极，以实现栅极结构230与外部电路或其他互连结构之间的电连接。
本实施例中，所述栅电极层220为金属栅电极，栅电极层220的材料为金属材料，例如：W、Al、Cu、Ag、Au、Pt、Ni或Ti等。
需要说明的是，在具体实施中，所述栅极结构230还可以包括：覆盖层（图未示），位于所述功函数层210与所述栅介质层240之间；阻挡层（图未示），位于所述功函数层210上。
所述栅电极层220相应位于所述阻挡层上。在另一些实施例中，所述栅极结构还可以不包括所述覆盖层和阻挡层。
栅介质层240用于实现栅极结构230与导电沟道之间的电隔离。更具体地，本实施例中，所述栅介质层240用于实现功函数层210与导电沟道之间的电隔离。所述栅介质层240的材料包括氧化硅、掺氮氧化硅、HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2O 3和Al 2O 3中的一种或多种。
本实施例中，所述栅介质层240包括高k栅介质层，高k栅介质层的材料为高k介质材料。高k栅介质层的材料可以选自ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al 2O 3。在其他实施例中，所述栅介质层还可以包括栅氧化层和位于所述栅氧化层上的高k栅介质层。
所述栅极结构230位于相邻的沟道层40之间、以及位于凸起部110和与凸起部110相邻的沟道层40之间的部分作为第一部分230(1)，所述栅极结构230横跨所述沟道结构层200的部分作为第二部分230(2)；沿所述沟道结构层200的延伸方向，所述第一部分230(1)和第二部分230(2)的侧壁相对于所述沟道层40的端部缩进。
本实施例中，所述半导体结构还包括：内侧墙150，位于所述第一部分230(1)的侧壁上且暴露出所述沟道结构层200沿延伸方向的端部。
所述内侧墙150用于实现源漏掺杂区140与栅极结构230之间的隔离，而且还增大栅极结构230与源漏掺杂区140之间的距离，有利于减小栅极结构230与源漏掺杂区140之间的寄生电容。
本实施例中，所述内侧墙150的材料为绝缘材料，以实现栅极结构230与源漏掺杂区140之间的隔离。本实施例中，内侧墙150的材料包括氮化硅、氧化硅、氮氧化硅、低k介质材料或超低k介质材料。作为示例，内侧墙150的材料为氮化硅。
所述半导体结构还包括：栅极侧墙165，位于所述第二部分230(2)的侧壁上且暴露出所述沟道结构层200沿延伸方向的端部。
所述栅极侧墙165用于定义源漏掺杂区的形成位置，所述栅极侧墙165还用于保护栅极结构230的侧壁。
本实施例中，所述栅极侧墙165的材料包括氮化硅、氧化硅、氮氧化硅、低k介质材料或超低k介质材料，所述栅极侧墙165为单层或叠层结构。作为一种示例，所述栅极侧墙165为单层结构，栅极侧墙165的材料为氮化硅。
所述源漏掺杂区140用于作为场效应晶体管的源极或漏极，在场效应晶体管工作时，源漏掺杂区140用于提供载流子源。本实施例中，所述源漏掺杂区140位于所述栅极结构230、栅极侧墙165和内侧墙150的两侧。
本实施例中，所述源漏掺杂区140包括掺杂有离子的应力层，应力层用于为沟道区提供应力，从而提高载流子的迁移率。具体地，当形成NMOS晶体管时，所述源漏掺杂区140包括掺杂有N型离子的应力层，应力层的材料为Si或SiC；当形成PMOS晶体管时，所述源漏掺杂区140包括掺杂有P型离子的应力层，应力层的材料为Si或SiGe。
本实施例中，所述半导体结构还包括：层间介质层120，位于所述栅极结构230侧部的隔离层115上。层间介质层120覆盖所述栅极侧墙165的侧壁以及所述源漏掺杂区140。
所述层间介质层120用于隔离相邻器件。本实施例中，层间介质层120的材料为氧化硅。层间介质层120的材料还可以是其他绝缘材料。
相应的，本发明还提供一种半导体结构的形成方法。图4至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
以下结合附图，对本实施例半导体结构的形成方法进行详细说明。
参考图4和图5，图4为沿垂直于沟道层延伸方向的剖面图，图5是图4沿A-A1方向的剖面图，提供基底10，用于形成MOS晶体管，所述基底10包括衬底100、分立于衬底100上的凸起部110以及位于所述凸起部110上的多个堆叠的沟道叠层130，每个所述沟道叠层130包括牺牲层30和位于所述牺牲层30上的沟道层40；位于所述凸起部110和与凸起部110相邻的所述沟道层40之间的牺牲层30用于作为第一牺牲层30(1)，位于所述第一牺牲层30(1)上方的所述沟道叠层130中的牺牲层30用于作为第二牺牲层30(2)，所述第一牺牲层30(1)的厚度大于所述第二牺牲层30(2)的厚度。
所述基底10用于为后续制程提供工艺平台。本实施例中，所述基底10用于为形成全包围栅极（GAA）晶体管（即围栅晶体管）提供工艺平台。
本实施例中，衬底100为硅衬底，即衬底100的材料为单晶硅。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种，衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
本实施例中，凸起部110与衬底100为一体型结构，所述凸起部110与衬底100的材料相同，均为硅。在其他实施例中，所述凸起部的材料可以与衬底的材料不同，所述凸起部的材料可以是其他适宜的材料，例如：锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。
所述沟道叠层210为后续形成悬空间隔设置的沟道层40提供工艺基础。具体地，所述沟道层40用于提供场效应晶体管的导电沟道，所述牺牲层30用于支撑沟道层40，从而为后续实现沟道层40的间隔悬空设置提供工艺基础，牺牲层30还用于为后续形成栅极结构占据空间位置。
本实施例中，所述基底10用于形成NMOS晶体管，沟道层40的材料为Si，牺牲层30的材料为SiGe。在后续去除牺牲层30的过程中，SiGe和Si的刻蚀选择比较高，所以通过将牺牲层30的材料设置为SiGe、将沟道层40的材料设置为Si的做法，能够有效降低牺牲层30的去除工艺对沟道层40的影响，从而提高沟道层40的质量，进而有利于改善器件性能。
本实施例中，所述沟道层40与所述凸起部110的材料相同。在其他实施例中，所述沟道层与凸起部的材料还可以不同。
在其他实施例中，当形成PMOS晶体管时，为提升PMOS晶体管的性能，可采用SiGe沟道技术，沟道层的材料为SiGe，牺牲层的材料为Si。在另一些实施例中，所述沟道层的材料还可以为锗、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。
本实施例中，所述沟道叠层130的数量为多个，多个沟道叠层130的堆叠方向垂直于衬底100表面。作为一种示例，所述沟道叠层130的数量为三个。在其他实施例中，沟道叠层还可以为其他数量，例如：两个、四个、五个等。
所述第一牺牲层30(1)的厚度大于所述第二牺牲层30(2)的厚度，从而在后续去除牺牲层30形成通槽的步骤中，去除第一牺牲层30(1)形成第一通槽、去除第二牺牲层30(2)形成第二通槽，所述第一通槽的高度相应大于第二通槽的高度，以便后续形成填充于通槽内的功函数层的步骤中，填充于第一通槽内的功函数层的厚度，大于填充于第二通槽内的功函数层的厚度。
需要说明的是，所述第一牺牲层30(1)的厚度大于所述第二牺牲层30(2)的厚度，所述第一牺牲层30(1)与第二牺牲层30(2)的厚度差值不宜过小，否则所述后续第一通槽和第二通槽的高度差过小，相应地，填充于第一通槽内的功函数层与填充于第二通槽内的功函数层的厚度差异不明显，功函数层对凸起部所对应的寄生器件的阈值电压调节效果不明显，不利于使得所述寄生器件的阈值电压显著地大于与沟道层对应的器件的阈值电压，对器件的漏电流的减小效果相应也不明显。为此，本实施例中，所述第一牺牲层30(1)的厚度大于1.2倍的所述第二牺牲层30(2)的厚度。
与第二牺牲层30(2)的厚度相比，所述第一牺牲层30(1)的厚度也不宜过大，当第一牺牲层30(1)过厚时，后续形成第二通槽、以及形成填充于第二通槽内的功函数层时，距离凸起部110较远的功函数层材料对寄生器件的沟道的影响越弱，并且还导致第二通槽的高度过大，功函数层不易将第二通槽填充满，而且还容易导致器件的高度过大。
为此，本实施例中，所述第一牺牲层30(1)的厚度，小于或等于3倍的所述第二牺牲层30(2)的厚度。也即，所述第一牺牲层30(1)的厚度，大于1.2倍的所述第二牺牲层30(2)的厚度，且小于或等于3倍的所述第二牺牲层30(2)的厚度。
需要说明的是，本实施例中，所述牺牲层30的材料包括SiGe，且所述第二牺牲层30(2)中的锗浓度大于所述第一牺牲层30(1)中的锗浓度。具体地，本实施例中，与第一牺牲层30(1)相比，第二牺牲层30(2)较薄，后续去除第二牺牲层30(2)的难度相较于去除第一牺牲层30(1)的难度更大，通过使所述第二牺牲层30(2)中的锗浓度大于所述第一牺牲层30(1)中的锗浓度，从而提高第二牺牲层30(2)在后续去除牺牲层30的过程中的去除速率。
继续参考图4和图5，本实施例中，提供基底10后，形成伪栅结构之前，所述半导体结构的形成方法还包括：在所述衬底100上形成围绕所述凸起部110的隔离层115，所述隔离层115暴露出所述沟道叠层130。
所述隔离层115用于隔离相邻的凸起部110，还用于隔离衬底100与栅极结构。本实施例中，隔离层115的材料为氧化硅。隔离层115的材料还可以是其他的绝缘材料，例如：氧化硅、氮化硅、氮氧化硅和氧化锗硅中的一种或多种。
作为一示例，所述隔离层115的顶面低于所述凸起部110的顶面。在其他实施例中，所述隔离层的顶面还可以与所述凸起部的顶面相齐平。
参考图6和图7，图6是基于图4的剖面图，图7是图5沿A-A1方向的剖面图，形成横跨所述沟道叠层130的伪栅结构160。
具体地，所述伪栅结构160形成在所述隔离层110上且横跨所述沟道叠层130；伪栅结构160覆盖沟道叠层130的部分顶部和部分侧壁。伪栅结构160的延伸方向垂直于所述沟道叠层的延伸方向。
所述伪栅结构160用于为后续形成栅极结构预先占据空间位置。
所述伪栅结构160可以为叠层结构或单层结构。本实施例中，所述伪栅结构160为叠层结构，包括伪栅氧化层（图未示）和位于所述伪栅氧化层上的伪栅层（图未示）。具体地，所述伪栅结构160为多晶硅栅极结构，所述伪栅氧化层的材料可以为氧化硅或氮氧化硅，所述伪栅层的材料可以为多晶硅。
本实施例中，在形成所述伪栅结构160之后，所述半导体结构的形成方法还包括：在所述伪栅结构160的侧壁上形成栅极侧墙165。
所述栅极侧墙165用于与伪栅结构160共同作为后续形成凹槽的刻蚀工艺的刻蚀掩膜，以定义源漏掺杂区的形成位置，栅极侧墙165还用于保护伪栅结构160以及后续栅极结构的侧壁。
本实施例中，栅极侧墙165的材料包括氮化硅、氧化硅、氮氧化硅、低k介质材料或超低k介质材料，栅极侧墙165为单层或叠层结构。作为一种示例，栅极侧墙165为单层结构，栅极侧墙165的材料为氮化硅。
参考图8，本实施例中，形成所述伪栅结构160之后，去除伪栅结构160之前，所述半导体结构的形成方法还包括：在所述伪栅结构160两侧的沟道叠层130中形成源漏掺杂区140，所述源漏掺杂区140与所述沟道叠层130中的每一个沟道层40沿延伸方向的端部相接触。
所述源漏掺杂区140用于作为场效应晶体管的源极或漏极，在场效应晶体管工作时，源漏掺杂区140用于提供载流子源。
本实施例中，源漏掺杂区140包括掺杂有离子的应力层，应力层用于为沟道区提供应力，从而提高载流子的迁移率。具体地，当形成NMOS晶体管时，源漏掺杂区140包括掺杂有N型离子的应力层，应力层的材料为Si或SiC；当形成PMOS晶体管时，源漏掺杂区140包括掺杂有P型离子的应力层，应力层的材料为Si或SiGe。
继续参考图8，在所述伪栅结构160露出的隔离层115上形成层间介质层120。层间介质层120覆盖所述栅极侧墙165的侧壁以及所述源漏掺杂区140。
层间介质层120用于隔离相邻器件。本实施例中，层间介质层120的材料为氧化硅。层间介质层120的材料还可以是其他绝缘材料。
参考图9和图10，图9是在栅极开口位置处沿垂直于沟道叠层130延伸方向的剖面示意图，图10是图9沿A-A1方向的剖视图，去除所述伪栅结构160，形成栅极开口170，暴露出所述沟道叠层130。
栅极开口170用于为形成栅极结构提供空间位置。栅极开口170露出沟道叠层130，以便后续通过栅极开口170去除所述沟道叠层130中的牺牲层30。
本实施例中，所述栅极开口170的底部还暴露出所述隔离层115。
具体地，去除所述伪栅结构160的步骤中，在所述层间介质层120中形成所述栅极开口170。
参考图11和图12，图11为基于图9的剖面图，图12为图9沿A-A1方向的剖面图，去除所述沟道叠层130中的牺牲层30，形成通槽180，与所述栅极开口170相连通，所述通槽180包括去除所述第一牺牲层30(1)形成的第一通槽180(1)、以及去除所述第二牺牲层30(2)形成的第二通槽180(2)。
通槽180和栅极开口170共同为形成栅极结构提供空间位置。通槽180与所述栅极开口170相连通。
本实施例中，所述第一牺牲层30(1)的厚度大于所述第二牺牲层30(2)的厚度，在去除第一牺牲层30(1)形成第一通槽180(1)、去除第二牺牲层30(2)形成第二通槽180(2)的步骤中，所述第一通槽180(1)的高度相应大于第二通槽180(2)的高度。
本实施例中，去除牺牲层30后，沟道层40与所述凸起部110之间间隔设置，且相邻的沟道层40之间间隔设置。所述多个间隔设置的沟道层40用于构成沟道结构层200。
本实施例中，所述牺牲层30的材料包括SiGe，去除所述牺牲层30的工艺包括湿法刻蚀工艺。湿法刻蚀工艺具有各向同性刻蚀的特性，便于将各个牺牲层30去除干净。
本实施例中，与第一牺牲层30(1)相比，第二牺牲层30(2)较薄，去除第二牺牲层30(2)的难度相较于去除第一牺牲层30(1)的难度更大，本实施例中通过使所述第二牺牲层30(2)中的锗浓度大于所述第一牺牲层30(1)中的锗浓度，从而提高第二牺牲层30(2)在去除牺牲层30的过程中的被去除速率，并且有利于降低第二牺牲层30(2)产生残留的几率。
具体地，所述湿法刻蚀工艺的刻蚀溶液或刻蚀蒸汽为HCl。
参考图13至图16，图13至图15示出了剖面示意图，图16是图15沿A-A1方向的剖面图，在所述栅极开口170和通槽180内形成栅极结构230，所述栅极结构230包括包围于所述沟道层40的表面且填充于所述通槽180内的功函数层210。
在器件工作时，栅极结构230用于控制导电沟道的开启和关断。本实施例中，所述栅极结构230为金属栅极结构。
功函数层210用于调节栅极结构230的功函数，进而调节场效应晶体管的阈值电压。
其中，当形成NMOS晶体管时，功函数层210的材料为P型功函数材料。也即功函数层210材料的功函数更靠近凸起部110和沟道层40材料的价带顶，从而增大NMOS器件的阈值电压。
当形成PMOS时，功函数层210的材料为N型功函数材料。也即功函数层210材料的功函数更靠近凸起部110和沟道层40材料的导带底，从而增大PMOS器件的阈值电压。
并且，由于所述第一通槽180(1)的高度相应大于第二通槽180(2)的高度，相应地，填充于第一通槽180(1)内的功函数层210的厚度，大于填充于第二通槽180(2)内的功函数层210的厚度，在半导体领域中，在功函数层210材料相同的情况下，通常功函数层210越厚，对器件的阈值电压的调节效果越明显，位于第一通槽180(1)内的功函数层210比位于第二通槽180(2)内的功函数层210更厚，从而和与所述沟道层40对应的器件相比，与凸起部110对应的寄生器件的阈值电压更高，所述寄生器件越更不易开启，进而有利于减小在凸起部110中产生的底部漏电流，提升了半导体结构的性能。
本实施例中，所述凸起部110和沟道层40的材料包括硅；当形成NMOS晶体管时，所述功函数层210材料的功函数为4.5eV至5.5eV。
具体地，当形成NMOS晶体管时，所述功函数层210的材料包括TiN、TaC、MoN、Ta、TaN、TaSiN和TiSiN中的一种或多种。
本实施例中，当形成PMOS晶体管时，所述功函数层210材料的功函数层为3.9eV至4.3eV。具体地，当形成PMOS晶体管时，所述功函数层210的材料包括TiAl、Al、TaAlN、TiAlN、TaCN和AlN中的一种或多种。
本实施例中，形成所述功函数层210的步骤包括：如图13所示，形成包围于所述栅极开口170和通槽180露出的沟道层40表面的功函数膜201，所述功函数膜201填充于所述通槽180；如图14所示，去除位于栅极开口170露出的沟道层40侧壁上、以及最远离衬底100的沟道层40顶部上的部分厚度所述功函数膜201，剩余的所述功函数膜201用于作为所述功函数层210。
通过先形成填充于所述通槽180的功函数膜201，再对位于栅极开口170露出的沟道层40侧壁上、以及最远离衬底100的沟道层40顶部上的功函数膜201进行刻蚀，以保证功函数层210能够将第一通槽180(1)和第二通槽180(2)填充满，同时还有利于保证位于栅极开口170露出的沟道层40侧壁上以及最远离衬底100的沟道层40顶部上的功函数层210厚度满足工艺需求。
作为一种示例，形成所述功函数膜201的工艺包括原子层沉积工艺。原子层沉积工艺的间隙填充能力和保形覆盖能力强，有利于功函数膜201在所述通槽180内的填充，还有利于提高功函数膜201的形成质量。
本实施例中，采用各向同性的刻蚀工艺，去除位于栅极开口170露出的沟道层40侧壁上、以及最远离衬底100的沟道层40顶部上的部分厚度所述功函数膜201。各向同性的刻蚀工艺具有各向同性刻蚀的特性，从而能够对位于栅极开口170露出的沟道层40侧壁上、以及最远离衬底100的沟道层40顶部上的功函数膜201进行刻蚀，以实现对所述位置的功函数膜201的厚度减薄。
本实施例中，所述栅极结构230还包括位于所述功函数层210上且填充所述栅极开口170的栅电极层220。栅电极层220用于作为外接电极，以实现栅极结构230与外部电路或其他互连结构之间的电连接。
本实施例中，所述栅电极层220为金属栅电极，栅电极层220的材料为金属材料，例如：W、Al、Cu、Ag、Au、Pt、Ni或Ti等。
具体地，如图15和图16所示，在形成所述功函数层210之后，在所述功函数层210上形成填充所述栅极开口170的所述栅电极层220。
需要说明的是，所述半导体结构的形成方法还包括：在形成栅极开口170和通槽180之后，在形成栅极结构230之前，在所述栅极开口170和通槽180暴露出的沟道层40的表面形成栅介质层240。
栅介质层240用于实现栅极结构230与导电沟道之间的电隔离。更具体地，本实施例中，栅介质层240用于实现功函数层210与导电沟道之间的电隔离。所述栅介质层240的材料包括氧化硅、掺氮氧化硅、HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2O 3和Al 2O 3中的一种或多种。
本实施例中，所述栅介质层240包括高k栅介质层，高k栅介质层的材料为高k介质材料。高k栅介质层的材料可以选自ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或Al 2O 3。在其他实施例中，所述栅介质层还可以包括栅氧化层和位于所述栅氧化层上的高k栅介质层。
还需要说明的是，在具体实施中，所述栅极结构230还可以包括：覆盖层（图未示），位于所述功函数层210与所述栅介质层240之间；阻挡层（图未示），位于所述功函数层210上。
所述栅电极层220相应位于所述阻挡层上。在另一些实施例中，所述栅极结构还可以不包括所述覆盖层和阻挡层。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括：
    衬底；
    位于所述衬底上的围栅晶体管，所述围栅晶体管包括：分立于衬底上的凸起部以及与所述凸起部间隔悬空设置的沟道结构层，所述沟道结构层包括多个依次间隔设置的沟道层，所述沟道层沿垂直于衬底表面的方向竖直堆叠，且沿垂直于衬底表面的方向，所述凸起部和与所述凸起部相邻的沟道层之间的距离，大于相邻的所述沟道层之间的距离；
    栅极结构，横跨所述沟道结构层且包围所述沟道结构层中每一个所述沟道层；所述栅极结构包括包围于所述沟道层表面的功函数层，所述功函数层填充于所述凸起部和与所述凸起部相邻的沟道层之间、以及相邻的所述沟道层之间；其中，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料；当形成PMOS晶体管时，所述功函数层的材料为N型功函数材料；
    栅介质层，位于所述栅极结构与所述沟道层之间、以及所述栅极结构与所述凸起部之间；
    源漏掺杂区，位于所述栅极结构两侧的凸起部上且与所述沟道结构层中的每一个沟道层沿延伸方向的端部相接触。
  2. 如权利要求1所述的半导体结构，其特征在于，所述沟道层与所述凸起部的材料相同。
  3. 如权利要求1或2所述的半导体结构，其特征在于，沿垂直于衬底表面的方向，所述凸起部和与所述凸起部相邻的沟道层之间的距离为第一距离，相邻的所述沟道层之间的距离为第二距离；所述第一距离大于或等于1.2倍的所述第二距离，且小于或等于3倍的所述第二距离。
  4. 如权利要求1所述的半导体结构，其特征在于，所述凸起部和沟道层的材料包括硅；当形成NMOS晶体管时，所述功函数层材料的功函数为4.5eV至5.5eV；
    当形成PMOS晶体管时，所述功函数层材料的功函数为3.9eV至4.3eV。
  5. 如权利要求1所述的半导体结构，其特征在于，当形成NMOS晶体管时，所述功函数层的材料包括TiN、TaC、MoN、Ta、TaN、TaSiN和TiSiN中的中的一种或多种；
    当形成PMOS晶体管时，所述功函数层的材料包括TiAl、Al、TaAlN、TiAlN、TaCN和AlN中的一种或多种。
  6. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：隔离层，位于所述衬底上且围绕所述凸起部；层间介质层，位于所述栅极结构侧部的隔离层上；所述栅极结构位于所述隔离层上且横跨所述沟道结构层；
    所述栅极结构位于相邻的沟道层之间、以及位于凸起部和与凸起部相邻的沟道层之间的部分作为第一部分，所述栅极结构横跨所述沟道结构层的部分作为第二部分；
    沿所述沟道结构层的延伸方向，所述第一部分和第二部分的侧壁相对于所述沟道层的端部缩进；
    所述半导体结构还包括：内侧墙，位于所述第一部分的侧壁上且暴露出所述沟道结构层沿延伸方向的端部；栅极侧墙，位于所述第二部分的侧壁上且暴露出所述沟道结构层沿延伸方向的端部；
    所述源漏掺杂区位于所述栅极结构、栅极侧墙和内侧墙的两侧。
  7. 如权利要求1所述的半导体结构，其特征在于，所述沟道结构层与沟道结构层之间的距离，大于所述沟道结构层中的沟道层与沟道层之间的距离。
  8. 如权利要求1所述的半导体结构，其特征在于，所述栅极结构还包括：覆盖层，位于所述功函数层与所述栅介质层之间；阻挡层，位于所述功函数层上；栅电极层，位于所述阻挡层上。
  9. 如权利要求1或2所述的半导体结构，其特征在于，所述衬底的材料包括：单晶硅、锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种；
    所述沟道层和所述凸起部的材料包括：单晶硅、锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种；
    所述栅介质层的材料包括：HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2O 3、Al 2O 3、氧化硅和掺氮氧化硅中的一种或多种。
  10. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底，用于形成MOS晶体管，所述基底包括衬底、分立于衬底上的凸起部以及位于所述凸起部上的多个堆叠的沟道叠层，每个所述沟道叠层包括牺牲层和位于所述牺牲层上的沟道层；位于所述凸起部和与凸起部相邻的所述沟道层之间的牺牲层用于作为第一牺牲层，位于所述第一牺牲层上方的所述沟道叠层中的牺牲层用于作为第二牺牲层，所述第一牺牲层的厚度大于所述第二牺牲层的厚度；
    形成横跨所述沟道叠层的伪栅结构；
    在所述伪栅结构两侧的沟道叠层中形成源漏掺杂区，所述源漏掺杂区与所述沟道叠层中的每一个沟道层沿延伸方向的端部相接触；
    在形成所述源漏掺杂区后，去除所述伪栅结构，形成栅极开口，暴露出所述沟道叠层；
    去除所述沟道叠层中的牺牲层，形成通槽，与所述栅极开口相连通，所述通槽包括去除所述第一牺牲层形成的第一通槽、以及去除所述第二牺牲层形成的第二通槽；
    在所述栅极开口和通槽内形成栅极结构，所述栅极结构包括包围于所述沟道层的表面且填充于所述通槽内的功函数层；其中，当形成NMOS晶体管时，所述功函数层的材料为P型功函数材料；当形成PMOS晶体管时，所述功函数层的材料为N型功函数材料。
  11. 如权利要求10所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述沟道层与所述凸起部的材料相同。
  12. 如权利要求10或11所述的半导体结构的形成方法，其特征在于，所述第一牺牲层的厚度，大于或等于1.2倍的所述第二牺牲层的厚度，且小于或等于3倍的所述第二牺牲层的厚度。
  13. 如权利要求10所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述牺牲层的材料包括SiGe，且所述第二牺牲层中的锗浓度大于所述第一牺牲层中的锗浓度。
  14. 如权利要求10所述的半导体结构的形成方法，其特征在于，形成所述功函数层的工艺包括原子层沉积工艺。
  15. 如权利要求10所述的半导体结构的形成方法，其特征在于，所述凸起部和沟道层的材料包括硅；当形成NMOS晶体管时，所述功函数层材料的功函数为4.5eV至5.5eV；
    当形成PMOS晶体管时，所述功函数层材料的功函数为3.9eV至4.3eV。
  16. 如权利要求10所述的半导体结构的形成方法，其特征在于，所述牺牲层的材料包括SiGe，去除所述牺牲层的工艺包括湿法刻蚀工艺。
  17. 如权利要求10所述的半导体结构的形成方法，其特征在于，提供基底后，形成伪栅结构之前，所述半导体结构的形成方法还包括：在所述衬底上形成围绕所述凸起部的隔离层，所述隔离层暴露出所述沟道叠层；
    形成所述源漏掺杂区之后，去除伪栅结构之前，所述半导体结构的形成方法还包括：在所述伪栅结构露出的隔离层上形成层间介质层，所述层间介质层覆盖所述源漏掺杂区；
    去除所述伪栅结构的步骤中，在所述层间介质层中形成所述栅极开口。
  18. 如权利要求10所述的半导体结构的形成方法，其特征在于，形成所述功函数层的步骤包括：形成包围于所述栅极开口和通槽露出的沟道层表面的功函数膜，所述功函数膜填充于所述通槽；去除位于栅极开口露出的沟道层侧壁上、以及最远离衬底的沟道层顶部上的部分厚度所述功函数膜，剩余的所述功函数膜用于作为所述功函数层。
  19. 如权利要求10所述的半导体结构的形成方法，其特征在于，所述半导体结构的形成方法还包括：在形成栅极开口和通槽之后，在形成栅极结构之前，在所述栅极开口和通槽暴露出的沟道层的表面形成栅介质层。
  20. 如权利要求10所述的半导体结构的形成方法，其特征在于，所述栅极结构还包括位于所述功函数层上且填充所述栅极开口的栅电极层。
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