WO2023010632A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2023010632A1
WO2023010632A1 PCT/CN2021/115284 CN2021115284W WO2023010632A1 WO 2023010632 A1 WO2023010632 A1 WO 2023010632A1 CN 2021115284 W CN2021115284 W CN 2021115284W WO 2023010632 A1 WO2023010632 A1 WO 2023010632A1
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WIPO (PCT)
Prior art keywords
layer
light
display panel
display area
dummy
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PCT/CN2021/115284
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English (en)
French (fr)
Inventor
杨程
江盼
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/605,497 priority Critical patent/US20240049521A1/en
Publication of WO2023010632A1 publication Critical patent/WO2023010632A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • CUP Camera Under Panel
  • the screen using the under-screen camera technology can divide the display area into an under-screen camera area and a normal display area. These two areas have different structural designs and pixel designs. However, in the current technology, due to the different structural design of the camera area under the screen and the normal display area, the circuit routing and process of the two areas are different, which leads to the electrical and normal display of the driving device located in the camera area under the screen. The area is different, resulting in uneven display in the camera area under the screen.
  • the purpose of the present application is to provide a display panel and its preparation method, which is used to solve the problem that in the prior art, the electricity of the drive device located in the imaging area under the screen is different from that in the normal display area, resulting in uneven display in the imaging area under the screen. technical problems.
  • the present application provides a display panel, the display panel is defined with a first display area and a second display area, and the display panel includes: a substrate; a driving device layer, the driving device layer is arranged on the On the substrate and including a plurality of thin film transistors; and a light emitting device layer, the light emitting device layer is arranged on the driving device layer and includes a plurality of light emitting sub-pixels arranged in an array;
  • the driving device layer is further provided with a dummy through hole located within the range of the orthographic projection of at least one of the light-emitting sub-pixels on the substrate, and the dummy through hole is connected to the At least one light-emitting sub-pixel is insulated from each other.
  • the thin film transistor in the second display area, is disposed on an edge of the second display area close to the first display area.
  • the thin film transistor and the dummy via are arranged in the same layer.
  • the thin film transistor includes: an active layer, the active layer is disposed on the substrate; a first insulating layer, the first insulating layer covers the active layer; a first a metal layer, the first metal layer is disposed on the first insulating layer; a second insulating layer, the second insulating layer is disposed on the first metal layer; and a second metal layer, the second The metal layer is disposed on the second insulating layer and patterned to form a source electrode and a drain electrode, and the source electrode and the drain electrode respectively pass through the first through hole and the second insulating layer through the first insulating layer and the second insulating layer.
  • the second through hole is electrically connected with the active layer;
  • the dummy via hole is disposed in the same layer as the first via hole and the second via hole.
  • the number of dummy through holes located within the range of the orthographic projection of the at least one light-emitting sub-pixel on the substrate is greater than or equal to one.
  • the shape of the dummy via hole includes at least one of rectangle and circle.
  • the light-emitting sub-pixels have different sizes, and the number of the dummy via holes is proportional to the size of the light-emitting sub-pixels.
  • the driving device layer in the first display area, is provided with a through hole corresponding to the light-emitting sub-pixel, and the through-hole is electrically connected to the light-emitting sub-pixel;
  • the density of the dummy via holes in the second display area is equal to the density of the via holes in the first display area.
  • the display panel further includes an organic planar layer, the organic planar layer is disposed between the driving device layer and the light emitting device layer, and the organic planar layer fills through the first insulation layer and the dummy vias of the second insulating layer.
  • the present application also provides a method for preparing a display panel, the display panel is defined with a first display area and a second display area, and the preparation method includes the following steps:
  • a substrate is provided; a driving device layer is formed on the substrate, and the driving device layer includes a plurality of thin film transistors; and a light emitting device layer is formed on the driving device layer, and the light emitting device layer includes a plurality of light-emitting sub-pixels;
  • the driving device layer is further provided with dummy through holes located within the range of the orthographic projection of each of the light-emitting sub-pixels on the substrate, and the dummy through holes are connected to the The light-emitting sub-pixels are insulated from each other.
  • the present application also provides a method for preparing a display panel, the display panel is defined with a first display area and a second display area, wherein the preparation method includes the following steps:
  • a substrate form a driving device layer on the substrate, wherein the driving device layer includes a plurality of thin film transistors; and form a light emitting device layer on the driving device layer, wherein the light emitting device layer includes a plurality of array rows Light-emitting sub-pixels of cloth;
  • the driving device layer is further provided with a dummy through hole located within the range of the orthographic projection of at least one of the light-emitting sub-pixels on the substrate, and the dummy through hole is connected to at least one The light-emitting sub-pixels are insulated from each other.
  • the thin film transistor in the second display area, is disposed on an edge of the second display area close to the first display area.
  • the thin film transistor and the dummy via are arranged in the same layer.
  • the step of forming the driving device layer on the substrate includes sequentially disposing an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer on the substrate. layer, wherein the second metal layer is patterned to form a source and a drain; the dummy vias in the display area;
  • the source and the drain are electrically connected to the active layer through the first through hole and the second through hole respectively.
  • the step of forming the driving device layer on the substrate further includes: forming an organic planar layer on the second metal layer.
  • the number of dummy through holes located within the range of the orthographic projection of the at least one light-emitting sub-pixel on the substrate is greater than or equal to one.
  • the light-emitting sub-pixels have different sizes, and the number of the dummy via holes is proportional to the size of the light-emitting sub-pixels.
  • the driving device layer in the first display area, is provided with a through hole corresponding to the light-emitting sub-pixel, and the through-hole is electrically connected to the light-emitting sub-pixel;
  • the density of the dummy via holes in the second display area is equal to the density of the via holes in the first display area.
  • the organic planarization layer fills the dummy via holes penetrating through the first insulating layer and the second insulating layer.
  • the dummy vias are filled with non-conductive substances.
  • a dummy through hole is provided in the second display region within the range of the orthographic projection of at least one of the light-emitting sub-pixels on the substrate, and the dummy through hole is connected to at least one One of the light-emitting sub-pixels is insulated from each other.
  • the setting of the dummy via holes can enable the driving device layer to have a uniform opening density in the second display area, so that impurity elements such as hydrogen can be uniformly removed in the annealing process, so as to ensure that the first The thin film transistors in the two display areas can have uniform electrical properties, thereby improving the phenomenon of uneven display.
  • FIG. 1 is a schematic plan view of a display panel in an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of a display panel in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the shape of a light-emitting sub-pixel in an embodiment of the present application
  • FIG. 4 is a schematic diagram of a pseudo-via in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another dummy via in the embodiment of the present application.
  • FIG. 6 is a schematic diagram of yet another dummy via in the embodiment of the present application.
  • FIG. 7 is a flowchart of a method for manufacturing a display panel in an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • the present application provides a display panel 100, more specifically an organic light emitting diode (Organic Light-Emitting Diode, OLED) display panel.
  • the display panel 100 defines a first display area AA and a second display area TA.
  • the first display area AA can be a normal display area
  • the second display area TA can be a screen Lower camera area (CUP area).
  • the second display area TA which is the under-screen camera area (CUP area), has a large area of transparent area to achieve sufficient light transmittance for the camera to capture images in the camera mode.
  • the display panel 100 includes a substrate 10 , a driving device layer 3 and a light emitting device layer 60 .
  • the substrate 10 may be a glass substrate or a flexible substrate, which is not particularly limited in this application.
  • the driving device layer 3 is disposed on the substrate 10 and includes a plurality of thin film transistors 30 ; the light emitting device layer 60 is disposed on the driving device layer 3 and includes a plurality of light emitting sub-pixels 605 arranged in an array.
  • the display panel 100 is further provided with a buffer layer 20 between the driving device layer 3 and the substrate 10 .
  • the driving device layer 3 is further provided with a dummy through hole 103 located within the range of the orthographic projection of at least one of the light-emitting sub-pixels 605 on the substrate 10, the dummy through hole 103
  • the through hole 103 and the at least one light-emitting sub-pixel 605 are insulated from each other.
  • through holes are provided and filled with conductive substances, so as to electrically connect the upper and lower metal layers, and then conduct electronic components.
  • the dummy via holes of the present application are filled with non-conductive substances, and thus have the property of being insulated from electronic components.
  • the non-conductive substance may include an organic flat layer material, which has excellent flatness and light transmittance.
  • the setting of the dummy via holes 103 can enable the driving device layer 3 to have a uniform opening density in the second display area TA while maintaining flatness and a large area of transparent area, so as to facilitate the annealing process.
  • Impurity elements such as hydrogen can be uniformly removed during the process, so as to ensure that the thin film transistors 30 in the second display area TA can have uniform electrical properties, thereby improving the display unevenness of the display panel 100 .
  • the dummy via 103 and the at least one light-emitting sub-pixel 605 are insulated from each other, so that the dummy via 103 does not affect the second display when improving the electrical properties of the second display area TA. The display effect of area TA.
  • the dummy via holes 103 are located within the range of the orthographic projection of each of the light-emitting sub-pixels 605 on the substrate 10 , so as to make the hole density more uniform.
  • the sizes of the plurality of dummy via holes 103 may be the same or different, as long as the second display area TA has a uniform opening density.
  • the thin film transistor 30 is disposed on the edge of the second display area TA close to the first display area AA. It can be understood that, in the second display area TA, by disposing the thin film transistor 30 at the edge of the second display area TA close to the first display area AA, the thin film transistor can be 30 and the lines connecting the thin film transistor 30 (such as gate lines or data lines, etc.) only occupy a small part of the area of the second display area TA, so that the second display area TA can further have a larger In order to achieve sufficient light transmittance for the camera to capture images when in the camera mode.
  • the thin film transistor 30 and the dummy via hole 103 are arranged in the same layer.
  • the driving device layer 3 is provided with through holes corresponding to the light-emitting sub-pixels 605, and the through holes are electrically connected to the light-emitting sub-pixels 605;
  • the density of the dummy via holes 103 in the second display area TA is equal to the density of the via holes in the first display area AA.
  • the thin film transistor 30 includes an active layer 301 , a first insulating layer 302 , a first metal layer 303 , a second insulating layer 306 and a second metal layer 307 .
  • the active layer 301 is disposed on the substrate 10; the first insulating layer 302 covers the active layer 301; the first metal layer 303 is disposed on the first insulating layer 302 and forms The first gate; the second insulating layer 306 is disposed on the first metal layer 303; the second metal layer 307 is disposed on the second insulating layer 306 and patterned to form a source 3071 and a drain 3072, the source 3071 and the drain 3072 are electrically connected to the active layer 301 through the first through hole 101 and the second through hole 102 penetrating through the first insulating layer 302 and the second insulating layer 306 respectively. connect.
  • the through holes corresponding to the light-emitting sub-pixels 605 include the first through holes 101 and the second through
  • the dummy via 103 is disposed in the same layer as the first via 101 and the second via 102 .
  • the dummy via 103 By arranging the dummy via 103 on the same layer as the first via 101 and the second via 102, the dummy via 103 where the dummy via 103 is located and the first via
  • the hole 101 and the second through hole 102 are simultaneously formed in the same hole opening process without an additional hole opening process, and no additional preparation process is required when forming the dummy via hole 103, so the preparation process can be simplified And reduce the preparation cost.
  • the present application sets the density of the dummy via holes 103 in the second display area TA to be equal to the density of the via holes in the first display area AA, ensuring that the second display area On the premise that TA has a uniform opening density, it can also ensure that the first display area AA and the second display area TA have a uniform opening density, thereby improving the overall display uniformity of the display panel 100 .
  • the thin film transistor 30 further includes a third insulating layer 304 and a third metal layer 305 .
  • the third insulating layer 304 is disposed between the first insulating layer 302 and the second insulating layer 306 and covers the first metal layer 303, and the third metal layer 305 is disposed on the third insulating layer 306.
  • Layer 304 and covered by the second insulating layer 306, the third metal layer 305 is formed with a second gate, the second gate and the first gate can form a capacitance to further prevent the The thin film transistor 30 leaks electricity.
  • the source electrode 3071 and the drain electrode 3072 respectively pass through the first through hole 101 and the second insulating layer 302, the third insulating layer 304 and the second insulating layer 306.
  • the second via hole 102 is electrically connected to the active layer 301 .
  • the dummy via 103 can also be formed through the first insulating layer 302, the third insulating layer 304 and the second insulating layer 306, so that the dummy via 103 and the first via
  • the hole 101 and the second through hole 102 are simultaneously formed in the same hole opening process without an additional hole opening process, and no additional preparation process is required when forming the dummy via hole 103, so the preparation process can be simplified And reduce the preparation cost.
  • the display panel 100 also includes an organic planar layer 40, the organic planar layer 40 is disposed between the driving device layer 3 and the light emitting device layer 60, and the dummy via hole 103 can be directly formed by the The organic planarization layer 40 fills the dummy vias 103 .
  • additional manufacturing processes can be omitted, thus simplifying the manufacturing process and reducing manufacturing costs.
  • the driving device layer 3 includes the active layer 301, the first insulating layer 302, the first metal layer 303, the second insulating layer 306, the second metal layer 307 , the third insulating layer 304 and the third metal layer 305 .
  • the first insulating layer 302, the third insulating layer 304 and the second insulating layer 306 can be inorganic insulating layers, and the second insulating layer 306 can be used to improve stress and supplement hydrogen source to further repair the TFT trench Road defects, improve electrical properties.
  • the display panel 100 further includes a transparent metal layer 50, the transparent metal layer 50 is arranged between the organic planar layer 40 and the light emitting device layer 60, and passes through the organic planar layer 40 through the first
  • the three vias 104 are electrically connected to the drain 3072 .
  • the material of the transparent metal layer 50 may be indium tin oxide (ITO).
  • the transparent metal layer 50 is patterned to form a transparent metal line 501, and the transparent metal line 501 extends from a position corresponding to the light-emitting sub-pixel 605 below to a corresponding
  • the thin film transistor 30 is located above the edge of the second display area TA, and the thin film transistor 30 is electrically connected to the light-emitting sub-pixel 605 through the transparent metal line 501 .
  • the present application uses the transparent metal line 501 to electrically connect the light-emitting sub-pixel 605 and the thin film transistor 30 located at the edge of the second display area TA, thereby achieving the desired results. While the light-emitting sub-pixel 605 is electrically connected to the thin film transistor 30, the second display area TA can also maintain a large area of transparent area, so as to achieve sufficient transparency in the imaging mode state. Luminosity provides a camera to capture images.
  • the organic planar layer 40 includes a first organic planar layer 41 and a second organic planar layer 42, the second organic planar layer 42 is disposed on the second insulating layer 306, the The first organic planar layer 41 is disposed on the second organic planar layer 42, and the display panel 100 further includes a fourth metal layer 80 disposed on the first organic planar layer 41 and the second organic planar layer 42. between.
  • the material of the fourth metal layer 80 may be indium zinc oxide (IZO).
  • the fourth metal layer 80 is electrically connected to the transparent metal layer 50 and the drain 3072 , specifically, the transparent metal layer 50 is connected to the drain 3072 through the third via hole 104
  • the fourth metal layer 80 is electrically connected, and the fourth metal layer 80 is electrically connected to the drain 3072 through the fourth via hole 105 .
  • the light emitting device layer 60 may specifically include an anode 601 , a pixel definition layer 602 , a light emitting material layer 603 and a cathode 604 .
  • the light-emitting sub-pixel 605 is located in the opening area of the pixel definition layer 602 and includes the anode 601 and the light-emitting material layer 603, and the cathode 604 covers the light-emitting sub-pixel 605 and the pixel definition Layer 602.
  • the material of the anode 601 may be ITO/Ag/ITO.
  • the light-emitting sub-pixel 605 includes a first red sub-pixel unit R1, a first green sub-pixel unit G1, and a first blue sub-pixel unit B1, wherein the first red sub-pixel unit
  • the pixel unit R1 is used to emit red light
  • the first green sub-pixel unit G1 is used to emit green light
  • the first blue sub-pixel unit B1 is used to emit blue light.
  • the light-emitting sub-pixel 605 includes a second red sub-pixel unit R2, a second green sub-pixel unit G2, and a second blue sub-pixel unit B2, wherein the second red sub-pixel unit
  • the pixel unit R2 is used to emit red light
  • the second green sub-pixel unit G2 is used to emit green light
  • the second blue sub-pixel unit B2 is used to emit blue light.
  • the first red sub-pixel unit R1, the first green sub-pixel unit G1 and the first blue sub-pixel unit are all rectangular, the light-emitting area of the first blue sub-pixel unit B1 is larger than the light-emitting area of the first red sub-pixel unit R1 and the first green sub-pixel unit G1, and the first red sub-pixel unit The light emitting area of the sub-pixel unit R1 is larger than the light emitting area of the first green sub-pixel unit G1.
  • the shapes of the first red sub-pixel unit R1, the first green sub-pixel unit G1 and the first blue sub-pixel unit B1 are not limited to rectangles, and may also be based on the first display The shape of the area AA to correspond to the setting.
  • the light-emitting area of the first blue sub-pixel unit B1 can be set to the maximum, and set the light emitting area of the first green sub-pixel unit G1 to the minimum, so that the first red sub-pixel unit R1, the first green sub-pixel unit G1 and the first blue The luminance of the sub-pixel unit B1 is more uniform.
  • the second red sub-pixel unit R2, the second green sub-pixel unit G2 and the second blue sub-pixel unit B2 are all circular, and the second blue sub-pixel unit
  • the light-emitting area of the color sub-pixel unit B2 is larger than the light-emitting area of the second red sub-pixel unit R2 and the second green sub-pixel unit G2, and the light-emitting area of the second red sub-pixel unit R2 is larger than the second The light emitting area of the green sub-pixel unit G2.
  • the shape of the second red sub-pixel unit R2, the second green sub-pixel unit G2 and the second blue sub-pixel unit B2 is limited to a circle, so that the second red sub-pixel unit The area of the pixel unit R2, the second green sub-pixel unit G2 and the second blue sub-pixel unit B2 is minimized to further increase the light transmittance, so that the second display area TA has a larger area The transparent area, in order to achieve sufficient light transmittance for the camera to capture images when in the camera mode.
  • the light-emitting area of the second blue sub-pixel unit B2 can be Set to the maximum, and set the light emitting area of the second green sub-pixel unit G2 to the minimum, so that the second red sub-pixel unit R2, the second green sub-pixel unit G2 and the second blue The luminance of the sub-pixel unit B2 is more uniform.
  • the number of dummy through holes 103 located within the range of the orthographic projection of at least one of the light-emitting sub-pixels 605 on the substrate 10 is greater than or equal to 1.
  • the shape of the dummy via 103 includes at least one of rectangle and circle.
  • the light-emitting sub-pixels 605 have different sizes, and the number of the dummy vias 103 is proportional to the size of the light-emitting sub-pixels 605 .
  • the size of the second blue sub-pixel unit B2 is larger than that of the second red sub-pixel unit R2, and the size of the second red sub-pixel unit R2 is larger than that of the second green sub-pixel unit G2 ;
  • the number of dummy through holes 103 corresponding to the second red sub-pixel unit R2 is 5, and the number of dummy through holes 103 corresponding to the second green sub-pixel unit G2 is 3, corresponding to The number of dummy via holes 103 in the second blue sub-pixel unit B2 is 7, and the shape of the dummy via holes 103 is a rectangle.
  • the number of the dummy through holes 103 is set to be proportional to the size of the light-emitting sub-pixels 605 , it can further ensure that the second display area TA has a uniform hole density.
  • the only difference from FIG. 4 is that the shape of the dummy via hole 103 is circular.
  • the only difference from FIG. 4 is that the number of dummy via holes 103 corresponding to the second red sub-pixel unit R2 is 7, corresponding to the The number of dummy through holes 103 in the second green sub-pixel unit G2 is four, and the number of dummy through holes 103 corresponding to the second blue sub-pixel unit B2 is ten.
  • the number of the dummy through holes 103 located within the range of the orthographic projection of the at least one light-emitting sub-pixel 605 on the substrate 10 is not limited, and can be set according to specific requirements. It is only necessary to ensure uniform opening density in the second display area TA so that impurity elements such as hydrogen can be uniformly removed in the annealing process. Therefore, it is ensured that the thin film transistors 30 in the second display area TA can have uniform electrical properties, thereby improving the display unevenness of the display panel 100 .
  • the shape of the dummy via 103 may include a rectangle or a circle, which may be set according to specific requirements.
  • the display panel 100 further includes a thin film encapsulation layer 70 for isolating external water and oxygen to prevent the display panel 100 from failing.
  • the present application further provides a method for preparing the above-mentioned display panel 100, and the method for preparing includes the following steps:
  • the light-emitting device layer 60 includes a plurality of light-emitting sub-pixels 605 arranged in an array; wherein, in the second display area TA, the driving device The layer 3 is further provided with a dummy via hole 103 located within the range of the orthographic projection of the at least one light-emitting sub-pixel 605 on the substrate 10 , and the dummy through-hole 103 is insulated from the at least one light-emitting sub-pixel 605 .
  • through holes are provided and filled with conductive substances, so as to electrically connect the upper and lower metal layers, and then conduct electronic components.
  • the dummy via holes of the present application are filled with non-conductive substances, and thus have the property of being insulated from electronic components.
  • the non-conductive substance may include an organic flat layer material, which has excellent flatness and light transmittance.
  • the manufacturing method of the display panel described in this application can enable the driving device layer 3 to have a flatness and a large transparent area in the second display area TA by setting the dummy via hole 103.
  • Uniform opening density so that impurity elements such as hydrogen can be uniformly removed in the annealing process, so as to ensure that the thin film transistors 30 in the second display area TA can have uniform electrical properties, thereby improving the display quality of the display panel 100. average phenomenon.
  • the dummy via 103 and the at least one light-emitting sub-pixel 605 are insulated from each other, so that the dummy via 103 does not affect the second display when improving the electrical properties of the second display area TA. The display effect of area TA.
  • the preparation method further includes S11: forming a buffer layer 20 on the substrate 10.
  • Described step S20 specifically comprises the following steps:
  • S201 sequentially disposing an active layer 301, a first insulating layer 302, a first metal layer 303, a third insulating layer 304, the third metal layer 305, and a second insulating layer 306 on the buffer layer 20;
  • S203 Forming a second metal layer 307 on the second insulating layer 306, the second metal layer 307 is patterned to form a source electrode 3071 and a drain electrode 3072, and the source electrode 3071 and the drain electrode 3072 respectively pass through the second metal layer 307 A through hole 101 and the second through hole 102 are electrically connected to the active layer 301 .
  • the dummy through hole 103 can be formed simultaneously with the first through hole 101 and the second through hole 102 in the same hole opening process without an additional hole opening process, and then the dummy hole 103 can be formed in the formation of the dummy hole. No additional manufacturing process is required for the through hole 103 , so the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the preparation method further includes S21: forming an organic planar layer 40 on the second metal layer 307.
  • the dummy vias 103 can be directly filled by the organic planarization layer 40 .
  • additional manufacturing processes can be omitted, thereby simplifying the manufacturing process and reducing manufacturing costs.
  • the preparation method further includes S22 after the step S21: forming a transparent metal layer 50 on the organic planar layer 40, wherein, in the second display area TA, the transparent metal layer 50 is patterned and formed with A transparent metal line 501, the transparent metal line 501 extends from a position corresponding to the lower side of the light-emitting sub-pixel 605 to a position corresponding to the upper side of the thin film transistor 30 located at the edge of the second display area TA, and the thin film transistor 30
  • the transparent metal circuit 501 is electrically connected to the light-emitting sub-pixel 605 .
  • the present application uses the transparent metal line 501 to electrically connect the light-emitting sub-pixel 605 and the thin film transistor 30 located at the edge of the second display area TA, thereby achieving the desired results. While the light-emitting sub-pixel 605 is electrically connected to the thin film transistor 30, the second display area TA can also maintain a large area of transparent area, so as to achieve sufficient transparency in the imaging mode state. Luminosity provides a camera to capture images.
  • the preparation method further includes S40: forming a thin film encapsulation layer 70 on the light emitting device layer 60 .
  • each layer can refer to the above-mentioned display panel 100 , which will not be repeated in this preparation method.

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Abstract

一种显示面板（100）及其制备方法。显示面板（100）包括定义有第一显示区（AA）及第二显示区（TA），且包括：基板（10）、驱动器件层（3）及发光器件层（60）。在第二显示区（TA）中，驱动器件层（3）还设置有位于至少一发光子像素（605）在基板（10）上的正投影范围内的伪通孔（103），伪通孔（103）与至少一发光子像素（605）彼此绝缘设置。显示面板（100）可以保证第二显示区（TA）中的薄膜晶体管（30）具有均一的电性，进而改善显示不均的现象。

Description

显示面板及其制备方法
本申请要求于2021年08月05日提交中国专利局、申请号为202110897314.6、发明名称为“显示面板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及其制备方法。
 背景技术
近年来，智能手机进入“全面屏”时代，追求极致的高屏占比成为新的发展趋势。因此，屏下摄像（Camera Under Panel，CUP）技术应运而生。CUP技术是将摄像头置于屏幕下方，该区域称为屏下摄像区（CUP区），此技术在实现全屏显示的同时还能做到屏下摄像功能，是全面屏的终极解决方案。
应用屏下摄像技术的屏幕可将显示区域分为屏下摄像区及正常显示区，此两区有不同的结构设计和像素设计。然而在目前的技术中，由于屏下摄像区和正常显示区有着不同的结构设计，导致这两区的电路走线和工艺不同，进而导致位于屏下摄像区的驱动器件的电性和正常显示区不同，使得屏下摄像区出现显示不均的现象。
因此，急需改善屏下摄像区的驱动器件的电性，以提升屏下摄像区和正常显示区的电性均一性，进而改善显示不均的现象。
 技术问题
在目前的技术中，由于屏下摄像区和正常显示区有着不同的结构设计，导致这两区的电路走线和工艺不同，进而导致位于屏下摄像区的驱动器件的电性和正常显示区不同，使得屏下摄像区出现显示不均的现象。
 技术解决方案
本申请的目的在于，提供一种显示面板及其制备方法，用于解决现有技术中，位于屏下摄像区的驱动器件的电性和正常显示区不同，使得屏下摄像区出现显示不均的技术问题。
为了解决上述问题，本申请提供一种显示面板，所述显示面板定义有第一显示区及第二显示区，且所述显示面板包括：基板；驱动器件层，所述驱动器件层设置在所述基板上且包括多个薄膜晶体管；及发光器件层，所述发光器件层设置在所述驱动器件层上且包括多个阵列排布的发光子像素；
其中，在所述第二显示区中，所述驱动器件层还设置有位于至少一所述发光子像素在所述基板上的正投影范围内的伪通孔，所述伪通孔与所述至少一发光子像素彼此绝缘设置。
在一些实施例中，在所述第二显示区中，所述薄膜晶体管设置在所述第二显示区靠近所述第一显示区的边缘。
在一些实施例中，所述薄膜晶体管与所述伪通孔同层设置。
在一些实施例中，所述薄膜晶体管包括:有源层，所述有源层设置在所述基板上；第一绝缘层，所述第一绝缘层覆盖在所述有源层上；第一金属层，所述第一金属层设置在所述第一绝缘层上；第二绝缘层，所述第二绝缘层设置在所述第一金属层上；及第二金属层，所述第二金属层设置在所述第二绝缘层上并图案化形成源极及漏极，所述源极及漏极分别通过贯穿所述第一绝缘层与所述第二绝缘层的第一通孔及第二通孔与所述有源层电性连接；
其中，所述伪通孔与所述第一通孔及所述第二通孔同层设置。
在一些实施例中，位于所述至少一发光子像素在所述基板上的正投影范围内的伪通孔的数量大于等于1。
在一些实施例中，所述伪通孔的形状包括矩形或圆形中的至少一种。
在一些实施例中，所述发光子像素具有不同尺寸大小，所述伪通孔的数量与所述发光子像素的尺寸大小成正比。
在一些实施例中，在所述第一显示区中，所述驱动器件层设置有对应所述发光子像素的通孔，所述通孔与所述发光子像素电性连接；
其中，所述伪通孔在所述第二显示区中的密度与所述通孔在所述第一显示区中的密度相等。
在一些实施例中，所述显示面板还包括有机平坦层，所述有机平坦层设置于所述驱动器件层及所述发光器件层之间，且所述有机平坦层填充贯穿所述第一绝缘层与所述第二绝缘层的所述伪通孔。
本申请还提供一种显示面板的制备方法，所述显示面板定义有第一显示区及第二显示区，所述制备方法包括下列步骤:
提供一基板；在所述基板上形成驱动器件层，所述驱动器件层包括多个薄膜晶体管；及在所述驱动器件层上形成发光器件层，所述发光器件层包括多个阵列排布的发光子像素；
其中，在所述第二显示区中，所述驱动器件层还设置有位于每一所述发光子像素在所述基板上的正投影范围内的伪通孔，所述伪通孔与所述发光子像素彼此绝缘设置。
本申请还提供一种显示面板的制备方法，所述显示面板定义有第一显示区及第二显示区，其中，所述制备方法包括下列步骤:
提供一基板；在所述基板上形成驱动器件层，其中所述驱动器件层包括多个薄膜晶体管；及在所述驱动器件层上形成发光器件层，其中所述发光器件层包括多个阵列排布的发光子像素；
其中，在所述第二显示区中，所述驱动器件层还设置有位于至少一所述发光子像素在所述基板上的正投影范围内的伪通孔，所述伪通孔与至少一所述发光子像素彼此绝缘设置。
在一些实施例中，在所述第二显示区中，所述薄膜晶体管设置在所述第二显示区靠近所述第一显示区的边缘。
在一些实施例中，所述薄膜晶体管与所述伪通孔同层设置。
在一些实施例中，在所述基板上形成所述驱动器件层的步骤包括在所述基板上依序设置有源层、第一绝缘层、第一金属层、第二绝缘层及第二金属层，其中所述第二金属层图案化形成源极及漏极；及开设贯穿所述第一绝缘层与所述第二绝缘层的第一通孔、第二通孔及位于所述第二显示区的所述伪通孔；
其中所述源极及漏极分别通过所述第一通孔及所述第二通孔与所述有源层电性连接。
在一些实施例中，在所述基板上形成所述驱动器件层的步骤还包括:在所述第二金属层上形成有机平坦层。
在一些实施例中，位于所述至少一发光子像素在所述基板上的正投影范围内的伪通孔的数量大于等于1。
在一些实施例中，所述发光子像素具有不同尺寸大小，所述伪通孔的数量与所述发光子像素的尺寸大小成正比。
在一些实施例中，在所述第一显示区中，所述驱动器件层设置有对应所述发光子像素的通孔，所述通孔与所述发光子像素电性连接；
其中，所述伪通孔在所述第二显示区中的密度与所述通孔在所述第一显示区中的密度相等。
在一些实施例中，所述有机平坦层填充贯穿所述第一绝缘层与所述第二绝缘层的所述伪通孔。
在一些实施例中，所述伪通孔填充有非导电性物质。
 有益效果
本申请的显示面板及其制备方法在所述第二显示区中设置有位于至少一所述发光子像素在所述基板上的正投影范围内的伪通孔，且所述伪通孔与至少一所述发光子像素彼此绝缘设置。
所述伪通孔的设置可使所述驱动器件层在所述第二显示区中也能具有均一的开孔密度，以在退火工艺中能均一的去除氢等杂质元素，而保证所述第二显示区中的薄膜晶体管能具有均一的电性，进而改善显示不均的现象。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中显示面板的平面示意图；
图2为本申请实施例中显示面板的截面结构示意图；
图3为本申请实施例中一种发光子像素形状的示意图；
图4为本申请实施例中一种伪通孔的示意图；
图5为本申请实施例中另一种伪通孔的示意图；
图6为本申请实施例中又另一种伪通孔的示意图；
图7为本申请实施例中显示面板制备方法的流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
现结合具体实施例对本申请的技术方案进行描述。
如图1及图2所示，本申请提供一种显示面板100，更具体的是一种有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板。所述显示面板100定义有第一显示区AA及第二显示区TA，在本申请实施例中，所述第一显示区AA可为正常显示区，而所述第二显示区TA可为屏下摄像区（CUP区）。作为所述屏下摄像区（CUP区）的所述第二显示区TA具有大面积的透明区域，以达成在摄像模式状态时，能有充足的透光度提供摄像头进行拍摄影像。
在一种实施例中，所述显示面板100包括基板10、驱动器件层3及发光器件层60。
所述基板10可以为玻璃基板，也可以为柔性基板，本申请不特别限定。
所述驱动器件层3设置在所述基板10上且包括多个薄膜晶体管30；所述发光器件层60设置在所述驱动器件层3上且包括多个阵列排布的发光子像素605。
进一步地，所述显示面板100在所述驱动器件层3与所述基板10之间还设置有缓冲层20。
其中，在所述第二显示区TA中，所述驱动器件层3还设置有位于至少一所述发光子像素605在所述基板10上的正投影范围内的伪通孔103，所述伪通孔103与所述至少一发光子像素605彼此绝缘设置。
一般而言，本领域藉由设置通孔并以导电性物质填充其内，而得以电性连接上层与下层金属层，进而导通电子构件。而本申请的所述伪通孔是将非导电性物质填充其内，进而具有与电子构件绝缘的特性。
所述非导电性物质可包括有机平坦层材料，所述有机平坦层材料具有优良的平坦性及透光性。
因此所述伪通孔103的设置可使所述驱动器件层3在所述第二显示区TA中在保有平坦性与大面积的透明区域情况下也能具有均一的开孔密度，以在退火工艺中能均一的去除氢等杂质元素，而保证所述第二显示区TA中的薄膜晶体管30能具有均一的电性，进而改善所述显示面板100显示不均的现象。且所述伪通孔103与至少一所述发光子像素605彼此绝缘设置，而可使所述伪通孔103在改善所述第二显示区TA的电性时能不影响所述第二显示区TA的显示效果。
较佳地，所述伪通孔103位于每一所述发光子像素605在所述基板10上的正投影范围内，以使开孔密度更均一。
在本申请的一种实施例中，多个所述伪通孔103的尺寸大小可以相同也可以不同，只要使所述第二显示区TA具有均一的开孔密度即可。
进一步地，在所述第二显示区TA中，所述薄膜晶体管30是设置在所述第二显示区TA靠近所述第一显示区AA的边缘。可以理解的是，在所述第二显示区TA中，藉由将所述薄膜晶体管30设置在所述第二显示区TA靠近所述第一显示区AA的边缘处，可以使所述薄膜晶体管30及连接所述薄膜晶体管30的线路(如栅极线或数据线等)仅占用一小部分的所述第二显示区TA的面积，进而能使所述第二显示区TA进一步具有较大面积的透明区域，以达成在摄像模式状态时，能有充足的透光度提供摄像头进行拍摄影像。
在本申请的一种实施例中，所述薄膜晶体管30与所述伪通孔103同层设置。
进一步地，在所述第一显示区AA中，所述驱动器件层3设置有对应所述发光子像素605的通孔，所述通孔与所述发光子像素605电性连接；
其中，所述伪通孔103在所述第二显示区TA中的密度与所述通孔在所述第一显示区AA中的密度相等。
具体而言，所述薄膜晶体管30包括有源层301、第一绝缘层302、第一金属层303、第二绝缘层306及第二金属层307。所述有源层301设置在所述基板10上；所述第一绝缘层302覆盖在所述有源层301上；所述第一金属层303设置在所述第一绝缘层302上且形成第一栅极；所述第二绝缘层306设置在所述第一金属层303上；所述第二金属层307设置在所述第二绝缘层306上并图案化形成源极3071及漏极3072，所述源极3071及漏极3072分别通过贯穿所述第一绝缘层302与所述第二绝缘层306的第一通孔101及第二通孔102与所述有源层301电性连接。在所述第一显示区AA中，对应所述发光子像素605的通孔包括所述第一通孔101及所述第二通孔102。
其中，所述伪通孔103与所述第一通孔101及所述第二通孔102同层设置。藉由将所述伪通孔103与所述第一通孔101及所述第二通孔102同层设置，而可使所述伪通孔103所在的伪通孔103与所述第一通孔101及所述第二通孔102在同一开孔工艺中同时形成，而不需额外的开孔工艺，进而在形成所述伪通孔103时不需额外的制备工艺，因此可以简化制备流程且减少制备成本。
且本申请通过将所述伪通孔103在所述第二显示区TA中的密度设置成与所述通孔在所述第一显示区AA中的密度相等，在保证所述第二显示区TA具有均一的开孔密度的前提下，也能保证所述第一显示区AA与所述第二显示区TA具有均一的开孔密度，进而提升所述显示面板100整体的显示均一性。
在本申请的另一个实施例中，所述薄膜晶体管30还包括第三绝缘层304及第三金属层305。所述第三绝缘层304设置在所述第一绝缘层302与所述第二绝缘层306之间并覆盖所述第一金属层303，所述第三金属层305设置在所述第三绝缘层304上并被所述第二绝缘层306所覆盖，所述第三金属层305形成有第二栅极，所述第二栅极与所述第一栅极可形成电容以进一步防止所述薄膜晶体管30漏电。
在此实施例中，所述源极3071及漏极3072分别通过贯穿所述第一绝缘层302、所述第三绝缘层304与所述第二绝缘层306的所述第一通孔101及所述第二通孔102与所述有源层301电性连接。所述伪通孔103亦可贯穿所述第一绝缘层302、所述第三绝缘层304与所述第二绝缘层306而形成，进而可使所述伪通孔103与所述第一通孔101及所述第二通孔102在同一开孔工艺中同时形成，而不需额外的开孔工艺，进而在形成所述伪通孔103时不需额外的制备工艺，因此可以简化制备流程且减少制备成本。
进一步地，所述显示面板100还包括有机平坦层40，所述有机平坦层40设置于所述驱动器件层3及所述发光器件层60之间，所述伪通孔103可直接由所述有机平坦层40填充所述伪通孔103。藉由直接以所述有机平坦层40填充所述伪通孔103，而可省略额外的制备工艺，因此可以简化制备流程且减少制备成本。
可以理解的是，所述驱动器件层3包括所述有源层301、所述第一绝缘层302、所述第一金属层303、所述第二绝缘层306、所述第二金属层307、所述第三绝缘层304及所述第三金属层305。所述第一绝缘层302、所述第三绝缘层304及所述第二绝缘层306可为无机绝缘层，所述第二绝缘层306可用于改善应力和补充氢源，以进一步修补TFT沟道缺陷，改善电性。
进一步地，所述显示面板100还包括透明金属层50，所述透明金属层50设置在所述有机平坦层40及所述发光器件层60之间，且经由贯穿所述有机平坦层40的第三通孔104与所述漏极3072电性连接。其中，所述透明金属层50的材料可为氧化铟锡(ITO)。
须注意的是，在所述第二显示区TA中，所述透明金属层50图案化形成有透明金属线路501，所述透明金属线路501从对应所述发光子像素605下方的位置延伸到对应位于所述第二显示区TA边缘的所述薄膜晶体管30上方的位置，且所述薄膜晶体管30通过所述透明金属线路501与所述发光子像素605电性连接。
在所述第二显示区TA中，本申请藉由所述透明金属线路501电性连接所述发光子像素605及位于所述第二显示区TA边缘的所述薄膜晶体管30，进而在达成所述发光子像素605与所述薄膜晶体管30的电性连接的同时，还能使所述第二显示区TA维持有较大面积的透明区域，以达成在摄像模式状态时，能有充足的透光度提供摄像头进行拍摄影像。
在另一种实施例中，所述有机平坦层40包括第一有机平坦层41及第二有机平坦层42，所述第二有机平坦层42设置在所述第二绝缘层306上，所述第一有机平坦层41设置在所述第二有机平坦层42上，且所述显示面板100还包括第四金属层80设置在所述第一有机平坦层41及所述第二有机平坦层42之间。所述第四金属层80的材料可为氧化铟锌(IZO)。
在此实施例中，所述第四金属层80电性连接所述透明金属层50与所述漏极3072，具体而言，所述透明金属层50通过所述第三通孔104与所述第四金属层80电性连接，且所述第四金属层80通过第四通孔105与所述漏极3072电性连接。藉由所述第四金属层80电性连接所述透明金属层50与所述漏极3072可以进一步降低压降，改善显示效果。
进一步地，所述发光器件层60具体可包括阳极601、像素定义层602、发光材料层603及阴极604。所述发光子像素605位于所述像素定义层602设置的开口区域内且包括所述阳极601及所述发光材料层603，而所述阴极604覆盖于所述发光子像素605与所述像素定义层602上。所述阳极601的材料可为ITO/Ag/ITO。在所述第一显示区AA中，所述发光子像素605包括第一红色子像素单元R1、第一绿色子像素单元G1和第一蓝色子像素单元B1，其中，所述第一红色子像素单元R1用于发出红色的光，所述第一绿色子像素单元G1用于发出绿色的光，所述第一蓝色子像素单元B1用于发出蓝色的光。
在所述第二显示区TA中，所述发光子像素605包括第二红色子像素单元R2、第二绿色子像素单元G2和第二蓝色子像素单元B2，其中，所述第二红色子像素单元R2用于发出红色的光，所述第二绿色子像素单元G2用于发出绿色的光，所述第二蓝色子像素单元B2用于发出蓝色的光。
在一种实施例中，如图3所示，在所述第一显示区AA中，所述第一红色子像素单元R1、所述第一绿色子像素单元G1和所述第一蓝色子像素单元B1皆为矩形，所述第一蓝色子像素单元B1的发光面积大于所述第一红色子像素单元R1及所述第一绿色子像素单元G1的发光面积，且所述第一红色子像素单元R1的发光面积大于所述第一绿色子像素单元G1的发光面积。
须注意的是，所述第一红色子像素单元R1、所述第一绿色子像素单元G1和所述第一蓝色子像素单元B1的形状不限定为矩形，还可根据所述第一显示区AA的形状来对应设置。此外，由于所述第一蓝色子像素单元B1的发光效率较差而所述第一绿色子像素单元G1的发光效率较佳，因此可将所述第一蓝色子像素单元B1的发光面积设置成最大，且将所述第一绿色子像素单元G1的发光面积设置成最小，以使所述第一红色子像素单元R1、所述第一绿色子像素单元G1和所述第一蓝色子像素单元B1的发光亮度更均匀。
在所述第二显示区TA中，所述第二红色子像素单元R2、所述第二绿色子像素单元G2和所述第二蓝色子像素单元B2皆为圆形，所述第二蓝色子像素单元B2的发光面积大于所述第二红色子像素单元R2及所述第二绿色子像素单元G2的发光面积，且所述第二红色子像素单元R2的发光面积大于所述第二绿色子像素单元G2的发光面积。
须注意的是，所述第二红色子像素单元R2、所述第二绿色子像素单元G2和所述第二蓝色子像素单元B2的形状限定为圆形，可使所述第二红色子像素单元R2、所述第二绿色子像素单元G2和所述第二蓝色子像素单元B2的面积最小化，以进一步增大透光度，而使所述第二显示区TA有较大面积的透明区域，以达成在摄像模式状态时，能有充足的透光度提供摄像头进行拍摄影像。此外，由于所述第二蓝色子像素单元B2的发光效率较差而所述第二绿色子像素单元G2的发光效率较佳，因此可将所述第二蓝色子像素单元B2的发光面积设置成最大，且将所述第二绿色子像素单元G2的发光面积设置成最小，以使所述第二红色子像素单元R2、所述第二绿色子像素单元G2和所述第二蓝色子像素单元B2的发光亮度更均匀。
对于所述第二显示区TA中所述发光子像素605的形状尺寸设计及其与所述薄膜晶体管30的连接线路设计，具体可参考相关专利文献CN112103329A和CN112259596A，在此不再赘述。
在本申请的一种实施例中，在所述第二显示区TA中，位于至少一所述发光子像素605在所述基板10上的正投影范围内的伪通孔103的数量大于等于1。所述伪通孔103的形状包括矩形或圆形中的至少一种。
在本申请的一种实施例中，所述发光子像素605具有不同尺寸大小，所述伪通孔103的数量与所述发光子像素605的尺寸大小成正比。
具体而言，所述第二蓝色子像素单元B2的尺寸大小大于所述第二红色子像素单元R2，所述第二红色子像素单元R2的尺寸大小大于所述第二绿色子像素单元G2；如图4所示，对应于所述第二红色子像素单元R2的伪通孔103的数量为5，对应于所述第二绿色子像素单元G2的伪通孔103的数量为3，对应于所述第二蓝色子像素单元B2的伪通孔103的数量为7，且所述伪通孔103的形状为矩形。
本申请通过将所述伪通孔103的数量设置成与所述发光子像素605的尺寸大小成正比，而可进一步保证所述第二显示区TA具有均一的开孔密度。
在本申请的另一种实施例中，如图5所示，与图4的区别仅在于，所述伪通孔103的形状为圆形。
在本申请的又另一种实施例中，如图6所示，与图4的区别仅在于，对应于所述第二红色子像素单元R2的伪通孔103的数量为7，对应于所述第二绿色子像素单元G2的伪通孔103的数量为4，对应于所述第二蓝色子像素单元B2的伪通孔103的数量为10。
可以理解的是，所述位于至少一所述发光子像素605在所述基板10上的正投影范围内的伪通孔103的数量没有一定限制，可以根据具体需求来设置。只要确保在所述第二显示区TA中能具有均一的开孔密度，以在退火工艺中能均一的去除氢等杂质元素即可。因此得以保证所述第二显示区TA中的薄膜晶体管30能具有均一的电性，进而改善所述显示面板100显示不均的现象。
且，所述伪通孔103的形状可包括矩形或圆形，可以根据具体需求来设置。
进一步地，所述显示面板100还包括薄膜封装层70，所述薄膜封装层70用以隔绝外界水氧，以防止所述显示面板100失效。
如图7所示，本申请更提供上述显示面板100的制备方法，所述制备方法包括下列步骤:
S10:提供一基板10。
S20:在所述基板10上形成驱动器件层3，所述驱动器件层3包括多个薄膜晶体管30。
S30:在所述驱动器件层3上形成发光器件层60，所述发光器件层60包括多个阵列排布的发光子像素605；其中，在所述第二显示区TA中，所述驱动器件层3还设置有位于至少一所述发光子像素605在所述基板10上的正投影范围内的伪通孔103，所述伪通孔103与至少一所述发光子像素605彼此绝缘设置。
一般而言，本领域藉由设置通孔并以导电性物质填充其内，而得以电性连接上层与下层金属层，进而导通电子构件。而本申请的所述伪通孔是将非导电性物质填充其内，进而具有与电子构件绝缘的特性。
所述非导电性物质可包括有机平坦层材料，所述有机平坦层材料具有优良的平坦性及透光性。
本申请所述的显示面板的制备方法通过设置所述伪通孔103可使所述驱动器件层3在所述第二显示区TA中在保有平坦性与大面积的透明区域情况下也能具有均一的开孔密度，以在退火工艺中能均一的去除氢等杂质元素，而保证所述第二显示区TA中的薄膜晶体管30能具有均一的电性，进而改善所述显示面板100显示不均的现象。且所述伪通孔103与至少一所述发光子像素605彼此绝缘设置，而可使所述伪通孔103在改善所述第二显示区TA的电性时能不影响所述第二显示区TA的显示效果。
所述制备方法还包括S11:在所述基板10上形成缓冲层20。
所述步骤S20具体包括下列步骤:
S201:在所述缓冲层20上依序设置有源层301、第一绝缘层302、第一金属层303、第三绝缘层304、所述第三金属层305及第二绝缘层306；
S202:开设贯穿所述第一绝缘层302、所述第三绝缘层304与所述第二绝缘层306的第一通孔101、第二通孔102及位于所述第二显示区TA的伪通孔103；
S203:在所述第二绝缘层306上形成第二金属层307，所述第二金属层307图案化形成源极3071及漏极3072，所述源极3071及漏极3072分别通过所述第一通孔101及所述第二通孔102与所述有源层301电性连接。
因此，可使所述伪通孔103与所述第一通孔101及所述第二通孔102在同一开孔工艺中同时形成，而不需额外的开孔工艺，进而在形成所述伪通孔103时不需额外的制备工艺，因此可以简化制备流程且减少制备成本。
所述制备方法在所述步骤S203之后还包括S21:在所述第二金属层307上形成有机平坦层40。
所述伪通孔103可直接由所述有机平坦层40填充。藉由直接以所述有机平坦层40填充于所述伪通孔103，而可省略额外的制备工艺，因此可以简化制备流程且减少制备成本。
所述制备方法在所述步骤S21之后还包括S22:在所述有机平坦层40上形成透明金属层50，其中，在所述第二显示区TA中，所述透明金属层50图案化形成有透明金属线路501，所述透明金属线路501从对应所述发光子像素605下方的位置延伸到对应位于所述第二显示区TA边缘的所述薄膜晶体管30上方的位置，且所述薄膜晶体管30通过所述透明金属线路501与所述发光子像素605电性连接。
在所述第二显示区TA中，本申请藉由所述透明金属线路501电性连接所述发光子像素605及位于所述第二显示区TA边缘的所述薄膜晶体管30，进而在达成所述发光子像素605与所述薄膜晶体管30的电性连接的同时，还能使所述第二显示区TA维持有较大面积的透明区域，以达成在摄像模式状态时，能有充足的透光度提供摄像头进行拍摄影像。
所述制备方法在所述步骤S30之后还包括S40:在所述发光器件层60上形成薄膜封装层70。
所述各层的具体描述可以参照上述显示面板100，在本制备方法中不多赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，所述显示面板定义有第一显示区及第二显示区，且所述显示面板包括：
    基板；
    驱动器件层，所述驱动器件层设置在所述基板上且包括多个薄膜晶体管；及
    发光器件层，所述发光器件层设置在所述驱动器件层上且包括多个阵列排布的发光子像素；
    其中，在所述第二显示区中，所述驱动器件层还设置有位于至少一所述发光子像素在所述基板上的正投影范围内的伪通孔，所述伪通孔与所述至少一发光子像素彼此绝缘设置。
  2. 根据权利要求1所述的显示面板，其中，在所述第二显示区中，所述薄膜晶体管设置在所述第二显示区靠近所述第一显示区的边缘。
  3. 根据权利要求1所述的显示面板，其中，所述薄膜晶体管与所述伪通孔同层设置。
  4. 根据权利要求3所述的显示面板，其中，所述薄膜晶体管包括:
    有源层，所述有源层设置在所述基板上；
    第一绝缘层，所述第一绝缘层覆盖在所述有源层上；
    第一金属层，所述第一金属层设置在所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层设置在所述第一金属层上；及
    第二金属层，所述第二金属层设置在所述第二绝缘层上并图案化形成源极及漏极，所述源极及漏极分别通过贯穿所述第一绝缘层与所述第二绝缘层的第一通孔及第二通孔与所述有源层电性连接；
    其中，所述伪通孔与所述第一通孔及所述第二通孔同层设置。
  5. 根据权利要求1所述的显示面板，其中，位于所述至少一发光子像素在所述基板上的正投影范围内的伪通孔的数量大于等于1。
  6. 根据权利要求1所述的显示面板，其中，所述伪通孔的形状包括矩形或圆形中的至少一种。
  7. 根据权利要求5所述的显示面板，其中，所述发光子像素具有不同尺寸大小，所述伪通孔的数量与所述发光子像素的尺寸大小成正比。
  8. 根据权利要求1所述的显示面板，其中，在所述第一显示区中，所述驱动器件层设置有对应所述发光子像素的通孔，所述通孔与所述发光子像素电性连接；
    其中，所述伪通孔在所述第二显示区中的密度与所述通孔在所述第一显示区中的密度相等。
  9. 根据权利要求4所述的显示面板，其中，所述显示面板还包括有机平坦层，所述有机平坦层设置于所述驱动器件层及所述发光器件层之间，且所述有机平坦层填充贯穿所述第一绝缘层与所述第二绝缘层的所述伪通孔。
  10. 根据权利要求1所述的显示面板，其中，所述伪通孔填充有非导电性物质。
  11. 一种显示面板的制备方法，所述显示面板定义有第一显示区及第二显示区，其中，所述制备方法包括下列步骤:
    提供一基板；
    在所述基板上形成驱动器件层，其中所述驱动器件层包括多个薄膜晶体管；及
    在所述驱动器件层上形成发光器件层，其中所述发光器件层包括多个阵列排布的发光子像素；
    其中，在所述第二显示区中，所述驱动器件层还设置有位于至少一所述发光子像素在所述基板上的正投影范围内的伪通孔，所述伪通孔与至少一所述发光子像素彼此绝缘设置。
  12. 根据权利要求11所述的显示面板的制备方法，其中，在所述第二显示区中，所述薄膜晶体管设置在所述第二显示区靠近所述第一显示区的边缘。
  13. 根据权利要求11所述的显示面板的制备方法，其中，所述薄膜晶体管与所述伪通孔同层设置。
  14. 根据权利要求11所述的显示面板的制备方法，其中，在所述基板上形成所述驱动器件层的步骤包括:
    在所述基板上依序设置有源层、第一绝缘层、第一金属层、第二绝缘层及第二金属层，其中所述第二金属层图案化形成源极及漏极；及
    开设贯穿所述第一绝缘层与所述第二绝缘层的第一通孔、第二通孔及位于所述第二显示区的所述伪通孔；
    其中所述源极及漏极分别通过所述第一通孔及所述第二通孔与所述有源层电性连接。
  15. 根据权利要求14所述的显示面板的制备方法，其中，在所述基板上形成所述驱动器件层的步骤还包括:在所述第二金属层上形成有机平坦层。
  16. 根据权利要求11所述的显示面板的制备方法，其中，位于所述至少一发光子像素在所述基板上的正投影范围内的伪通孔的数量大于等于1。
  17. 根据权利要求16所述的显示面板的制备方法，其中，所述发光子像素具有不同尺寸大小，所述伪通孔的数量与所述发光子像素的尺寸大小成正比。
  18. 根据权利要求11所述的显示面板的制备方法，其中，在所述第一显示区中，所述驱动器件层设置有对应所述发光子像素的通孔，所述通孔与所述发光子像素电性连接；
    其中，所述伪通孔在所述第二显示区中的密度与所述通孔在所述第一显示区中的密度相等。
  19. 根据权利要求15所述的显示面板的制备方法，其中，所述有机平坦层填充贯穿所述第一绝缘层与所述第二绝缘层的所述伪通孔。
  20. 根据权利要求11所述的显示面板的制备方法，其中，所述伪通孔填充有非导电性物质。
PCT/CN2021/115284 2021-08-05 2021-08-30 显示面板及其制备方法 WO2023010632A1 (zh)

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