WO2023008138A1 - 水晶発振器及びその製造方法 - Google Patents

水晶発振器及びその製造方法 Download PDF

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Publication number
WO2023008138A1
WO2023008138A1 PCT/JP2022/027066 JP2022027066W WO2023008138A1 WO 2023008138 A1 WO2023008138 A1 WO 2023008138A1 JP 2022027066 W JP2022027066 W JP 2022027066W WO 2023008138 A1 WO2023008138 A1 WO 2023008138A1
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layer
crystal
recess
package
crystal element
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PCT/JP2022/027066
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English (en)
French (fr)
Japanese (ja)
Inventor
貴博 植田
正明 太田
孝男 楠木
広幸 石川
和也 竺原
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京セラ株式会社
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Priority to JP2023538393A priority Critical patent/JPWO2023008138A1/ja
Publication of WO2023008138A1 publication Critical patent/WO2023008138A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present disclosure relates to crystal oscillators and manufacturing methods thereof.
  • a crystal oscillator having a crystal element, an IC (Integrated Circuit), and a package holding them is known (for example, Patent Document 1 below).
  • the crystal element has, for example, a crystal blank and excitation electrodes that overlap the crystal blank.
  • the IC includes, for example, an oscillator circuit and is electrically connected to excitation electrodes via a package.
  • the oscillating circuit vibrates the crystal blank by applying an alternating voltage to the excitation electrodes, and uses this vibration to generate an oscillating signal.
  • an IC is mounted on a package by bumps made of solder.
  • a crystal oscillator includes a crystal element, an IC, a package, a connecting member, and a first Au layer.
  • the IC has terminals.
  • the package holds the crystal element and the IC.
  • the connecting members are bumps or bonding wires made of gold and bonded to the terminals and the package.
  • the terminal has a first Au layer forming a surface of the terminal and to which the connection member is bonded.
  • FIG. 1 is an exploded perspective view showing a schematic configuration of a crystal oscillator according to a first embodiment
  • FIG. FIG. 2 is a cross-sectional view of the crystal oscillator taken along line II-II of FIG. 1
  • FIG. 2 is a plan view showing the inside of the crystal oscillator of FIG. 1
  • region IV of FIG. 2 is a flow chart showing an example of the procedure of a method for manufacturing the crystal oscillator of FIG. 1; Sectional drawing corresponding to a part of FIG. 4 which shows the structure of a comparative example.
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a second embodiment
  • FIG. 8 is an enlarged view of region VIII of FIG.
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a third embodiment
  • FIG. 5 is a cross-sectional view showing a schematic configuration of a crystal oscillator according to a fourth embodiment
  • FIG. 5 is a diagram showing temporal changes in the characteristics of an oscillator according to a comparative example
  • FIG. 4 is a diagram showing temporal changes in the characteristics of the oscillator according to the example
  • the drawings may be labeled with an orthogonal coordinate system D1-D2-D3 for convenience.
  • any direction may be the upper side or the lower side, but for the sake of convenience, the +D3 side may be referred to as the upper side, and terms such as the upper surface and the lower surface may be used hereinafter.
  • first insulating layer 31A and “second insulating layer 31B”
  • simply "insulating layer 31" may be indicated by a number and additional signs may be omitted to distinguish between them.
  • rectangle may include a shape with chamfered corners unless otherwise specified. The same is true for other polygons. Also, shapes other than polygons do not have to be shapes that are strictly defined by mathematics. Of course, the various shapes may be strictly mathematically defined shapes.
  • the "main component” may be, for example, a component that accounts for 50% by mass or more of the material. When two or more components are the main components, the total of the two or more components is 50% by mass or more. It should be noted that the mass % of various main components to be described later may be, for example, 80 mass % or more or 90 mass % or more upon implementation.
  • the member When the member is made of "gold" (or Au), the member may be made of metal containing 99.9% or more by mass of Au. That is, the member may contain less than 0.1% by mass of impurities. Impurities may be unavoidably mixed (unintended) or intentionally added. Impurities that are intentionally added include, for example, those that adjust the crystalline state. In addition, the mass % of Au in various members made of Au, which will be described later, may be 99.99% or more or more in practice.
  • the metal in the completed oscillator may be formed by firing a conductive paste. Therefore, even materials referred to simply as metals in the following description may include inorganic materials contained in the conductive paste.
  • FIG. 1 is an exploded perspective view showing a schematic configuration of a crystal oscillator 1 (hereinafter, "crystal” may be omitted) according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II--II of FIG.
  • FIG. 3 is a plan view showing the inside of the oscillator 1.
  • FIG. 2 for the sake of convenience, strictly speaking, members that are not located on the same cross section are also shown together.
  • the oscillator 1 is, for example, an electronic component that generally has a thin rectangular parallelepiped shape as a whole.
  • the dimensions of oscillator 1 are arbitrary.
  • the length of the long side and short side is 1 mm or more and 10 mm or less.
  • the thickness is 0.2 mm or more and 2 mm or less on the premise that it is smaller than the length of the short side.
  • the oscillator 1 generates an oscillation signal, for example, by being supplied with DC power of a predetermined voltage.
  • An oscillating signal is a signal whose signal level (for example, potential) oscillates at a constant period.
  • the frequency of the oscillation signal generated by the oscillator 1 is arbitrary. For example, when it is assumed that the crystal element (described later) applied to the embodiment may have various aspects (shape, vibration mode, etc.), the frequency of the oscillation signal may be 1 kHz or more and 1 GHz or less.
  • the oscillator 1 has, for example, a crystal element 3, an IC 5, and a package 7 that holds (for example, accommodates) these elements, as particularly shown in FIG. Package 7 has a base 9 and a lid 11 . Note that FIG. 3 shows the inside of the oscillator 1 by omitting the lid 11 .
  • the crystal element 3 generates natural vibration when an AC voltage is applied.
  • the IC5 includes an oscillation circuit (not shown).
  • the oscillation circuit applies a voltage to the crystal element 3 and utilizes the natural oscillation in the crystal element 3 to generate an oscillation signal.
  • the package 7 contributes to protection of the crystal element 3 and the IC 5, transmission of electrical signals to these elements, and the like.
  • the crystal element 3 and the IC 5 are mounted on the base 9 of the package 7, for example. That is, the crystal element 3 and the IC 5 are fixed to the base 9 and electrically connected.
  • a lid 11 of the package 7 is fixed to the base 9 so as to form a closed space S1 in which the crystal element 3 and the IC 5 are accommodated.
  • the closed space S1 is, for example, evacuated or filled with an appropriate gas (eg, nitrogen).
  • the crystal element 3 is fixed and electrically connected to the base 9 by two conductive adhesives 41 (FIGS. 2 and 3).
  • the IC 5 is fixed to the base 9 by an adhesive 43 (FIG. 2) and electrically connected to the base 9 by a plurality (eight in the example shown) of bonding wires 45 (FIGS. 2 and 3). It is connected to the. At least part of the IC 5 may be covered with a sealing resin 49 (see FIG. 11 described later).
  • a member (bonding wire 45 in the illustrated example) that electrically connects the IC 5 and the package 7 (base 9) is sometimes called a connection member.
  • the oscillator 1 has, for example, a new configuration regarding the bonding between the connecting member and the IC 5 .
  • Other configurations may be in various aspects, for example, may be in known aspects.
  • the structure of the crystal element 3, the structure of the IC 5 (excluding the structure related to the bonding described above), the structure of the package 7, and the mounting structure of each element (the bonding described above) shown in FIGS. ) etc. is merely an example.
  • the outer shape of the oscillator 1 does not have to be rectangular parallelepiped.
  • the description of (1) may include description of novel aspects without any particular notice. Also, the description of (1) will be made by taking the mode shown in FIGS. 1 to 3 as an example. In the explanation of (1), the crystal element 3, the IC 5, the package 7 (the base portion 9 and the lid 11), and the members involved in mounting (the conductive adhesive 41, the adhesive 43 and the bonding wire 45) are explained in order. After that, the positional relationship between the crystal element 3 and the IC 5 will be described.
  • the crystal element 3 includes, for example, a crystal blank 13 , two or more (one pair in the illustrated example) excitation electrodes 15 for applying a voltage to the crystal blank 13 , and the crystal element 3 mounted on the base 9 of the package 7 . It has two or more (one pair in the illustrated example) extraction electrodes 17 for the purpose.
  • the shape of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 is such that either of the two surfaces of the crystal element 3 may be the mounting side (-D3 side). (longitudinal direction)), and may be formed into a shape approximately 180° rotationally symmetrical with respect to a center line (not shown).
  • the shapes of the crystal blank 13, the excitation electrode 15, and the extraction electrode 17 do not have to be rotationally symmetrical.
  • the planar shape of the crystal blank 13 may be rectangular (example shown), circular, or elliptical.
  • the thickness of the crystal blank 13 may be constant or may not be constant (example shown). As an example of the latter, although not shown, a so-called mesa shape in which the central portion is thicker than the outer peripheral portion can be cited.
  • the crystal blank 13 has a relatively thin portion and a relatively thick portion.
  • a pair of excitation electrodes 15 are located in the thin portion.
  • the thick portion is located, for example, at one end (one side) of the crystal blank 13, and a pair of extraction electrodes 17 are located.
  • the thicker portions can, for example, increase the strength of the crystal blank 13 .
  • the thick portions may be formed, for example, on two sides, three sides, or four sides of the crystal blank 13 . From another point of view, the thick portion may be formed in a region where the extraction electrode 17 is not located.
  • the planar shape of the excitation electrode 15 may be a circular shape (example shown in the drawing), a rectangular shape, or an elliptical shape. Further, the planar shape of the excitation electrode 15 may be a shape similar to the planar shape of the crystal blank 13 (or the planar shape of the mesa portion), or may not be such a shape (example shown in the figure). ).
  • the former includes a rectangular-rectangular combination, a circular-circular combination, and an elliptical-elliptical combination.
  • the lead-out electrode 17 has, for example, a wiring portion extending from the excitation electrode 15 and a pad-like terminal portion connected to the tip of the wiring portion, although no particular reference numeral is attached.
  • the terminal portion is a portion that is joined to the base portion 9 of the package 7 .
  • the terminal portion included in one extraction electrode 17 has two portions located on both sides of the crystal blank 13 so that either side of the crystal element 3 can be the mounting side. are doing. These two portions are, for example, the end surface of the crystal blank 13 (the surface on the -D1 side), the side surface of the crystal blank 13 (the surface on the +D2 side or the -D2 side), and a through hole (not shown) formed in the crystal blank 13. They are connected to each other through at least one of the holes.
  • the crystal element 3 may have a configuration other than the above.
  • the crystal element 3 may be a tuning fork type element using bending vibration, a CT cut or DT cut element using contour shear vibration, or an element using SAW (surface acoustic wave).
  • Such an element also has a crystal blank 13 and two or more excitation electrodes 15 overlapping the crystal blank 13 .
  • the crystal blank layer of crystal may overlap layers of other materials.
  • the thickness of the crystal blank 13 may be set as appropriate for the crystal blank 13 that is not plate-shaped and/or the crystal blank 13 whose thickness is not a factor that determines the frequency.
  • the thickness of such a crystal blank 13 may be 5 ⁇ m or more and 30 ⁇ m or less.
  • the thickness direction of the non-platy crystal blank 13 may be reasonably determined from its overall shape. For example, in a tuning fork type, the dimension in the direction orthogonal to both the direction in which two or more arms extend in parallel and the direction in which the two or more arms are arranged is the thickness.
  • the IC 5 has a chip body 19 having various circuits inside, and a plurality of IC terminals 21 that mediate connections between the circuits and the outside of the IC 5 .
  • eight IC terminals 21 are shown as shown in FIG. In FIG. 2, only one IC terminal 21 on the -D1 side is shown. In FIG. 3, the two IC terminals on the -D1 side are hidden by the crystal element 3 and are not shown.
  • the chip body 19 has a substrate made of, for example, a semiconductor (eg, silicon). have a circuit.
  • the circuit included in the chip body 19 is, for example, the oscillation circuit described above.
  • the chip body 19 may include a temperature sensor and a temperature compensation circuit that compensates for temperature changes in the oscillation signal based on the temperature detected by the temperature sensor.
  • the IC 5 (chip body 19) may be packaged or may be a bare chip.
  • the shape of the chip body 19 is arbitrary. In general, the shape of the chip body 19 is a thin rectangular parallelepiped, as shown in the drawing. Moreover, the dimensions of the chip body 19 are also arbitrary. For example, the width (area) of the chip body 19 in plan view may be larger than the width of the crystal element 3 in plan view (example shown), may be the same, or may be smaller. The width of the crystal element 3 in plan view may be the minimum rectangular width that includes the crystal element 3 when the crystal element 3 is not plate-shaped like a tuning fork.
  • the thickness of the chip body 19 may be thicker than the thickness of the crystal element 3 (the thickness of the portion where the excitation electrode 15 overlaps, or the maximum thickness) (example shown), or may be the same. It may be fine, or it may be thin.
  • the number and roles of the IC terminals 21 may be appropriately set according to the functions required of the IC 5 (oscillator 1).
  • the IC terminals 21 may include the following terminals.
  • the IC terminals 21 may include the following terminals.
  • the IC terminal 21 is composed of, for example, a pad that overlaps one of the two main surfaces (the widest surface; front and back) of the IC 5 .
  • the planar shape, size and arrangement position of the IC terminal 21 are arbitrary.
  • the planar shape and dimensions of the plurality of IC terminals 21 may be the same (example shown) or may be different.
  • the planar shape of the IC terminal 21 may be rectangular (illustrated example), circular, or elliptical.
  • the width of one IC terminal 21 in plan view may be smaller than the width of the portion facing the -D3 side of the terminal portion of one extraction electrode 17 (example shown), or may be the same. and can be larger.
  • the plurality of IC terminals 21 may be arranged in a row generally along the outer edge of the chip body 19 (example shown), or unlike the example shown in the figure, may be arranged in a row along the outer edge. It may also include another IC terminal 21 positioned inside the plurality of IC terminals 21 .
  • the package 7 has a base 9 and a lid 11 fixed to the base 9, as described above.
  • the base 9 and the lid 11 form a sealed space S1 that accommodates the crystal element 3 and the IC5.
  • the specific shapes of the base portion 9 and the lid 11, the mounting structure of the crystal element 3 and the IC 5 with respect to the base portion 9, the relative positions of the crystal element 3 and the IC 5, and the like may be made as appropriate.
  • the base portion 9 has a first surface 9a (the bottom surface of the recess in the illustrated example) facing the +D3 side.
  • the lid 11 is fixed to the base 9 so as to form a closed space S1 on the first surface 9a.
  • the IC 5 is fixed to the first surface 9a and accommodated in the sealed space S1.
  • the crystal element 3 is accommodated in the closed space S1 at a position facing the first surface 9a through the IC5. That is, the illustrated package 7 accommodates the crystal element 3 and the IC 5 in a stacked manner on the first surface 9a. Specifically, it is as follows.
  • the base 9 has, for example, an insulating substrate 23 and various conductors (eg, metal) provided on the substrate 23 .
  • the base 23 for example, occupies most of the base 9 , and the base 9 has substantially the same shape as the base 23 .
  • Various conductors constitute, for example, pads to which the crystal element 3 and the IC 5 are electrically connected.
  • the shape, size and material of the substrate 23 are arbitrary.
  • the outer shape of the base 23 is substantially rectangular parallelepiped.
  • the base 23 includes a first recess 25 opening on the top surface, a second recess 27 opening on the bottom surface of the first recess 25, and a bottom surface of the second recess 27 opening on the bottom surface. and a third recessed portion 29 which is provided.
  • the third recess 29 accommodates the IC5.
  • the bottom surface of the third concave portion 29 (strictly speaking, a die pad 42 described later overlapping with the bottom surface) is an example of the first surface 9a described above.
  • the second recess 27 accommodates the bonding wire 45 .
  • the first recess 25 accommodates the crystal element 5 .
  • the base 23 may be regarded as having one recess. Further, assuming that the one concave portion has a first bottom surface including the bottom surface (first surface 9a) of the third concave portion 29, the first bottom surface is provided with a first pedestal (the upper surface of which is the bottom surface of the second concave portion 27). ) is formed, and the second pedestal (the upper surface of which includes the bottom surface of the first recess 25 ) is formed on the upper surface of the first pedestal.
  • the base 23 is composed of, for example, a plurality of (four in this embodiment) first insulating layers 31A to fourth insulating layers 31D.
  • the base 9 comprises a first insulating layer 31A, a second insulating layer 31B having an opening forming a third recess 29, and a second recess 27, in this order from the bottom surface of the base 9. It has a third insulating layer 31 ⁇ /b>C having an opening and a fourth insulating layer 31 ⁇ /b>D having an opening forming the first recess 25 .
  • the substrate 23 may be produced by laminating the insulating layer 31, or may be produced by a manufacturing method different from such a manufacturing method.
  • a method of laminating and firing a plurality of ceramic green sheets to be a plurality of insulating layers 31 can be used.
  • the latter method for example, there is a method of forming concave portions (25, 27 and 29) in one ceramic green sheet by pressing and firing.
  • the former manufacturing method and the latter manufacturing method may be combined.
  • the insulating layer 31 may be of convenience that is conceived based on the shape of the substrate 23 and/or the conductor layers within the substrate 23 .
  • the shape of the outer edges of the plurality of insulating layers 31 is, for example, a rectangular shape corresponding to the rectangular parallelepiped shape of the substrate 23 .
  • the planar shape of each recess (25, 27 and 29) is, for example, a rectangular shape having four sides parallel to the rectangle of the outer edge of the insulating layer 31.
  • the thickness of each insulating layer 31 (the depth of each recess) may be the same as or different from each other, and may be appropriately set according to the thicknesses of the crystal element 3 and the IC 5. .
  • the second recess 27 is, for example, smaller than the first recess 25 in at least one of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23) (the D1 direction in the illustrated example).
  • the bottom surface of the first recess 25 (the upper surface of the third insulating layer 31C) is exposed upward around the second recess 27 .
  • the bottom surface of the first recess 25 may refer to only the area around the second recess 27 (only the area excluding the area where the second recess 27 is open).
  • the bottom surface of the first concave portion 25 is used for mounting the crystal element 3, for example.
  • the third recess 29 is smaller than the second recess 27, for example, in at least one (both in the illustrated example) of the D1 direction (longitudinal direction of the base 23) and the D2 direction (lateral direction of the base 23).
  • the bottom surface of the second recess 27 (the upper surface of the second insulating layer 31B) is exposed upward around the third recess 29 .
  • the bottom surface of the second recess 27 may refer to only the area around the third recess 29 (only the area excluding the area where the third recess 29 is open).
  • the bottom surface of the second recess 27 is used, for example, for electrical connection with the IC 5 and the conductors of the base 9 .
  • the relative positions and relative sizes of the plurality of recesses (25, 27 and 29) in plan view are arbitrary. These are appropriately set in consideration of, for example, the size of the elements accommodated in each recess, and the arrangement position of a conductor layer (for example, pads connected to various elements) formed on the bottom surface of each recess. you can A specific example thereof will be described later together with the description of the conductor layer.
  • the material of the substrate 23 may be ceramic, for example.
  • the plurality of insulating layers 31 are made of ceramic, for example, and are integrally formed. Any specific type of ceramic may be used, and examples include aluminum oxide (alumina, Al 2 O 3 ), aluminum nitride (AlN), and LTCC (Low Temperature Co-fired Ceramics).
  • the coefficient of linear expansion of the material is, for example, 3 ppm/K or more and 13 ppm/K or less.
  • the Young's modulus of the material is, for example, 50 GPa or more and 350 GPa or less.
  • the material of the substrate 23 may be an insulating material other than ceramic (for example, resin).
  • a pair of crystal pads 33 are connected to two IC pads 35 via wiring conductors of the base 9 . This allows the IC 5 to apply voltage to the crystal element 3 .
  • IC pads 35 other than the two IC pads 35 are connected to external terminals 37 via, for example, wiring conductors of the base portion 9 . This allows the IC 5 to input an electric signal from outside the oscillator 1 and output an electric signal to the outside of the oscillator 1 .
  • the crystal pad 33 is positioned, for example, on the bottom surface of the first recess 25 (the area around the second recess 27).
  • the planar shape and dimensions of the bottom surface of the first recess 25 and the planar shape and dimensions of the crystal pad 33 are arbitrary, and the relative relationship between them is also arbitrary.
  • the crystal pad 33 may be positioned on any of the -D1 side (example shown), +D1 side, -D2 side and +D2 side with respect to the second concave portion 27 .
  • the second recess 27 has the same size as the first recess 25 in the D2 direction.
  • the +D1 side edge of the second recess 27 coincides with the +D1 side edge of the first recess 25 . That is, the bottom surface of the first recess 25 (the area surrounding the second recess 27) is exposed only on the -D1 side.
  • the pair of crystal pads 33 extends over the bottom surface of the first recess 25 in the D1 direction.
  • the pair of crystal pads 33 are separated from each other in the D2 direction and extend to the end of the bottom surface of the first recess 25 in the D2 direction. With such a configuration, for example, both the area of the crystal pad 33 and the area of the second recess 27 can be increased.
  • the length of the crystal pad 33 in the D1 direction may be shorter than the length of the bottom surface of the first recess 25 in the D1 direction. Further, the crystal pad 33 does not have to extend to the end of the bottom surface of the first recess 25 in the D2 direction.
  • the bottom surface of the first recess 25 (region around the second recess 27) has a portion located on the +D1 side, the ⁇ D2 side and/or the +D2 side in addition to or instead of the portion located on the ⁇ D1 side. You may have These portions may or may not overlap with the crystal element 3 in planar see-through.
  • the crystal element 3 When the crystal element 3 is supported at both ends, for example, it may be supported by the ⁇ D1 side portion and the +D1 side portion of the bottom surface of the first concave portion 25 . Also, for example, part of the second recess 27 may be located between the pair of crystal pads 33 .
  • the IC pad 35 is located, for example, on the bottom surface of the second recess 27 (region around the third recess 29).
  • the planar shape and dimensions of the bottom surface of the second recess 27 and the planar shape and dimensions of the IC pad 35 are arbitrary, and the relative relationship between them is also arbitrary.
  • the IC pad 35 may be located on the -D1 side (illustrated example), the +D1 side, the -D2 side (illustrated example), or the +D2 side (illustrated example) with respect to the third recess 29. .
  • the third recess 29 is smaller than the second recess 27 in both the D1 direction and the D2 direction. Also, the third recess 29 is biased toward the +D1 side with respect to the second recess 27 . As a result, the bottom surface of the second recess 27 (region around the third recess 29) is mainly exposed on the -D1 side, the -D2 side and the +D2 side.
  • a plurality of IC pads 35 are provided in the same number as the IC terminals 21 (eight in the illustrated example), and are arranged along the opening edge of the third recess 29 . For example, the IC pad 35 extends over the bottom surface of the second recess 27 from the inner peripheral side (the third recess 29 side) to the outer peripheral side.
  • the number of IC pads 35 may be greater than the number of IC terminals 21 . In other words, there may be dummy IC pads 35 that are not used. Further, for example, the length from the inner circumference side to the outer circumference side of the IC pad 35 may be shorter than the length from the inner circumference side to the outer circumference side of the bottom surface of the second recess 27 .
  • the bottom surface of the second recess 27 (the area surrounding the third recess 29) may have a sufficient width on the +D1 side, or conversely, may be wide enough on the -D1 side, the -D2 side and/or the +D2 side. It does not have to have a portion to be located. Also, for example, a part of the third recess 29 may be positioned between the IC pads 35 adjacent to each other along the opening edge of the third recess 29 .
  • the material of the crystal pad 33 is arbitrary.
  • the crystal pad 33 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the crystal pads 33 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. may In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 .
  • the thickness of the crystal pad 33 is also arbitrary.
  • the thickness of the crystal pad 33 may be the same as or different from the thickness of the IC pad 35 (described later). In any case, the description of the thickness of the IC pad 35 may be used for the thickness of the crystal pad 33 .
  • the plurality of external terminals 37 are composed of, for example, layered conductors (pads) located on the lower surface of the substrate 23 .
  • the oscillator 1 is mounted on the circuit board by joining the pads of the circuit board (not shown) and the external terminals 37 with solder or the like interposed therebetween. That is, the oscillator 1 in the illustrated example is of a surface mount type.
  • the number of external terminals 37, planar shape, size, position on the bottom surface, etc. are arbitrary. In the illustrated example, four external terminals 37 are positioned at four corners of the rectangular base 23 .
  • the shape of the external terminal 37 is, for example, rectangular. Note that, unlike the illustrated example, the number of external terminals 37 may be five or more. Also, the external terminal 37 may be pin-shaped. That is, the oscillator 1 does not have to be of the surface mount type.
  • the number and roles of the external terminals 37 may be appropriately set according to the functions required of the oscillator 1.
  • the plurality of external terminals 37 includes at least three external terminals 37 corresponding to the ground potential, power supply voltage and oscillation signal described in the description of the IC terminal 21 .
  • the plurality of external terminals 37 may further include external terminals 37 corresponding to control signals and the like.
  • the external terminals 37 may include dummy external terminals 37 that are used only for joining the oscillator 1 to the circuit board (not used for transmitting electrical signals).
  • the material of the external terminal 37 is arbitrary.
  • the external terminal 37 may be composed of one metal layer, or may be composed of two or more metal layers. At least part of the material of the external terminals 37 may be the same as at least part of the material of other conductor layers (for example, the material of the IC pads 35 (described later)) of the base 9, or may be completely different. good too. In any case, the description of the material of the IC pads 35 to be described later may be applied to the material of the crystal pads 33 .
  • the thickness of the external terminal 37 is also arbitrary.
  • the wiring conductor may be composed of a layered conductor (layered wiring) located on the upper surface or the lower surface of the insulating layer 31 and/or a penetrating conductor (via conductor) penetrating the insulating layer 31 .
  • any material can be used for the wiring conductor.
  • at least part of these materials may be the same as at least part of the materials of the other conductor layers of the base 9, or may be completely different.
  • the material of the portion of the wiring conductor embedded in the substrate 23 may be the same as the material of the lower layer 59 (described later) of the IC pad 35 .
  • the description of the material of the IC pads 35 may be applied to the wiring conductors as appropriate.
  • the first joining metal layer 39 is a member joined to the lid 11 by seam welding, for example.
  • the first bonding metal layer 39 is located on the upper surface of the base 23 (the portion surrounding the first recess 25 ) and extends over the entire circumference of the first recess 25 .
  • the width of the first bonding metal layer 39 is, for example, equivalent to the width of the upper surface of the base 23 . However, the former may be thinner than the latter.
  • the material and thickness of the first joining metal layer 39 may be set as appropriate.
  • the material of the first bonding metal layer 39 may be the same as or different from the material of the other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the first bonding metal layer 39 .
  • the first bonding metal layer 39 is composed of a layer made of W or Mo or an alloy containing at least one of these as a main component, a Ni layer overlapping the layer, and an Au layer overlapping the Ni layer. you can
  • the thickness of the first bonding metal layer 39 is, for example, 10 ⁇ m or more and 25 ⁇ m or less.
  • the die pad 42 is a member to which the lower surface of the IC 5 is adhered on its upper surface.
  • the die pad 42 contributes, for example, to improving the adhesive strength between the IC 5 and the base 9, improving the heat dissipation of the IC 5, and/or reducing noise.
  • Any material can be used for the die pad 42 .
  • the material of the die pad 42 may be the same as or different from the material of other conductor layers of the base 9 (for example, the material of the IC pads 35 (described later)). In any case, the description of the material of the IC pad 35 to be described later may be applied to the material of the die pad 42 . Note that the die pad 42 may not be provided.
  • the lid 11 is, for example, a plate-like member.
  • the lid 11 has, for example, a frame-shaped second bonding metal layer 47 on its lower surface.
  • the inside of the package 7 is hermetically sealed by joining the first joining metal layer 39 and the second joining metal layer 47 by seam welding or the like. That is, a closed space S1 is formed.
  • the lid 11 may be joined by a method other than seam welding.
  • the shape, material and dimensions of the lid body are arbitrary.
  • the shape and size of the outer edge of the lid body in plan view are generally the same as the shape and size of the outer edge of the upper surface of the base 9 in plan view.
  • the material of the lid body may be, for example, metal.
  • the metal may be, for example, iron, nickel or cobalt, or an alloy based on at least one of these.
  • the shape, material and dimensions of the second bonding metal layer 47 are arbitrary.
  • the shape and dimensions of the second bonding metal layer 47 are substantially the same as the shape and dimensions of the first bonding metal layer 39 .
  • the second bonding metal layer 47 is made of, for example, silver solder or gold tin.
  • the thickness of the second bonding metal layer 47 is, for example, 10 ⁇ m or more and 40 ⁇ m.
  • the mass % of Au may be, for example, 75 mass % or more and 85 mass % or less.
  • the conductive adhesive 41 has an insulating binder and conductive filler (conductive powder) dispersed in the binder.
  • the binder may be an organic material (eg, resin) or an inorganic material.
  • the resin may be, for example, a silicone resin, an epoxy resin, a polyimide resin, or a bismaleimide resin.
  • the material of the conductive filler may be metal, for example.
  • the metal may be, for example, aluminum, molybdenum, tungsten, platinum, palladium, silver, titanium, nickel or iron, or an alloy based on one or more of these.
  • the conductive adhesive 41 is interposed between the extraction electrode 17 (more specifically, its terminal portion) and the crystal pad 33 to join them together.
  • the conductive adhesive 41 is bonded, for example, to at least the area of the extraction electrode 17 facing the -D3 side.
  • the conductive adhesive 41 may be bonded to the area facing the -D1 side and/or the area facing the -D2 side or the +D2 side of the extraction electrode 17 .
  • the adhesive 43 is interposed between the bottom surface of the IC 5 and the bottom surface of the third recess 29 (the first surface 9a and the die pad 42) to bond them together.
  • the adhesive 43 spreads over substantially the entire lower surface of the IC 5, for example.
  • the material of the adhesive 43 is arbitrary.
  • the material of the adhesive 43 may be an insulating material or a conductive material.
  • the insulating material may be an organic material or an inorganic material.
  • the organic insulating material is, for example, a resin, and more specifically, may be a thermosetting resin that hardens when heated.
  • the resin may be the same as the resin forming the conductive adhesive 41, or may be different.
  • the conductive material may be, for example, a suitable metal. When the conductive material is solder, a material with a relatively high melting point may be selected so as not to be melted by an annealing treatment or the like, which will be described later.
  • Each bonding wire 45 has one end joined to the IC terminal 21 and the other end joined to the IC pad 35 . Thereby, the IC 5 is electrically connected to the package 7 (base portion 9).
  • the package 7 base portion 9
  • the bonding wires 45 may be formed by so-called ball bonding (the example shown in the figure) or may be formed by wedge bonding.
  • one end of the bonding wire 45 may be ball-shaped (dome-shaped or disk-shaped after bonding; hereinafter sometimes referred to as an enlarged diameter portion) having a diameter larger than that of the other portion. (illustrated example), but need not be such a shape. If ball bonding is used, the enlarged diameter portion may be located at the IC terminal 21 (example shown) or at the IC pad 35 .
  • enlarged diameter portions are formed at both ends of the bonding wire 45. may be configured.
  • the specific shape and dimensions of the bonding wire 45 are arbitrary.
  • the bonding wire 45 extends with a generally constant cross-section except at both ends.
  • the cross-sectional shape is, for example, circular.
  • the bonding wire 45 extends in a curved shape (loop shape) that is convex upward (+D3 side). In plan view, the bonding wire 45 extends linearly. The extending direction may be set appropriately. From another point of view, the relative positions of the IC terminals 21 and the IC pads 35 that are connected to each other are arbitrary.
  • the diameter of the portion of the bonding wire excluding both ends is, for example, 10 ⁇ m or more and 50 ⁇ m or less.
  • the diameter of the enlarged diameter portion of the bonding wire 45 in plan view (after bonding) is, for example, 70 ⁇ m or more and 100 ⁇ m or less.
  • the crystal element 3 faces the first surface 9a (bottom surface of the third recess 29) via the IC5.
  • the width, etc., where the crystal element 3 and the IC 5 overlap is arbitrary.
  • the term "IC5" may be replaced with "first surface 9a" as long as there is no contradiction.
  • a portion of the crystal element 3 overlaps the bottom surface of the first concave portion 25 and is bonded to the bottom surface with a conductive adhesive 41 . Therefore, the crystal element 3 may partially (illustrated example) or all of the remaining portion overlap the IC 5 .
  • the relative extent of the overlapping regions in the crystal element 3 is arbitrary.
  • the ratio of the area of the overlapping region to the area of the crystal element 3 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more.
  • the overlapping region may occupy a part (illustrated example) or the whole of the thin portion of the crystal element 3 and may occupy a part (illustrated example) or the whole of the excitation electrode 15 .
  • the IC 5 may partially or wholly overlap the crystal element 3 .
  • the relative width of the overlapping region at IC5 is arbitrary.
  • the ratio of the area of the overlapping region to the area of the IC 5 may be less than 1/2 (the example shown in the figure) or may be 1/2 or more.
  • the position of the geometric center of the crystal element 3 in the D2 direction and the position of the geometric center of the IC 5 in the D2 direction match. Unlike the illustrated example, both may be offset from each other. Also, the width of the crystal element 3 in the D2 direction is smaller than the width of the IC 5 in the D2 direction. The width of the former is within the width of the latter. Unlike the illustrated example, the width of the former may be greater than the width of the latter, or the width of the former may protrude from the width of the latter due to this or due to the displacement of the geometric center.
  • the crystal element 3 may overlap at least a portion of at least one IC pad 35, at least a portion of at least one bonding wire 45, and/or at least a portion of at least one IC terminal 21. However, it does not have to overlap these members at all.
  • the crystal element 3 is part of the two IC pads 35 on the -D1 side, all of the two bonding wires 45 connected to the IC pads 35, and connected to the two bonding wires 45. are overlapped for all of the two IC terminals 21 connected.
  • the term “crystal element 3" may be replaced with the term "thin portion of crystal element 3" or "excitation electrode 15" as long as there is no contradiction.
  • FIG. 4 is a cross-sectional view showing an enlarged region IV of FIG.
  • a bonding wire 45 (an example of a connection member) is made of gold (Au). At least the surface (more strictly, the upper surface (+D3 side surface)) of the IC terminal 21 is made of Au. Therefore, the bonding between the bonding wire 45 and the IC terminal 21 is a Au-to-Au bonding. This reduces the possibility of voids (and cracks) occurring in the bonding wires 45, as will be described in detail later.
  • the structure related to the bonding of the bonding wire 45 may take various forms, for example, a known form, except that the surfaces of the bonding wire 45 and the IC terminal 21 are made of Au as described above. I don't mind. Of course, novel aspects may also be applied.
  • the material of the IC terminal 21 and the material of the IC pad 35 will be described below, focusing on the illustrated example.
  • the IC terminal 21 is composed of, for example, four metal layers. Specifically, in the IC terminal 21 , a first layer 51 , a second layer 53 , a third layer 55 and an Au layer 57 made of different materials are laminated in order from the chip body 19 side of the IC 5 .
  • the Au layer 57 is, as its name suggests, a layer made of Au. Since the Au layer 57 forms the upper surface of the IC terminal 21, the upper surface of the IC terminal 21 is made of Au.
  • the first layer 51 may be located below the insulating protective layer of the chip body 19, and the IC terminal 21 may be formed by a portion exposed through an opening formed in the protective layer.
  • the side surface of each layer is exposed.
  • the side surfaces of some layers on the chip body 19 side may be covered with the chip body 19 (for example, the protective layer described above).
  • the side surface of the relatively lower ( ⁇ D3 side) layer may be covered with the relatively upper (+D3 side) layer (for example, the Au layer 57).
  • the influence of the side surface is limited. Therefore, the description of the conductor layer may not distinguish between the upper surface and the front surface.
  • the materials of the first layer 51, the second layer 53 and the third layer 55 are arbitrary.
  • the first layer 51 is made of aluminum or an alloy containing aluminum as a main component.
  • the second layer 53 is made of nickel or an alloy containing nickel as a main component.
  • the third layer 55 is made of palladium or a palladium-based alloy.
  • each layer constituting the IC terminal 21 is arbitrary.
  • each layer generally has a constant thickness.
  • each layer may have a different thickness, such as being thinner on the outer edge side.
  • any of these layers may be thicker than the other layers.
  • one of the first layer 51 and the second layer 53 may be thicker than the other.
  • the third layer 55 and the Au layer 57 may be thinner than the first layer 51 and/or the second layer 53, for example. Either the third layer 55 or the Au layer 57 may be thicker than the other.
  • the thickness of each layer may be, for example, 0.05 ⁇ m or more and 10 ⁇ m or less.
  • the second layer 53 and/or the third layer 55 may be omitted. Conversely, additional layers may be added. Further, instead of the first layer 51, a through conductor (non-layered conductor) is exposed from the chip body 19, and another layer (second layer 53, third layer 55 or Au layer 57) is superimposed thereon. may The materials of the first layer 51, the second layer 53 and the third layer 55 may be other than the materials described above. For example, W, Cu, Ti or Cr, or an alloy containing at least one of these as a main component may be used.
  • the IC pad 35 is composed of, for example, two metal layers. Specifically, in the IC pad 35 , a lower layer 59 and an upper layer 61 made of different materials are laminated in order from the substrate 23 side of the base 9 . In addition, in FIG. 4, the side surface of each layer is exposed. In contrast to the illustrated example, the sides of lower layer 59 may be covered by upper layer 61 .
  • the material of the lower layer 59 and the upper layer 61 are arbitrary.
  • the material of the lower layer 59 may be Ni, W, Cu, Al, or an alloy containing at least one of these as a main component.
  • the material of the upper layer 61 may be Au, Ag, Pt, or an alloy containing at least one of these as a main component.
  • the upper layer 61 is made of Au
  • at least the surface (strictly, the upper surface (+D3 side surface)) of the IC pad 35 is made of Au. Similar to the bonding, the bonding between the connection member and the IC pad 35 is also bonding between Au.
  • the IC pad 35 may be composed of one layer of metal, or may be composed of three or more layers of metal. In a mode composed of three or more layers of metal, the above description of the material of the IC terminal 21 may be applied to the material of the IC pad 35 .
  • the thickness of the IC pad 35 and its layers are arbitrary.
  • the thickness of the IC pad 35 may be thinner than, equal to, or thicker than the thickness of the IC terminal 21 .
  • the thickness of the IC pad 35 may be, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • Top layer 61 may be thinner than bottom layer 59, for example.
  • the thickness of the lower layer 59 may be, for example, 1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the upper layer 61 may be, for example, 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the material of the conductor layer (the excitation electrode 15 and the extraction electrode 17) of the crystal element 3 is arbitrary.
  • the conductor layer of the crystal element 3 may be composed of one metal layer, or may be composed of two or more metal layers.
  • the conductor layer of the crystal element 3 is composed of two metal layers. Specifically, a base layer 63 and a main layer 65 made of different materials are laminated in order from the crystal blank 13 side. In addition, in FIG. 4, the side surface of each layer is exposed. Unlike the illustrated example, the side surface of the underlying layer 63 may be covered with the main layer 65 .
  • the material of the underlying layer 63 may be Ni, Cr, or an alloy containing at least one of these as a main component.
  • the material of the main layer 65 may be Au, Ag, or an alloy containing at least one of these as a main component.
  • the main layer 65 is made of Au
  • at least the surface (strictly, the upper surface (+D3 side surface of the excitation electrode 15 on the +D3 side and -D3 side surface of the -D3 side excitation electrode 15)) of the excitation electrode 15 is composed of Au.
  • the surface of the excitation electrode 15, the connection member (bonding wire 45) and the surface of the IC terminal 21 are made of the same metal (Au).
  • the thickness of the conductor layer (excitation electrode 15 and extraction electrode 17) of the crystal element 3 is arbitrary.
  • the thickness of the conductor layer may be 1000 ⁇ or more and 4000 ⁇ or less.
  • the main layer 65 may occupy most of the above thickness (eg, 80% or more or 90% or more).
  • the thickness of the underlying layer 63 may be, for example, 10 ⁇ or more and 100 ⁇ or less.
  • the manufacturing method of the oscillator 1 may be the same as various manufacturing methods except for the specific materials of the connection member (bonding wire 45) and the IC terminal 21, and may be, for example, a known manufacturing method. .
  • An example of a procedure relating to packaging among the procedures of the method for manufacturing the oscillator 1 will be described below.
  • FIG. 5 is a flow chart showing an example of the procedure of the method for manufacturing the oscillator 1.
  • step ST1 the IC 5 is mounted on the base 9 of the package 7. Specifically, for example, first, the IC 5 is adhered to the first surface 9 a (die pad 42 ) of the base 9 with the adhesive 43 . Next, a bonding wire 45 is formed to electrically connect the IC terminal 21 and the IC pad 35 .
  • Bonding of the bonding wire 45 to the IC terminal 21 and the IC pad 35 is performed by, for example, applying ultrasonic waves, pressure and heat to the bonding wire 45 (and the IC terminal 21 and the IC pad 35 as necessary). done by Since ultrasonic waves are applied, Au is joined at a temperature lower than its melting point.
  • the heating temperature is, for example, 100° C. or more and less than 200° C.
  • the heating method may be various methods, for example, it may be a known method. For example, heating may be done by raising the temperature of a heating table on which the package 7 rests. As the heating temperature, the temperature of the heating means (for example, a heating table) that heats the object to be heated may be referred to. However, for the sake of convenience, the temperature of the object to be heated and the heating temperature are sometimes expressed without distinction. The matter described in this paragraph may be applied not only to heating for bonding connecting members, but also to heating in other steps (eg, ST2, ST3, ST5 and ST8).
  • steps eg., ST2, ST3, ST5 and ST8.
  • step ST2 the crystal element 3 is mounted on the base 9 of the package 7. Specifically, for example, an uncured conductive adhesive 41 is supplied to the crystal pad 33 . Next, the crystal element 3 is placed on the conductive adhesive 41 . After that, the conductive adhesive 41 is cured by heat treatment.
  • the heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45).
  • the heating time is, for example, 10 minutes or more and 1 hour or less.
  • the heating temperature for the embodiment in which the type of thermosetting resin of the conductive adhesive 41 is a silicone resin is higher than the heating temperature in the embodiment in which the type of the thermosetting resin for the conductive adhesive 41 is an epoxy resin.
  • the former is about 350°C and the latter is about 200°C.
  • step ST3 heat treatment (a heat treatment different from the heat treatment for curing the conductive adhesive 41 in step ST2) is performed.
  • this heat treatment for example, the residual stress of the conductive adhesive 41 is reduced (annealing treatment) and/or the conductive adhesive 41 is degassed.
  • the heating temperature at this time is, for example, 200° C. or higher and 400° C. or lower. From another point of view, the heating temperature here is, for example, higher than the heating temperature when bonding the connection member (bonding wire 45).
  • the heating time is, for example, 1 hour or more and 5 hours or less.
  • This heat treatment may be performed, for example, under a vacuum atmosphere.
  • step ST4 the frequency of the crystal element 3 is adjusted. Specifically, for example, the crystal element 3 is excited through the pads of the base portion 9 electrically connected to the crystal element 3 to measure the frequency characteristics of the crystal element 3, and depending on the measurement result, the excitation electrode 15 is measured. Increase and/or decrease mass.
  • step ST5 heat treatment is performed.
  • the description of step ST3 may be incorporated into this step.
  • step ST6 the frequency of the crystal element 3 is adjusted.
  • the description of step ST4 may be incorporated into this step.
  • step ST7 the long sides of the lid 11 are joined to the upper surface of the base 9 by seam welding.
  • step ST8 heat treatment is performed.
  • the description of step ST3 may generally be used for this step.
  • the heating time may be equal to or less than the heating time in step ST3, and is, for example, 10 minutes or more and 1 hour or less.
  • step ST9 the short sides of the lid 11 are joined to the upper surface of the base 9 by seam welding.
  • the concave portion of the base portion 9 is sealed to form a sealed space S1.
  • seam welding is performed in an appropriate atmosphere, so that the closed space S1 is in a vacuum state or in a state in which an appropriate gas (for example, nitrogen) is enclosed.
  • the crystal oscillator 1 As described above, the crystal oscillator 1 according to the first embodiment has the crystal element 3, the IC 5, the package 7, and the connecting members (bonding wires 45).
  • IC 5 has an IC terminal 21 .
  • a package 7 holds the crystal element 3 and the IC 5 .
  • the bonding wires 45 are made of gold (Au) and are joined to the IC terminals 21 and the package 7 .
  • the IC terminal 21 has a first Au layer (Au layer 57) that constitutes the surface of the IC terminal 21 and to which the bonding wire 45 is bonded.
  • the probability of voids and/or cracks occurring in the bonding wires 45 can be reduced, and the deterioration of the characteristics of the oscillator 1 can be reduced. Specifically, for example, it is as follows.
  • FIG. 6 is a diagram showing a bonding structure between bonding wires 45 and IC terminals (first layer 51) according to a comparative example, and corresponds to part of FIG.
  • the IC terminal is composed only of the first layer 51 of the embodiment.
  • the material of the first layer 51 is, for example, Al as described in the description of the embodiment.
  • a plurality of voids V1 and/or one or more cracks C1 may be formed in a portion of the bonding wire 45 near the IC terminal. rice field.
  • the diameter of the void V1 and the width of the crack C1 are, for example, 0.1 ⁇ m or more and 3 ⁇ m or less.
  • voids V1 and cracks C1 can be reduced.
  • the applicant has confirmed the above effects by taking cross-sectional photographs as shown in FIG. 6 for prototypes according to comparative examples and examples. More specifically, voids V1 and cracks C1 seen in Comparative Examples were not observed in Examples.
  • Relatively high heat may be applied to the bonding wires 45 and IC terminals during the manufacturing process of the oscillator, the process of incorporating the oscillator into the device (for example, the reflow process), and the process of using the device.
  • the bonding wire 45 is exposed to heat of 200° C. or higher or 300° C. or higher after bonding (step ST1) (step ST2, ST3, ST5 and ST8).
  • the bonding wire 45 (Au) and the IC terminal (Al) are mutually diffused by exposure to high heat as described above. That is, an alloy layer of Au and Al grows. At this time, multiple kinds of alloys grow. More specifically, for example, AuAl 2 (9 ppm/° C.), AuAl (12 ppm/° C.), Au 2 Al (13 ppm/° C.), Au 5 Al 2 (14 ppm/° C.) and Au 4 Al (12 ppm/° C.) is formed.
  • the numerical values shown in parentheses after the above compositional formulas are the linear expansion coefficients of the respective alloys. Various alloys have different coefficients of linear expansion. After the growth of the alloy layer, if the oscillator according to the comparative example is exposed to temperature cycles during its use, etc., a difference in thermal expansion occurs between the alloys having different coefficients of linear expansion, causing voids V1 and cracks C1.
  • the bonding between the bonding wire 45 and the IC terminal 21 is Au-to-Au bonding. Therefore, even if they are exposed to high heat, the growth of an alloy layer between them is reduced, and the growth of a plurality of alloy layers having different coefficients of linear expansion is also reduced. As a result, voids V1 and cracks C1 are less likely to occur even when the oscillator 1 is exposed to temperature cycles.
  • the IC terminal 21 may have the first layer 51 , the second layer 53 and the third layer 55 .
  • the first layer 51 may be made of aluminum or an alloy containing aluminum as a main component.
  • the second layer 53 may be made of nickel or a nickel-based alloy, and may overlap the first layer on the Au layer 57 side.
  • the third layer 55 may be composed of palladium or a palladium-based alloy, and may overlap the Au layer 57 side with respect to the second layer.
  • Au layer 57 may overlay the third layer.
  • the package 7 may have a base 9 and a lid 11 .
  • the base 9 may have a first surface 9a.
  • the lid 11 may be fixed to the base 9 such that the closed space S1 is formed on the first surface 9a.
  • the IC 5 may be fixed to the first surface 9a and accommodated in the sealed space S1.
  • the crystal element 3 may be accommodated in the sealed space S1 at a position facing the first surface 9a via the IC 5, and is bonded to the base 9 with a conductive adhesive 41 made of a resin in which conductive filler is dispersed. It can be.
  • the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective.
  • the reason is as follows.
  • the IC 5 it is necessary to mount the IC 5 on the base portion 9 before bonding the crystal element 3 to the base portion 9 with the conductive adhesive 41 .
  • the bonding wires 45 and the IC terminals 21 are exposed to heat for annealing and/or degassing the conductive adhesive 41 . Therefore, in the case where the aforementioned comparative example has the structure as described above, various alloy layers tend to grow between the bonding wire 45 and the IC terminal (the first layer 51), which in turn causes voids.
  • the probability of occurrence of V1 and crack C1 is particularly high. However, in this embodiment, such inconvenience is reduced.
  • the crystal element 3 may have a crystal blank 13 and an excitation electrode 15 overlapping the crystal blank 13 .
  • the thickness of the portion of the crystal blank 13 where the excitation electrode 15 overlaps may be 5 ⁇ m or more and 30 ⁇ m or less.
  • the effect of reducing the occurrence of voids V1 and cracks C1 described above is particularly effective.
  • it is as follows.
  • the adhesion amount of the gas generated from the conductive adhesive 41 and adhering to the crystal element 3 increases the mass and/or volume of the excitation region of the crystal element 3. increases relative to As a result, the effect of gas adhesion on the characteristics of the crystal element 3 increases. Therefore, heating for degassing the conductive adhesive 41 is carefully performed. As a result, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is particularly high. However, in this embodiment, such inconvenience is reduced.
  • the package 7 may have pads (IC pads 35) to which connection members (bonding wires 45) are bonded.
  • the IC pad 35 may have a second Au layer (upper layer 61).
  • the upper layer 61 constitutes the surface of the IC pad 35 and may be bonded with the bonding wire 45 .
  • bonding wires 45 are Au-to-Au bonding not only to IC terminals 21 but also to IC pads 35 . Therefore, as with the IC terminal 21 side, the probability of voids V1 and cracks C1 occurring in the bonding wires 45 is reduced.
  • the crystal element 3 and IC 5 may be accommodated in the same closed space S1.
  • the excitation electrode 15 of the crystal element 3 may have a third Au layer (main layer 65 ) forming the surface of the excitation electrode 15 .
  • connection member bonding wire 45
  • surface of the IC terminal 21 the surface of the excitation electrode 15 are all made of Au.
  • the effects (dissolution and/or reduction, etc.) of any material present in the package 7 during the manufacturing process or after completion on the Au are likely to be distributed to these members.
  • the change in the characteristics of the oscillator 1 as a whole is suppressed compared to the case where the substance affects only one member, and thus the change in the characteristics of the one member becomes large.
  • the method of manufacturing the crystal oscillator 1 according to the first embodiment manufactures the oscillator 1 configured such that the connecting member (bonding wire 45) made of Au and the Au layer 57 of the IC terminal 21 are bonded as described above. . Therefore, the various effects described above are achieved.
  • the manufacturing method of the oscillator 1 includes a bonding step (see step ST1) and one or more heating steps (see steps ST2, ST3, ST5 and ST8).
  • the bonding step the connection member (bonding wire 45 ) is bonded to the first Au layer (Au layer 57 ) and the base 9 of the package 7 .
  • the heating step after the bonding step, the bonding wires 45 are exposed to a temperature higher than the temperature of the bonding wires 45 during the bonding step (which may be the temperature of the heating means for heating the bonding wires 45 as described above). .
  • the bonding wire 45 is exposed to a temperature higher than the temperature at the time of bonding after bonding, so voids V1 and cracks C1 are likely to occur due to the growth of the alloy layer as described above. In other words, the effect of reducing the occurrence of voids V1 and cracks C1 is effectively exhibited by the bonding between Au layers in this embodiment.
  • the temperature of the bonding wires 45 does not necessarily have to reach the temperature of the heating means used in the heating step.
  • FIG. 7 is a cross-sectional view showing the configuration of a crystal oscillator 201 according to the second embodiment.
  • the connecting member for electrically connecting the IC 5 and the package 7 was the bonding wire 45 .
  • the connection member is the bump 245 . Specifically, for example, it is as follows.
  • the oscillator 201 has a crystal element 3, an IC 5, and a package 207, like the oscillator 1 of the first embodiment.
  • the package 207 has a base 209 and a lid 11 that closes the recess of the base 209, like the package 7 of the first embodiment.
  • the crystal element 3 and IC 5 are accommodated in the recess.
  • the IC 5 faces the first surface 209a of the base portion 209 (the bottom surface of the recess in the illustrated example), and the crystal element 3 faces the first surface 9a through the IC 5. facing each other.
  • the specific shape of the base 209 differs from that of the first embodiment due to the difference in the mounting structure of the IC5.
  • the base 9 of the first embodiment has three recesses
  • the base 209 has two recesses, a first recess 225 and a second recess 227 opening at the bottom surface of the first recess 225.
  • the insulating substrate 223 of the base 209 is drawn as a laminate of three insulating layers (first insulating layer 31E, second insulating layer 31F and third insulating layer 31G).
  • the first concave portion 225 corresponds to the first concave portion 25 of the first embodiment. That is, the first concave portion 225 contributes to accommodation of the crystal element 3 .
  • the crystal element 3 is mounted on the bottom surface of the first concave portion 225 as in the first embodiment.
  • the second recessed portion 227 corresponds to the second recessed portion 27 and the third recessed portion 29 of the first embodiment. That is, the second concave portion 227 contributes to accommodation of the IC 5 and the connection member (bump 245).
  • the IC 5 is surface-mounted on the bottom surface of the second recess 227 (from another point of view, the bottom surface of the recess of the base 209) as the first surface 209a.
  • the base 209 has the IC pad 35 on the bottom surface of the second recess 227 .
  • the IC 5 is arranged so that the IC terminal 21 faces the IC pad 35 .
  • the IC 5 is fixed and electrically connected to the package 7 by bonding the IC pads 35 and the IC terminals 21 with the bumps 245 interposed therebetween.
  • the IC pads 35 are basically the same as the IC pads 35 of the first embodiment, except that they are provided on the first surface 209a and face the IC terminals 21 .
  • the number, planar shape and dimensions of the IC pads 35 are arbitrary, as in the first embodiment.
  • the IC pad 35 may be wider than the IC terminal 21 (the example shown in the figure), may be of the same width, or may be narrower than the IC terminal 21 when viewed through the plane.
  • the IC terminal 21 is as described in the first embodiment. However, the details may differ from the first embodiment due to the difference in connection members (bonding wires 45 and bumps 245).
  • the IC terminals 21 (as well as the bumps 245 and IC pads 35) serve to support the IC5. Therefore, the plurality of IC terminals 21 may be arranged symmetrically in each of the D1 direction and the D2 direction so as to support the IC 5 in a well-balanced manner.
  • the shape and dimensions of the bump 245 are arbitrary.
  • the side surface of the bump 245 may bulge outward (the example shown), may be recessed inward, or may have a shape that cannot be said to be either of the former.
  • Either the area where the bump 245 and the IC terminal 21 are bonded or the area where the bump 245 and the IC pad 35 are bonded may be larger.
  • An example of the diameter (for example, maximum diameter) of the bump 245 is 90 ⁇ m or more and 120 ⁇ m or less.
  • the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
  • a sealing resin 49 see FIG. 11, in other words, an underfill
  • FIG. 8 is an enlarged view of region VIII in FIG.
  • the bumps 245 are made of Au, like the bonding wires 45 . Therefore, in this embodiment as well, the bonding between the connection member (bump 245) and the IC terminal 21 (at least the surface of which is made of Au) is Au-to-Au bonding. Also, similarly to the first embodiment, bonding between the bumps 245 and the IC pads 35 may be performed by bonding between Au.
  • connection member is made of gold (Au)
  • the IC terminal 21 has the first Au layer (Au layer 57), as in the first embodiment.
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first embodiment can be obtained. Specifically, it is as follows.
  • FIG. 9 is a diagram showing a bonding structure between the bump 245 and the IC terminal (first layer 51) according to the comparative example, and corresponds to FIG.
  • the IC terminal is composed only of the first layer 51 of the embodiment, similar to the comparative example in FIG.
  • voids V1 and cracks C1 are generated in portions of the bumps 245 near the IC terminals by the same principle as the voids V1 and cracks C1 in the portions of the bonding wires 45 near the IC terminals in the comparative example of FIG.
  • a crack C1 occurs.
  • the probability of occurrence of voids V1 and cracks C1 is reduced by the same principle as in the oscillator 1 of the first embodiment.
  • FIG. 10 is a cross-sectional view showing the configuration of a crystal oscillator 301 according to the third embodiment.
  • the crystal element 3 is mounted on the package 67 in this embodiment.
  • Package 67 is mounted on package 307 .
  • the package 307 corresponds to the packages 7 and 207 of the first and second embodiments.
  • the package 307 is a package to which connection members (bumps 245 in the illustrated example) that are bonded to the IC 5 are bonded.
  • the crystal element 3 may be indirectly held by the package 307 rather than directly by the package 7 or 207 to which the connection member (bonding wire 45 or bump 245) is bonded.
  • Various modes of indirectly holding the crystal element 3 in the package 307 are possible. In the illustrated example:
  • the package 307 has a base 309 and a lid 11 as in other embodiments.
  • the insulating substrate 323 of the base portion 309 has a first recess 325 and a second recess 327 opening at the bottom surface of the first recess 325 .
  • the first concave portion 325 contributes to housing the IC5.
  • An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the first recess 325 (around the opening of the second recess 327).
  • the IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the surface on the -D3 side.
  • the IC 5 is mounted on the package 307 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 .
  • FIG. 8 may be taken as a cross-sectional view of the bump 245 and its surroundings in this embodiment.
  • the second recess 327 contributes to housing the package 67.
  • a pad (not shown) is formed on the bottom surface of the second recess 327 .
  • the package 67 also has terminals (not shown) on its lower surface.
  • the package 67 is mounted on the package 307 (base portion 309) by bonding the pads and terminals with the bumps 69. As shown in FIG. That is, the package 67 is fixed and electrically connected to the package 307 .
  • a combination of the crystal element 3 and the package 67 may be regarded as a crystal oscillator 68 .
  • the crystal oscillator 68 may be a general-purpose one that is not assumed to be mounted in the package 307 . From another point of view, the crystal oscillator 68 may be distributed alone. However, the crystal oscillator 68 may be one that is assumed to be mounted in the package 307 . In the illustrated example, the crystal oscillator 68 has only the crystal element 3 as an electronic element. However, the crystal oscillator 68 may have other electronic elements such as a temperature sensor.
  • the configuration of the package 67 is arbitrary.
  • the package 67 has a base portion having a recess and a lid that closes (seales) the recess, although no particular reference numerals are attached.
  • a crystal pad 33 (not shown here) is provided on the bottom surface of the recess. Then, the crystal element 3 is mounted in the package 67 by, for example, bonding the lead-out electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
  • the package 67 may have a plate-like base (substrate) on which the crystal element 3 is mounted, and a cap-like lid that covers the base from above the crystal element 3 .
  • the package 67 may have two or more recesses like the package 307, or may be H-shaped like the package 407 (FIG. 11) described later.
  • the description of the package 7 may be appropriately applied to the package 67, except that the IC5 is not mounted inside the package 67.
  • the base may have a base made of an insulating material such as ceramic, and a conductive layer and through conductors provided on the base.
  • the lid may be a metal plate that is secured to the base by seam welding or the like.
  • the configuration of pads, bumps 69 and terminals for mounting the package 67 on the package 307 is arbitrary.
  • the description of the IC pads 35 , bumps 245 and IC terminals 21 may be incorporated into the pads, bumps 69 and terminals associated with mounting the package 67 .
  • the bonding between the pads and the bumps 69 and/or the bonding between the bumps 69 and the terminals may be Au-to-Au bonding.
  • the IC 5 may be covered with a sealing resin 49 (see FIG. 11, in other words, an underfill) at least partly (for example, the surface where the IC terminals 21 are located). good.
  • a sealing resin 49 see FIG. 11, in other words, an underfill
  • the crystal element 3 is positioned below the IC 5 (on the -D3 side).
  • the positional relationship between the IC 5 and the crystal element 3 is not limited to the configuration in which the crystal element 3 cannot be mounted unless the IC 5 is mounted.
  • the IC 5 may be positioned below the crystal element 3 as in the first or second embodiment.
  • the bump 245 is taken as an example of the connection member.
  • the bonding wire 45 may be used as the connecting member as in the first embodiment.
  • the IC 5 may be arranged so that the IC terminal 21 faces the +D3 side and fixed to the bottom surface of the first recess 325 .
  • the IC pads 35 may be provided on the bottom surface of the first recess 325 or on the top surface of a pedestal provided on the bottom surface.
  • a bonding wire 45 may be bonded to the IC terminal 21 and the IC pad 35 .
  • the connecting members are made of gold (Au)
  • the IC terminals 21 are made of the first Au layer (Au layer 57), as in the first and second embodiments. have.
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first and second embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
  • the crystal element 3 is housed in the package 67 .
  • the process of heating the conductive adhesive 41 is performed before the crystal oscillator 68 and the IC 5 are mounted on the package 307 .
  • the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced.
  • the same inconvenience as the inconvenience described with reference to FIG. is reduced.
  • FIG. 11 is a cross-sectional view showing the configuration of a crystal oscillator 401 according to the fourth embodiment.
  • the package 407 of the oscillator 401 is a so-called H-shaped one that exhibits an H shape in cross section. That is, the base 409 of the package 407 has a first recess 425 and a second recess 427 that opens on the side opposite to the first recess 425 .
  • the crystal element 3 is housed in the first concave portion 425 .
  • IC5 is housed in the second recess 427 .
  • the first recess 425 is sealed with the lid 11 .
  • the crystal element 3 does not have to be arranged in the same space (recess) as the IC 5 .
  • the base portion 409 has a base 423 made of an insulating material, and a conductor layer and through conductors provided on the base 423 .
  • the base 423 is integrally formed as a whole. As described in the description of the substrate 23 in the first embodiment, such a substrate 423 may be produced by stacking insulating layers, or may be produced by another method. Lid 11 may be a metal plate secured to base 409 by seam welding or the like, as in other embodiments.
  • the first recess 425 contributes to housing the crystal element 3 .
  • a crystal pad 33 (not shown here) is provided on the bottom surface of the first recess 425 . Then, the crystal element 3 is mounted in the package 407 by, for example, bonding the extraction electrodes 17 (not shown here) and the crystal pads 33 with the conductive adhesive 41 in the same manner as in the first embodiment. be.
  • the second recess 427 contributes to housing the IC5.
  • An IC pad 35 (not shown here, see FIG. 8) is provided on the bottom surface of the second recess 427 .
  • the IC 5 is provided with an IC terminal 21 (not shown here, see FIG. 8) on the +D3 side surface.
  • the IC 5 is mounted on the package 407 by bonding the IC terminals 21 and the IC pads 35 with the bumps 245 .
  • FIG. 8 can be regarded as a cross-sectional view of the bump 245 and its surroundings in this embodiment, with the sign of the D3 direction reversed.
  • the IC 5 is entirely covered with a sealing resin 49 .
  • the sealing resin 49 may be provided so that the ⁇ D3 side surface is located at any position in the range from the +D3 side surface of the IC 5 to the ⁇ D3 side surface. Also, the sealing resin 49 may not be provided.
  • the sealing resin 49 may be made of, for example, a thermosetting resin that hardens when heated.
  • thermosetting resins include silicone resins and epoxy resins.
  • the sealing resin 49 may be the same as or different from the resin forming the conductive adhesive 41 and/or the resin forming the adhesive 43 .
  • the bump 245 is taken as an example of the connection member.
  • the bonding wire 45 may be used as the connection member.
  • the IC 5 may be arranged so that the IC terminal 21 faces the ⁇ D 3 side and fixed to the bottom surface of the second recess 427 .
  • the IC pads 35 may be provided on the bottom surface of the second recess 427 or on the top surface (surface on the -D3 side) of the pedestal provided on the bottom surface. Then, the IC terminal 21 and the IC pad 35 may be bonded by the bonding wire 45 .
  • the H-shaped package has a container-shaped package similar to the package 67 shown in the third embodiment, and a circuit board bonded to the lower surface (the outer surface on the ⁇ D3 side) of the container-shaped package. you can By forming the opening in the circuit board, an H shape in a cross-sectional view may be obtained.
  • the IC 5 may be mounted on the bottom surface of the container-type package and housed in the opening.
  • the connection member (bump 245) is made of gold (Au)
  • the IC terminal 21 is made of the first Au layer (Au layer 57).
  • the Au layer 57 constitutes the surface of the IC terminal 21, and the bump 245 is bonded thereto. Therefore, the same effects as those of the first to third embodiments can be obtained. For example, the probability of occurrence of voids V1 and cracks C1 is reduced.
  • the crystal element 3 can be mounted on the package 407 before the IC 5 is mounted.
  • the process of heating the conductive adhesive 41 is performed before the IC 5 is mounted on the package 407 .
  • the probability and/or frequency that the connection member (bump 245) is exposed to high temperatures is reduced.
  • the same inconvenience as the inconvenience described with reference to FIG. is reduced.
  • the oscillator 1 may further include an insulating resin (sealing resin 49) covering at least the surface of the IC 5 where the IC terminal 21 is located (the surface on the +D3 side in this embodiment).
  • an insulating resin covering at least the surface of the IC 5 where the IC terminal 21 is located (the surface on the +D3 side in this embodiment).
  • the sealing resin 49 contributes to reducing the probability that the plurality of IC terminals 21 are short-circuited with each other and that foreign matter enters between the IC 5 and the package 7 .
  • the sealing resin 49 when the sealing resin 49 is provided, stress is applied to the IC terminals 21 due to shrinkage during curing. As a result, the void V1 or crack C1 in the bonding wire 45 may expand.
  • the probability of voids V1 and cracks C1 being generated is reduced, so naturally the probability of expansion of voids V1 and cracks C1 is also reduced. As a result, the probability that the characteristics of the oscillator 1 will deteriorate is reduced.
  • FIG. 12 is a diagram showing temporal changes in the characteristics of the oscillator according to the comparative example.
  • the horizontal axis indicates the elapsed time (unit: hours), and is on a logarithmic scale.
  • the vertical axis indicates the ratio DF/D (ppm) of the change amount DF of the frequency F with elapsed time to the initial value F of the frequency of the oscillation signal output by the oscillator.
  • a plurality of lines in the figure indicate changes over time in DF/D of a plurality of prototypes.
  • the configuration of the comparative example has been described with reference to FIG. That is, in the oscillator 1 according to the first embodiment, the IC terminals are configured only by the first layer 51 (specifically, Al).
  • a prototype according to this comparative example was produced under the same conditions as those of the manufacturing method described with reference to FIG. 5, and then exposed to an environment of 125.degree.
  • FIG. 12 shows the change over time of DF/D under the 125° C. environment.
  • the absolute value of DF/D after 1000 hours is 3 ppm or more.
  • the absolute value of DF/D after 1000 hours has passed is 10 ppm or less, and the oscillator according to the comparative example has the ability to maintain characteristics required for general oscillators.
  • FIG. 13 is a diagram showing temporal changes in the characteristics of the oscillator according to the example.
  • FIG. 12 This figure is similar to FIG. However, unlike FIG. 12, the horizontal axis does not have a logarithmic scale. Similar to the comparative example, the example also shows changes over time in DF/D of a plurality of prototypes.
  • the configuration of the oscillator according to the example is the same as the configuration of the oscillator 1 of the first embodiment.
  • the IC terminal in the comparative example is replaced with an IC terminal composed of four layers (specifically, Al/Ni/Pd/Au).
  • Other conditions are the same between the example and the comparative example.
  • the absolute value of DF/D after 1000 hours is 3 ppm or less (more specifically, less than 2 ppm). That is, the DF/D after 1000 hours in the example is smaller than the DF/D after 1000 hours in the example. As a result, it was confirmed that the ability to maintain characteristics of the examples was higher than the ability to maintain characteristics of the comparative examples.
  • the bonding wires 45 and the bumps 245 are examples of connection members.
  • the IC terminal 21 is an example of a terminal that the IC has.
  • the Au layer 57 of the IC terminal 21 is an example of the first Au layer.
  • the sealing resin 49 is an example of an insulating resin that covers the surface of the IC where the terminals are located.
  • the IC pad 35 is an example of a pad to which a connection member is bonded.
  • the upper layer 61 of the IC pad 35 is an example of the second Au layer.
  • the main layer 65 of the excitation electrode 15 is an example of the third Au layer.
  • Step ST1 is an example of a joining step.
  • Each of steps ST2, ST3, ST5 and ST8 is an example of a heating step.
  • the oscillator may be a clock oscillator, a voltage controlled oscillator (abbreviation: VCXO), a temperature compensated oscillator (abbreviation: TCXO), or a It may be an oscillator in a constant temperature oven of an oscillator (abbreviation: OCXO).
  • VCXO voltage controlled oscillator
  • TCXO temperature compensated oscillator
  • OCXO constant temperature oven of an oscillator
  • the number and arrangement of external terminals, IC pads, and IC terminals may be appropriately set according to the functions required of these oscillators.
  • the oscillator had only a crystal element and an IC as electronic elements.
  • the oscillator may have other elements.
  • a temperature sensor may be provided separately from the IC.
  • a piezoelectric device a piezoelectric oscillator, or a crystal device, which are higher concepts than crystal oscillators.
  • a piezoelectric element containing a piezoelectric material other than crystal may be used in place of the crystal element.
  • the piezoelectric and crystal devices need not be oscillators.
  • piezoelectric devices and crystal devices may be vibrators with temperature sensors instead of ICs.
  • connection member wire bonding or bump
  • IC terminal whose surface at least is made of Au.
  • the surfaces of the connecting members and the IC terminals may be made of a material other than Au (for example, Al or Cu).

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JP2018074350A (ja) * 2016-10-28 2018-05-10 株式会社大真空 表面実装型圧電発振器とその回路基板への搭載構造
JP2020136999A (ja) * 2019-02-22 2020-08-31 京セラ株式会社 水晶素子、水晶デバイス及び電子機器

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