WO2023005596A1 - 显示面板的驱动方法、显示面板及显示装置 - Google Patents

显示面板的驱动方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2023005596A1
WO2023005596A1 PCT/CN2022/103254 CN2022103254W WO2023005596A1 WO 2023005596 A1 WO2023005596 A1 WO 2023005596A1 CN 2022103254 W CN2022103254 W CN 2022103254W WO 2023005596 A1 WO2023005596 A1 WO 2023005596A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
pull
display panel
row
input
Prior art date
Application number
PCT/CN2022/103254
Other languages
English (en)
French (fr)
Inventor
王慧
刘荣铖
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/271,840 priority Critical patent/US20240071272A1/en
Publication of WO2023005596A1 publication Critical patent/WO2023005596A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present disclosure belongs to the field of display technology, and in particular relates to a driving method of a display panel, a display panel and a display device.
  • the gate switch circuit composed of thin film transistor (Thin Film Transistor, TFT) is integrated on the array substrate of the display panel to form a scan drive for the display panel, so that the gate drive integrated circuit part can be saved, which can not only
  • TFT Thin Film Transistor
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a method for driving a display panel, a display panel, and a display device.
  • an embodiment of the present disclosure provides a method for driving a display panel, the display panel comprising: N gate lines and M data lines intersected, and a gate line and a data line within the defined area.
  • the pixel unit; the display panel also includes: N shift registers and P clock signal lines; every adjacent P shift registers in the N shift registers are respectively connected to the P clock signal lines; The signal output ends of the N shift registers are respectively connected to the N gate lines in one-to-one correspondence; wherein, P is an even number greater than or equal to 2; N is an integer greater than or equal to P; M is a positive integer;
  • the driving method of the display panel includes:
  • n is a positive integer less than or equal to N
  • the grayscale difference between the input data signal of the pixel unit in the nth row and the pixel unit in the n-1th row is greater than the threshold, adjust the phase of the clock signal input by the nth shift register so that the nth shift register The falling edge of the pull-up node is time-delayed to output a phase-delayed scan signal.
  • the grayscale difference between the pixel unit in the nth row and the data signal input by the pixel unit in the n-1th row is greater than the threshold
  • the time of the data signal input by the pixel unit in the nth row and the time of the shift register in the nth row is greater than 1H; wherein, 1H is the charging time of a row of pixel units.
  • said adjusting the phase of the clock signal input by the nth shift register includes:
  • the non-working level maintenance time of the clock signal input by the nth shift register is extended.
  • the non-working level maintenance time of the clock signal input by the nth shift register is 1H to 2H longer than the non-working level maintenance time of the preset clock signal.
  • the non-working level maintenance time of the clock signal input by the nth shift register is equal to the precharge maintenance time of the pull-up node.
  • said adjusting the phase of the clock signal input by the nth shift register includes:
  • the working level maintenance time of the clock signal input by the nth shift register is 1H to 2H longer than the working level maintenance time of the preset clock signal.
  • the maintaining time of the working level of the clock signal input by the nth shift register is equal to the charging time of the pull-up node.
  • the time of the data signal input by the pixel unit in the nth row overlaps with the charging time of the pull-up node, and the overlapping time is greater than or equal to 2H.
  • the driving method of the display panel further includes:
  • the grayscale value difference between the pixel unit in the n+m row and the data signal input by the pixel unit in the n+m-1 row is less than or equal to the threshold, then input the clock signal of the initial phase to the n+m shift register .
  • an embodiment of the present disclosure provides a display panel, the display panel includes a detection module, and the detection module is configured to detect the input data of the pixel unit in the nth row and the pixel unit in the n-1th row Whether the grayscale value difference of the signal is greater than the threshold value; if the grayscale difference value of the data signal input by the pixel unit in the nth row and the pixel unit in the n-1th row is greater than the threshold value, adjust the clock input by the nth shift register The phase of the signal makes the time delay of the falling edge of the pull-up node of the nth shift register to output a phase-delayed scan signal.
  • each of the N shift registers includes: an input subcircuit, an output subcircuit, and a pull-up reset subcircuit;
  • the input subcircuit is configured to respond to an input signal at a signal input terminal and write the input signal to a pull-up node;
  • the output subcircuit is configured to respond to the potential of the pull-up node, and output the clock signal input from the clock signal terminal through the signal output terminal;
  • the pull-up reset subcircuit is configured to respond to a pull-up reset signal input from a pull-up reset signal terminal, and reset the potential of the pull-up node through a non-working level signal.
  • the signal output end of the i-th shift register is connected to the signal input end of the i+p-th shift register; wherein, P/2 ⁇ p ⁇ N; i ⁇ N-p;
  • the pull-up reset signal end of the jth shift register is connected to the signal output end of the j+qth shift register; 2 ⁇ q-p ⁇ N/2; j ⁇ N-q.
  • the display panel further includes: a first frame start signal line and a second frame start signal line;
  • the signal input terminals of the odd-numbered rows in the first to N/2th shift registers are all connected to the first frame start signal line;
  • the signal input terminals of the even-numbered rows in the first to N/2th shift registers are all connected to the second frame-on signal line.
  • an embodiment of the present disclosure provides a display device, and the display device includes the display panel as provided above.
  • FIG. 1 is a timing diagram of an exemplary scan signal, data signal and common electrode signal of a display panel
  • FIG. 2 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an initial row in a gate drive circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of multiple redundant shift registers in a gate drive circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of signals input by a display panel including 12 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 6 is another timing diagram of signals input by a display panel including 12 clock signal lines provided by an embodiment of the present disclosure
  • Fig. 7 is a timing diagram of scan signals, data signals and common electrode signals of a display panel comprising 12 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 8 is a timing diagram of signals input by a display panel including 6 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 9 is another timing diagram of signals input by a display panel including 12 clock signal lines provided by an embodiment of the present disclosure.
  • FIG. 10 is another timing diagram of signals input by a display panel including 12 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 11 is another timing diagram of scanning signals, data signals and common electrode signals of a display panel including 12 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 12 is another timing diagram of signals input by a display panel including 6 clock signal lines provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 1 is a timing diagram of an exemplary scan signal and data signal of a display panel.
  • Switch to L255, or switch from L0 to L255, etc.
  • the switching of the data signal Data will easily cause the common electrode signal Vcom in the display panel to be pulled due to capacitive coupling, causing the common electrode signal Vcom to fluctuate.
  • the scanning signal Gate is turned off , the common electrode signal Vcom is not restored to the original state, which causes the common electrode signal Vcom corresponding to the row of pixel units to be different from the common electrode signal Vcom at other positions, resulting in poor display such as horizontal crosstalk.
  • the data signal Data changes, the pixel units in this row are not precharged or reversely precharged, so that the charging rate of the pixel units in this row is low, and display defects such as line afterimages are prone to occur.
  • embodiments of the present disclosure provide a method for driving a display panel, a display panel, and a display device.
  • the method for driving a display panel provided by an embodiment of the present disclosure will be described below in conjunction with the accompanying drawings and specific implementation methods. , the display panel and the display device are further described in detail.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, the source , Drain is no difference. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of transistors, transistors can be divided into N-type and P-type. In the following embodiments, N-type transistors are used for illustration. The drain of the N-type transistor, when the gate is input with a high level, the source and drain are turned on, and the P-type is opposite. It is conceivable that the implementation using P-type transistors can be easily conceived by those skilled in the art without any creative work, and thus also falls within the protection scope of the embodiments of the present disclosure.
  • the working level signal in the embodiment of the disclosure refers to a high-level signal
  • the non-working level signal is a low-level signal
  • the working level terminal is the high level signal terminal
  • the non-working level terminal is the low level signal terminal.
  • a display panel includes a plurality of gate lines and a plurality of data lines, and the intersecting arrangement of the gate lines and the data lines defines a plurality of pixel areas, and each pixel area is provided with a pixel unit.
  • the structure of the display panel is described by taking the extending direction of each gate line as the row direction and the extending direction of each data line as the column direction as an example.
  • the pole driving signal is provided by the gate driving circuit, and the data signal is provided by the source driving circuit;
  • the gate driving circuit can be integrated in the gate driving chip, and the source driving circuit can be integrated in the source driving chip Medium; currently, in order to reduce the number of chips and realize narrow borders or no borders, a technology of integrating the gate drive circuit on the array substrate (Gate On Array; GOA) is provided; wherein, the gate drive circuit includes integrated On the array substrate, a plurality of cascaded shift registers are connected one by one to the gate lines, and are used to provide scan signals for the gate lines connected thereto.
  • FIG. 2 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register includes: an input subcircuit, an output subcircuit, and a pull-up reset subcircuit; wherein, the input subcircuit is configured to respond to the input signal input by the signal input terminal INPUT, and write the input signal into the pull-up node PU to charge the pull-up node PU; the output sub-circuit is configured to respond to the potential of the pull-up node PU, and The clock signal input by the clock signal terminal CLK is output through the signal output terminal OUTPUT; the pull-up reset subcircuit is configured to respond to the pull-up reset signal output by the pull-up reset signal terminal RESET_PU, and pull up the node PU through a low level signal. The potential is reset.
  • the input subcircuit includes a first transistor M1; the pull-up reset subcircuit includes a second transistor M2; the output subcircuit includes a third transistor M3 and a storage capacitor C; wherein, the gate of the first transistor M1 The pole and source are connected to the signal input terminal INPUT, the drain is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL
  • the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal OUTPUT; the first terminal of the storage capacitor C is connected to the pull-up node PU, and the second terminal is connected to the signal output terminal OUTPUT.
  • the pull-up node PU is reset in the reset phase, the pull-up node PU is at a low level, at this time the third transistor M3 is turned off, and the signal output terminal OUTPUT no longer outputs, so as to complete the signal output Reset of terminal OUTPUT.
  • the shift register provided by the embodiment of the present disclosure further includes: a first pull-down control subcircuit, a second pull-down control subcircuit, a first pull-down subcircuit, a second pull-down subcircuit, a first noise reduction Sub-circuit, second noise reduction sub-circuit, discharging sub-circuit, first auxiliary sub-circuit, second auxiliary sub-circuit and cascade sub-circuit.
  • the discharge sub-circuit responds to the frame start signal input by the frame start signal terminal STV, and discharges the pull-up node PU through the low level input by the low level signal terminal VGL; the first pull-down control sub-circuit and the second pull-down control sub-circuit
  • the structure and function of the control sub-circuit are the same, and the two only work in time-sharing; in the same way, the structure and function of the first pull-down sub-circuit and the second pull-down sub-circuit are the same; the structure and function of the first auxiliary sub-circuit and the second auxiliary sub-circuit
  • the functions are the same; the structures and functions of the first noise reduction sub-circuit and the second noise reduction sub-circuit are the same.
  • the structure and function of the input sub-circuit, output sub-circuit and pull-up reset sub-circuit are the same as those mentioned above, so the details will not be repeated here.
  • Both the first auxiliary sub-circuit and the second auxiliary sub-circuit are configured to respond to the input signal input from the signal input terminal INPUT, and respectively pull down the potential of the first pull-down node PD1 and the second pull-down node PD2 through a low-level signal potential;
  • the first pull-down control subcircuit is configured to respond to the first power supply voltage input by the first power supply voltage signal terminal VDDO to control the potential of the first pull-down node PD1;
  • the second pull-down control subcircuit is configured to In response to the second power supply voltage input by the second power supply voltage signal terminal VDDE, to control the potential of the second pull-down node PD2;
  • the first pull-down sub-circuit is configured to respond to the potential of the pull-up node PU, and pass a low level
  • the low-level signal input by the signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the first pull-down control node PD_CN1;
  • the signals output by the cascaded signal output terminal OUT_C and the signal output terminal OUTPUT are the same, except that two output terminals are set in the shift register unit, one is the signal output terminal OUTPUT connected to the gate line , and the other is the cascading signal output terminal OUT_C for cascading.
  • the reason why the cascaded sub-circuit is provided separately is to reduce the load of the signal output terminal OUTPUT, so as to avoid affecting the scanning signal output by the signal output terminal OUTPUT.
  • both the first pull-down control subcircuit and the second pull-down control subcircuit include a fifth transistor and a ninth transistor; wherein, the first pull-down control subcircuit and the second pull-down control subcircuit
  • the fifth transistors in are denoted by M5 and M5' respectively
  • the ninth transistors are denoted by M9 and M9' respectively.
  • Both the first pull-down sub-circuit and the second pull-down sub-circuit include a sixth transistor and an eighth transistor; wherein, the sixth transistor in the first pull-down sub-circuit and the second pull-down sub-circuit is represented by M6 and M6' respectively, and The eight transistors are denoted by M8 and M8' respectively.
  • Both the first noise reduction sub-circuit and the second noise reduction sub-circuit include a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein, the tenth transistor in the first noise reduction sub-circuit and the second noise reduction sub-circuit respectively Denoted by M10 and M10', the eleventh transistor is denoted by M11 and M11' respectively; the discharge sub-circuit includes a seventh transistor M7.
  • Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include a sixteenth transistor, denoted by M16 and M16' respectively.
  • the gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down control node PD_CN1; the gate of the ninth transistor M9 is connected to the first pull-down control node PD_CN1, and the source is connected to the first pull-down control node PD_CN1.
  • the drain is connected to the first pull-down node PD1; the gate and source of the fifth transistor M5' are connected to the second power supply voltage terminal VDDE, and the drain is connected to the second pull-down control node PD_CN2;
  • the gate of the transistor M9' is connected to the second pull-down control node PD_CN2, the source is connected to the second power supply voltage terminal, and the drain is connected to the first pull-down node PD1;
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, and the source is connected to the first pull-down node PU.
  • a pull-down node PD1 the drain is connected to the low-level signal terminal; the gate of the eighth transistor M8 is connected to the pull-up node PU, the source is connected to the first pull-down control node PD_CN1, and the drain is connected to the low-level signal terminal VGL;
  • the gate of the sixth transistor M6' is connected to the pull-up node PU, the source is connected to the second pull-down node PD2, and the drain is connected to the low-level signal terminal VGL;
  • the gate of the eighth transistor M8' is connected to the pull-up node PU, and the source is connected to the second The second pull-down control node PD_CN2, the drain is connected to the low-level signal terminal;
  • the gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL;
  • the gate of a transistor M11 is connected to the first pull-
  • the gate of the sixteenth transistor M16 is connected to the signal input terminal INPUT, the source is connected to the first pull-down node PD1, and the drain is connected to the low level signal terminal.
  • the gate of the sixteenth transistor M16' is connected to the signal input terminal INPUT, the source is connected to the second pull-down node PD2, and the drain is connected to the low-level signal terminal VGL.
  • the fifth transistor M5 and the ninth transistor M9 form the first pull-down control sub-circuit and the fifth transistor M5' and the ninth transistor M9' form the second pull-down control sub-circuit to work in time-sharing (that is, work in turn); corresponding , since the first noise reduction sub-circuit composed of the tenth transistor M10 and the eleventh transistor M11 and the second noise reduction sub-circuit composed of the tenth transistor M10' and the eleventh transistor M11' are respectively controlled by the first pull-down The sub-circuit and the second pull-down control sub-circuit are controlled, so the first noise reduction sub-circuit and the second noise reduction sub-circuit also work in time-sharing.
  • the working principle of the first pull-down control subcircuit is the same as that of the second pull-down control subcircuit, and the working principle of the first noise reduction subcircuit and the second noise reduction subcircuit is the same; so only the first pull-down control subcircuit and When the first noise reduction sub-circuit works, the working principle of the shift register will be described. What needs to be explained here is that in the circuit structure shown in Figure 2, part of the low-level signal terminal VGL can also be represented by LVGL, which can provide a signal with a lower potential of the lower-level signal terminal VGL, and can more fully connect the corresponding The potential of the point is pulled down.
  • the seventh transistor M7 In the discharge phase, that is, before displaying, first input a high-level signal to the frame start signal terminal STV, the seventh transistor M7 is turned on, and discharge the pull-up node PU through the low-level signal input from the low-level signal terminal VGL , to prevent the display abnormality caused by the residual charge of the pull-up node PU.
  • the signal input terminal INPUT writes a high-level signal
  • the first transistor M1 is turned on, and the potential of the pull-up node PU is pulled up by the high-level signal, and the storage capacitor C is charged.
  • the third transistor M3 is turned on, and the high-level signal input from the clock signal terminal CLK is output to the gate line connected to the shift register through the signal output terminal OUTPUT .
  • the pull-up reset signal terminal RESET_PU inputs a high-level signal
  • the second transistor M2 is turned on
  • the low-level signal input through the low-level signal terminal VGL pulls down the potential of the pull-up node PU to control the pull-up node PU
  • the third transistor M3 is turned off, and the signal output terminal OUTPUT and the cascaded signal output terminal OUT_C no longer output high-level signals.
  • both the first pull-down control node PD_CN1 and the pull-down node are high-level signals, and the tenth transistor M10 and the eleventh transistor M11 are turned on, respectively for the pull-up node PU, the signal output terminal OUTPUT, and the cascaded signal output terminal
  • the output of OUT_C is denoised until the next frame scan starts and the potential of the pull-up node PU is pulled high.
  • the signal output by the signal output terminal OUTPUT is only used to control the gate line on and off, and a cascaded sub-circuit is also arranged in the shift register; the cascaded In response to the potential of the pull-up node PU, the sub-circuit passes the clock signal input from the clock signal terminal CLK through the cascaded signal output terminal OUT_C.
  • the cascade signal output terminal OUT_C and the signal output terminal OUTPUT output the same signal, that is, output a high-level signal to the pull-up reset signal terminal RESET_PU of other cascaded shift registers, and the signals of other cascaded shift registers Input terminal INPUT.
  • the cascade sub-circuit includes a thirteenth transistor M13, the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the cascade signal output terminal OUT_C.
  • a twelfth transistor is provided in both the first noise reduction sub-circuit and the second noise reduction sub-circuit, denoted by M12 and M12' respectively, for reducing the signal output by the cascaded signal output terminal OUT_C noise.
  • the gate of the twelfth transistor M12 is connected to the first pull-down node PD1, the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal; the gate of the twelfth transistor M12' is connected to the second pull-down node PD2 , the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal VGL.
  • FIG. 3 is a schematic structural diagram of the initial row in a gate drive circuit provided by an embodiment of the present disclosure.
  • the gate drive circuit includes: N shift registers and P clock signal lines; Each adjacent P of the N shift registers is respectively connected to the P clock signal lines; the signal output ends of the N shift registers are respectively connected to the N gate lines in one-to-one correspondence; wherein, P is an even number greater than or equal to 6; N is an integer greater than or equal to P; M is a positive integer.
  • the number of clock signal lines is 12 as an example.
  • the duty cycle of the clock signal input to each clock signal line can be 1/12 to 1/2, that is, the high value of the clock signal
  • the level maintenance time is 1H to 6H.
  • the duty cycle of the clock signal is 1/2 as an example.
  • the 1H time is 1.85 microseconds ( ⁇ s) . It can be understood that the number of clock signal lines in the gate drive circuit provided by the embodiments of the present disclosure can also be 4, 6, 8, 10, 14, 16, etc. to set.
  • the signal output end of the i-th shift register is connected to the signal input end of the i+p-th shift register; wherein, P/2 ⁇ p ⁇ N; i ⁇ N-p; the j-th shift register
  • the pull-up reset signal end of the j+q shift register is connected to the signal output end; 2 ⁇ q-p ⁇ N/2; j ⁇ N-q.
  • the value of p is 6 and the value of q is 8 for illustration.
  • the signal output terminal OUTPUT of the first shift register is connected to the input terminal INPUT of the seventh shift register, and the signal output terminal OUTPUT of the second The signal output terminal OUTPUT of the first shift register is connected to the input terminal INPUT of the eighth shift register.
  • the pull-up reset signal terminal RESET_PU of the ninth shift register is connected to the signal output terminal OUTPUT of the first shift register.
  • the pull-up reset signal terminal RESET_PU of the tenth shift register is connected to the signal output terminal OUTPUT of the second shift register, and so on, to form the entire gate drive circuit.
  • the pull-up reset signal terminal RESET_PU of the first shift register can be written into a high-level signal with a delay of 2H, that is, the potential of the pull-up node PU can be pulled low with a delay of 2H.
  • the output sub-circuit of a shift register works with a delay of 2H, which can make the output sub-circuit discharge the signal output terminal OUTPUT through the low-level signal written by the clock signal line, and alleviate the tailing of the signal output terminal OUTPUT falling edge Phenomenon.
  • the display panel further includes: a first frame start signal line and a second frame start signal line; the signal input ends of the odd rows in the first to N/2th shift registers are all connected to the first frame Turn on the signal line; the signal input ends of the even-numbered rows in the first to N/2 shift registers are all connected to the second frame turn-on signal line.
  • the first frame start signal line STV1 can provide a frame start signal for the signal input terminal INPUT of the odd row in the first to N/2 shift registers.
  • the second frame start signal line STV2 can be used for the first to N/2 shift registers
  • the signal input terminal INPUT of the even row in the N/2th shift register provides a frame start signal, so that the gate driving circuit can work normally.
  • the functions of the first frame opening signal line STV1 and the second frame opening signal line STV2 are the same, and the two can work in time division (that is, work in turn) to reduce the load of one of them, so as to avoid Affects the frame start signal output by the signal input terminal INPUT.
  • the first frame turn-on signal line STV1 and the second frame turn-on signal line STV2 can also input a high-level signal to the frame turn-on signal terminal STV in the gate drive circuit before displaying, so that the corresponding transistor is turned on,
  • the pull-up node PU is discharged through the low-level signal to prevent display abnormality caused by the residual charge of the pull-up node PU.
  • FIG. 4 is a schematic structural diagram of multiple redundant shift registers in a gate drive circuit provided by an embodiment of the present disclosure. As shown in FIG. 4 , 12 redundant shift registers are taken as an example in the embodiment of the present disclosure.
  • the clock signal terminals CLK of the 12 redundant shift registers are respectively connected to 12 clock signals, and the pull-up reset signal terminals RESET_PU of each of the 12 redundant shift registers are connected to the third frame start signal line STV0.
  • the signal output terminals OUTPUT of the 1st to 6th redundant shift registers are respectively connected to the pull-up reset signal terminals RESET_PU of the N-5th to Nth shift registers, and the signal output terminals of the 7th to 12th redundant shift registers
  • the OUTPUTs are respectively connected to the pull-up reset signal terminals RESET_PU of the 1st to 6th redundant shift registers.
  • the third frame open signal line can reset the potential of the pull-up node PU of the 12 redundant shift registers, and the cascade output signal output by the signal output terminal OUTPUT of the first to sixth redundant shift registers can be set to N
  • the pull-up nodes PU of the last 6 shift registers in the first shift register are reset, and at the same time, the cascaded output signal output by the signal output terminal OUTPUT of the 7th to 12th redundant shift registers can be used for the 1st to 6th
  • the pull-up node PU of the redundant shift register is reset to ensure the normal operation of the gate drive circuit.
  • An embodiment of the present disclosure also provides a method for driving a display panel, and the method for driving a display panel includes the following steps:
  • Step S101 according to the data signal transmitted in the data line, it is judged whether the grayscale value difference between the input data signal of the pixel unit in the nth row and the pixel unit in the n-1th row is greater than the threshold; n is a positive integer less than or equal to N .
  • step S102 is executed. Step S102 , adjusting the phase of the clock signal input by the nth shift register, so that the falling edge time of the pull-up node of the nth shift register is delayed, so as to output a phase-delayed scan signal.
  • the threshold involved in the embodiments of the present disclosure is a preset value of the difference between the input data signals of two adjacent rows. If the threshold is larger, it means The input data signal changes abruptly, and it is displayed on the display screen that the brightness of pixel units in two adjacent rows differ greatly.
  • the threshold can be set to a value such as 63, 128, or 255. For example, if the data signal is switched from L63 to L0, or from L127 to L255, or from L0 to L255, it can be considered that the data signal has switched between high and low gray scales. , the size of the threshold can be reasonably set according to actual needs.
  • adjusting the phase of the clock signal input by the nth shift register can be achieved by extending the low-level maintenance duration of the clock signal input by the nth shift register by 1H to 2H, or by extending This is achieved by extending the high-level maintenance duration of the clock signal input by the nth shift register by 1H to 2H.
  • extending the low-level maintenance duration of the clock signal input by the nth shift register by 1H and extending the high-level maintenance duration of the clock signal input by the nth shift register by 1H are Example to illustrate.
  • FIG. 5 is a timing diagram of signals input to a display panel including 12 clock signal lines provided by an embodiment of the present disclosure. As shown in FIG. 5 , The Gn row GOA working timing corresponding to CLK7 is taken as an example.
  • the timing controller detects the high-low grayscale switching of the data signal input by the data signal line in the pixel unit of the seventh row, or the high-low grayscale switching between the sixth row and the seventh row, and can adjust the seventh shift.
  • the timing of the clock signal in the clock signal line CLK7 connected to the bit register makes the low-level maintenance period of the clock signal in CLK7 extended from the original 6H to 7H, and its low-level maintenance period is lower than that of the clock signal in CLK6
  • the level maintenance time is longer than 1H.
  • the output signal of the signal output terminal OUTPUT of the first shift register is input to the signal input terminal INPUT as the input signal of the shift register of the current stage.
  • the first transistor M1 is turned on, and the pull-up node PU Precharge, the low-level maintenance time of the clock signal input by the seventh shift register is equal to the pre-charge maintenance time of the pull-up node PU, the potential of the pull-up node PU rises, and the third transistor M13 and the thirteenth transistor M13 Transistor M13 is turned on, because the clock signal of the shift register in this row is at low level, so the scanning signal output by the signal output terminal OUTPUT remains at low level, and the low level is maintained for 1H longer, but the timing of the data signal remains unchanged, and the pull-up When the potential of the node PU rises, the sixth transistor M6 and the eighth transistor M8 are turned on, and the potential of the pull-down node PD is pulled down.
  • the high level of the pull-up node PU turns on the third transistor M3.
  • the clock signal is high
  • the potential of the signal output terminal OUTPUT rises
  • the scanning signal is output.
  • the pull-up The potential of the node PU continues to rise; the sixth transistor M6 and the eighth transistor M8 are still turned on, the potential of the pull-down node PD is maintained at a low level and the low level is maintained for a period longer than 1H, and the scanning signal of the seventh row is relative to the data signal.
  • the timing delay is 1H, so that the pixel unit in the seventh row has an extra 1H pre-charging time, or, as shown in Figure 6, the potential of the pull-down node PD is maintained at a low level and the low-level maintenance time is longer than 2H, and the seventh row
  • the timing delay of the scanning signal relative to the data signal is 2H, so that the 7th line has an extra 2H pre-charging time.
  • the potential change of the pull-up node PUn of the nth shift register that is, the pull-up node PU of the seventh shift register can be divided into three stages, as shown in FIG. 5 and FIG. 6 .
  • the pre-charging phase of the pull-up node PU Since the input signal terminal INPUT inputs a high-level signal, the potential of the pull-up node PU is pulled up for the first time.
  • the pre-charging stage of the pull-up node PU due to the bootstrap effect of the capacitor, the potential of the pull-up node PU is pulled up for the second time.
  • the falling edge time of the pull-up node PU may specifically be the time when the potential of the pull-up node PU starts to be pulled down during the charging phase of the pull-up node PU, as shown in the second time shown in FIG. 5 and FIG. 6 The time when the step ends, at this time, the charging of the pull-up node PU ends, and the scanning signal input by the pixel unit in the corresponding row 7 of the display panel ends.
  • the high-level maintenance duration of the corresponding scanning signal is also delayed by 1H, which is equivalent to the data signal
  • the switching of high and low gray levels leads to the pulling of the common electrode signal in advance, that is, the time interval between the high and low switching of the data signal and the end time of the scanning signal is at least 1H, and the interval is relatively long, which avoids the fluctuation of the common electrode signal from affecting the charging of the pixel units in this row. Therefore, display defects such as crosstalk in the horizontal direction can be avoided.
  • Fig. 8 is a timing diagram of a signal input by a display panel containing 6 clock signal lines provided by an embodiment of the present disclosure.
  • the number of clock signal lines of the display panel is 6, and the pixel unit of the fourth row
  • the high and low grayscale switching of the input data signal is taken as an example. It can be seen that the scanning signal of the fourth row is delayed by 1H relative to the timing of the data signal, so that the pixel unit in the fourth row has an extra 1H pre-charging time, and the data signal is high or low.
  • the time of switching to the data signal of L255 and the Gn output signal overlap in timing by more than or equal to 2H, so that the pixel units in this row have a precharge time greater than or equal to 1H more than the pixel units in other rows.
  • the pixel unit is already at a higher potential, which can increase the charging rate of the row and avoid display defects such as line afterimages.
  • FIG. 9 is another timing diagram of signals input by a display panel including 12 clock signal lines provided by an embodiment of the present disclosure.
  • the working timing of Gn row GOA corresponding to CLK7 is taken as an example.
  • the timing controller detects that the data signal input by the data signal line to the pixel unit in the seventh row is switched between high and low gray scales, and can adjust the timing of the clock signal in the clock signal line CLK7 connected to the seventh shift register.
  • the high-level maintenance duration of the clock signal in CLK7 is extended from the original 6H to 7H, and the output signal of the signal output terminal OUTPUT of the first shift register is input to the signal input terminal INPUT as the input signal of the current-stage shift register.
  • the first transistor M1 is turned on to precharge the pull-up node PU, and the potential of the pull-up node PU rises.
  • the potential of the pull-up node PU continues to rise, and the third transistor M13 and the thirteenth transistor M13
  • the transistor M13 is turned on to charge the pull-up node PU, and the high-level maintenance time of the clock signal input by the seventh shift register is equal to the charging time of the pull-up node PU.
  • the scanning signal output by the signal output terminal OUTPUT still maintains a low potential, and the sixth transistor M6 and the eighth transistor M8 are turned on while the potential of the pull-up node PU rises. The potential of the pull-down node PD is pulled down.
  • the high level of the pull-up node PU turns on the third transistor M3.
  • the clock signal is high
  • the potential of the signal output terminal OUTPUT rises, and the scanning signal is output.
  • the pull-up The potential of the node PU continues to rise.
  • the bootstrap time of its capacitor is also 1H longer; the sixth transistor M6 and the eighth transistor M8 are still turned on.
  • the potential of the pull-down node PD is maintained at a low level. Since the bootstrap time of the capacitor is 1H longer, the charging time of the pull-up node PU is 1H longer.
  • the high-level duration of the scan signal Gn of this row is 1H longer.
  • the turn-on time of the driving transistor in the pixel unit of the row is 1H longer, or, as shown in Figure 10, the bootstrap time of the capacitor is 2H longer, so that the charging time of the pull-up node PU is 2H longer, correspondingly, the The high-level duration of the scanning signal Gn is also longer than 2H.
  • the time of switching to the data signal of L255 and the Gn output signal overlap in timing by more than or equal to 2H, so that the pixel units of this row are larger than other rows.
  • the pixel unit has an extra charging time greater than or equal to 1H, which can increase the charging rate of the line and avoid display defects such as line afterimages.
  • the high-level maintenance duration of the corresponding scanning signal is also delayed by 2H, which is equivalent to the data signal
  • the high and low gray scale switching leads to the pulling of the common electrode signal in advance, that is, the time interval between the high and low switching of the data signal and the end time of the scanning signal is at least 2H, and the interval is relatively long, which avoids the fluctuation of the common electrode signal from affecting the charging of the pixel units in this row. Therefore, display defects such as crosstalk in the horizontal direction can be avoided.
  • Figure 12 is another timing diagram of the input signal of the display panel containing 6 clock signal lines provided by the embodiment of the present disclosure.
  • the scanning signal Gn in the fourth row is at a high level 1H longer, so that the turn-on time of the drive transistor in the pixel unit of the fourth row is longer than 1H.
  • the charging time of the pixel units in this row is greater than or equal to 1H longer than that of the pixel units in other rows, so that the charging rate of this row can be improved, and display defects such as line afterimages can be avoided.
  • the driving method of the display panel further includes the following steps:
  • Step S103 according to the data signal transmitted in the data line, judge whether the grayscale value difference between the input data signal of the n+m row pixel unit and the n+m-1 row pixel unit is greater than the threshold; n+m is less than or a positive integer equal to N.
  • step S104 is performed. Step S104, inputting the clock signal of the initial phase to the n+mth shift register.
  • the high-low gray-scale switching After the high-low gray-scale switching, it can continue to detect whether the data signal input by the pixel unit of the adjacent row has a high-low gray-scale switching. If there is no high-low gray-scale switching of the data signal, the corresponding clock signal line can be input to the initial phase. Clock signal, until the next high-low switching of the data signal is detected, then timing adjustment is performed to avoid clock signal confusion, causing wrong charging, and affecting the display effect of the display screen. In addition, optionally, taking a shift register with a group of 12 clock signals as an example, if it is detected that the high-low gray scale switching occurs in the sixth and seventh row signals, the timing of the clock signal in the seventh row can be adjusted, and then The timing of the clock signal in the first 6 lines is consistent.
  • the consistency mentioned here means that the high level time and low level time of the clock signal are consistent (both are 6H high level and 6H low level), and then start from the seventh line , to the 12th row, the clock signal is the timing after the timing adjustment, and then when scanning from the first row again, the first row to the 12th row are restored to the timing of the unadjusted timing before the high-low switching (both are 6H high level and 6H low level).
  • the high-low gray-scale switching between the sixth row and the seventh row and adjust the timing of the clock signal of the seventh row.
  • the clock signal in row 7 can be restored to the original timing (6H high level and 6H low level), and the recovery time can be set according to actual needs, which is not limited here. It can be seen that when the data signal in the data line in the display panel is switched between high and low gray levels, the phase of the clock signal input by the shift register corresponding to the pixel unit in this row is adjusted so that the pull-up node of the corresponding shift register The falling edge time delay to output the phase-delayed scan signal, and the subsequent clock signal is also adjusted in the same way, and the previous clock signal is not adjusted.
  • the data signals in all data signal lines will return to the initial phase, so as to avoid clock signal disorder, resulting in disorder of scanning signal output, resulting in wrong charging and affecting the display effect.
  • FIG. 13 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes: N gate lines S arranged crosswise and M data lines D, and pixel units located in the area defined by the gate lines and data lines;
  • the display panel also includes: N shift registers GOA and P clock signal lines; every adjacent P of the N shift registers The shift registers are respectively connected to P clock signal lines; the signal output ends of N shift registers are respectively connected to N gate lines in one-to-one correspondence; wherein, P is an even number greater than or equal to 2; N is an integer greater than or equal to P ; M is a positive integer;
  • the display panel also includes a detection module Z, and the detection module Z is configured to perform steps S101 to S104 in the driving method of the display panel provided by any of the above-mentioned embodiments, and its implementation principle is the same as that of the above-mentioned
  • the realization principle of the driving method of the display panel is
  • the detection module Z can be a timing controller T-CON, the detection module Z can be set on the main board of the display panel, and electrically connected to the display panel through the main board, and the detection module can also be set on a separate main board B of the timing controller, It is electrically connected with the display panel, and the connection with the display panel can be directly connected, or connected through a flexible circuit board FPC, which is not limited here.
  • the display panel also includes a driver chip IC, and the driver chip IC can be arranged on the display panel, such as As shown in FIG. 13 , it can also be arranged on the FPC.
  • the signal of the timing controller can be electrically connected to the driving chip IC through wires, etc., to realize the electrical connection with the display panel.
  • An embodiment of the present disclosure also provides a display device, which includes the display panel provided in any of the above embodiments, and the display device can be any display device such as a TV, a mobile phone, a monitor, a notebook computer, a digital photo frame, a navigator, etc. functional product or component.
  • the realization principle thereof is similar to the realization principle of the above-mentioned display panel, and will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板的驱动方法、显示面板及显示装置，属于显示技术领域，其可解决现有的显示面板容易出现水平方向串扰及线残像等显示不良的问题。显示面板的驱动方法包括：根据数据线中传输的数据信号，判断第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n为小于或等于N的正整数；若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。

Description

显示面板的驱动方法、显示面板及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示面板的驱动方法、显示面板及显示装置。
背景技术
随着显示技术的不断发展,近些年的显示器发展逐渐呈现出了高集成度，低成本的发展趋势。其中一项非常重要的技术就是阵列基板行驱动(Gate Driver on Array,GOA)技术的量产化的实现。利用GOA技术将薄膜晶体管(Thin Film Transistor,TFT)组成的栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动集成电路部分，其不仅可以从材料成本和制作工艺两方面降低产品成本，而且显示面板可以做到两边对称和窄边框的美观设计。
大尺寸显示产品，例如电视(TV)当前发展方向为高分辨率，高刷新率，目前高端的TV产品已经发展到8K 120Hz，甚至8K 240Hz。但是大尺寸显示产品在显示过程中，尤其是在数据信号在发生高低灰阶切换时，容易出现水平串扰、线残像等显示不良，严重影响大尺寸显示产品品质，降低了大尺寸显示产品的良品率。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种显示面板的驱动方法、显示面板及显示装置。
第一方面，本公开实施例提供一种显示面板的驱动方法，所述显示面板包括：交叉设置的N条栅线和M条数据线、及位于所述栅线和所述数据线 限定区域内的像素单元；所述显示面板还包括：N个移位寄存器和P条时钟信号线；所述N个移位寄存器中的每相邻P个移位寄存器分别连接所述P条时钟信号线；所述N个移位寄存器的信号输出端分别与所述N条栅线一一对应连接；其中，P为大于或等于2的偶数；N为大于或等于P的整数；M为正整数；所述显示面板的驱动方法包括：
根据所述数据线中传输的数据信号，判断第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n为小于或等于N的正整数；
若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。
可选地，若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，第n行像素单元输入的数据信号的时间与第n行移位寄存器的上拉节点的下降沿时间间隔大于1H；其中，1H为一行像素单元的充电时间。
可选地，所述调整第n个移位寄存器所输入的时钟信号的相位，包括：
将第n个移位寄存器所输入的时钟信号的非工作电平维持时间延长。
可选地，第n个移位寄存器所输入的时钟信号的非工作电平维持时间较预设时钟信号的非工作电平维持时间延长1H至2H。
可选地，第n个移位寄存器所输入的时钟信号的非工作电平维持时间与上拉节点的预充电维持时间相等。
可选地，所述调整第n个移位寄存器所输入的时钟信号的相位，包括：
将第n个移位寄存器所输入的时钟信号的工作电平维持时间延长。
可选地，第n个移位寄存器所输入的时钟信号的工作电平维持时间较预设时钟信号的工作电平维持时间延长1H至2H。
可选地，第n个移位寄存器所输入的时钟信号的工作电平维持时间与上拉节点的充电时间相等。
可选地，第n行像素单元输入的数据信号的时间与上拉节点的充电时间有交叠，且交叠时间大于或等于2H。
可选地，所述显示面板的驱动方法还包括：
根据所述数据线中传输的数据信号，判断第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n+m为小于或等于N的正整数；
若第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值小于或等于阈值，则向第n+m个移位寄存器输入初始相位的时钟信号。
第二方面，本公开实施例提供一种显示面板，所述显示面板包括侦测模块，所述侦测模块被配置为侦测第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。
可选地，所述N个移位寄存器中的每个移位寄存器包括：输入子电路、输出子电路和上拉复位子电路；
所述输入子电路被配置为响应于信号输入端的输入信号，并将所述输入信号写入上拉节点；
所述输出子电路被配置为响应于所述上拉节点的电位，并将时钟信号端输入的时钟信号通过信号输出端输出；
所述上拉复位子电路被配置为响应于上拉复位信号端输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位。
可选地，第i个所述移位寄存器的信号输出端连接第i+p个所述移位寄存器的信号输入端；其中，P/2≤p＜N；i≤N-p；
第j个所述移位寄存器的上拉复位信号端连接第j+q个所述移位寄存器的信号输出端；2≤q-p＜N/2；j≤N-q。
可选地，所述显示面板还包括：第一帧开启信号线和第二帧开启信号线；
第1个至第N/2个所述移位寄存器中的奇数行的信号输入端均连接所述第一帧开启信号线；
第1个至第N/2个所述移位寄存器中的偶数行的信号输入端均连接所述第二帧开启信号线。
第三方面，本公开实施例提供一种显示装置，所述显示装置包括如上述提供的显示面板。
附图说明
图1为一种示例性的显示面板的扫描信号、数据信号和公共电极信号的时序图；
图2为本公开实施例提供的一种移位寄存器的结构示意图；
图3为本公开实施例提供的一种栅极驱动电路中起始部分行的结构示意图；
图4为本公开实施例提供的一种栅极驱动电路中多个冗余移位寄存器的结构示意图；
图5为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的一种时序图；
图6为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的另一种时序图；
图7为本公开实施例提供的包含12条时钟信号线的显示面板的扫描信 号、数据信号和公共电极信号的一种时序图；
图8为本公开实施例提供的包含6条时钟信号线的显示面板所输入信号的一种时序图；
图9为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的又一种时序图；
图10为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的再一种时序图；
图11为本公开实施例提供的包含12条时钟信号线的显示面板的扫描信号、数据信号和公共电极信号的另一种时序图；
图12为本公开实施例提供的包含6条时钟信号线的显示面板所输入信号的另一种时序图；
图13为本公开实施例提供的一种显示面板的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对 位置改变后，则该相对位置关系也可能相应地改变。
图1为一种示例性的显示面板的扫描信号和数据信号的时序图，如图1所示，当数据信号Data发生高低灰阶切换，例如，数据信号data由L63切换为L0，或者由L127切换为L255，或者由L0切换为L255等，此时，数据信号Data的切换容易使得显示面板中的公共电极信号Vcom由于电容耦合被拉动，使得公共电极信号Vcom发生波动，在扫描信号Gate关闭时，公共电极信号Vcom未恢复至原始状态，从而导致该行像素单元对应的公共电极信号Vcom与其他位置的公共电极信号Vcom不同而产生水平方向串扰等显示不良。另一方面，当数据信号Data发生变化时，该行的像素单元无预充电或者发生反向预充电，使得该行的像素单元充电率较低，容易出现线残像等显示不良。
为了至少解决上述的技术问题之一，本公开实施例提供了一种显示面板的驱动方法、显示面板及显示装置，下面将结合附图和具体实施方式对本公开实施例提供的显示面板的驱动方法、显示面板及显示装置作进一步详细描述。
在此需要说明的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。
其中，由于在本公开实施例中以所采用晶体管为N型晶体管，故在本公开实施例中的工作电平信号则是指高电平信号，非工作电平信号为低电平信号；相应的工作电平端为高电平信号端，非工作电平端为低电平信号端。
通常显示面板包括多条栅线和多条数据线，栅线和数据线交叉设置限定出多个像素区，每个像素区均设置有像素单元。其中，以各栅线的延伸方向为行方向，各数据线的延伸方向为列方向为例对显示面板的结构进行说明。在驱动显示面板进行显示时，可以根据待显示画面，逐行给栅线写入扫描信号，同时给各数据线写入数据信号，以使显示面板中的像素单元逐行被点亮。
其中，极驱动信号由栅极驱动电路提供，数据信号由源极驱动电路提供；在相关技术中可以将栅极驱动电路集成在栅极驱动芯片中，将源极驱动电路集成在源极驱动芯片中；而目前为了较少芯片数量，以及实现窄边框或者无边框，提供了一种将栅极驱动电路集成在阵列基板上(Gate On Array；GOA)的技术；其中，栅极驱动电路包括集成在阵列基板上、多个级联的移位寄存器，每个移位寄存器与栅线一一对应连接，用于为与之连接的栅线提供扫描信号。
为了更清楚移位寄存器如何实现扫描信号的输出，以下结合移位寄存器的具体示例进行说明。
图2为本公开实施例提供的一种移位寄存器的结构示意图，如图2所示，该移位寄存器包括：输入子电路、输出子电路、上拉复位子电路；其中，输入子电路被配置为响应于信号输入端INPUT所输入的输入信号，并将输入信号写入上拉节点PU，以给上拉节点PU进行充电；输出子电路被配置为响应于上拉节点PU的电位，并将时钟信号端CLK输入的时钟信号通过信号输出端OUTPUT输出；上拉复位子电路被配置为响应于上拉复位信号端RESET_PU输出的上拉复位信号，并通过低电平信号将上拉节点PU的电位进行复位。
具体的，如图2所示，输入子电路包括第一晶体管M1；上拉复位子电路包括第二晶体管M2；输出子电路包括第三晶体管M3和存储电容C；其中，第一晶体管M1的栅极和源极连接信号输入端INPUT，漏极连接上拉节点PU；第二晶体管M2的栅极连接上拉复位信号端RESET_PU，源极连接上拉节点PU，漏极连接低电平信号端VGL；第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接信号输出端OUTPUT；存储电容C的第一端连接上拉节点PU，第二端连接信号输出端OUTPUT。
在此需要说明的是，在复位阶段对上拉节点PU进行复位后，上拉节点PU为低电平，此时第三晶体管M3关断，信号输出端OUTPUT不再输出，以完成对信号输出端OUTPUT的复位。
如图2所示，本公开实施例提供的移位寄存器还包括：第一下拉控制子电路、第二下拉控制子电路、第一下拉子电路、第二下拉子电路、第一降噪子电路、第二降噪子电路、放电子电路、第一辅助子电路、第二辅助子电路和级联子电路。其中，放电子电路响应于帧开启信号端STV输入的帧开启信号，并通过低平信号端VGL所输入的低电平对上拉节点PU进行放电；第一下拉控制子电路和第二下拉控制子电路的结构和功能相同，二者只是分时工作；同理，第一下拉子电路和第二下拉子电路的结构和功能相同；第一辅助子电路和第二辅助子电路结构和功能相同；第一降噪子电路和第二降噪子电路的结构和功能相同。对于输入子电路、输出子电路、上拉复位子电路与上述结构和功能相同，故在此不再重复赘述。
第一辅助子电路和第二辅助子电路均被配置为响应于信号输入端INPUT所输入的输入信号，并分别通过低电平信号拉低第一下拉节点PD1的电位和第二下拉节点PD2的电位；第一下拉控制子电路被配置为响应于第一电源电压信号端VDDO所输入的第一电源电压，以控制第一下拉节点PD1的电位；第二下拉控制子电路被配置为响应于第二电源电压信号端VDDE所 输入的第二电源电压，以控制第二下拉节点PD2的电位；第一下拉子电路被配置为响应于上拉节点PU的电位，并通过低电平信号端VGL输入的低电平信号下拉第一下拉节点PD1和第一下拉控制节点PD_CN1的电位；第二下拉子电路被配置为响应于上拉节点PU的电位，并通过低电平信号端VGL输入的低电平信号下拉第二下拉节点PD2和第二下拉控制节点PD_CN2的电位；第一降噪子电路被配置为响应于第一下拉节点PD1的电位，通过低电平信号端VGL输入的低电平信号对上拉节点PU、信号输出端OUTPUT所输出的信号进行降噪。级联子电路被配置为响应于上拉节点PU的电位，将时钟信号端CLK所输入的时钟信号通过级联信号输出端OUT_C输出至级联的其他移位寄存器。
在此需要说明的是，级联信号输出端OUT_C和信号输出端OUTPUT所输出的信号相同，只不过在该移位寄存单元中设置两个输出端，一个为与栅线连接的信号输出端OUTPUT，另一个为用于级联的级联信号输出端OUT_C。之所以，单独设置级联子电路是为了降低信号输出端OUTPUT的负载，以避免影响信号输出端OUTPUT所输出的扫描信号。
具体的，如图2所示，第一下拉控制子电路和第二下拉控制子电路均包括第五晶体管和第九晶体管；其中，第一下拉控制子电路中和第二下拉控制子电路中的第五晶体管分别用M5和M5'表示，第九晶体管分别用M9和M9'表示。第一下拉子电路和第二下拉子电路均包括第六晶体管和第八晶体管；其中，第一下拉子电路和第二下拉子电路中的第六晶体管分别用M6和M6'表示，第八晶体管分别用M8和M8'表示。第一降噪子电路和第二降噪子电路均包括第十晶体管、第十一晶体管和第十二晶体管；其中，第一降噪子电路和第二降噪子电路中的第十晶体管分别用M10和M10'表示，第十一晶体管分别用M11和M11'表示；放电子电路包括第七晶体管M7。第一辅助子电路和第二辅助子电路均包括第十六晶体管，分别用M16和M16'表示。
其中，第五晶体管M5的栅极和源极均连接第一电源电压端VDDO，漏极连接第一下拉控制节点PD_CN1；第九晶体管M9的栅极连接第一下拉控制节点PD_CN1，源极连接第一电源电压端VDDO，漏极连接第一下拉节点PD1；第五晶体管M5'的栅极和源极均连接第二电源电压端VDDE，漏极连接第二下拉控制节点PD_CN2；第九晶体管M9'的栅极连接第二下拉控制节点PD_CN2，源极连接第二电源电压端，漏极连接第一下拉节点PD1；第六晶体管M6的栅极连接上拉节点PU，源极连接第一下拉节点PD1，漏极连接低电平信号端；第八晶体管M8的栅极连接上拉节点PU，源极连接第一下拉控制节点PD_CN1，漏极连接低电平信号端VGL；第六晶体管M6'的栅极连接上拉节点PU，源极连接第二下拉节点PD2，漏极连接低电平信号端VGL；第八晶体管M8'的栅极连接上拉节点PU，源极连接第二下拉控制节点PD_CN2，漏极连接低电平信号端；第十晶体管M10的栅极连接第一下拉节点PD1，源极连接上拉节点PU，漏极连接低电平信号端VGL；第十一晶体管M11的栅极连接第一下拉节点PD1，源极连接信号输出端OUTPUT，漏极连接低电平信号端VGL；第十晶体管M10'的栅极连接第二下拉节点PD2，源极连接上拉节点PU，漏极连接低电平信号端VGL；第十一晶体管M11'的栅极连接第二下拉节点PD2，源极连接信号输出端OUTPUT，漏极连接低电平信号端；第七晶体管M7的栅极连接帧开启信号端STV，源极连接上拉节点PU，漏极连接低电平信号端VGL；第十三晶体管M13的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接级联信号输出端OUT_C。第十六晶体管M16的栅极连接信号输入端INPUT，源极连接第一下拉节点PD1，漏极连接低电平信号端。第十六晶体管M16'的栅极连接信号输入端INPUT，源极连接第二下拉节点PD2，漏极连接低电平信号端VGL。
其中，第五晶体管M5和第九晶体管M9组成第一下拉控制子电路和第五晶体管M5'和第九晶体管M9'组成第二下拉控制子电路分时工作(也即轮 流工作)；相应的，由于由第十晶体管M10、第十一晶体管M11组成的第一降噪子电路和由第十晶体管M10'、第十一晶体管M11'组成的第二降噪子电路分别由第一下拉控制子电路和第二下拉控制子电路控制，故第一降噪子电路和第二降噪子电路也是分时工作。而第一下拉控制子电路和第二下拉控制子电路的工作原理相同，第一降噪子电路和第二降噪子电路的工作原理相同；故以下仅以第一下拉控制子电路和第一降噪子电路工作时，对移位寄存器的工作原理进行说明。在此需要说明的是，图2所示的电路结构中，部分低电平信号端VGL也可以用LVGL表示，其可以提供较低电平信号端VGL电位更低的信号，可以更加充分将对应点的电位进行拉低。
在放电阶段，也即显示之前，先给帧开启信号端STV输入高电平信号，第七晶体管M7打开，通过低电平信号端VGL所输入的低电平信号，对上拉节点PU进行放电，防止上拉节点PU残留电荷造成显示异常。
在输入阶段，信号输入端INPUT写入高电平信号，第一晶体管M1打开，通过高电平信号拉高上拉节点PU的电位，并对存储电容C进行充电。
在输出阶段，由于在输入阶段上拉节点PU的电位被拉高，第三晶体管M3打开，将时钟信号端CLK输入的高电平信号通过信号输出端OUTPUT输出至与移位寄存器连接的栅线。
在复位阶段，上拉复位信号端RESET_PU输入高电平信号，第二晶体管M2打开，通过低电平信号端VGL输入的低电平信号拉低上拉节点PU的电位，以对上拉节点PU进行复位，由于上拉节点PU被拉低，第三晶体管M3关断，信号输出端OUTPUT和级联信号输出端OUT_C均不再输出高电平信号。与此同时，第一下拉控制节点PD_CN1和下拉节点均为高电平信号，第十晶体管M10、第十一晶体管M11打开，分别对上拉节点PU、信号输出端OUTPUT、级联信号输出端OUT_C的输出进行降噪，直至下一帧扫描开始上拉节点PU电位被拉高。
如图2所示，为了降低信号输出端OUTPUT的负载，信号输出端OUTPUT所输出的信号仅用于控制栅线的选通与关断，移位寄存器中还设置有级联子电路；级联子电路响应于上拉节点PU的电位，将时钟信号端CLK所输入的时钟信号通过级联信号输出端OUT_C。级联信号输出端OUT_C与信号输出端OUTPUT所输出的信号相同，也即输出高电平信号给级联的其他移位寄存器的上拉复位信号端RESET_PU，以及级联的其他移位寄存器的信号输入端INPUT。其中，级联子电路包括第十三晶体管M13，第十三晶体管M13的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接级联信号输出端OUT_C。与此同时，在第一降噪子电路和第二降噪子电路中均还设置第十二晶体管，分别用M12和M12'表示，用于对级联信号输出端OUT_C所输出的信号进行降噪。第十二晶体管M12的栅极连接第一下拉节点PD1，源极连接级联信号输出端OUT_C，漏极连接低电平信号端；第十二晶体管M12'的栅极连接第二下拉节点PD2，源极连接级联信号输出端OUT_C，漏极连接低电平信号端VGL。
图3为本公开实施例提供的一种栅极驱动电路中起始部分行的结构示意图，如图3所示，该栅极驱动电路包括：N个移位寄存器和P条时钟信号线；所述N个移位寄存器中的每相邻P个分别连接所述P条时钟信号线；所述N个移位寄存器的信号输出端分别与所述N条栅线一一对应连接；其中，P为大于或等于6的偶数；N为大于或等于P的整数；M为正整数。
在本公开实施例中以时钟信号线的数量具体为12条为例进行说明，每条时钟信号线中输入的时钟信号的占空比可以为1/12至1/2，即时钟信号的高电平维持时间为1H至6H，在本公开实施例中以时钟信号的占空比为1/2为例进行说明，对于8K/120Hz的显示面板而言，1H时间为1.85微秒(μs)。可以理解的是，本公开实施例提供的栅极驱动电路中的时钟信号线的数量还可以为4条、6条、8条、10条、14条、16条等其他数量，可以根据实际需 要进行设置。
在一些实施例中，第i个移位寄存器的信号输出端连接第i+p个移位寄存器的信号输入端；其中，P/2≤p＜N；i≤N-p；第j个移位寄存器的上拉复位信号端连接第j+q个移位寄存器的信号输出端；2≤q-p＜N/2；j≤N-q。
在本公开实施例中以p的取值为6，q的取值为8为例进行说明，第1个移位寄存器的信号输出端OUTPUT连接第7个移位寄存器的输入端INPUT，第2个移位寄存器的信号输出端OUTPUT连接第8个移位寄存器的输入端INPUT，同样地，第9个移位寄存器的上拉复位信号端RESET_PU连接第1个移位寄存器的信号输出端OUTPUT，第10个移位寄存器的上拉复位信号端RESET_PU连接第2个移位寄存器的信号输出端OUTPUT，以此类推，连接形成整个栅极驱动电路。这样，第1个移位寄存器的上拉复位信号端RESET_PU可以延时2H被写入高电平信号，也即上拉节点PU的电位可以延时2H被拉低，这样一来，可以使得第1个移位寄存器的输出子电路延时工作2H，可以使得输出子电路通过时钟信号线所写入的低电平信号对信号输出端OUTPUT进行放电，缓解信号输出端OUTPUT下降沿的拖尾的现象。
在此需要说明的，在本公开实施例中，q-p≥2，此时，每个移位寄存器的上拉节点PU的电位可以至少延时2H被拉低，当然，q和p的关系还需要满足q-p＜N/2，这样一来，避免上拉节点PU的电位在下一帧信号被写入高电平时还没有被复位。
在一些实施例中，显示面板还包括：第一帧开启信号线和第二帧开启信号线；第1个至第N/2个移位寄存器中的奇数行的信号输入端均连接第一帧开启信号线；第1个至第N/2个移位寄存器中的偶数行的信号输入端均连接第二帧开启信号线。
第一帧开启信号线STV1可以为第1个至第N/2个移位寄存器中奇数行 的信号输入端INPUT提供帧开启信号，同理，第二帧开启信号线STV2可以为第1个至第N/2个移位寄存器中偶数行的信号输入端INPUT提供帧开启信号，以使得栅极驱动电路正常进行工作。在此需要说明的是，第一帧开启信号线STV1和第二帧开启信号线STV2的作用是相同的，二者可以分时工作(也即轮流工作)以降低其中一者的负载，以避免影响信号输入端INPUT所输出的帧开启信号。另一方面，第一帧开启信号线STV1和第二帧开启信号线STV2还可以在显示之前，先给栅极驱动电路中的帧开启信号端STV输入高电平信号，使得相应的晶体管打开，通过低电平信号对上拉节点PU进行放电，防止上拉节点PU残留电荷造成显示异常。
为了保证显示面板中最后的多个移位寄存器的正常工作，在本公开实施例中还需要在显示面板中设置多个冗余移位寄存器，在本公开实施例中，冗余寄存器的作用仅是为最后的多个移位寄存器提供级联信号，其输出信号不连接至显示面板的栅线中。图4为本公开实施例提供的一种栅极驱动电路中多个冗余移位寄存器的结构示意图，如图4所示，在本公开实施例中以12个冗余移位寄存器为例进行说明，12个冗余移位寄存器的时钟信号端CLK分别连接12条时钟信号，12各个冗余移位寄存器的上拉复位信号端RESET_PU均连接第三帧开启信号线STV0。第1至6个冗余移位寄存器的信号输出端OUTPUT分别连接第N-5至第N个移位寄存器的上拉复位信号端RESET_PU，第7至12个冗余移位寄存器的信号输出端OUTPUT分别连接第1至6个冗余移位寄存器的上拉复位信号端RESET_PU。第三帧开启信号线可以对12个冗余移位寄存器的上拉节点PU的电位进行复位，并且第1至6个冗余移位寄存器的信号输出端OUTPUT输出的级联输出信号可以对N个移位寄存器中的最后6个移位寄存器的上拉节点PU进行复位，同时第7至第12个冗余移位寄存器的信号输出端OUTPUT输出的级联输出信号可以对第1至6个冗余移位寄存器的上拉节点PU进行复位，以保证栅极驱动电 路的正常运行。
本公开实施例还提供了一种显示面板的驱动方法，该显示面板的驱动方法包括如下步骤：
步骤S101，根据数据线中传输的数据信号，判断第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n为小于或等于N的正整数。
若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则执行步骤S102。步骤S102，调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。
在此需要说明的是，本公开实施例中所涉及的阈值为相邻两行所输入的数据信号之间的差值的预设值，该阈值较大，则表示相邻两行像素单元中所输入的数据信号发生突变，在显示画面中显示为相邻两行的像素单元的亮度相差较大。具体地，阈值可以设置为63、128或者255等数值，例如数据信号由L63切换为L0，或者由L127切换为L255，或者由L0切换为L255等均可以认为是数据信号发生了高低灰阶切换，可以根据实际需要合理设置阈值的大小。在实际应用中，调整第n个移位寄存器所输入的时钟信号的相位可以通过将第n个移位寄存器所输入的时钟信号的低电平维持时长延长1H至2H来实现，还可以通过将第n个移位寄存器所输入的时钟信号的高电平维持时长延长1H至2H来实现。在本公开实施例中，以将第n个移位寄存器所输入的时钟信号的低电平维持时长延长1H和将第n个移位寄存器所输入的时钟信号的高电平维持时长延长1H为例进行说明。
下面将结合显示面板中所输入的信号的时序进行详细说明，图5为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的一种时序图，如图5所示，以CLK7对应的Gn行GOA工作时序为例。在输入阶段，时序 控制器监测到数据信号线在第7行像素单元输入的数据信号发生高低灰阶切换，或者说第6行和第7行发生了高低灰阶切换，可以调整第7个移位寄存器所连接的时钟信号线CLK7中的时钟信号的时序，使得CLK7中的时钟信号的低电平维持时长由原来的6H延长至7H，其低电平维持时长较CLK6中的时钟信号的低电平维持时长多1H，第1个移位寄存器的信号输出端OUTPUT的输出信号作为本级移位寄存器的输入信号输入至信号输入端INPUT，此时第一晶体管M1打开，对上拉节点PU进行预充电，第7个移位寄存器所输入的时钟信号的低电平维持时间与上拉节点PU的预充电维持时间相等，上拉节点PU的电位抬升，将第三晶体管M13和第十三晶体管M13打开，因本行移位寄存器的时钟信号为低电平，因此信号输出端OUTPUT输出的扫描信号仍保持低电位，低电平维持时间多1H，但数据信号的时序不变，上拉节点PU的电位升高的同时将第六晶体管M6和第八晶体管M8打开，下拉节点PD的电位被下拉。
在输出阶段，上拉节点PU的高电平将第三晶体管M3打开，此时时钟信号为高电平，信号输出端OUTPUT的电位升高，输出扫描信号，同时由于电容自举效应，上拉节点PU的电位持续升高；第六晶体管M6和第八晶体管M8仍保持开启，下拉节点PD的电位维持低电平并且低电平维持时间多1H，第7行的扫描信号相对于数据信号的时序延迟1H，使第7行的像素单元多出1H的预充电时间，或者说，如图6所示，其中下拉节点PD的电位维持低电平并且低电平维持时间多2H，第7行的扫描信号相对于数据信号的时序延迟2H，使得第7行多出2H的预充电时间，数据信号高低切换后，例如切换至L255的数据信号的时间和Gn输出信号在时序上交叠大于或等于2H，从而该行的像素单元较其他行的像素单元多出大于或等于1H的预充电时间，在真正信号输入时，像素单元已处于较高电位，从而可以提升该行充电率，避免出现线残像等显示不良。
在此需要说明的是，第n个移位寄存器的上拉节点PUn，即第7个移位寄存器的上拉节点PU的电位变化可以分为三个阶段，如图5和图6所示，在低电平维持阶段为上拉节点PU的预充电阶段，由于输入信号端INPUT输入高电平信号，上拉节点PU的电位第一次被拉高，在这段高电平维持阶段为上拉节点PU的预充电阶段，由于电容的自举作用，上拉节点PU的电位第二次被拉高，在这段高电平维持阶段为上拉节点PU的充电阶段，由于电容的存储作用，上拉节点PU的电位被拉低但是仍保持一定时间的高电平，在这段高电平维持阶段为上拉节点的放电阶段。在本公开实施例中，上拉节点PU的下降沿时间具体可以为上拉节点PU的充电阶段接收，其电位开始被拉低的时间，如图5和图6中所示的第二个时间台阶结束的时间，此时上拉节点PU充电结束，相应的显示面板中第7行像素单元输入的扫描信号结束。
另一方面，如图7所示，由于第7个移位寄存器中的上拉节点PU的下降沿时间延迟1H，使得相应的扫描信号的高电平维持时长也延迟了1H，相当于数据信号高低灰阶切换导致公共电极信号的拉动提前，即数据信号高低切换的时间与扫描信号的结束时间间隔至少1H，其间隔时间较远，避免了公共电极信号的波动影响该行像素单元的充电，从而可以避免水平方向串扰等显示不良。
图8为本公开实施例提供的包含6条时钟信号线的显示面板所输入信号的一种时序图，在图8中，显示面板的时钟信号线的数量为6个，以第4行像素单元输入的数据信号发生高低灰阶切换为例，可以看出其中的第4行的扫描信号相对于数据信号的时序延迟1H，使第4行的像素单元多出1H的预充电时间，数据信号高低切换后，例如切换至L255的数据信号的时间和Gn输出信号在时序上交叠大于或等于2H，从而该行的像素单元较其他行的像素单元多出大于或等于1H的预充电时间，在真正信号输入时，像素单元已 处于较高电位，从而可以提升该行充电率，避免出现线残像等显示不良。
图9为本公开实施例提供的包含12条时钟信号线的显示面板所输入信号的又一种时序图，如图9所示，以CLK7对应的Gn行GOA工作时序为例。在输入阶段，时序控制器监测到数据信号线在第7行像素单元输入的数据信号发生高低灰阶切换，可以调整第7个移位寄存器所连接的时钟信号线CLK7中的时钟信号的时序，使得CLK7中的时钟信号的高电平维持时长由原来的6H延长至7H，第1个移位寄存器的信号输出端OUTPUT的输出信号作为本级移位寄存器的输入信号输入至信号输入端INPUT，此时第一晶体管M1打开，对上拉节点PU进行预充电，上拉节点PU电位抬升，同时由于电容自举效应，上拉节点PU的电位持续升高，将第三晶体管M13和第十三晶体管M13打开，对上拉节点PU进行充电，第7个移位寄存器所输入的时钟信号的高电平维持时间与上拉节点PU的充电时间相等。因本行移位寄存器的时钟信号为低电平，因此信号输出端OUTPUT输出的扫描信号仍保持低电位，上拉节点PU的电位升高的同时将第六晶体管M6和第八晶体管M8打开，下拉节点PD的电位被下拉。
在输出阶段，上拉节点PU的高电平将第三晶体管M3打开，此时时钟信号为高电平，信号输出端OUTPUT的电位升高，输出扫描信号，同时由于电容自举效应，上拉节点PU的电位持续升高，此时，由于CLK7中的时钟信号的高电平维持时长多1H，其电容的自举时间也同样多1H；第六晶体管M6和第八晶体管M8仍保持开启，下拉节点PD的电位维持低电平，由于电容的自举时间多1H，使得上拉节点PU的充电时间多1H，相应地，该行的扫描信号Gn的高电平时长多1H，这样第7行的像素单元中驱动晶体管的开启时间多出1H，或者说，如图10所示，其中的电容的自举时间多2H，使得上拉节点PU的充电时间多2H，相应地，该行的扫描信号Gn的高电平时长也多2H，数据信号高低切换后，例如切换至L255的数据信号的时间和 Gn输出信号在时序上交叠大于或等于2H，从而该行的像素单元较其他行的像素单元多出大于或等于1H的充电时间，从而可以提升该行充电率，避免出现线残像等显示不良。
另一方面，如图11所示，由于第7个移位寄存器中的上拉节点PU的下降沿时间延迟2H，使得相应的扫描信号的高电平维持时长也延迟了2H，相当于数据信号高低灰阶切换导致公共电极信号的拉动提前，即数据信号高低切换的时间与扫描信号的结束时间间隔至少2H，其间隔时间较远，避免了公共电极信号的波动影响该行像素单元的充电，从而可以避免水平方向串扰等显示不良。
图12为本公开实施例提供的包含6条时钟信号线的显示面板所输入信号的另一种时序图，在图12中，显示面板的时钟信号线的数量为6个，以第4行像素单元输入的数据信号发生高低灰阶切换为例，可以看出由于电容的自举时间多1H，使得上拉节点PU的充电时间多1H，相应地，第4行的扫描信号Gn的高电平时长多1H，这样第4行的像素单元中驱动晶体管的开启时间多出1H，数据信号高低切换后，例如切换至L255的数据信号的时间和Gn输出信号在时序上交叠大于或等于2H，从而该行的像素单元较其他行的像素单元多出大于或等于1H的充电时间，从而可以提升该行充电率，避免出现线残像等显示不良。
在一些实施例中，显示面板的驱动方法还包括如下步骤：
步骤S103，根据数据线中传输的数据信号，判断第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n+m为小于或等于N的正整数。
若第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值小于或等于阈值，则则执行步骤S104。步骤S104，向第n+m个移位寄存器输入初始相位的时钟信号。
在高低灰阶切换之后，可以继续检测相邻行的像素单元所输入的数据信号是否发生高低灰阶切换，如果未发生数据信号的高低灰阶切换，可以将相应的时钟信号线输入初始相位的时钟信号，直至检测到下一次数据信号的高低切换再进行时序调整，以避免时钟信号发生错乱，造成错充，影响显示画面的显示效果。另外，可选的，以12个时钟信号为一组的移位寄存器为例，如检测到第六和第七行信号发生高低灰阶切换，可以调整第7行的时钟信号的时序，然后此时前6行时钟信号的时序保持一致，这里说的保持一致指的是时钟信号高电平时间和低电平时间一致(均为6H高电平和6H低电平)，然后从第7行开始，到第12行，时钟信号均为调整时序后的时序，然后当再次从第一行开始扫描时，第一行到第12行均恢复至高低切换前未调整时序的时序(均为6H高电平和6H低电平)。当然也可以例如检测第六行和第七行发生高低灰阶切换，可以调整第7行的时钟信号的时序，此后若检测无相邻行发生高低灰阶切换，例如扫描到第9行时候，可以将第7行的时钟信号恢复至初始时序(6H高电平和6H低电平)，具有恢复时间可以根据实际需要设定，在此不作限定。可以看出，当显示面板中数据线中的数据信号发生高低灰阶切换时，调整该行像素单元所对应的移位寄存器所输入的时钟信号的相位，使得对应的移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号，并且其后的时钟信号也进行同样的调整，其前的时钟信号不做调整。若后续检测到无相邻行发生高低灰阶切换，则所有的数据信号线中的数据信号恢复至初始相位，以避免时钟信号紊乱，造成扫描信号输出紊乱，造成错充，影响显示效果。
本公开施实施例还提供了一种显示面板，图13为本公开实施例提供的一种显示面板的结构示意图，如图13所示，该显示面板包括：交叉设置的N条栅线S和M条数据线D、及位于栅线和数据线限定区域内的像素单元；显示面板还包括：N个移位寄存器GOA和P条时钟信号线；N个移位寄存器 中的每相邻P个移位寄存器分别连接P条时钟信号线；N个移位寄存器的信号输出端分别与N条栅线一一对应连接；其中，P为大于或等于2的偶数；N为大于或等于P的整数；M为正整数；该显示面板还包括侦测模块Z，侦测模块Z被配置为执行与上述任一实施例提供的显示面板的驱动方法中的步骤S101至步骤S104，其实现原理与上述的显示面板的驱动方法的实现原理相同，在此不在赘述。侦测模块Z可以是时序控制器T-CON，侦测模块Z可以设置在显示面板的主板上，通过主板和显示面板电连接，侦测模块也可以设置在时序控制器单独的主板B上，与显示面板电连接，与显示面板的连接可以是直接连接，或者在通过一个柔性电路板FPC连接，在此不作限定，显示面板还包括驱动芯片IC，驱动芯片IC可以设置在显示面板上，如图13所示，也可以设置在FPC上，另外，时序控制器的信号可以通过引线等方式电连接到驱动芯片IC上，实现与显示面板的电连接。
本公开实施例还提供了一种显示装置，该显示装置包括上述任一实施例提供的显示面板，该显示装置可以为电视机、手机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。其实现原理与上述的显示面板的实现原理类似，在此不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示面板的驱动方法，所述显示面板包括：交叉设置的N条栅线和M条数据线、及位于所述栅线和所述数据线限定区域内的像素单元；所述显示面板还包括：N个移位寄存器和P条时钟信号线；所述N个移位寄存器中的每相邻P个移位寄存器分别连接所述P条时钟信号线；所述N个移位寄存器的信号输出端分别与所述N条栅线一一对应连接；其中，P为大于或等于2的偶数；N为大于或等于P的整数；M为正整数；其特征在于，所述显示面板的驱动方法包括：
    根据所述数据线中传输的数据信号，判断第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n为小于或等于N的正整数；
    若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。
  2. 根据权利要求1所述的显示面板的驱动方法，其特征在于，若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，第n行像素单元输入的数据信号的时间与第n行移位寄存器的上拉节点的下降沿时间间隔大于1H；其中，1H为一行像素单元的充电时间。
  3. 根据权利要求1所述的显示面板的驱动方法，其特征在于，所述调整第n个移位寄存器所输入的时钟信号的相位，包括：
    将第n个移位寄存器所输入的时钟信号的非工作电平维持时间延长。
  4. 根据权利要求3所述的显示面板的驱动方法，其特征在于，第n个移位寄存器所输入的时钟信号的非工作电平维持时间较预设时钟信号的非工作电平维持时间延长1H至2H。
  5. 根据权利要求3所述的显示面板的驱动方法，其特征在于，第n个移位寄存器所输入的时钟信号的非工作电平维持时间与上拉节点的预充电 维持时间相等。
  6. 根据权利要求1所述的显示面板的驱动方法，其特征在于，所述调整第n个移位寄存器所输入的时钟信号的相位，包括：
    将第n个移位寄存器所输入的时钟信号的工作电平维持时间延长。
  7. 根据权利要求6所述的显示面板的驱动方法，其特征在于，第n个移位寄存器所输入的时钟信号的工作电平维持时间较预设时钟信号的工作电平维持时间延长1H至2H。
  8. 根据权利要求6所述的显示面板的驱动方法，其特征在于，第n个移位寄存器所输入的时钟信号的工作电平维持时间与上拉节点的充电时间相等。
  9. 根据权利要求1所述的显示面板的驱动方法，其特征在于，第n行像素单元输入的数据信号的时间与上拉节点的充电时间有交叠，且交叠时间大于或等于2H。
  10. 根据权利要求1所述的显示面板的驱动方法，其特征在于，所述显示面板的驱动方法还包括：
    根据所述数据线中传输的数据信号，判断第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；n+m为小于或等于N的正整数；
    若第n+m行像素单元与第n+m-1行像素单元所输入的数据信号的灰阶值差值小于或等于阈值，则向第n+m个移位寄存器输入初始相位的时钟信号。
  11. 一种显示面板，所述显示面板包括：交叉设置的N条栅线和M条数据线、及位于所述栅线和所述数据线限定区域内的像素单元；所述显示面板还包括：N个移位寄存器和P条时钟信号线；所述N个移位寄存器中的每相邻P个移位寄存器分别连接所述P条时钟信号线；所述N个移位寄存器的信号输出端分别与所述N条栅线一一对应连接；其中，P为大于或等于 2的偶数；N为大于或等于P的整数；M为正整数；其特征在于，所述显示面板还包括侦测模块，所述侦测模块被配置为侦测第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶值差值是否大于阈值；若第n行像素单元与第n-1行像素单元所输入的数据信号的灰阶差值大于阈值，则调整第n个移位寄存器所输入的时钟信号的相位，使得第n个移位寄存器的上拉节点的下降沿时间延迟，以输出相位延迟的扫描信号。
  12. 根据权利要求11所述的显示面板，其特征在于，所述N个移位寄存器中的每个移位寄存器包括：输入子电路、输出子电路和上拉复位子电路；
    所述输入子电路被配置为响应于信号输入端的输入信号，并将所述输入信号写入上拉节点；
    所述输出子电路被配置为响应于所述上拉节点的电位，并将时钟信号端输入的时钟信号通过信号输出端输出；
    所述上拉复位子电路被配置为响应于上拉复位信号端输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位。
  13. 根据权利要求12所述的显示面板，其特征在于，第i个所述移位寄存器的信号输出端连接第i+p个所述移位寄存器的信号输入端；其中，P/2≤p＜N；i≤N-p；
    第j个所述移位寄存器的上拉复位信号端连接第j+q个所述移位寄存器的信号输出端；2≤q-p＜N/2；j≤N-q。
  14. 根据权利要求12所述的显示面板，其特征在于，所述显示面板还包括：第一帧开启信号线和第二帧开启信号线；
    第1个至第N/2个所述移位寄存器中的奇数行的信号输入端均连接所述第一帧开启信号线；
    第1个至第N/2个所述移位寄存器中的偶数行的信号输入端均连接所述第二帧开启信号线。
  15. 一种显示装置，其特征在于，所述显示装置包括如权利要求11-14 任一项所述的显示面板。
PCT/CN2022/103254 2021-07-30 2022-07-01 显示面板的驱动方法、显示面板及显示装置 WO2023005596A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/271,840 US20240071272A1 (en) 2021-07-30 2022-07-01 Display Panel Driving Method, Display Panel, and Display Apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110871022.5 2021-07-30
CN202110871022.5A CN115691373A (zh) 2021-07-30 2021-07-30 显示面板的驱动方法、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2023005596A1 true WO2023005596A1 (zh) 2023-02-02

Family

ID=85058129

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/103254 WO2023005596A1 (zh) 2021-07-30 2022-07-01 显示面板的驱动方法、显示面板及显示装置

Country Status (3)

Country Link
US (1) US20240071272A1 (zh)
CN (1) CN115691373A (zh)
WO (1) WO2023005596A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390394A (zh) * 2013-07-30 2013-11-13 深圳市华星光电技术有限公司 一种液晶面板和液晶面板的驱动方法
CN104867474A (zh) * 2015-06-19 2015-08-26 合肥鑫晟光电科技有限公司 用于tft-lcd的源极驱动器、驱动电路及驱动方法
CN107068086A (zh) * 2017-03-30 2017-08-18 京东方科技集团股份有限公司 像素充电方法和电路
CN107507585A (zh) * 2017-08-25 2017-12-22 惠科股份有限公司 显示面板及其像素单元预充电切换方法
CN111508448A (zh) * 2020-05-28 2020-08-07 京东方科技集团股份有限公司 显示面板及其控制方法
CN111554242A (zh) * 2020-05-13 2020-08-18 深圳市华星光电半导体显示技术有限公司 显示装置和终端
CN111883084A (zh) * 2020-07-30 2020-11-03 惠科股份有限公司 一种驱动方法、补偿时间表的构建方法和显示装置
US20200365090A1 (en) * 2019-05-17 2020-11-19 Samsung Display Co., Ltd. Display device compensating for horizontal crosstalk
CN113763857A (zh) * 2021-08-31 2021-12-07 惠科股份有限公司 显示面板驱动方法、驱动装置及计算机设备

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390394A (zh) * 2013-07-30 2013-11-13 深圳市华星光电技术有限公司 一种液晶面板和液晶面板的驱动方法
CN104867474A (zh) * 2015-06-19 2015-08-26 合肥鑫晟光电科技有限公司 用于tft-lcd的源极驱动器、驱动电路及驱动方法
CN107068086A (zh) * 2017-03-30 2017-08-18 京东方科技集团股份有限公司 像素充电方法和电路
CN107507585A (zh) * 2017-08-25 2017-12-22 惠科股份有限公司 显示面板及其像素单元预充电切换方法
US20200365090A1 (en) * 2019-05-17 2020-11-19 Samsung Display Co., Ltd. Display device compensating for horizontal crosstalk
CN111554242A (zh) * 2020-05-13 2020-08-18 深圳市华星光电半导体显示技术有限公司 显示装置和终端
CN111508448A (zh) * 2020-05-28 2020-08-07 京东方科技集团股份有限公司 显示面板及其控制方法
CN111883084A (zh) * 2020-07-30 2020-11-03 惠科股份有限公司 一种驱动方法、补偿时间表的构建方法和显示装置
CN113763857A (zh) * 2021-08-31 2021-12-07 惠科股份有限公司 显示面板驱动方法、驱动装置及计算机设备

Also Published As

Publication number Publication date
US20240071272A1 (en) 2024-02-29
CN115691373A (zh) 2023-02-03

Similar Documents

Publication Publication Date Title
EP3125250B1 (en) Gate driving circuit and driving method therefor and display device
US10593284B2 (en) Shift register unit and method for driving same, shift register circuit and display apparatus
JP5504313B2 (ja) シフトレジスタ駆動方法
WO2019134221A1 (zh) Goa电路
US9305509B2 (en) Shift register unit, gate driving circuit and display apparatus
JP5079350B2 (ja) シフトレジスタ回路
US7289096B2 (en) Shift register and a display device using the same
KR101443126B1 (ko) 게이트 드라이버 온 어레이, 시프팅 레지스터 및 디스플레이 스크린
US9558843B2 (en) Shift register unit, gate driving circuit, and display device comprising the same
WO2019161669A1 (zh) 栅极驱动电路、触控显示装置及驱动方法
US9666152B2 (en) Shift register unit, gate driving circuit and display device
US20170025079A1 (en) Shift register unit and driving method thereof, gate driving circuit and display device
WO2017118057A1 (zh) 一种栅极驱动电路、阵列基板、显示面板以及驱动方法
JP2004157508A (ja) シフトレジスタ、該シフトレジスタを用いた液晶表示装置、及び液晶装置のスキャンライン駆動方法
US10748465B2 (en) Gate drive circuit, display device and method for driving gate drive circuit
CN111105762B (zh) 扫描信号线驱动电路、显示装置及扫描信号线的驱动方法
US20210225312A1 (en) Shift register unit and driving method thereof, gate driving circuit and display device
WO2019024481A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路及显示装置
JP2011085680A (ja) 液晶表示装置、走査線駆動回路および電子機器
US20180261178A1 (en) Shift Register with Fault Tolerance Mechanism and Driving Method Thereof, and Gate Driving Circuit
JP2008140522A (ja) シフトレジスタ回路およびそれを備える画像表示装置、並びに電圧信号生成回路
KR102015848B1 (ko) 액정표시장치
WO2023005596A1 (zh) 显示面板的驱动方法、显示面板及显示装置
CN113393799A (zh) 栅极驱动电路、显示面板及显示装置
US10714511B2 (en) Pull-down circuit of gate driving unit and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22848201

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18271840

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE