WO2023000989A1 - 显示基板及其亮度补偿方法、显示装置 - Google Patents

显示基板及其亮度补偿方法、显示装置 Download PDF

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Publication number
WO2023000989A1
WO2023000989A1 PCT/CN2022/104301 CN2022104301W WO2023000989A1 WO 2023000989 A1 WO2023000989 A1 WO 2023000989A1 CN 2022104301 W CN2022104301 W CN 2022104301W WO 2023000989 A1 WO2023000989 A1 WO 2023000989A1
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Prior art keywords
transistor
emitting element
pole
circuit
control
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PCT/CN2022/104301
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English (en)
French (fr)
Inventor
刘伟星
彭宽军
秦斌
郭凯
王铁石
张方振
Original Assignee
京东方科技集团股份有限公司
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Publication of WO2023000989A1 publication Critical patent/WO2023000989A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate, a brightness compensation method thereof, and a display device.
  • LED Light Emitting Diode
  • 3D three-dimensional
  • Embodiments of the present disclosure provide a display substrate, a brightness compensation method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a plurality of pixel units and at least one compensation circuit.
  • At least one pixel unit includes: a main light emitting unit and an auxiliary light emitting unit; at least one compensation circuit is connected to the auxiliary light emitting unit of the at least one pixel unit.
  • the at least one compensation circuit is configured to detect the brightness or temperature of the at least one pixel unit, and control the auxiliary light emitting unit of the at least one pixel unit to emit light according to the detection result.
  • the compensation circuit includes: a compensation control circuit and at least one detection circuit connected to the compensation control circuit; the detection circuit is connected to an auxiliary light emitting unit of a pixel unit.
  • the detection circuit is configured to detect the brightness of the connected pixel unit.
  • the compensation control circuit is configured to control the auxiliary light-emitting unit connected to the detection circuit to emit light according to the detection result of the detection circuit.
  • the compensation control circuit includes: a first control subcircuit and a second control subcircuit.
  • the first control subcircuit is connected to the first scan line, a voltage detection circuit and a detection circuit, and is configured to transmit the detection result of the detection circuit to the voltage under the control of the first scan line.
  • a detection circuit so that an external control circuit connected to the voltage detection circuit updates a compensation control signal according to the detection result.
  • the second control subcircuit is connected to the first scan line, the compensation data line, the second power supply line and at least one detection circuit, and is configured to control the compensation data line under the control of the first scan line
  • the provided compensation control signal is transmitted to the at least one detection circuit, so as to control the at least one detection circuit to transmit the detection result to the corresponding auxiliary light emitting unit.
  • the first control subcircuit includes: a seventh transistor; the second control subcircuit includes: an eighth transistor and a second capacitor.
  • the control electrode of the seventh transistor is connected to the first scanning line, the first electrode of the seventh transistor is connected to the voltage detection circuit, and the second electrode of the seventh transistor is connected to the detection circuit.
  • the control electrode of the eighth transistor is connected to the first scanning line, the first electrode of the eighth transistor is connected to the compensation data line, the second electrode of the eighth transistor is connected to the second capacitor
  • the second pole is connected, and the first pole of the second capacitor is connected to the second power line.
  • the second pole of the eighth transistor is connected to the at least one detection circuit.
  • the detection circuit includes: a detection element, a fifth transistor and a sixth transistor.
  • the first pole of the detection element is connected to the second pole of the sixth transistor, and the second pole of the detection element is connected to the second power line; the control pole and the first pole of the sixth transistor are connected to the first The power line is connected; the control pole of the fifth transistor is connected to the compensation control circuit, the first pole of the fifth transistor is connected to the first pole of the detection element, and the second pole of the fifth transistor is connected to the first pole of the detection element.
  • the auxiliary light emitting unit is connected.
  • the main light emitting unit includes: a main light emitting element and a main driving circuit connected to the main light emitting element.
  • the main driving circuit includes: a first transistor, a second transistor, a third transistor and a first capacitor; the control electrode of the first transistor is connected to the first scanning line, and the first electrode of the first transistor is connected to the data line connected, the second pole of the first transistor is connected to the control pole of the second transistor; the first pole of the second transistor is connected to the first power line, and the second pole of the second transistor is connected to the The first pole of the third transistor is connected; the control pole of the third transistor is connected to the second scanning line, the second pole of the third transistor is connected to the voltage detection circuit; the first pole of the first capacitor is connected to the The control electrode of the second transistor is connected, and the second electrode of the first capacitor is connected with the second electrode of the second transistor.
  • the first pole of the main light-emitting element is connected to the second pole of the second transistor, and the second pole of the main light-emitting element
  • the auxiliary light emitting unit includes: an auxiliary light emitting element and an auxiliary driving circuit connected to the auxiliary light emitting element.
  • the auxiliary driving circuit includes: a fourth transistor; the control pole of the fourth transistor is connected to the detection circuit, the first pole of the fourth transistor is connected to the first power line, and the second pole of the fourth transistor The pole is connected to the first pole of the auxiliary light-emitting element; the second pole of the auxiliary light-emitting element is connected to the second power line.
  • the compensation circuit includes: a detection circuit connected to the auxiliary light emitting unit of at least one pixel unit.
  • the detection circuit is configured to detect the temperature of the at least one pixel unit, and control the auxiliary light emitting unit of the at least one pixel unit to emit light according to the detection result.
  • the detection circuit includes: a first detection transistor and a second detection transistor.
  • the control electrode and the first electrode of the first detection transistor are connected to the first power supply line, the second electrode of the first detection transistor is connected to the second electrode of the second detection transistor, and connected to at least one pixel unit
  • the auxiliary light-emitting unit is connected; the control electrode and the first electrode of the second detection transistor are connected to the second power line.
  • the doping types of the first detection transistor and the second detection transistor are opposite.
  • the main light emitting unit includes: a main light emitting element and a main driving circuit connected to the main light emitting element.
  • the main driving circuit includes: a data writing subcircuit, a driving subcircuit, a threshold compensation subcircuit, a storage subcircuit, an initialization subcircuit and a light emission control subcircuit.
  • the data writing sub-circuit is connected to the third scanning line, the data line and the fifth node, and is configured to write the data provided by the data line into the storage sub-circuit under the control of the third scanning line Signal.
  • the storage sub-circuit is connected to the fifth node and the sixth node.
  • the driving sub-circuit is connected to the sixth node, the first power line and the first pole of the main light-emitting element, and is configured to output a driving current to the main light-emitting element under the control of the sixth node .
  • the threshold compensation sub-circuit is connected to the third scanning line, the sixth node and the first pole of the main light-emitting element, and is configured to control the driving sub-circuit under the control of the third scanning line.
  • the threshold voltage of the circuit is compensated.
  • the initialization subcircuit is connected to the fifth node, the initial signal line, the first reset line, and the second reset line, and is configured to, under the control of the first reset line or the second reset line, Five nodes are initialized.
  • the light emission control sub-circuit is connected with the light emission control line, the second power supply line and the second pole of the main light emitting element, and is configured to turn on the second electrode of the main light emitting element under the control of the light emission control line. pole and the second power line.
  • the data writing sub-circuit includes: a ninth transistor; the driving sub-circuit includes: a tenth transistor; the threshold compensation sub-circuit includes: an eleventh transistor; The circuit includes: a fourth capacitor.
  • the light emission control sub-circuit includes: a twelfth transistor.
  • the initialization sub-circuit includes: a thirteenth transistor and a fourteenth transistor. The control electrode of the ninth transistor is connected to the third scanning line, the first electrode of the ninth transistor is connected to the data line, and the second electrode of the ninth transistor is connected to the fifth node.
  • the control electrode of the tenth transistor is connected to the fifth node, the first electrode of the tenth transistor is connected to the first power line, and the second electrode of the tenth transistor is connected to the main light-emitting element.
  • first pole connection The control electrode of the eleventh transistor is connected to the third scan line, the first electrode of the eleventh transistor is connected to the sixth node, and the second electrode of the eleventh transistor is connected to the tenth node.
  • the second pole connection of the transistor is connected to the light-emitting control line, the first electrode of the twelfth transistor is connected to the second electrode of the main light-emitting element, and the second electrode of the twelfth transistor is connected to the The second power cord is connected.
  • the control electrode of the thirteenth transistor is connected to the first reset line, the first electrode of the thirteenth transistor is connected to the initial signal line, and the second electrode of the thirteenth transistor is connected to the first Five-node connection.
  • the control pole of the fourteenth transistor is connected to the second reset line, the first pole of the fourteenth transistor is connected to the initial signal line, and the second pole of the fourteenth transistor is connected to the first Five-node connection.
  • a first pole of the fourth capacitor is connected to the fifth node, and a second pole of the fourth capacitor is connected to the sixth node.
  • the auxiliary light emitting unit includes: an auxiliary light emitting element and an auxiliary driving circuit connected with the auxiliary light emitting element and a main driving circuit.
  • the auxiliary driving circuit includes: a fifteenth transistor. The control electrode of the fifteenth transistor is connected to the sixth node, the first electrode of the fifteenth transistor is connected to the detection circuit, and the second electrode of the fifteenth transistor is connected to the auxiliary light-emitting element first pole connection. The second pole of the auxiliary light emitting element is connected with the second pole of the main light emitting element.
  • the main light emitting unit includes a main light emitting element and a main driving circuit; the auxiliary light emitting unit includes an auxiliary light emitting element and an auxiliary driving circuit; both the main light emitting element and the auxiliary light emitting element are micro light emitting elements ; The light emitting area of the main light emitting element is larger than the light emitting area of the auxiliary light emitting element.
  • the display substrate includes: a substrate, a circuit structure layer disposed on the substrate, and a plurality of light-emitting diode chips;
  • the circuit structure layer includes: the compensation circuit and the pixel
  • the main driving circuit and the auxiliary driving circuit of the unit; at least one light-emitting diode chip includes: the main light-emitting element and the auxiliary light-emitting element of the pixel unit.
  • Each of the main light-emitting element and the auxiliary light-emitting element includes: a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked in sequence; the doping types of the first semiconductor layer and the second semiconductor layer are different.
  • the main light-emitting element and the auxiliary light-emitting element each further include: at least one of a first binding electrode and a second binding electrode.
  • the first binding electrode of the main light emitting element is connected to the first semiconductor layer of the main light emitting element
  • the second binding electrode of the main light emitting element is connected to the second semiconductor layer of the main light emitting element.
  • the first binding electrode of the auxiliary light-emitting element is connected to the first semiconductor layer of the auxiliary light-emitting element
  • the second binding electrode of the auxiliary light-emitting element is connected to the second semiconductor layer of the auxiliary light-emitting element.
  • the first semiconductor layer of the main light-emitting element and the first semiconductor layer of the auxiliary light-emitting element are integrated and connected to the same first binding electrode.
  • the LED chip further includes a substrate, and the main light-emitting element and the auxiliary light-emitting element are located on the same side of the substrate.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a brightness compensation method for a display substrate, which is applied to the above-mentioned display substrate, and the brightness compensation method includes: a compensation circuit detects the brightness or temperature of at least one pixel unit; the compensation circuit controlling the auxiliary light emitting unit of the at least one pixel unit to emit light according to the detection result.
  • Fig. 1 is a schematic diagram of the relationship between the luminous efficiency of an LED and the current density flowing through the LED;
  • FIG. 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a circuit structure of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a partial circuit structure of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a voltage detection circuit according to at least one embodiment of the present disclosure.
  • FIG. 6 is a working timing diagram of a main driving circuit of a pixel unit according to at least one embodiment of the present disclosure
  • FIG. 7 is a working sequence diagram of the compensation control circuit of at least one embodiment of the present disclosure.
  • FIG. 8 is a working timing diagram of the compensation control circuit in the multi-frame display stage of at least one embodiment of the present disclosure.
  • FIG. 9A is a schematic plan view of a light emitting diode chip in at least one embodiment of the present disclosure.
  • Figure 9B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 9A;
  • 10A is a schematic plan view of a light emitting diode chip after forming a second semiconductor layer according to at least one embodiment of the present disclosure
  • Figure 10B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 10A;
  • 11A is a schematic plan view of a light emitting diode chip after forming a first insulating layer according to at least one embodiment of the present disclosure
  • Figure 11B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 11A;
  • FIG. 12A is a schematic plan view of a light-emitting diode chip after forming a transfer electrode layer according to at least one embodiment of the present disclosure
  • Figure 12B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 12A;
  • FIG. 13A is a schematic plan view of a light emitting diode chip after forming an encapsulation layer according to at least one embodiment of the present disclosure
  • Figure 13B is a schematic partial cross-sectional view along the Q-Q' direction in Figure 13A;
  • FIG. 14 is a schematic partial cross-sectional view of a circuit structure layer of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 15 is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • 16 is a schematic structural diagram of a main driving circuit of a pixel unit according to at least one embodiment of the present disclosure
  • 17 is a schematic diagram of a circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a partial circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 19 is a working timing diagram of a pixel unit in at least one embodiment of the present disclosure.
  • FIG. 20 is a flowchart of a brightness compensation method for a display substrate according to at least one embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense unless otherwise specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes the situation that the constituent elements are connected together through an element having some kind of electrical effect.
  • the “element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • parallel means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus may include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° to 100°, and therefore, an angle of 85° to 95° may be included.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic diagram of the relationship between the luminous efficiency of an LED and the current density flowing through the LED. As shown in Figure 1, at a lower current density (such as curve section I), the current density flowing through the LED is small, and the luminous efficiency is low; Higher efficiency.
  • the LED has a larger light-emitting area, which tends to reduce the current density flowing through the LED, thereby reducing the luminous efficiency of the LED.
  • the LED in the case of increasing the current density to increase the luminous efficiency of the LED, it is easy to increase the power consumption.
  • the LED maintains a high luminous efficiency for a long time, it will work under the condition of high current density for a long time, which will cause the temperature of the LED to rise, and the phenomenon of heat accumulation will affect the stability of the LED structure. , reduce the luminous efficiency of LED.
  • An embodiment of the present disclosure provides a display substrate, including: a plurality of pixel units and at least one compensation circuit.
  • At least one pixel unit includes a main light emitting unit and an auxiliary light emitting unit.
  • At least one compensation circuit is connected to the auxiliary light emitting unit of at least one pixel unit.
  • the at least one compensation circuit is configured to detect the temperature or brightness of the at least one pixel unit, and control the auxiliary light emitting unit of the at least one pixel unit to emit light according to the detection result.
  • the display substrate provided in this embodiment can use the compensation circuit and the auxiliary light-emitting unit to emit light to compensate for the reduced brightness when the main light-emitting unit causes brightness attenuation due to temperature rise, thereby improving the brightness attenuation caused by temperature rise , and improve the display effect.
  • the compensation circuit includes: a compensation control circuit and at least one detection circuit connected to the compensation control circuit.
  • One detection circuit is connected with the auxiliary light-emitting unit of one pixel unit.
  • the detection circuit is configured to detect the brightness of the connected pixel unit.
  • the compensation control circuit is configured to control the auxiliary light emitting unit connected to the detection circuit to emit light according to the detection result of the detection circuit.
  • the compensation circuit may include a compensation control circuit and a plurality of detection circuits (for example, four detection circuits), and the plurality of detection circuits are connected to the auxiliary light emitting units of the plurality of pixel units in a one-to-one correspondence.
  • the auxiliary light-emitting unit of each pixel unit can emit light according to the detection result of the connected detection circuit under the control of the compensation control circuit, so as to realize brightness compensation.
  • the number of pixel units connected to one compensation circuit is not limited.
  • the compensation control circuit includes: a first control subcircuit and a second control subcircuit.
  • the first control subcircuit is connected to the first scanning line, a voltage detection circuit and a detection circuit, and is configured to transmit the detection result of the detection circuit to the voltage detection circuit under the control of the first scanning line, so as to
  • the external control circuit connected to the voltage detection circuit is configured to update the compensation control signal according to the detection result.
  • the second control subcircuit is connected to the first scanning line, the compensation data line, the second power supply line and at least one detection circuit, and is configured to transmit the compensation control signal provided by the compensation data line to at least one of the detection circuits under the control of the first scanning line.
  • the voltage detection circuit may be configured to obtain the threshold voltage of the driving transistor of the main light emitting unit, and obtain a detection result of the detection circuit.
  • the external control circuit can be integrated in the timing controller, so as to provide the compensation control signal to the compensation data line through the data driver. However, this embodiment does not limit it.
  • the compensation circuit may include: a detection circuit connected to the auxiliary light emitting unit of at least one pixel unit.
  • the detection circuit is configured to detect the temperature of at least one pixel unit, and control the auxiliary light-emitting unit of the at least one pixel unit to emit light according to the detection result.
  • the detection circuit can realize temperature detection and light emission control of the auxiliary light emitting unit.
  • this embodiment does not limit it.
  • the main light emitting unit includes a main light emitting element and a main driving circuit; the auxiliary light emitting unit includes an auxiliary light emitting element and an auxiliary driving circuit. Both the main light-emitting element and the auxiliary light-emitting element are micro-light-emitting elements.
  • the light emitting area of the main light emitting element is larger than the light emitting area of the auxiliary light emitting element.
  • the main light-emitting element and the auxiliary light-emitting element may be a sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED for short), or may be a Micro Light Emitting Diode (Micro Light Emitting Diode, Micro LED for short).
  • this embodiment does not limit it.
  • setting the auxiliary light-emitting element with a smaller light-emitting area can help to increase the current density flowing through the auxiliary light-emitting element, thereby improving the luminous efficiency of the auxiliary light-emitting element.
  • the display substrate includes: a substrate, a circuit structure layer disposed on the substrate, and a plurality of light emitting diode chips.
  • the circuit structure layer includes: the compensation circuit and the main driving circuit and the auxiliary driving circuit of the pixel unit.
  • At least one light emitting diode chip includes: a main light emitting element and an auxiliary light emitting element of the pixel unit.
  • Each of the main light-emitting element and the auxiliary light-emitting element includes: a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked in sequence; wherein, the doping types of the first semiconductor layer and the second semiconductor layer are different.
  • Each of the main light-emitting element and the auxiliary light-emitting element further includes: at least one of a first binding electrode and a second binding electrode.
  • the first binding electrode of the main light emitting element is connected to the first semiconductor layer of the main light emitting element
  • the second binding electrode of the main light emitting element is connected to the second semiconductor layer of the main light emitting element.
  • the first binding electrode of the auxiliary light-emitting element is connected to the first semiconductor layer of the auxiliary light-emitting element
  • the second binding electrode of the auxiliary light-emitting element is connected to the second semiconductor layer of the auxiliary light-emitting element.
  • the main light-emitting element and the auxiliary light-emitting element on one light-emitting diode chip, so that the light-emitting areas of the main light-emitting element and the auxiliary light-emitting element are smaller than the entire area of the light-emitting diode chip, it is possible to improve the flow through the main light-emitting element.
  • the current density of components and auxiliary light-emitting components thereby improving the luminous efficiency of light-emitting diode chips.
  • FIG. 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes: a timing controller, a data driver, a scan driver, a pixel array, and a plurality of compensation circuits.
  • the pixel array may include a plurality of scan lines (eg, G(1) to G(m)), a plurality of data lines (eg, D(1) to D(n)), a plurality of pixel units, and a plurality of compensation data lines (eg, P-D(1) to P-D(o)).
  • o, m and n are all natural numbers.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the Scan the drive.
  • the data driver may generate data voltages to be supplied to the data lines D(1) to D(n) using gray values and control signals received from the timing controller.
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D( 1 ) to D(n) in units of pixel unit rows.
  • the data driver may also generate compensation control signals provided to the compensation data lines P-D(1) to P-D(o) using control signals received from the timing controller.
  • the scan driver may generate scan signals to be supplied to the scan lines G( 1 ) to G(m) by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan lines G(1) to G(m).
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal .
  • the pixel array may include a plurality of pixel units (eg, pixel units P11, P12, P21, and P22). Each pixel unit may be connected to a corresponding data line and a corresponding scan line.
  • the pixel unit P11 may be connected to the first data line and the first scan line.
  • one compensation data line is connected to one compensation circuit. However, this embodiment does not limit it. For example, one compensation data line can be connected to multiple compensation circuits.
  • At least one pixel unit includes a main light emitting unit and an auxiliary light emitting unit.
  • At least one compensation circuit includes: a compensation control circuit and a plurality of detection circuits (for example, four detection circuits) connected to the compensation control circuit.
  • the multiple detection circuits of the compensation circuit and the auxiliary light emitting units of the multiple pixel units may be connected in a one-to-one correspondence.
  • the detection circuit is configured to detect the brightness of the connected pixel unit
  • the compensation control circuit is configured to control the auxiliary light-emitting units of the plurality of pixel units to emit light according to the detection result of the connected detection circuit, so as to realize compensation for the light-emitting brightness of the main light-emitting unit.
  • one compensation circuit is connected to four adjacent pixel units (eg, pixel units P11 , P12 , P21 and P22 ).
  • the four detection circuits included in the compensation circuit are connected to the auxiliary light-emitting units of the four pixel units in one-to-one correspondence.
  • the compensation circuit is located in the middle of the four pixel units, the compensation control circuit is located in the middle of the four detection circuits, and the compensation control circuit is close to the detection circuit connected to the pixel unit P11.
  • the arrangement of the compensation circuit in this embodiment can facilitate wiring. However, this embodiment does not limit it.
  • FIG. 3 is a schematic diagram of a circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • Four pixel units are illustrated in FIG. 3 (for example, the i-th row and j-column pixel unit, the i-th row and j+1 column pixel unit, the i+1-th row and j-column pixel unit, and the i+1-th row and j-th pixel unit. +1 column of pixel units), four detection circuits and an equivalent circuit structure of a compensation control circuit.
  • FIG. 4 schematically shows an equivalent circuit structure of a pixel unit (for example, a pixel unit in row i and column j), a detection circuit and a compensation control circuit. Wherein, i and j are both integers.
  • the structure of the pixel unit will be described below by taking the pixel unit in row i and column j as an example.
  • the main light-emitting unit of the i-th row and j-th column of the pixel unit may include: a main driving circuit 11 and a main light-emitting element E1 connected to the main driving circuit 11 .
  • the main driving circuit 11 is configured to receive the data voltage transmitted by the data line D(j) and output a corresponding current to the main light emitting element E1 under the control of the first scanning line GA(i).
  • the main light-emitting element E1 is configured to emit light of corresponding brightness in response to the current output by the main driving circuit 11 of the pixel unit where it is located.
  • the main driving circuit 11 of the pixel unit in the i-th row and j-th column may be a pixel circuit with a 3T1C structure.
  • the main driving circuit 11 includes: a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1.
  • the control electrode of the first transistor T1 is connected to the first scan line GA(i)
  • the first electrode of the first transistor T1 is connected to the data line D(j)
  • the second electrode of the first transistor T1 is connected to the control electrode of the second transistor T2. pole connection.
  • the first pole of the second transistor T2 is connected to the first power line PL1, and the second pole of the second transistor T2 is connected to the first pole of the main light emitting element E1.
  • the control pole of the third transistor T3 is connected to the second scanning line GB(i), the first pole of the third transistor T3 is connected to the second pole of the second transistor T2, and the second pole of the third transistor T3 is connected to the voltage detection circuit .
  • the second pole of the main light emitting element E1 is connected to the second power line PL2.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the second transistor T2, and the second electrode of the first capacitor C1 is connected to the first electrode of the main light emitting element E1.
  • the potential of the first node g is the same as the potential of the control electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the first capacitor C1.
  • the potential of the second node u is the same as the potential of the second pole of the second transistor T2, the second pole of the first capacitor C1, the second pole of the third transistor T3 and the first pole of the main light emitting element E1.
  • the first transistor T1 may also be called an input transistor
  • the second transistor T2 may also be called a driving transistor
  • the third transistor T3 may also be called a sensing transistor.
  • the number of transistors and capacitors included in the main driving circuit is not limited.
  • the first to third transistors T1 to T3 may be N-type transistors. However, this embodiment does not limit it.
  • the auxiliary light-emitting unit of the i-th row and j-th column pixel unit includes: an auxiliary driving circuit 12 and an auxiliary light-emitting element E2 connected to the auxiliary driving circuit 12 .
  • the auxiliary drive circuit 12 is connected to the detection circuit 13 .
  • the auxiliary driving circuit 12 is configured to output a corresponding current to the auxiliary light-emitting element E2 under the control of the detection circuit 13 .
  • the auxiliary light-emitting element E2 is configured to respond to the current output by the auxiliary driving circuit 12 to emit light with a corresponding brightness, so as to compensate the brightness of the main light-emitting unit.
  • the auxiliary driving circuit 12 of the pixel unit in the i-th row and j-th column includes: a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is connected to the detection circuit 13
  • the first electrode of the fourth transistor T4 is connected to the first power line PL1
  • the second electrode of the fourth transistor T4 is connected to the first electrode of the auxiliary light-emitting element E2 .
  • the second pole of the auxiliary light-emitting element E2 is connected to the second power line PL2.
  • the fourth transistor T4 may be a P-type transistor. However, this embodiment does not limit it.
  • the detection circuit 13 is connected to the auxiliary driving circuit 12 and the compensation control circuit 14 of the pixel unit in the i-th row and j-th column.
  • the detection circuit 13 is configured to detect the luminance of the pixel unit in the i-th row and the j-th column, and output the detection result to the auxiliary driving circuit 12 under the control of the compensation control circuit 14, so as to control the auxiliary light-emitting element E2 to emit light with a corresponding brightness.
  • one compensation control circuit 14 is connected to four detection circuits 13 .
  • Four detection circuits 13 and four pixel units that is, the i-th row and j-column pixel unit, the i-th row and j+1 column pixel unit, the i+1-th row and j-column pixel unit, and the i+1-th row and j-th pixel unit +1 row of pixel units) are connected in one-to-one correspondence.
  • the compensation control circuit 14 is also connected to the voltage detection circuit connected to the pixel unit in the i-th row and j-th column.
  • the voltage detection circuit connected to the pixel unit in the i-th row and the j-th column is configured to extract the threshold voltage of the drive transistor of the main drive circuit 11, and is also configured to obtain the detection result of the detection circuit 13, so that the external control circuit determines whether to adjust the compensation circuit according to the result.
  • the connected four pixel units perform brightness compensation.
  • the voltage detection circuits connected to the pixel units except the i-th row and j-th column among the four pixel units are only configured to extract the threshold voltage of the driving transistor of the corresponding main driving circuit to compensate the threshold voltage.
  • the compensation control circuit 14 is also connected to the first scan line GA(i) and the compensation data line P-D(k).
  • the compensation control circuit 14 is configured to control the detection circuit 13 to output the detection result to the correspondingly connected auxiliary driving circuit 12 according to the compensation control signal provided by the compensation data line P-D(k), so that the corresponding auxiliary light-emitting element E2 emits a corresponding brightness according to the detection result of light.
  • the detection circuit 13 connected to the pixel unit in the i-th row and j-th column includes: a fifth transistor T5 , a sixth transistor T6 and a detection element PD.
  • the first electrode of the detection element PD is connected to the second electrode of the sixth transistor T6, and the second electrode of the detection element PD is connected to the second power supply line PL2.
  • Both the control electrode and the first electrode of the sixth transistor T6 are connected to the first power line PL1.
  • the control electrode of the fifth transistor T5 is connected to the compensation control circuit 14
  • the first electrode of the fifth transistor T5 is connected to the second electrode of the sixth transistor T6
  • the second electrode of the fifth transistor T5 is connected to the auxiliary driving circuit 12 .
  • the second pole of the fifth transistor T5 may be connected to the control pole of the fourth transistor T4 of the auxiliary driving circuit 12 .
  • the potential of the third node e is the same as that of the first electrode of the detection element PD, the second electrode of the sixth transistor T6, the first electrode of the fifth transistor T5, and the second electrode of the seventh transistor T7.
  • the fifth transistor T5 and the sixth transistor T6 may be N-type transistors. However, this embodiment does not limit it.
  • the detection element PD may be a PIN type photodiode. Under light conditions, the PIN photodiode can generate a corresponding electrical signal according to the sensed light signal.
  • a PIN-type photodiode may include a stacked second pole (eg, cathode), a photoelectric conversion structure, and a first pole (eg, anode).
  • this embodiment does not limit it.
  • the compensation control circuit 14 includes: a first control subcircuit 141 and a second control subcircuit 142 .
  • the first control sub-circuit 141 is connected to the first scanning line GA(i), the voltage detection circuit connected to the i-th row and the j-th column pixel unit, and the detection circuit 13, and is configured to control the first scanning line GA(i).
  • the detection result of the detection circuit 13 is transmitted to the voltage detection circuit, so that the external control circuit connected to the voltage detection circuit updates the compensation control signal according to the detection result.
  • the second control sub-circuit 142 is connected to the first scanning line GA(i), the compensation data line P-D(k), the second power supply line PL2 and the four detection circuits 13, and is configured to be connected to the first scanning line GA(i). Under control, the compensation control signal provided by the compensation data line P-D(k) is transmitted to the four detection circuits 13, so as to control the four detection circuits 13 to transmit the detection results to the corresponding auxiliary light-emitting units.
  • k is an integer.
  • the detection result of one detection circuit is used to determine whether to perform brightness compensation, and after determining to perform brightness compensation, four auxiliary light-emitting elements can be controlled simultaneously to perform brightness compensation.
  • the first control subcircuit 141 of the compensation control circuit 14 may include: a seventh transistor T7; the second control subcircuit 142 may include: an eighth transistor T8 and a second capacitor C2.
  • the control electrode of the seventh transistor T7 is connected to the first scanning line GA(i), the first electrode of the seventh transistor T7 is connected to a voltage detection circuit, and the second electrode of the seventh transistor T7 is connected to a detection circuit 13 .
  • the control pole of the eighth transistor T8 is connected to the first scanning line GA(i), the first pole of the eighth transistor T8 is connected to the compensation data line P-D(k), and the second pole of the eighth transistor T8 is connected to the four detection circuits 13 connect.
  • the second pole of the second capacitor C2 is connected to the second pole of the eighth transistor T8, and the first pole of the second capacitor C2 is connected to the second power line PL2.
  • the first pole of the seventh transistor T7 is connected to the first pole of the detection element PD of one detection circuit 13 ; the eighth transistor T8 is connected to the control electrodes of the fifth transistor T5 of four detection circuits 13 .
  • the potential of the fourth node r is the same as the potential of the second electrode of the second capacitor C2, the second electrode of the eighth transistor T8, and the control electrodes of the fifth transistor T5 of the four detection circuits.
  • the seventh transistor T7 and the eighth transistor T8 may be N-type transistors. However, this embodiment does not limit it.
  • the first power line PL1 may continuously provide a high-level signal
  • the second power line PL2 may continuously provide a low-level signal.
  • the first transistor T1 to the eighth transistor T8 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • a low temperature polysilicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, and the advantages of both can be utilized, It can achieve high resolution (PPI, Pixel Per Inch), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 5 is a schematic structural diagram of a voltage detection circuit according to at least one embodiment of the present disclosure.
  • the voltage detection circuit may include: a filter amplifier circuit and an analog-to-digital (A/D) conversion circuit.
  • the input terminal Vin of the filter amplifier circuit may be connected to the second pole of the third transistor T3 of the main driving circuit of a pixel unit.
  • the output terminal of the filter amplifier circuit can be connected with the analog-to-digital conversion circuit.
  • the filter amplifier circuit may include: a comparator A, a third capacitor C3, a first resistor R1, a second resistor R2 and a third resistor R3.
  • the first terminal of the first resistor R1 is connected to the input terminal Vin of the filter amplifier circuit, and the second terminal of the first resistor R1 is connected to the first input terminal of the comparator A.
  • a first pole of the third capacitor C3 is connected to the first input terminal of the comparator A, and a second pole of the third capacitor C3 is connected to the ground terminal.
  • the first terminal of the third resistor R3 is connected to the second input terminal of the comparator A, and the second terminal of the third resistor R3 is connected to the ground terminal.
  • the first end of the second resistor R2 is connected to the first input end of the comparator A, and the second end of the second resistor R2 is connected to the output end of the comparator A.
  • the output terminal of the comparator A is connected with the analog-to-digital conversion circuit.
  • the threshold voltage of the driving transistor (that is, the second transistor T2) of the main driving circuit can be extracted .
  • the extracted threshold voltage can be transmitted to the timing controller, and the timing controller uses the threshold voltage to compensate the data voltage, obtains the compensated data signal, and provides the compensated data signal to the data driver, so that the data driver passes the data Lines are provided to pixel units.
  • the main driving circuit and the voltage detection circuit are used to implement threshold compensation through external compensation, so as to improve the display effect.
  • the electrical signal output by the seventh transistor T7 of the compensation control circuit 14 is the electrical signal converted by the detection element PD of the detection circuit 13 according to the received optical signal.
  • a corresponding voltage value can be extracted.
  • the extracted voltage value can be transmitted to the timing controller, and the timing controller can judge whether brightness compensation is required. For example, when the extracted voltage value is inconsistent with the displayed grayscale voltage value of the pixel unit (for example, the mentioned voltage value is greater than the displayed grayscale voltage value), the timing controller determines that brightness compensation needs to be performed on the pixel unit.
  • the timing controller can provide a control signal to the data driver, so that the data driver can provide the compensation control signal to the compensation control circuit through the compensation data line.
  • the compensation control circuit can use the compensation control signal to turn on the fifth transistor T5 of the detection circuit 13, so that the detection circuit 13 uses the detection result to control the auxiliary light-emitting element E2 to emit light with a corresponding brightness.
  • the control electrode of the fourth transistor T4 of the auxiliary driving circuit 12 is controlled by the third node e, and the potential of the third node e is controlled by the detection result of the detection element PD of the detection circuit 13 .
  • FIG. 6 is a working timing diagram of a main driving circuit of a pixel unit according to at least one embodiment of the present disclosure.
  • the main driving circuit of the pixel unit in the i-th row and the j-th column is taken as an example for illustration.
  • the working process of the main driving circuit of the pixel unit in row i and column j includes: an idle phase S1 and a display phase S2 .
  • the threshold compensation operation for a row of pixel units can be completed, for example, the detection of the threshold voltage Vth and the mobility of the driving transistor of the main driving circuit of a row of pixel units can be completed,
  • the display is completed by obtaining the compensated data signal using the detected data in the display stage S1.
  • the idle phase S1 includes a first phase S11 and a second phase S12 .
  • the first scan line GA(i) and the second scan line GB(i) provide a high level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the first transistor T1 is turned on to transmit the data voltage provided by the data line D(j) to the first node g, so that the potential of the first node g is the data voltage Vdata.
  • the third transistor T3 is turned on to transmit the reset voltage to the second node u, so that the potential of the second node u is the reset voltage Vref.
  • the second transistor T2 is turned on.
  • the first power line PL1 charges the second node u through the second transistor T2.
  • the voltage detection circuit may store the potential of the second node u.
  • the first scan line GA(i) and the second scan line GB(i) provide a low level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second transistor T2 is turned on, and after the second node u is charged to Vdata-Vth, the second transistor T2 is turned off.
  • Vth is the threshold voltage of the second transistor T2.
  • the voltage Vdata-Vth of the second node u can be read by using the voltage detection circuit, since the data voltage Vdata is known, the threshold voltage Vth of the second transistor T2 can be obtained accordingly, and the threshold voltage Vth It is stored for subsequent use in threshold compensation.
  • the process of extracting the threshold voltage of the driving transistor (ie, the second transistor) of the main driving circuit is performed in an idle phase, for example, it may be performed before the display device is started, or it may be performed after the display device is turned off.
  • this embodiment does not limit it.
  • the timing controller may determine the compensated data voltage according to the stored and extracted threshold voltage of the driving transistor and the data voltage Vdata' as Vdata'+Vth, and provide the compensated data voltage to the pixel unit through the data driver and the data line.
  • the first scanning line GA(i) provides a high-level signal
  • the first transistor T1 is turned on, and the data voltage provided by the data line D(j) transmitted to the first node g, so that the potential of the first node g is Vdata'+Vth.
  • the second scan line GB(i) provides a low level signal
  • the third transistor T3 is turned off.
  • the first scan line GA(i) and the second scan line GB(i) provide a low-level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second transistor T2 is turned on.
  • the first power line PL1 supplies a driving current to the second node u through the second transistor T2.
  • the driving current flowing through the main light emitting element E1 can be:
  • K is a constant related to the process parameters and geometric dimensions of the driving transistor; Vdata' is the data voltage; Vdd is the first power supply voltage provided by the first power line PL1.
  • the driving current of the main light emitting element has nothing to do with the threshold voltage of the second transistor T2, so that the stable display of the main light emitting element can be ensured.
  • This example enables external compensation of the threshold voltage.
  • the detection circuit connected to the pixel unit is configured to detect the luminance of the corresponding pixel unit, and transmit the detection result to the voltage detection circuit during the display phase.
  • FIG. 7 is a working timing diagram of the compensation control circuit according to at least one embodiment of the present disclosure.
  • the compensation control circuit 14 can extract the detection result in a frame display stage (that is, the brightness detection stage S21), and control the auxiliary light-emitting element E2 to emit light in a subsequent frame display stage. To perform brightness compensation (that is, the brightness compensation stage S22).
  • the first scanning line GA(i) provides a high-level signal
  • the seventh transistor T7 and the eighth transistor T8 of the compensation control circuit 14 are turned on.
  • the detection element PD of the detection circuit 13 senses the optical signal emitted by the pixel unit in the i-th row and the j-th column, and converts the optical signal into an electrical signal. Wherein, the higher the brightness of the light signal sensed by the detection element PD is, the lower the potential of the third node e is.
  • the seventh transistor T7 is turned on, and the voltage detection circuit can extract the voltage value of the third node e and provide it to the timing controller.
  • the timing controller can judge whether brightness compensation needs to be performed on the pixel unit according to the voltage value of the third node e.
  • the first scanning line GA(i) provides a high-level signal
  • the second scanning line GB(i) provides a low-level signal. Therefore, when the seventh transistor T7 is turned on, the main The third transistor T3 of the driving circuit 11 is turned off, and the main driving circuit 11 will not affect the extraction of the voltage value of the third node e by the voltage detection circuit.
  • the compensation data line P-D(k) provides a low-level signal
  • the eighth transistor T8 is turned on, so that the fourth node r is at a low potential
  • the fifth transistor T5 of the detection circuit 13 is turned off, and the auxiliary light-emitting element E2 Does not shine.
  • the timing controller determines that brightness compensation needs to be performed, and provides a compensation control signal that is a high-level signal in the next scanning stage to the compensation data line P-D(k) through the data driver.
  • the timing controller can provide a compensation control signal of a low-level signal to the compensation data line P-D(k) through the data driver, so that the compensation control circuit 14
  • the eighth transistor T8 is turned off, that is, no brightness compensation is performed.
  • the first scan line GA(i) provides a high-level signal
  • the seventh transistor T7 and the eighth transistor T8 are turned on.
  • the compensation data line P-D(k) provides a high-level signal, and writes a high-level signal to the fourth node r, so that the fifth transistor T5 is turned on.
  • the potential of the gate electrode of the fourth transistor T4 is controlled by the third node e. In this way, the luminance of the auxiliary light-emitting element E2 can be controlled according to the real-time detection result of the detection element PD, so as to provide real-time variable compensation luminance.
  • the potential of the control electrode of the fourth transistor T4 of the auxiliary driving circuit 12 is controlled by the detection element PD.
  • the lower the brightness of the light signal detected by the detection element PD is, the lower the brightness to be compensated is.
  • the lower the brightness of the optical signal detected by the detection element PD is, the greater the resistance value of the detection element PD is, and the higher the voltage value of the third node e is, the smaller the gate-source voltage difference Vgs of the fourth transistor T4 is, which is provided to the auxiliary light emission
  • the drive current of element E2 is smaller.
  • the brightness of the auxiliary light-emitting element E2 in this example conforms to the trend that the lower the grayscale display, the lower the brightness needs to be compensated.
  • the luminance to be compensated by a pixel unit is associated with the luminance displayed by the pixel unit, the lower the luminance displayed by the pixel unit, the lower the luminance to be compensated.
  • FIG. 8 is a working timing diagram of the compensation control circuit in the multi-frame display stage according to at least one embodiment of the present disclosure.
  • the display substrate detects the luminance of the pixel units through the detection element PD, and determines that a plurality of pixel units need to perform luminance according to the detection result. compensate.
  • a high-level signal is provided through the compensation data line P-D(k) to control multiple auxiliary light-emitting elements E2 to emit light according to the detection results of the corresponding detection elements PD, so as to realize brightness compensation.
  • the detection result of the detection element PD can be reused to determine whether to perform brightness compensation.
  • This embodiment does not limit the time point of brightness detection and the time point of brightness compensation.
  • the display substrate provided in this exemplary embodiment utilizes the detection element to perform brightness detection, and controls the auxiliary light-emitting element to provide corresponding compensation brightness according to the detection result, so as to improve the brightness attenuation caused by the temperature rise of the display substrate.
  • the display substrate includes: a substrate, a circuit structure layer disposed on the substrate, and a plurality of light emitting diode chips.
  • the circuit structure layer may include: a compensation circuit, a main driving circuit and an auxiliary driving circuit of the pixel unit.
  • At least one light emitting diode chip may include a main light emitting element and an auxiliary light emitting element of a pixel unit.
  • Each of the main light-emitting element and the auxiliary light-emitting element includes: a first semiconductor layer, a quantum well layer (MQW, Multiple Quantum Well) and a second semiconductor layer stacked in sequence. The doping types of the first semiconductor layer and the second semiconductor layer are different.
  • the light emitting diode chip may be a submillimeter light emitting diode (Mini LED) chip, or may be a micro light emitting diode (Micro LED) chip.
  • the light emitting diode chip may be in a front-mount structure, a vertical structure, or a flip-chip structure. However, this embodiment does not limit it.
  • FIG. 9A is a schematic plan view of an LED chip in at least one embodiment of the present disclosure.
  • Fig. 9B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 9A.
  • 10A is a schematic plan view of a light emitting diode chip after forming a second semiconductor layer according to at least one embodiment of the present disclosure.
  • Fig. 10B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 10A.
  • 11A is a schematic plan view of a light emitting diode chip after forming a first insulating layer according to at least one embodiment of the present disclosure.
  • Fig. 11B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 11A.
  • FIG. 12A is a schematic plan view of a light emitting diode chip after forming a via electrode layer according to at least one embodiment of the present disclosure.
  • Fig. 12B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 12A.
  • 13A is a schematic plan view of an LED chip after forming an encapsulation layer according to at least one embodiment of the present disclosure.
  • Fig. 13B is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 13A.
  • the structure of the light emitting diode chip is a flip-chip structure as an example for illustration.
  • the LED chip may include: a substrate 30 , and a main light emitting element E1 and an auxiliary light emitting element E2 located on the same side of the substrate 30 . That is, the main light emitting element E1 and the auxiliary light emitting element E2 belong to the same light emitting diode chip.
  • the main light emitting element E1 includes a first semiconductor layer 311 , a quantum well layer 321 and a second semiconductor layer 331 stacked in sequence.
  • the auxiliary light-emitting element E2 includes a first semiconductor layer 312 , a quantum well layer 322 and a second semiconductor layer 332 stacked in sequence.
  • the first semiconductor layer 311 of the main light emitting element E1 may be in direct contact with the quantum well layer 321 , and the quantum well layer 321 may be in direct contact with the second semiconductor layer 331 .
  • the first semiconductor layer 312 of the auxiliary light-emitting element E2 may be in direct contact with the quantum well layer 322 , and the quantum well layer 322 may be in direct contact with the second semiconductor layer 332 .
  • the first semiconductor layer 311 of the main light-emitting element E1 and the first semiconductor layer 312 of the auxiliary light-emitting element E2 may have an integrated structure. There is a gap between the quantum well layer 321 of the main light emitting element E1 and the quantum well layer 322 of the auxiliary light emitting element E2.
  • the main light-emitting element E1 and the auxiliary light-emitting element E2 are set independently of each other, so as to facilitate flexible control of the light-emitting states of the main light-emitting element E1 and the auxiliary light-emitting element E2.
  • the light-emitting region of the main light-emitting element E1 is the overlapping region of the first semiconductor layer 311 , the quantum well layer 321 and the second semiconductor layer 331 in the stacking direction, and the first The area of the overlapping region of the semiconductor layer 311 , the quantum well layer 321 and the second semiconductor layer 331 in the stacking direction is the light emitting area of the main light emitting element E1 .
  • the light-emitting region of the auxiliary light-emitting element E2 is the overlapping region of the first semiconductor layer 312, the quantum well layer 322 and the second semiconductor layer 332 in the lamination direction, and the first semiconductor layer 312, the quantum well layer 322 and the second semiconductor layer 332 are in the lamination direction.
  • the area of the overlapping region of is the light emitting area of the auxiliary light emitting element E2.
  • the light emitting area of the main light emitting element E1 is larger than the light emitting area of the auxiliary light emitting element E2.
  • the light-emitting areas of the main light-emitting element E1 and the auxiliary light-emitting element E2 are smaller than the overall area of the LED chip, so that the current density passing through the main light-emitting element E1 and the auxiliary light-emitting element E2 can be increased, and the luminous efficiency can be improved.
  • the LED chip further includes: a via electrode layer and a binding electrode layer.
  • the via electrode layer is located on a side of the second semiconductor layer away from the substrate 30
  • the bonding electrode layer is located on a side of the via electrode layer away from the substrate 30 .
  • a first insulating layer 36 is disposed between the second semiconductor layer and the via electrode layer, and a second insulating layer 37 and an encapsulation layer 38 are disposed between the via electrode layer and the bonding electrode layer.
  • the encapsulation layer 38 is located on a side of the second insulating layer 37 away from the via electrode layer.
  • the via electrode layer includes: a first via electrode 341 and a second via electrode 342 .
  • the first transfer electrode 341 is connected to the second main semiconductor layer 331 of the main light emitting element E1 through the first via hole K1 opened on the first insulating layer 36
  • the second transfer electrode 342 is connected to the second main semiconductor layer 331 of the main light emitting element E1 through the first via hole K1 opened on the first insulating layer 36
  • the second via hole K2 is connected to the second auxiliary semiconductor layer 332 of the auxiliary light-emitting element E2.
  • the binding electrode layer includes: a first binding electrode 353 , and second binding electrodes 351 and 352 .
  • the second binding electrode 351 is connected to the first transfer electrode 341 through the third via hole K3
  • the second binding electrode 352 is connected to the second transfer electrode 342 through the fourth via hole K4
  • the first binding electrode 353 is connected to the second transfer electrode 342 through the fourth via hole K4.
  • the five vias K5 are connected to the first semiconductor layer.
  • the light-emitting diode chip includes the main light-emitting element E1 and the auxiliary light-emitting element E2 that can emit light independently, which can reduce the current density flowing through the main light-emitting element E1 and the auxiliary light-emitting element E2, which is beneficial to improve the heat accumulation. Phenomenon.
  • FIG. 14 is a schematic partial cross-sectional view of a circuit structure layer of a display substrate according to at least one embodiment of the present disclosure.
  • a detection element PD and a transistor are taken as an example for illustration.
  • the circuit structure layer may include: a light-shielding layer, a third semiconductor layer, a first conductive layer, The second conductive layer, the third conductive layer, the photoelectric conversion layer and the fourth conductive layer.
  • a third insulating layer 41 may be provided between the substrate 40 and the light shielding layer, a fourth insulating layer 42 may be provided between the light shielding layer and the third semiconductor layer, and a fifth insulating layer may be provided between the third semiconductor layer and the first conductive layer. 43.
  • a sixth insulating layer 44 may be provided between the first conductive layer and the second conductive layer, a seventh insulating layer 45 may be provided between the second conductive layer and the third conductive layer, and a seventh insulating layer 45 may be provided between the photoelectric conversion layer and the fourth conductive layer.
  • An eighth insulating layer 46 may be provided.
  • a pixel definition layer 47 may be provided on the side of the fourth conductive layer away from the substrate 40 .
  • the third insulating layer 41 to the seventh insulating layer 45 may be inorganic insulating layers, and the eighth insulating layer 46 may be an organic insulating layer. However, this embodiment does not limit it.
  • the light shielding layer may include a light shielding electrode 50 .
  • the third semiconductor layer at least includes: a first active layer 51 .
  • the orthographic projection of the light-shielding electrode 50 on the substrate 40 may cover the orthographic projection of the first active layer 51 on the substrate 40 to avoid the influence of external light on the active layer.
  • the first conductive layer at least includes: a first gate electrode 52 and a first electrode of a capacitor (not shown).
  • the second conductive layer at least includes: a second electrode of the capacitor (not shown).
  • the third conductive layer at least includes: a first source electrode 53 , a first drain electrode 54 , and a first electrode 61 of the detection element.
  • the photoelectric conversion layer includes: a photoelectric conversion structure 62 of a detection element.
  • the fourth conductive layer includes: the second pole 63 of the detection element.
  • the transistor shown in FIG. 14 may include: a first active layer 51 , a first gate electrode 52 , a first source electrode 53 and a first drain electrode 54 .
  • the detection element may include: a first pole 61 , a photoelectric conversion structure 62 and a second pole 63 stacked in sequence.
  • the first electrode 61 of the detection element and the first drain electrode 54 of the connected transistor may be integrally structured. However, this embodiment does not limit it.
  • the structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate.
  • the “patterning process” mentioned in this disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the projection of A includes the projection of B means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.
  • the manufacturing process of the light emitting diode chip may include the following operations, as shown in FIGS. 9A to 13B .
  • a first semiconductor layer, a quantum well layer and a second semiconductor layer are sequentially formed on the substrate 30 , as shown in FIG. 10A and FIG. 10B .
  • a first semiconductor film is formed on one side of the substrate 30, and the first semiconductor film is patterned to form the first semiconductor layer 311 of the main light-emitting element E1 and the first semiconductor layer of the auxiliary light-emitting element E2.
  • the first semiconductor layer 311 of the main light emitting element E1 and the first semiconductor layer 312 of the auxiliary light emitting element E2 are integrally structured.
  • the quantum well layer 321 of the main light-emitting element E1 and the quantum well layer 322 of the auxiliary light-emitting element E2 are formed on the side of the first semiconductor layer away from the substrate 30 .
  • the second semiconductor layer 331 of the main light-emitting element E1 and the second semiconductor layer 332 of the auxiliary light-emitting element E2 are formed on the side of the quantum well layer away from the substrate 30 .
  • the substrate 30 may be a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, a silicon substrate, a silicon carbide substrate, a sapphire substrate, or the like.
  • GaP gallium phosphide
  • GaAs gallium arsenide
  • silicon substrate silicon carbide substrate
  • sapphire substrate sapphire substrate
  • the material of the quantum well layer may include gallium nitride (GaN).
  • the doping types of the first semiconductor layer and the second semiconductor layer may be different.
  • the material of the first semiconductor layer may be an N-type semiconductor material
  • the material of the second semiconductor layer may be a P-type semiconductor material.
  • the material of the first semiconductor layer may be a P-type semiconductor material
  • the material of the second semiconductor layer may be an N-type semiconductor material.
  • the intrinsic semiconductor material in the first semiconductor layer and the second semiconductor layer may be the same, and the intrinsic semiconductor material may be any one of GaN, GaP, aluminum gallium arsenide (AlGaAs) and aluminum gallium indium phosphide (AlGaInP) .
  • the thicknesses of the first semiconductor layer, the multi-quantum well layer and the second semiconductor layer can be set according to actual needs, and are not limited herein.
  • a first insulating film is formed on the side of the second semiconductor layer away from the substrate 30, and the first insulating film is patterned to form the first insulating layer 36, as shown in FIG. 11A and FIG. 11B .
  • a first via hole K1 and a second via hole K2 are opened on the first insulating layer 36 .
  • the first insulating layer 36 in the first via hole K1 is etched away, exposing the surface of the second semiconductor layer 331, and the first insulating layer 36 in the second via hole K2 is etched away, exposing the second semiconductor layer 332 surface.
  • Orthographic projections of the first via hole K1 and the second via hole K2 on the substrate 30 may be rectangular. However, this embodiment is not limited to this.
  • a via electrode film is formed on the side of the first insulating layer 36 away from the substrate 30, and the via electrode film is patterned to form a via electrode layer, as shown in FIG. 12A and FIG. 12B .
  • the via electrode layer includes: a first via electrode 341 and a second via electrode 342 .
  • the first transfer electrode 341 is connected to the second semiconductor layer 331 of the main light emitting element E1 through the first via hole K1
  • the second transfer electrode 342 is connected to the second semiconductor layer 332 of the auxiliary light emitting element E2 through the second via hole K2.
  • a second insulating layer 37 and an encapsulation layer 38 are sequentially formed on the side of the via electrode layer away from the substrate 30 , as shown in FIGS. 13A and 13B .
  • the second insulating layer 37 is provided with a first sub-via hole, a second sub-via hole and a third sub-via hole
  • the packaging layer 38 is provided with a fourth sub-via hole corresponding to the first sub-via hole and a The fifth sub-via corresponding to the via hole and the sixth sub-via corresponding to the third sub-via.
  • the first sub-via and the fourth sub-via form the third via K3, the second sub-via and the fifth sub-via form the fourth via K4, and the third sub-via and the sixth sub-via form the fifth via.
  • the third via hole K3 exposes the surface of the first via electrode 341
  • the fourth via hole K4 exposes the surface of the second via electrode 342
  • the fifth via hole K5 exposes the surface of the first semiconductor layer.
  • Orthographic projections of the third via hole K3 , the fourth via hole K4 and the fifth via hole K5 on the substrate 30 may be rectangular. However, this embodiment does not limit it.
  • a metal thin film is formed on the side of the encapsulation layer 38 away from the substrate 30 , and the metal thin film is patterned to form a binding electrode layer, as shown in FIGS. 9A and 9B .
  • the binding electrode layer includes: a first binding electrode 353 , and second binding electrodes 351 and 352 .
  • the second binding electrode 351 is connected to the first transfer electrode 341 through the third via hole K3, the second binding electrode 352 is connected to the second transfer electrode 342 through the fourth via hole K4, and the first binding electrode 353 is connected to the second transfer electrode 342 through the fourth via hole K4.
  • the five vias K5 are connected to the first semiconductor layer.
  • the main light-emitting element E1 can be connected to the main driving circuit through the second binding electrode 351, the auxiliary light-emitting element E2 can be connected to the auxiliary driving circuit through the second binding electrode 352, and the main light-emitting element E1 and the auxiliary light-emitting element E3 can be connected through the first binding electrode.
  • the fixed electrode 353 is connected to the second power line.
  • the first binding electrodes of the main light-emitting element E1 and the auxiliary light-emitting element E2 have an integrated structure. However, this embodiment does not limit it.
  • the orthographic projection of the first semiconductor layer 311 of the main light-emitting element E1 on the substrate 30 includes the orthographic projection of the quantum well layer 321 on the substrate 30, and the orthographic projection of the quantum well layer 321 on the substrate 30 includes Orthographic projection of the second semiconductor layer 331 on the substrate 30 .
  • the orthographic projection of the first semiconductor layer 312 of the auxiliary light-emitting element E2 on the substrate 30 includes the orthographic projection of the quantum well layer 322 on the substrate 30, and the orthographic projection of the quantum well layer 322 on the substrate 30 includes the second semiconductor layer 332 on the substrate 30. Orthographic projection on . In this way, it is convenient to realize the electrical connection between the first binding electrode 353 and the first semiconductor layer.
  • the first insulating layer 36 and the second insulating layer 37 may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) , which can be single layer, multilayer or composite layer.
  • the material of the via electrode layer can be a material with a relatively high light transmittance, for example, indium tin oxide (ITO).
  • the binding electrode layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals , such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc. However, this embodiment does not limit it.
  • a plurality of LED chips may be transferred onto the substrate to realize electrical connection between the LED chips and the circuit structure layer.
  • the bonding electrode layer of the light emitting diode chip faces the circuit structure layer to realize electrical connection with the circuit structure layer, so that the circuit structure layer provides electrical signals to the light emitting diode chip.
  • the structure of the circuit structure layer can be referred to as shown in FIG. 14 , so it will not be repeated here.
  • the base of the light emitting diode chip can be peeled off, so that the light emitting diode chip in the display substrate is only Including main light-emitting element and auxiliary light-emitting element.
  • this embodiment does not limit it.
  • the substrate may remain after bonding the light emitting diode chip with the circuit structure layer.
  • FIG. 15 is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate includes: a timing controller, a data driver, a scan driver, a light emitting driver, a pixel array, and a plurality of compensation circuits.
  • the pixel array may include a plurality of scan lines (eg, G(1) to G(m)), a plurality of data lines (eg, D(1) to D(n)), a plurality of pixel units, and a plurality of light emission control lines (eg, EM(1) to EM(m)).
  • m and n are both natural numbers.
  • the compensation circuit may include a detection circuit.
  • the detection circuit is configured to detect the temperature of the pixel unit.
  • one detection circuit can be connected with auxiliary light emitting units of four pixel units.
  • this embodiment does not limit it.
  • FIG. 16 is a schematic structural diagram of a main driving circuit according to at least one embodiment of the present disclosure.
  • the main driving circuit includes: a data writing subcircuit, a driving subcircuit, a threshold compensation subcircuit, a storage subcircuit, an initialization subcircuit and a light emission control subcircuit.
  • the data writing subcircuit is connected to the third scanning line G, the data line D and the fifth node a, and is configured to write data into the storage subcircuit under the control of the third scanning line G
  • Line D provides the data signal.
  • the storage subcircuit is connected to the fifth node a and the sixth node b.
  • the driving sub-circuit is connected to the sixth node b, the first power line PL1 and the first pole of the main light emitting element E1, configured to output a driving current to the main light emitting element E1 under the control of the sixth node b.
  • the threshold compensation subcircuit is connected to the third scanning line G, the sixth node b and the first pole of the main light emitting element E1, configured to compensate the threshold voltage of the driving subcircuit under the control of the third scanning line G.
  • the initialization subcircuit is connected to the fifth node a, the initial signal line INT, the first reset line RST1, and the second reset line RST2, and is configured to control the fifth node a under the control of the first reset line RST1 or the second reset line RST2. a to initialize.
  • the light emission control sub-circuit is connected with the light emission control line EM, the second power supply line PL2 and the second pole of the main light emitting element E1, and is configured to conduct the second pole of the main light emitting element E1 and the second pole of the main light emitting element E1 under the control of the light emission control line EM.
  • the first power line PL1 continuously provides a high-level signal
  • the second power line PL2 continuously provides a low-level signal.
  • the first reset line RST1 of the main driver circuit of the i-th row of pixel circuits is connected to the third scanning line G(i+1) connected to the main driver circuit of the i+1-th row of pixel circuits, and the main driver circuit of the i-th row of pixel circuits
  • the second reset line RST2 is connected to the third scanning line G(i-1) connected to the main driving circuit of the i-1th row of pixel circuits.
  • i can be an integer.
  • FIG. 17 is a schematic diagram of a circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a partial circuit structure of a display substrate according to at least one embodiment of the present disclosure.
  • Four pixel units are illustrated in FIG. 17 (for example, the i-th row and j-column pixel unit, the i-th row and j+1 column pixel unit, the i+1-th row and j-column pixel unit, and the i+1-th row and j-th pixel unit. +1 column of pixel units) and a detection circuit.
  • FIG. 18 schematically shows a pixel unit (for example, a pixel unit in row i and column j) and a detection circuit. Wherein, i and j are both integers.
  • the data writing sub-circuit of the main driving circuit 21 of the pixel unit in the i-th row and the j-th column includes: a ninth transistor T9, and the driving control sub-circuit includes a tenth transistor T10,
  • the threshold compensation subcircuit includes an eleventh transistor T11, the light emission control subcircuit includes a twelfth transistor T12, the initialization subcircuit includes a thirteenth transistor T13 and a fourteenth transistor T14, and the storage subcircuit includes a fourth capacitor C4.
  • the control electrode of the ninth transistor T9 is connected to the first scanning line G(i), the first electrode of the ninth transistor T9 is connected to the data line D(j), and the second electrode of the ninth transistor T9 is connected to the fifth node a.
  • the control electrode of the tenth transistor T10 is connected to the sixth node b, the first electrode of the tenth transistor T10 is connected to the first power line PL1, and the second electrode of the tenth transistor T10 is connected to the first electrode of the main light emitting element E1.
  • the control pole of the eleventh transistor T11 is connected to the first scan line G(i), the first pole of the eleventh transistor T11 is connected to the sixth node b, the second pole of the eleventh transistor T11 is connected to the tenth transistor T10 Second pole connection.
  • the control electrode of the twelfth transistor T12 is connected to the light emission control line EM(i), the first electrode of the twelfth transistor T12 is connected to the second electrode of the main light emitting element E1, the second electrode of the twelfth transistor T12 is connected to the second The power line PL2 is connected.
  • the control pole of the thirteenth transistor T13 is connected to the first reset line G(i+1), the first pole of the thirteenth transistor T13 is connected to the initial signal line INT, the second pole of the thirteenth transistor T13 is connected to the fifth node a connection.
  • the control pole of the fourteenth transistor T14 is connected to the second reset line G(i-1), the first pole of the fourteenth transistor T14 is connected to the initial signal line INT, and the second pole of the fourteenth transistor T14 is connected to the fifth node a connection.
  • the potential of the fifth node a is related to the second pole of the ninth transistor T9, the first pole of the fourth capacitor C4, the second pole of the thirteenth transistor T13, and the second pole of the fourteenth transistor T14 same potential.
  • the potential of the sixth node b is the same as the potential of the second electrode of the fourth capacitor C4, the control electrode of the tenth transistor T10 and the first electrode of the eleventh transistor T11.
  • the auxiliary driving circuit 22 of the pixel unit in the i-th row and j-th column includes: a fifteenth transistor T15 .
  • the control electrode of the fifteenth transistor T15 is connected to the main driving circuit 21
  • the first electrode of the fifteenth transistor T15 is connected to the detection circuit 23
  • the second electrode of the fifteenth transistor T15 is connected to the first electrode of the auxiliary light-emitting element E2 .
  • the control electrode of the fifteenth transistor T15 is connected to the sixth node b
  • the first electrode of the fifteenth transistor T15 is connected to the seventh node c.
  • the second pole of the auxiliary light emitting element E2 is connected with the second pole of the main light emitting element E1.
  • the detection circuit 23 includes: a first detection transistor T16 and a second detection transistor T17 . Both the control electrode and the first electrode of the first detection transistor T16 are connected to the first power line PL1, and the second electrode of the first detection transistor T16 is connected to the seventh node c. The control electrode and the first electrode of the second detection transistor T17 are connected to the second power supply line PL2, and the second electrode of the second detection transistor T17 is connected to the seventh node c.
  • the doping types of the first detection transistor T16 and the second detection transistor T17 are opposite.
  • the first detection transistor T16 may be a P-type transistor
  • the second detection transistor T17 may be an N-type transistor.
  • the potential of the seventh node c is the same as the potentials of the second poles of the first detection transistor T16 and the second detection transistor T17 .
  • the seventh node c is connected to the first poles of the fifteenth transistors T15 of the plurality of auxiliary driving circuits 22 .
  • the sixth node b simultaneously controls the driving transistor of the main driving circuit 21 (ie, the tenth transistor T10 ) and the driving transistor of the auxiliary driving circuit 22 (ie, the fifteenth transistor T15 ).
  • the threshold voltages of the two driving transistors can be basically the same.
  • the detection circuit 23 is configured to detect the temperature of a plurality of pixel units.
  • a temperature sensor is formed by connecting a P-type transistor and an N-type transistor in series. Since the leakage current of the P-type transistor increases with temperature, and the leakage current of the N-type transistor changes little with temperature, the potential of the seventh node c increases with temperature. The potential of the seventh node c can be provided to the fifteenth transistor T15 of the auxiliary driving circuit 22 to generate a driving current, so that the driving current passing through the auxiliary light-emitting element E2 becomes larger, so as to realize brightness compensation after temperature rise.
  • FIG. 19 is a working timing diagram of a pixel unit according to at least one embodiment of the present disclosure.
  • the working process of the pixel unit in row i and column j is taken as an example for illustration.
  • the working process of the pixel unit in row i and column j includes the following stages.
  • the second reset line G(i-1) provides a low-level signal
  • the fourteenth transistor T14 is turned on
  • the initial voltage provided by the initial signal line INT is provided to the fifth node a, that is, the fourth capacitor C4
  • the first scanning line G(i), the first reset line G(i+1) and the light emitting control line EM(i) provide high-level signals
  • the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12 and The fourteenth transistor T14 is turned off.
  • the first scanning line G(i) provides a low level signal
  • the ninth transistor T9 and the eleventh transistor T11 are turned on.
  • the ninth transistor T9 is turned on, so that the data voltage output by the data line D(j) is provided to the fifth node a, and the potential of the fifth node a is the data voltage Vdata.
  • the eleventh transistor T11 is turned on to charge the first power voltage Vdd provided by the first power line PL1 and the threshold voltage Vth of the tenth transistor T10 into the sixth node b, so that the potential of the sixth node b is Vdd+Vth.
  • the light-emitting control line EM(i) and the first reset line G(i+1) provide a low-level signal, and the twelfth transistor T12 and the thirteenth transistor T13 are turned on.
  • the tenth transistor T10 can provide driving current to the main light emitting element E1.
  • the driving current flowing through the main light emitting element E1 can be:
  • K is a fixed constant related to the process parameters and geometric dimensions of the driving transistor; Vdata is the data voltage, and Vint is the initial voltage provided by the initial signal line.
  • the driving current of the main light emitting element E1 has nothing to do with the threshold voltage of the tenth transistor T10 , so that the stable display of the main light emitting element E1 can be ensured.
  • This example enables internal compensation of the threshold voltage.
  • the auxiliary driving circuit 22 may provide driving current to the auxiliary light-emitting element E2 according to the potential of the seventh node c, so as to perform brightness compensation for the main light-emitting element E1.
  • the detection result of the detection circuit 23 can control the light-emitting brightness of the auxiliary light-emitting element E2, so that the light-emitting brightness of the auxiliary light-emitting element E2 can compensate the brightness loss caused by the temperature rise.
  • FIG. 20 is a flowchart of a brightness compensation method for a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 20 , the brightness compensation method of this embodiment is applied to the above-mentioned display substrate.
  • the brightness compensation method comprises the following steps:
  • Step 801 the compensation circuit detects the brightness or temperature of at least one pixel unit
  • Step 802 the compensation circuit controls the auxiliary light-emitting unit of the at least one pixel unit to emit light according to the detection result.
  • FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 21 , this embodiment provides a display device 91 including the display substrate 910 of the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate or a QLED display substrate.
  • the display device 91 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit it.

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Abstract

一种显示基板（910），包括：多个像素单元（P11，P12，P21，P22）和至少一个补偿电路。至少一个像素单元（P11，P12，P21，P22）包括：主发光单元和辅发光单元；至少一个补偿电路与至少一个像素单元（P11，P12，P21，P22）的辅发光单元连接。至少一个补偿电路配置为检测至少一个像素单元（P11，P12，P21，P22）的亮度或温度，并控制至少一个像素单元（P11，P12，P21，P22）的辅发光单元根据检测结果发光。

Description

显示基板及其亮度补偿方法、显示装置
本申请要求于2021年7月20日提交中国专利局、申请号为202110818829.2、发明名称为“显示基板及其亮度补偿方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其亮度补偿方法、显示装置。
背景技术
发光二极管(LED，Light Emitting Diode)因具有高效率、高亮度、高可靠度、节能及反应速度快等诸多优点，被较为广泛地应用在传统显示、近眼显示、三维(3D)显示以及透明显示等领域中。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其亮度补偿方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：多个像素单元和至少一个补偿电路。至少一个像素单元包括：主发光单元和辅发光单元；至少一个补偿电路与至少一个像素单元的辅发光单元连接。至少一个补偿电路配置为检测至少一个像素单元的亮度或温度，并控制至少一个像素单元的辅发光单元根据检测结果发光。
在一些示例性实施方式中，所述补偿电路包括：补偿控制电路以及与所述补偿控制电路连接的至少一个检测电路；所述检测电路与一个像素单元的辅发光单元连接。所述检测电路配置为检测所连接的像素单元的亮度。所述补偿控制电路，配置为控制所述检测电路所连接的辅发光单元根据所述检测 电路的检测结果发光。
在一些示例性实施方式中，所述补偿控制电路，包括：第一控制子电路和第二控制子电路。所述第一控制子电路，与第一扫描线、一个电压检测电路以及一个检测电路连接，配置为在所述第一扫描线的控制下，将所述检测电路的检测结果传输至所述电压检测电路，以使所述电压检测电路连接的外部控制电路根据所述检测结果更新补偿控制信号。所述第二控制子电路，与所述第一扫描线、补偿数据线、第二电源线以及至少一个检测电路连接，配置为在所述第一扫描线的控制下，将所述补偿数据线提供的所述补偿控制信号传输给所述至少一个检测电路，以控制所述至少一个检测电路将所述检测结果传输给对应的辅发光单元。
在一些示例性实施方式中，所述第一控制子电路包括：第七晶体管；所述第二控制子电路包括：第八晶体管和第二电容。所述第七晶体管的控制极与所述第一扫描线连接，所述第七晶体管的第一极与所述电压检测电路连接，所述第七晶体管的第二极与所述检测电路连接。所述第八晶体管的控制极与所述第一扫描线连接，所述第八晶体管的第一极与所述补偿数据线连接，所述第八晶体管的第二极与所述第二电容的第二极连接，所述第二电容的第一极与所述第二电源线连接。所述第八晶体管的第二极与所述至少一个检测电路连接。
在一些示例性实施方式中，所述检测电路包括：检测元件、第五晶体管和第六晶体管。所述检测元件的第一极与所述第六晶体管的第二极连接，所述检测元件的第二极与第二电源线连接；所述第六晶体管的控制极和第一极与第一电源线连接；所述第五晶体管的控制极和所述补偿控制电路连接，所述第五晶体管的第一极与所述检测元件的第一极连接，所述第五晶体管的第二极与所述辅发光单元连接。
在一些示例性实施方式中，所述主发光单元包括：主发光元件以及与所述主发光元件连接的主驱动电路。所述主驱动电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容；所述第一晶体管的控制极与第一扫描线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述第二晶体管的控制极连接；所述第二晶体管的第一极与第一电源线连接， 所述第二晶体管的第二极与所述第三晶体管的第一极连接；所述第三晶体管的控制极与第二扫描线连接，所述第三晶体管的第二极与电压检测电路连接；所述第一电容的第一极与所述第二晶体管的控制极连接，所述第一电容的第二极与所述第二晶体管的第二极连接。所述主发光元件的第一极与所述第二晶体管的第二极连接，所述主发光元件的第二极与第二电源线连接。
在一些示例性实施方式中，所述辅发光单元包括：辅发光元件以及与所述辅发光元件连接的辅驱动电路。所述辅驱动电路包括：第四晶体管；所述第四晶体管的控制极与所述检测电路连接，所述第四晶体管的第一极与第一电源线连接，所述第四晶体管的第二极与所述辅发光元件的第一极连接；所述辅发光元件的第二极与第二电源线连接。
在一些示例性实施方式中，所述补偿电路包括：一个检测电路，所述检测电路与至少一个像素单元的辅发光单元连接。所述检测电路配置为检测所述至少一个像素单元的温度，并控制所述至少一个像素单元的辅发光单元根据检测结果发光。
在一些示例性实施方式中，所述检测电路包括：第一检测晶体管和第二检测晶体管。所述第一检测晶体管的控制极和第一极与第一电源线连接，所述第一检测晶体管的第二极与所述第二检测晶体管的第二极连接，并与至少一个像素单元的辅发光单元连接；所述第二检测晶体管的控制极和第一极与第二电源线连接。所述第一检测晶体管和第二检测晶体管的掺杂类型相反。
在一些示例性实施方式中，所述主发光单元包括：主发光元件以及与所述主发光元件连接的主驱动电路。所述主驱动电路包括：数据写入子电路、驱动子电路、阈值补偿子电路、存储子电路、初始化子电路和发光控制子电路。所述数据写入子电路，与第三扫描线、数据线和第五节点连接，配置为在所述第三扫描线的控制下，向所述存储子电路写入所述数据线提供的数据信号。所述存储子电路，与所述第五节点和第六节点连接。所述驱动子电路，与所述第六节点、第一电源线和所述主发光元件的第一极连接，配置为在所述第六节点的控制下，向所述主发光元件输出驱动电流。所述阈值补偿子电路，与所述第三扫描线、所述第六节点和所述主发光元件的第一极连接，配置为在所述第三扫描线的控制下，对所述驱动子电路的阈值电压进行补偿。 所述初始化子电路，与所述第五节点、初始信号线、第一复位线、第二复位线连接，配置为在所述第一复位线或第二复位线的控制下，对所述第五节点进行初始化。所述发光控制子电路，与发光控制线、第二电源线和所述主发光元件的第二极连接，配置为在所述发光控制线的控制下，导通所述主发光元件的第二极和所述第二电源线。
在一些示例性实施方式中，所述数据写入子电路，包括：第九晶体管；所述驱动子电路包括：第十晶体管；所述阈值补偿子电路包括：第十一晶体管；所述存储子电路包括：第四电容。所述发光控制子电路包括：第十二晶体管。所述初始化子电路包括：第十三晶体管和第十四晶体管。所述第九晶体管的控制极与第三扫描线连接，所述第九晶体管的第一极与数据线连接，所述第九晶体管的第二极与所述第五节点连接。所述第十晶体管的控制极与所述第五节点连接，所述第十晶体管的第一极与所述第一电源线连接，所述第十晶体管的第二极与所述主发光元件的第一极连接。所述第十一晶体管的控制极与所述第三扫描线连接，所述第十一晶体管的第一极与所述第六节点，所述第十一晶体管的第二极与所述第十晶体管的第二极连接。所述第十二晶体管的控制极与所述发光控制线连接，所述第十二晶体管的第一极与所述主发光元件的第二极连接，所述第十二晶体管的第二极与所述第二电源线连接。所述第十三晶体管的控制极与所述第一复位线连接，所述第十三晶体管的第一极与所述初始信号线连接，所述第十三晶体管的第二极与所述第五节点连接。所述第十四晶体管的控制极与所述第二复位线连接，所述第十四晶体管的第一极与所述初始信号线连接，所述第十四晶体管的第二极与所述第五节点连接。所述第四电容的第一极与所述第五节点连接，所述第四电容的第二极与所述第六节点连接。
在一些示例性实施方式中，所述辅发光单元包括：辅发光元件以及与所述辅发光元件和主驱动电路连接的辅驱动电路。所述辅驱动电路包括：第十五晶体管。所述第十五晶体管的控制极与所述第六节点连接，所述第十五晶体管的第一极与所述检测电路连接，所述第十五晶体管的第二极与所述辅发光元件的第一极连接。所述辅发光元件的第二极与所述主发光元件的第二极连接。
在一些示例性实施方式中，所述主发光单元包括主发光元件和主驱动电路；所述辅发光单元包括辅发光元件和辅驱动电路；所述主发光元件和辅发光元件均为微发光元件；所述主发光元件的发光面积大于所述辅发光元件的发光面积。
在一些示例性实施方式中，所述显示基板包括：衬底、设置在所述衬底上的电路结构层和多个发光二极管芯片；所述电路结构层包括：所述补偿电路以及所述像素单元的主驱动电路和辅驱动电路；至少一个发光二极管芯片包括：所述像素单元的主发光元件和辅发光元件。所述主发光元件和辅发光元件各自包括：依次层叠的第一半导体层、量子阱层和第二半导体层；所述第一半导体层和第二半导体层的掺杂类型不同。所述主发光元件和辅发光元件还各自包括：第一绑定电极和第二绑定电极中的至少一者。所述主发光元件的第一绑定电极与主发光元件的第一半导体层连接，所述主发光元件的第二绑定电极与主发光元件的第二半导体层连接。所述辅发光元件的第一绑定电极与辅发光元件的第一半导体层连接，所述辅发光元件的第二绑定电极与辅发光元件的第二半导体层连接。
在一些示例性实施方式中，所述主发光元件的第一半导体层和所述辅发光元件的第一半导体层为一体结构，并与同一个第一绑定电极连接。
在一些示例性实施方式中，所述发光二极管芯片还包括基底，所述主发光元件和辅发光元件位于所述基底的同一侧。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的亮度补偿方法，应用于如上所述的显示基板，所述亮度补偿方法包括：补偿电路检测至少一个像素单元的亮度或温度；所述补偿电路控制所述至少一个像素单元的辅发光单元根据检测结果发光。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与 本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为LED的发光效率和流经该LED的电流密度的关系示意图；
图2为本公开至少一实施例的显示基板的结构示意图；
图3为本公开至少一实施例的显示基板的电路结构示意图；
图4为本公开至少一实施例的显示基板的局部电路结构示意图；
图5为本公开至少一实施例的电压检测电路的结构示意图；
图6为本公开至少一实施例的像素单元的主驱动电路的工作时序图；
图7为本公开至少一实施例的补偿控制电路的工作时序图；
图8为本公开至少一实施例的补偿控制电路在多帧显示阶段的工作时序图；
图9A本公开至少一实施例中的发光二极管芯片的平面示意图；
图9B为图9A中沿Q-Q’方向的局部剖面示意图；
图10A为本公开至少一实施例形成第二半导体层后的发光二极管芯片的平面示意图；
图10B为图10A中沿Q-Q’方向的局部剖面示意图；
图11A为本公开至少一实施例形成第一绝缘层后的发光二极管芯片的平面示意图；
图11B为图11A中沿Q-Q’方向的局部剖面示意图；
图12A为本公开至少一实施例形成转接电极层后的发光二极管芯片的平面示意图；
图12B为图12A中沿Q-Q’方向的局部剖面示意图；
图13A为本公开至少一实施例形成封装层后的发光二极管芯片的平面示意图；
图13B为图13A中沿Q-Q’方向的局部剖面示意图；
图14为本公开至少一实施例的显示基板的电路结构层的局部剖面示意图；
图15为本公开至少一实施例的显示基板的另一结构示意图；
图16为本公开至少一实施例的像素单元的主驱动电路的结构示意图；
图17为本公开至少一实施例的显示基板的电路结构示意图；
图18为本公开至少一实施例的显示基板的局部电路结构示意图；
图19为本公开至少一实施例的像素单元的工作时序图；
图20为本公开至少一实施例的显示基板的亮度补偿方法的流程图；
图21为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定 的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
图1为LED的发光效率和流经该LED的电流密度的关系示意图。如图1所示，在较低电流密度下(例如曲线段I)，流经该LED的电流密度较小，发光效率较低；在较高电流密度下(例如曲线段Ⅱ)，LED的发光效率较高。
在一些实现方式中，LED具有较大的发光面积，这样容易降低流经该LED的电流密度，进而降低LED的发光效率。然而，在提高电流密度以提高LED的发光效率的情况下，又容易增加功耗。而且，如果LED长时间保持较高的发光效率，就会长时间工作在较高电流密度的条件下，这样会导致LED的温度升高，出现热量聚集的现象，进而会影响LED结构的稳定性，降低LED的发光效率。
本公开实施例提供一种显示基板，包括：多个像素单元和至少一个补偿电路。至少一个像素单元包括主发光单元和辅发光单元。至少一个补偿电路与至少一个像素单元的辅发光单元连接。至少一个补偿电路配置为检测至少一个像素单元的温度或亮度，并控制至少一个像素单元的辅发光单元根据检测结果发光。
本实施例提供的显示基板，可以在主发光单元由于温度升高而引起亮度衰减的情况下，利用补偿电路和辅发光单元发光来补偿降低的亮度，从而改善由于温度升高而引起的亮度衰减，并提高显示效果。
在一些示例性实施方式中，补偿电路包括：补偿控制电路以及与补偿控制电路连接的至少一个检测电路。一个检测电路与一个像素单元的辅发光单元连接。检测电路配置为检测所连接的像素单元的亮度。补偿控制电路，配置为控制检测电路所连接的辅发光单元根据所述检测电路的检测结果发光。在一些示例中，补偿电路可以包括补偿控制电路和多个检测电路(例如，四个检测电路)，多个检测电路与多个像素单元的辅发光单元一一对应连接。每个像素单元的辅发光单元可以在补偿控制电路的控制下，根据所连接的检测电路的检测结果发光，以实现亮度补偿。本实施例对于一个补偿电路所连接的像素单元的数目并不限定。
在一些示例性实施方式中，补偿控制电路，包括：第一控制子电路和第二控制子电路。第一控制子电路，与第一扫描线、一个电压检测电路以及一个检测电路连接，配置为在第一扫描线的控制下，将所述检测电路的检测结果传输至所述电压检测电路，以使所述电压检测电路连接的外部控制电路根据所述检测结果更新补偿控制信号。第二控制子电路，与第一扫描线、补偿数据线、第二电源线以及至少一个检测电路连接，配置为在第一扫描线的控制下，将补偿数据线提供的补偿控制信号传输给至少一个检测电路，以控制至少一个检测电路将检测结果传输给对应的辅发光单元。在一些示例中，电压检测电路可以配置为获取主发光单元的驱动晶体管的阈值电压，以及获取检测电路的检测结果。外部控制电路可以集成在时序控制器内，以便于通过数据驱动器向补偿数据线提供补偿控制信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，补偿电路可以包括：一个检测电路，所述检 测电路与至少一个像素单元的辅发光单元连接。检测电路配置为检测至少一个像素单元的温度，并控制至少一个像素单元的辅发光单元根据检测结果发光。在本示例性实施方式中，检测电路可以实现温度检测和辅发光单元的发光控制。然而，本实施例对此并不限定。
在一些示例性实施方式中，主发光单元包括主发光元件和主驱动电路；辅发光单元包括辅发光元件和辅驱动电路。主发光元件和辅发光元件均为微发光元件。主发光元件的发光面积大于辅发光元件的发光面积。在一些示例中，主发光元件和辅发光元件可以为次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)，或者，可以为微型发光二极管(Micro Light Emitting Diode，简称Micro LED)。然而，本实施例对此并不限定。在本示例中，设置发光面积较小的辅发光元件，可以有利于提高流经辅发光元件的电流密度，从而提高辅发光元件的发光效率。
在一些示例性实施方式中，显示基板包括：衬底、设置在衬底上的电路结构层和多个发光二极管芯片。电路结构层包括：所述补偿电路以及所述像素单元的主驱动电路和辅驱动电路。至少一个发光二极管芯片包括：所述像素单元的主发光元件和辅发光元件。主发光元件和辅发光元件各自包括：依次层叠的第一半导体层、量子阱层和第二半导体层；其中，第一半导体层和第二半导体层的掺杂类型不同。主发光元件和辅发光元件还各自包括：第一绑定电极和第二绑定电极中的至少一者。主发光元件的第一绑定电极与主发光元件的第一半导体层连接，主发光元件的第二绑定电极与主发光元件的第二半导体层连接。辅发光元件的第一绑定电极与辅发光元件的第一半导体层连接，辅发光元件的第二绑定电极与辅发光元件的第二半导体层连接。本示例性实施方式中，通过将主发光元件和辅发光元件设置在一个发光二极管芯片上，使得主发光元件和辅发光元件的发光面积均小于发光二极管芯片的整体面积，可以提高流经主发光元件和辅发光元件的电流密度，从而提高发光二极管芯片的发光效率。
下面通过一些示例对本实施例的方案进行举例说明。
图2为本公开至少一实施例的显示基板的结构示意图。在一些示例性实施方式中，如图2所示，显示基板包括：时序控制器、数据驱动器、扫描驱 动器、像素阵列以及多个补偿电路。像素阵列可以包括多条扫描线(例如，G(1)至G(m))、多条数据线(例如，D(1)至D(n))、多个像素单元以及多条补偿数据线(例如，P-D(1)至P-D(o))。其中，o、m和n均为自然数。
在一些示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D(1)至D(n)的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素单元行为单位将与灰度值对应的数据电压施加到数据线D(1)至D(n)。数据驱动器还可以利用从时序控制器接收的控制信号来产生提供到补偿数据线P-D(1)至P-D(o)的补偿控制信号。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线G(1)至G(m)的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线G(1)至G(m)。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。像素阵列可以包括多个像素单元(例如，像素单元P11、P12、P21和P22)。每个像素单元可以连接到对应的数据线和对应的扫描线。例如，像素单元P11可以连接第一条数据线和第一条扫描线。在一些示例中，一条补偿数据线与一个补偿电路连接。然而，本实施例对此并不限定。例如，一条补偿数据线可以与多个补偿电路连接。
在一些示例性实施方式中，如图2所示，至少一个像素单元包括主发光单元和辅发光单元。至少一个补偿电路包括：补偿控制电路以及与补偿控制电路连接的多个检测电路(例如，四个检测电路)。在一些示例中，补偿电路的多个检测电路和多个像素单元的辅发光单元可以一一对应连接。检测电路配置为检测所连接的像素单元的亮度，补偿控制电路配置为控制多个像素单元的辅发光单元根据所连接的检测电路的检测结果发光，以实现对主发光单元的发光亮度进行补偿。
在一些示例性实施方式中，如图2所示，一个补偿电路与四个相邻的像素单元(例如，像素单元P11、P12、P21和P22)连接。补偿电路包括的四 个检测电路与四个像素单元的辅发光单元一一对应连接。补偿电路位于四个像素单元的中间位置，补偿控制电路位于四个检测电路的中间位置，且补偿控制电路靠近与像素单元P11连接的检测电路。本实施例的补偿电路的排布方式可以方便布线。然而，本实施例对此并不限定。
图3为本公开至少一实施例的显示基板的电路结构示意图。图4为本公开至少一实施例的显示基板的局部电路结构示意图。图3中示意了四个像素单元(例如，第i行第j列像素单元、第i行第j+1列像素单元、第i+1行第j列像素单元以及第i+1行第j+1列像素单元)、四个检测电路以及一个补偿控制电路的等效电路结构。四个检测电路与四个像素单元一一对应连接，补偿控制电路与四个检测电路连接。图4中示意了一个像素单元(例如，第i行第j列像素单元)、一个检测电路和一个补偿控制电路的等效电路结构。其中，i和j均为整数。
下面以第i行第j列像素单元为例说明像素单元的结构。
在一些示例性实施方式中，如图4所示，第i行第j列像素单元的主发光单元可以包括：主驱动电路11以及与主驱动电路11连接的主发光元件E1。主驱动电路11配置为在第一扫描线GA(i)的控制下，接收数据线D(j)传输的数据电压，向主发光元件E1输出相应的电流。主发光元件E1配置为响应所在像素单元的主驱动电路11输出的电流发出相应亮度的光。
在一些示例性实施方式中，如图4所示，第i行第j列像素单元的主驱动电路11可以为3T1C结构的像素电路。主驱动电路11包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1。第一晶体管T1的控制极与第一扫描线GA(i)连接，第一晶体管T1的第一极与数据线D(j)连接，第一晶体管T1的第二极与第二晶体管T2的控制极连接。第二晶体管T2的第一极与第一电源线PL1连接，第二晶体管T2的第二极与主发光元件E1的第一极连接。第三晶体管T3的控制极与第二扫描线GB(i)连接，第三晶体管T3的第一极与第二晶体管T2的第二极连接，第三晶体管T3的第二极与电压检测电路连接。主发光元件E1的第二极与第二电源线PL2连接。第一电容C1的第一极与第二晶体管T2的控制极连接，第一电容C1的第二极与主发光元件E1的第一极连接。在本示例中，第一节点g的电位与第二晶体管 T2的控制极、第一晶体管T1的第二极以及第一电容C1的第一极的电位相同。第二节点u的电位与第二晶体管T2的第二极、第一电容C1的第二极、第三晶体管T3的第二极以及主发光元件E1的第一极的电位相同。在本示例中，第一晶体管T1还可以称为输入晶体管，第二晶体管T2还可以称为驱动晶体管，第三晶体管T3还可以称为感测晶体管。本实施例对于主驱动电路包括的晶体管数目和电容数目并不限定。
在一些示例性实施方式中，第一晶体管T1至第三晶体管T3可以为N型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，第i行第j列像素单元的辅发光单元包括：辅驱动电路12以及与辅驱动电路12连接的辅发光元件E2。辅驱动电路12与检测电路13连接。辅驱动电路12配置为在检测电路13的控制下，向辅发光元件E2输出相应的电流。辅发光元件E2配置为响应辅驱动电路12输出的电流发出相应亮度的光，以对主发光单元进行亮度补偿。
在一些示例性实施方式中，如图4所示，第i行第j列像素单元的辅驱动电路12包括：第四晶体管T4。第四晶体管T4的控制极与检测电路13连接，第四晶体管T4的第一极与第一电源线PL1连接，第四晶体管T4的第二极与辅发光元件E2的第一极连接。辅发光元件E2的第二极与第二电源线PL2连接。在一些示例中，第四晶体管T4可以为P型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，检测电路13与第i行第j列像素单元的辅驱动电路12和补偿控制电路14连接。检测电路13配置为检测第i行第j列像素单元的发光亮度，并在补偿控制电路14的控制下，向辅驱动电路12输出检测结果，以控制辅发光元件E2发出相应亮度的光。
在一些示例性实施方式中，如图3所示，一个补偿控制电路14与四个检测电路13连接。四个检测电路13与四个像素单元(即第i行第j列像素单元、第i行第j+1列像素单元、第i+1行第j列像素单元和第i+1行第j+1列像素单元)一一对应连接。补偿控制电路14还与第i行第j列像素单元所连接的电压检测电路连接。第i行第j列像素单元所连接的电压检测电路配置为提取主驱动电路11的驱动晶体管的阈值电压，还配置为获取检测电路13 的检测结果，以便外部控制电路根据结果确定是否对补偿电路连接的四个像素单元进行亮度补偿。上述四个像素单元中除第i行第j列像素单元以外的其余像素单元所连接的电压检测电路仅配置为提取对应的主驱动电路的驱动晶体管的阈值电压，以对阈值电压进行补偿。补偿控制电路14还与第一扫描线GA(i)和补偿数据线P-D(k)连接。补偿控制电路14配置为根据补偿数据线P-D(k)提供的补偿控制信号，控制检测电路13向对应连接的辅驱动电路12输出检测结果，以使得对应的辅发光元件E2根据检测结果发出相应亮度的光。
在一些示例性实施方式中，如图4所示，第i行第j列像素单元所连接的检测电路13包括：第五晶体管T5、第六晶体管T6和检测元件PD。检测元件PD的第一极与第六晶体管T6的第二极连接，检测元件PD的第二极与第二电源线PL2连接。第六晶体管T6的控制极和第一极均与第一电源线PL1连接。第五晶体管T5的控制极与补偿控制电路14连接，第五晶体管T5的第一极与第六晶体管T6的第二极连接，第五晶体管T5的第二极与辅驱动电路12连接。在本示例中，第五晶体管T5的第二极可以与辅驱动电路12的第四晶体管T4的控制极连接。在本示例中，第三节点e的电位与检测元件PD的第一极、第六晶体管T6的第二极、第五晶体管T5的第一极以及第七晶体管T7的第二极的电位相同。在一些示例中，第五晶体管T5和第六晶体管T6可以为N型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，检测元件PD可以为PIN型光电二极管。在光照条件下，PIN型光电二极管可以根据所感应的光信号，生成相应的电信号。例如，PIN型光电二极管可以包括叠设的第二极(例如，阴极)、光电转换结构和第一极(例如，阳极)。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，补偿控制电路14包括：第一控制子电路141和第二控制子电路142。第一控制子电路141，与第一扫描线GA(i)、第i行第j列像素单元所连接的电压检测电路以及检测电路13连接，配置为在第一扫描线GA(i)的控制下，将检测电路13的检测结果传输至所述电压检测电路，以使所述电压检测电路连接的外部控制电路根据所述检测结果更新补偿控制信号。第二控制子电路142，与第一扫描线GA(i)、补偿数据 线P-D(k)、第二电源线PL2以及四个检测电路13连接，配置为在第一扫描线GA(i)的控制下，将补偿数据线P-D(k)提供的补偿控制信号传输给四个检测电路13，以控制四个检测电路13分别将检测结果传输给对应的辅发光单元。其中，k为整数。在本示例中，利用一个检测电路的检测结果来判断是否进行亮度补偿，在确定进行亮度补偿后，可以同时控制四个辅发光元件进行亮度补偿。
在一些示例性实施方式中，如图4所示，补偿控制电路14的第一控制子电路141可以包括：第七晶体管T7；第二控制子电路142可以包括：第八晶体管T8和第二电容C2。第七晶体管T7的控制极与第一扫描线GA(i)连接，第七晶体管T7的第一极与一个电压检测电路连接，第七晶体管T7的第二极与一个检测电路13连接。第八晶体管T8的控制极与第一扫描线GA(i)连接，第八晶体管T8的第一极与补偿数据线P-D(k)连接，第八晶体管T8的第二极与四个检测电路13连接。第二电容C2的第二极与第八晶体管T8的第二极连接，第二电容C2的第一极与第二电源线PL2连接。在本示例中，第七晶体管T7的第一极与一个检测电路13的检测元件PD的第一极连接；第八晶体管T8与四个检测电路13的第五晶体管T5的控制极连接。在本示例中，第四节点r的电位与第二电容C2的第二极、第八晶体管T8的第二极、以及四个检测电路的第五晶体管T5的控制极的电位相同。在一些示例中，第七晶体管T7和第八晶体管T8可以为N型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一电源线PL1可以持续提供高电平信号，第二电源线PL2可以持续提供低电平信号。第一晶体管T1到第八晶体管T8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在一些示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline  Oxide)显示基板，可以利用两者的优势，可以实现高分辨率(PPI，Pixel Per Inch)，低频驱动，可以降低功耗，可以提高显示品质。
图5为本公开至少一实施例的电压检测电路的结构示意图。在一些示例性实施方式中，如图5所示，电压检测电路可以包括：滤波放大电路和模数(A/D)转换电路。滤波放大电路的输入端Vin可以与一个像素单元的主驱动电路的第三晶体管T3的第二极连接。滤波放大电路的输出端可以与模数转换电路连接。
在一些示例性实施方式中，滤波放大电路可以包括：比较器A、第三电容C3、第一电阻R1、第二电阻R2以及第三电阻R3。第一电阻R1的第一端与滤波放大电路的输入端Vin连接，第一电阻R1的第二端与比较器A的第一输入端连接。第三电容C3的第一极与比较器A的第一输入端连接，第三电容C3的第二极与接地端连接。第三电阻R3的第一端与比较器A的第二输入端连接，第三电阻R3的第二端与接地端连接。第二电阻R2的第一端与比较器A的第一输入端连接，第二电阻R2的第二端与比较器A的输出端连接。比较器A的输出端与模数转换电路连接。
在一些示例性实施方式中，像素单元的主驱动电路的第三晶体管T3输出的电信号经过电压检测电路的转换之后，可以提取得到主驱动电路的驱动晶体管(即第二晶体管T2)的阈值电压。提取到的阈值电压可以被传输至时序控制器，由时序控制器利用阈值电压对数据电压进行补偿，得到补偿后的数据信号，并将补偿后的数据信号提供给数据驱动器，以便数据驱动器通过数据线提供给像素单元。本示例性实施例利用主驱动电路和电压检测电路，通过外部补偿方式实现阈值补偿，以提高显示效果。
在一些示例性实施方式中，补偿控制电路14的第七晶体管T7输出的电信号即为检测电路13的检测元件PD根据接收的光信号转换得到的电信号。补偿控制电路14的第七晶体管T7输出的电信号经过电压检测电路的转换之后，可以提取得到对应的电压值。提取到的电压值可以被传输至时序控制器，由时序控制器判断是否需要进行亮度补偿。例如，在提取到的电压值与像素单元的显示灰阶电压值不一致时(例如，提起到的电压值大于显示灰阶电压值)，时序控制器确定需要对像素单元进行亮度补偿。时序控制器可以向数 据驱动器提供控制信号，以使数据驱动器通过补偿数据线向补偿控制电路提供补偿控制信号。补偿控制电路可以利用补偿控制信号，导通检测电路13的第五晶体管T5，使得检测电路13利用检测结果控制辅发光元件E2发出相应亮度的光。其中，第五晶体管T5导通后，辅驱动电路12的第四晶体管T4的控制极由第三节点e控制，第三节点e的电位由检测电路13的检测元件PD的检测结果控制。
图6为本公开至少一实施例的像素单元的主驱动电路的工作时序图。在一些示例性实施方式中，以第i行第j列像素单元的主驱动电路为例进行说明。如图4和图6所示，第i行第j列像素单元的主驱动电路的工作过程包括：空闲阶段S1和显示阶段S2。在每两帧显示阶段S2之间的空闲阶段S1，可以完成对一行像素单元的阈值补偿操作，例如，完成对一行像素单元的主驱动电路的驱动晶体管的阈值电压Vth以及迁移率的侦测，以在显示阶段S1使用侦测到的数据得到补偿数据信号完成显示。
在一些示例性实施方式中，如图4和图6所示，空闲阶段S1包括第一阶段S11和第二阶段S12。
在第一阶段S11，第一扫描线GA(i)和第二扫描线GB(i)提供高电平信号，第一晶体管T1和第三晶体管T3导通。第一晶体管T1导通，将数据线D(j)提供的数据电压传输至第一节点g，使得第一节点g的电位为数据电压Vdata。第三晶体管T3导通，将复位电压传输至第二节点u，使得第二节点u的电位为复位电压Vref。之后，在第一节点g的电位控制下，第二晶体管T2导通。第一电源线PL1通过第二晶体管T2给第二节点u充电。电压检测电路可以存储第二节点u的电位。
在第二阶段S12，第一扫描线GA(i)和第二扫描线GB(i)提供低电平信号，第一晶体管T1和第三晶体管T3断开。第二晶体管T2导通，将第二节点u充电至Vdata-Vth之后，第二晶体管T2断开。其中，Vth为第二晶体管T2的阈值电压。
在一些示例性实施方式中，利用电压检测电路可以读取第二节点u的电压Vdata-Vth，由于数据电压Vdata已知，可以据此获得第二晶体管T2的阈值电压Vth，并将阈值电压Vth进行存储，以便后续进行阈值补偿使用。
在一些示例性实施方式中，主驱动电路的驱动晶体管(即第二晶体管)的阈值电压的提取过程在空闲阶段进行，例如，可以在显示装置启动之前执行，或者可以在显示装置关闭后执行。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4和图6所示，在显示阶段S2，时序控制器可以根据存储的提取到的驱动晶体管的阈值电压以及数据电压Vdata’，确定补偿后的数据电压为Vdata’+Vth，并通过数据驱动器和数据线将补偿后的数据电压提供给像素单元。
在一些示例性实施方式中，在显示阶段S2的数据写入阶段，第一扫描线GA(i)提供高电平信号，第一晶体管T1导通，将数据线D(j)提供的数据电压传输至第一节点g，使得第一节点g的电位为Vdata’+Vth。第二扫描线GB(i)提供低电平信号，第三晶体管T3断开。在显示阶段S2的发光阶段，第一扫描线GA(i)和第二扫描线GB(i)提供低电平信号，第一晶体管T1和第三晶体管T3断开。在第一节点g的电位控制下，第二晶体管T2导通。第一电源线PL1通过第二晶体管T2向第二节点u提供驱动电流。
在本示例中，流经主发光元件E1的驱动电流可以为：
I＝K(Vgs-Vth) 2＝K(Vdata’+Vth-Vdd-Vth) 2＝K(Vdata’-Vdd) 2；
其中，K为与驱动晶体管的工艺参数和几何尺寸有关的常数；Vdata’为数据电压；Vdd为第一电源线PL1提供的第一电源电压。
由此可见，主发光元件的驱动电流与第二晶体管T2的阈值电压无关，从而可以确保主发光元件的稳定显示。本示例可以实现阈值电压的外部补偿。
在一些示例性实施方式中，与像素单元连接的检测电路配置为检测对应的像素单元的发光亮度，并在显示阶段将检测结果传输给电压检测电路。
图7为本公开至少一实施例的补偿控制电路的工作时序图。在一些示例性实施方式中，如图4和图7所示，补偿控制电路14可以在一帧显示阶段提取检测结果(即亮度检测阶段S21)，在后续一帧显示阶段控制辅发光元件E2发光以进行亮度补偿(即亮度补偿阶段S22)。
在亮度检测阶段S21，第一扫描线GA(i)提供高电平信号，补偿控制电路14的第七晶体管T7和第八晶体管T8导通。检测电路13的检测元件PD感 应第i行第j列像素单元发出的光信号，并将光信号转换为电信号。其中，检测元件PD感应到的光信号的亮度越高，第三节点e的电位越低。第七晶体管T7导通，电压检测电路可以提取到第三节点e的电压值，并提供给时序控制器。时序控制器可以根据第三节点e的电压值来判断是否需要对像素单元进行亮度补偿。在本示例中，在显示阶段，第一扫描线GA(i)提供高电平信号时，第二扫描线GB(i)提供低电平信号，因此，在第七晶体管T7导通时，主驱动电路11的第三晶体管T3断开，主驱动电路11不会对电压检测电路提取第三节点e的电压值产生影响。在亮度检测阶段S21，补偿数据线P-D(k)提供低电平信号，第八晶体管T8导通，使得第四节点r处于低电位，检测电路13的第五晶体管T5断开，辅发光元件E2不发光。
在一些示例中，当数据电压对应255灰阶，理论上第三节点e的电位为第一电压值。当电压检测电路读取的第三节点e的实际电压值大于第一电压值，说明检测元件PD检测到的光信号的亮度低于255灰阶。此时，时序控制器确定需要进行亮度补偿，并通过数据驱动器向补偿数据线P-D(k)提供下一扫描阶段为高电平信号的补偿控制信号。在检测元件PD检测到的光信号的亮度与数据电压对应的亮度一致时，时序控制器可以通过数据驱动器向补偿数据线P-D(k)提供低电平信号的补偿控制信号，使得补偿控制电路14的第八晶体管T8断开，即不进行亮度补偿。
在亮度补偿阶段S22，第一扫描线GA(i)提供高电平信号，第七晶体管T7和第八晶体管T8导通。补偿数据线P-D(k)提供高电平信号，向第四节点r写入高电平信号，使得第五晶体管T5导通。此时，第四晶体管T4的控制极的电位由第三节点e控制。如此一来，可以根据检测元件PD的实时检测结果来控制辅发光元件E2的发光亮度，以提供实时可变的补偿亮度。
在本示例性实施方式中，在亮度补偿阶段S22，辅驱动电路12的第四晶体管T4的控制极的电位由检测元件PD控制。检测元件PD检测到的光信号的亮度越低，所需补偿的亮度也越低。检测元件PD检测到的光信号的亮度越低，检测元件PD的电阻值越大，第三节点e的电压值越高，则第四晶体管T4的栅源电压差Vgs越小，提供给辅发光元件E2的驱动电流越小。本示例的辅发光元件E2的亮度符合灰阶显示越低，要补偿亮度越低的趋势。在 本示例中，像素单元所需补偿的亮度与该像素单元所显示的亮度相关联，像素单元显示的亮度越低，所需补偿的亮度越低。
图8为本公开至少一实施例的补偿控制电路在多帧显示阶段的工作时序图。在一些示例性实施方式中，如图8所示，显示基板在第一帧显示阶段F(1)，通过检测元件PD检测像素单元的发光亮度，并根据检测结果确定多个像素单元需要进行亮度补偿。在第二帧显示阶段F(2)，通过补偿数据线P-D(k)提供高电平信号，控制多个辅发光元件E2根据对应的检测元件PD的检测结果来发光，以实现亮度补偿。经过n帧之后，在第n+1帧显示阶段F(n+1)可以重新利用检测元件PD的检测结果来判断是否进行亮度补偿。本实施例对于亮度检测的时间点和进行亮度补偿的时间点并不限定。在一些示例中，在第n+1帧显示阶段根据检测元件PD的检测结果确定需要进行亮度补偿，可以在第n+x帧显示阶段进行亮度补偿，例如，x可以为大于2的整数。由于温度不具有骤降性，采用间隔多个显示帧后进行亮度补偿，仍可以改善由于温度升高引起的亮度衰减情况。
本示例性实施方式提供的显示基板，利用检测元件进行亮度检测，并根据检测结果来控制辅发光元件提供相应的补偿亮度，从而改善由于显示基板温度升高引起的亮度衰减情况。
在一些示例性实施方式中，显示基板包括：衬底、设置在衬底上的电路结构层和多个发光二极管芯片。电路结构层可以包括：补偿电路、像素单元的主驱动电路和辅驱动电路。至少一个发光二极管芯片可以包括一个像素单元的主发光元件和辅发光元件。主发光元件和辅发光元件各自包括：依次层叠的第一半导体层、量子阱层(MQW，Multiple Quantum Well)和第二半导体层。第一半导体层和第二半导体层的掺杂类型不同。
在一些示例性实施方式中，发光二极管芯片可以为次毫米发光二极管(Mini LED)芯片，或者，可以为微型发光二极管(Micro LED)芯片。在一些示例中，发光二极管芯片可以为正装结构、垂直结构或者倒装结构。然而，本实施例对此并不限定。
图9A为本公开至少一实施例中的发光二极管芯片的平面示意图。图9B为图9A中沿Q-Q’方向的局部剖面示意图。图10A为本公开至少一实施例的 形成第二半导体层后的发光二极管芯片的平面示意图。图10B为图10A中沿Q-Q’方向的局部剖面示意图。图11A为本公开至少一实施例的形成第一绝缘层后的发光二极管芯片的平面示意图。图11B为图11A中沿Q-Q’方向的局部剖面示意图。图12A为本公开至少一实施例的形成转接电极层后的发光二极管芯片的平面示意图。图12B为图12A中沿Q-Q’方向的局部剖面示意图。图13A为本公开至少一实施例的形成封装层后的发光二极管芯片的平面示意图。图13B为图13A中沿Q-Q’方向的局部剖面示意图。本示例以发光二极管芯片的结构为倒装结构为例进行说明。
在一些示例性实施方式中，如图9至图13B所示，发光二极管芯片可以包括：基底30、以及位于基底30同一侧的主发光元件E1和辅发光元件E2。即，主发光元件E1和辅发光元件E2属于同一个发光二极管芯片。主发光元件E1包括依次层叠的第一半导体层311、量子阱层321和第二半导体层331。辅发光元件E2包括依次层叠的第一半导体层312、量子阱层322和第二半导体层332。其中，主发光元件E1的第一半导体层311与量子阱层321可以直接接触，量子阱层321与第二半导体层331可以直接接触。辅发光元件E2的第一半导体层312和量子阱层322可以直接接触，量子阱层322和第二半导体层332可以直接接触。主发光元件E1的第一半导体层311和辅发光元件E2的第一半导体层312可以为一体结构。主发光元件E1的量子阱层321和辅发光元件E2的量子阱层322之间具有间隙。主发光元件E1的第二半导体层331和辅发光元件E2的第二半导体层332之间具有间隙。在本示例中，主发光元件E1和辅发光元件E2相互独立设置，便于对主发光元件E1和辅发光元件E2的发光状态进行灵活控制。
在一些示例性实施方式中，如图9至图13B所示，主发光元件E1的发光区域为第一半导体层311、量子阱层321和第二半导体层331在层叠方向的重叠区域，第一半导体层311、量子阱层321和第二半导体层331在层叠方向的重叠区域的面积为主发光元件E1的发光面积。辅发光元件E2的发光区域为第一半导体层312、量子阱层322和第二半导体层332在层叠方向的重叠区域，第一半导体层312、量子阱层322和第二半导体层332在层叠方向的重叠区域的面积为辅发光元件E2的发光面积。在本示例中，主发光元 件E1的发光面积大于辅发光元件E2的发光面积。主发光元件E1和辅发光元件E2的发光面积均小于发光二极管芯片的整体面积，如此一来，可以提高经过主发光元件E1和辅发光元件E2的电流密度，提高发光效率。
在一些示例性实施方式中，如图9至图13B所示，发光二极管芯片还包括：转接电极层和绑定电极层。转接电极层位于第二半导体层远离基底30的一侧，绑定电极层位于转接电极层远离基底30的一侧。第二半导体层和转接电极层之间设置有第一绝缘层36，转接电极层和绑定电极层之间设置有第二绝缘层37和封装层38。封装层38位于第二绝缘层37远离转接电极层的一侧。
在一些示例性实施方式中，如图9至图13B所示，转接电极层包括：第一转接电极341和第二转接电极342。第一转接电极341通过第一绝缘层36上开设的第一过孔K1与主发光元件E1的第二主半导体层331连接，第二转接电极342通过第一绝缘层36上开设的第二过孔K2与辅发光元件E2的第二辅半导体层332连接。绑定电极层包括：第一绑定电极353、第二绑定电极351和352。第二绑定电极351通过第三过孔K3与第一转接电极341连接，第二绑定电极352通过第四过孔K4与第二转接电极342连接，第一绑定电极353通过第五过孔K5与第一半导体层连接。
在本示例性实施方式中，发光二极管芯片包括可以独立进行发光的主发光元件E1和辅发光元件E2，可以降低流经主发光元件E1和辅发光元件E2的电流密度，有利于改善热量聚集的现象。
图14为本公开至少一实施例的显示基板的电路结构层的局部剖面示意图。图14中以检测元件PD和一个晶体管(例如，与检测元件PD连接的一个晶体管)为例进行示意。
在一些示例性实施方式中，如图14所示，在垂直于显示基板的平面内，电路结构层可以包括：依次设置在衬底40上的遮光层、第三半导体层、第一导电层、第二导电层、第三导电层、光电转换层和第四导电层。衬底40和遮光层之间可以设置第三绝缘层41，遮光层和第三半导体层之间可以设置第四绝缘层42，第三半导体层和第一导电层之间可以设置第五绝缘层43，第一导电层和第二导电层之间可以设置第六绝缘层44，第二导电层和第三导电层之 间可以设置第七绝缘层45，光电转换层和第四导电层之间可以设置第八绝缘层46。第四导电层远离衬底40的一侧可以设置像素定义层47。在一些示例中，第三绝缘层41至第七绝缘层45可以为无机绝缘层，第八绝缘层46可以为有机绝缘层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图14所示，遮光层可以包括遮光电极50。第三半导体层至少包括：第一有源层51。遮光电极50在衬底40上的正投影可以覆盖第一有源层51在衬底40上的正投影，以避免外部光线对有源层的影响。第一导电层至少包括：第一栅电极52以及电容的第一电极(图未示)。第二导电层至少包括：电容的第二电极(图未示)。第三导电层至少包括：第一源电极53、第一漏电极54、检测元件的第一极61。光电转换层包括：检测元件的光电转换结构62。第四导电层包括：检测元件的第二极63。图14所示的晶体管可以包括：第一有源层51、第一栅电极52、第一源电极53以及第一漏电极54。检测元件可以包括：依次叠设的第一极61、光电转换结构62和第二极63。在一些示例中，检测元件的第一极61与相连的晶体管的第一漏电极54可以为一体结构。然而，本实施例对此并不限定。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“图案化工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的投影包含B的投影”，是指B的投影的边界落入A的投影的边界范围内，或者A的投影的边界与B的投影的边界重叠。
在一些示例性实施方式中，发光二极管芯片的制备过程可以包括如下操 作，如图9A至图13B所示。
(1)、在基底30上依次形成第一半导体层、量子阱层和第二半导体层，如图10A和图10B所示。
在一些示例性实施方式中，在基底30的一侧形成第一半导体薄膜，对第一半导体薄膜进行图案化处理后形成主发光元件E1的第一半导体层311和辅发光元件E2的第一半导体层312。主发光元件E1的第一半导体层311和辅发光元件E2的第一半导体层312为一体结构。随后，在第一半导体层远离基底30的一侧形成主发光元件E1的量子阱层321和辅发光元件E2的量子阱层322。随后，在量子阱层远离基底30的一侧形成主发光元件E1的第二半导体层331和辅发光元件E2的第二半导体层332。
在一些示例性实施方式中，基底30可以为磷化镓(GaP)基底、砷化镓(GaAs)基底、硅基底、碳化硅基底或蓝宝石基底等。然而，本实施例对此并不限定。
在一些示例性实施方式中，量子阱层的材料可以包括氮化镓(GaN)。第一半导体层和第二半导体层的掺杂类型可以不同。例如，第一半导体层的材料可以为N型半导体材料，第二半导体层的材料可以为P型半导体材料。或者，第一半导体层的材料可以为P型半导体材料，第二半导体层的材料可以为N型半导体材料。第一半导体层和第二半导体层中的本征半导体材料可以相同，该本征半导体材料可以为GaN、GaP、砷化铝镓(AlGaAs)和磷化铝镓铟(AlGaInP)中的任一种。
在一些示例性实施方式中，第一半导体层、多量子阱层和第二半导体层的厚度可以根据实际需要设置，在此不作限定。
(2)、形成第一绝缘层。
在一些示例性实施方式中，在第二半导体层远离基底30的一侧形成第一绝缘薄膜，对第一绝缘薄膜进行图案化处理而形成第一绝缘层36，如图11A和图11B所示。第一绝缘层36上开设有第一过孔K1和第二过孔K2。第一过孔K1内的第一绝缘层36被刻蚀掉，暴露出第二半导体层331的表面，第二过孔K2内的第一绝缘层36被刻蚀掉，暴露出第二半导体层332的表面。第一过孔K1和第二过孔K2在基底30上的正投影可以为矩形。然而，本实 施例对此并不限定。
(3)、形成转接电极层。
在一些示例性实施方式中，在第一绝缘层36远离基底30的一侧形成转接电极薄膜，对转接电极薄膜进行图案化处理，形成转接电极层，如图12A和图12B所示。转接电极层包括：第一转接电极341和第二转接电极342。第一转接电极341通过第一过孔K1与主发光元件E1的第二半导体层331连接，第二转接电极342通过第二过孔K2与辅发光元件E2的第二半导体层332连接。
(4)、形成第二绝缘层和封装层。
在一些示例性实施方式中，在转接电极层远离基底30的一侧依次形成第二绝缘层37和封装层38，如图13A和图13B所示。第二绝缘层37上开设有第一子过孔、第二子过孔和第三子过孔，封装层38上开设有与第一子过孔对应的第四子过孔、与第二子过孔对应的第五子过孔和与第三子过孔对应的第六子过孔。第一子过孔和第四子过孔形成第三过孔K3，第二子过孔和第五子过孔形成第四过孔K4，第三子过孔和第六子过孔形成第五过孔K5。第三过孔K3暴露出第一转接电极341的表面，第四过孔K4暴露出第二转接电极342的表面，第五过孔K5暴露出第一半导体层的表面。第三过孔K3、第四过孔K4和第五过孔K5在基底30上的正投影可以为矩形。然而，本实施例对此并不限定。
(5)、形成绑定电极层。
在一些示例性实施方式中，在封装层38远离基底30的一侧形成金属薄膜，对金属薄膜进行图案化处理，形成绑定电极层，如图9A和图9B所示。绑定电极层包括：第一绑定电极353、第二绑定电极351和352。第二绑定电极351通过第三过孔K3与第一转接电极341连接，第二绑定电极352通过第四过孔K4与第二转接电极342连接，第一绑定电极353通过第五过孔K5与第一半导体层连接。主发光元件E1可以通过第二绑定电极351与主驱动电路连接，辅发光元件E2可以通过第二绑定电极352与辅驱动电路连接，主发光元件E1和辅发光元件E3可以通过第一绑定电极353与第二电源线连接。在本示例中，主发光元件E1和辅发光元件E2的第一绑定电极为一体结 构。然而，本实施例对此并不限定。
在一些示例性实施方式中，主发光元件E1的第一半导体层311在基底30上的正投影包含量子阱层321在基底30上的正投影，量子阱层321在基底30上的正投影包含第二半导体层331在基底30上的正投影。辅发光元件E2的第一半导体层312在基底30上的正投影包含量子阱层322在基底30上的正投影，量子阱层322在基底30上的正投影包含第二半导体层332在基底30上的正投影。如此一来，便于实现第一绑定电极353与第一半导体层的电连接。
在一些示例性实施方式中，第一绝缘层36和第二绝缘层37可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。转接电极层的材料可以为具有较高光线透过率的材料，例如，氧化铟锡(ITO)。绑定电极层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。然而，本实施例对此并不限定。
在一些示例性实施方式中，在显示基板的衬底上形成电路结构层后，可以将多个发光二极管芯片转印到衬底上，以实现发光二极管芯片与电路结构层的电连接。发光二极管芯片的绑定电极层面对电路结构层，实现与电路结构层的电连接，以便电路结构层向发光二极管芯片提供电信号。在一些示例中，电路结构层的结构可以参照图14所示，故于此不再赘述。
在一些示例性实施方式中，在将发光二极管芯片与电路结构层中的主驱动电路和辅驱动电路进行绑定之后，可以对发光二极管芯片的基底进行剥离，使得显示基板中的发光二极管芯片仅包括主发光元件和辅发光元件。然而，本实施例对此并不限定。例如，在将发光二极管芯片与电路结构层进行绑定之后，可以保留基底。
图15为本公开至少一实施例的显示基板的另一结构示意图。在一些示例性实施方式中，如图15所示，显示基板包括：时序控制器、数据驱动器、扫描驱动器、发光驱动器、像素阵列以及多个补偿电路。像素阵列可以包括多条扫描线(例如，G(1)至G(m))、多条数据线(例如，D(1)至D(n))、多个 像素单元以及多条发光控制线(例如，EM(1)至EM(m))。其中，m和n均为自然数。在本示例中，补偿电路可以包括一个检测电路。检测电路配置为检测像素单元的温度。例如，一个检测电路可以与四个像素单元的辅发光单元连接。然而，本实施例对此并不限定。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图16为本公开至少一实施例的主驱动电路的结构示意图。在一些示例性实施方式中，如图16所示，主驱动电路包括：数据写入子电路、驱动子电路、阈值补偿子电路、存储子电路、初始化子电路和发光控制子电路。
在一些示例性实施方式中，数据写入子电路，与第三扫描线G、数据线D和第五节点a连接，配置为在第三扫描线G的控制下，向存储子电路写入数据线D提供的数据信号。存储子电路与第五节点a和第六节点b连接。驱动子电路，与第六节点b、第一电源线PL1和主发光元件E1的第一极连接，配置为在第六节点b的控制下，向主发光元件E1输出驱动电流。阈值补偿子电路，与第三扫描线G、第六节点b和主发光元件E1的第一极连接，配置为在第三扫描线G的控制下，对驱动子电路的阈值电压进行补偿。初始化子电路，与第五节点a、初始信号线INT、第一复位线RST1、第二复位线RST2连接，配置为在第一复位线RST1或第二复位线RST2的控制下，对第五节点a进行初始化。发光控制子电路，与发光控制线EM、第二电源线PL2和主发光元件E1的第二极连接，配置为在发光控制线EM的控制下，导通主发光元件E1的第二极和第二电源线PL2。
在一些示例性实施方式中，第一电源线PL1持续提供高电平信号，第二电源线PL2持续提供低电平信号。第i行像素电路的主驱动电路的第一复位线RST1与第i+1行像素电路的主驱动电路连接的第三扫描线G(i+1)连接，第i行像素电路的主驱动电路的第二复位线RST2与第i-1行像素电路的主驱动电路连接的第三扫描线G(i-1)连接。其中，i可以为整数。
图17为本公开至少一实施例的显示基板的电路结构示意图。图18为本公开至少一实施例的显示基板的局部电路结构示意图。图17中示意了四个像素单元(例如，第i行第j列像素单元、第i行第j+1列像素单元、第i+1行 第j列像素单元以及第i+1行第j+1列像素单元)以及一个检测电路。图18中示意了一个像素单元(例如，第i行第j列像素单元)和一个检测电路。其中，i和j均为整数。
在一些示例性实施方式中，如图18所示，第i行第j列像素单元的主驱动电路21的数据写入子电路包括：第九晶体管T9，驱动控制子电路包括第十晶体管T10，阈值补偿子电路包括：第十一晶体管T11，发光控制子电路包括：第十二晶体管T12，初始化子电路包括：第十三晶体管T13和第十四晶体管T14，存储子电路包括第四电容C4。第九晶体管T9的控制极与第一扫描线G(i)连接，第九晶体管T9的第一极与数据线D(j)连接，第九晶体管T9的第二极与第五节点a连接。第十晶体管T10的控制极与第六节点b连接，第十晶体管T10的第一极与第一电源线PL1连接，第十晶体管T10的第二极与主发光元件E1的第一极连接。第十一晶体管T11的控制极与第一扫描线G(i)连接，第十一晶体管T11的第一极与第六节点b连接，第十一晶体管T11的第二极与第十晶体管T10的第二极连接。第十二晶体管T12的控制极与发光控制线EM(i)连接，第十二晶体管T12的第一极与主发光元件E1的第二极连接，第十二晶体管T12的第二极与第二电源线PL2连接。第十三晶体管T13的控制极与第一复位线G(i+1)连接，第十三晶体管T13的第一极与初始信号线INT连接，第十三晶体管T13的第二极与第五节点a连接。第十四晶体管T14的控制极与第二复位线G(i-1)连接，第十四晶体管T14的第一极与初始信号线INT连接，第十四晶体管T14的第二极与第五节点a连接。
在本示例中，第五节点a的电位与第九晶体管T9的第二极、第四电容C4的第一极、第十三晶体管T13的第二极以及第十四晶体管T14的第二极的电位相同。第六节点b的电位与第四电容C4的第二极、第十晶体管T10的控制极以及第十一晶体管T11的第一极的电位相同。
在一些示例性实施方式中，如图18所示，第i行第j列像素单元的辅驱动电路22包括：第十五晶体管T15。第十五晶体管T15的控制极与主驱动电路21连接，第十五晶体管T15的第一极与检测电路23连接，第十五晶体管T15的第二极与辅发光元件E2的第一极连接。在本示例中，第十五晶体管T15的控制极与第六节点b连接，第十五晶体管T15的第一极与第七节点c 连接。辅发光元件E2的第二极与主发光元件E1的第二极连接。
在一些示例性实施方式中，如图18所示，检测电路23包括：第一检测晶体管T16和第二检测晶体管T17。第一检测晶体管T16的控制极和第一极均与第一电源线PL1连接，第一检测晶体管T16的第二极与第七节点c连接。第二检测晶体管T17的控制极和第一极与第二电源线PL2连接，第二检测晶体管T17的第二极与第七节点c连接。在一些示例中，第一检测晶体管T16和第二检测晶体管T17的掺杂类型相反。例如，第一检测晶体管T16可以为P型晶体管，第二检测晶体管T17可以为N型晶体管。在本示例中，第七节点c的电位与第一检测晶体管T16的第二极和第二检测晶体管T17的第二极的电位相同。第七节点c连接多个辅驱动电路22的第十五晶体管T15的第一极。
在本示例性实施方式中，第六节点b同时控制主驱动电路21的驱动晶体管(即第十晶体管T10)和辅驱动电路22的驱动晶体管(即第十五晶体管T15)。通过设置第十晶体管T10和第十五晶体管T15的沟道宽长比一致，可以使得两个驱动晶体管的阈值电压基本一致。
在本示例性实施方式中，检测电路23配置为检测多个像素单元的温度。利用P型晶体管和N型晶体管串联组成一个温度传感器。由于P型晶体管的漏电流随着温度升高而增大，N型晶体管的漏电流随着温度变化很小，因此第七节点c的电位大小随着温度升高而变大。第七节点c的电位可以提供给辅驱动电路22的第十五晶体管T15产生驱动电流，使得通过辅发光元件E2的驱动电流变大，从而实现温度升高后的亮度补偿。
图19为本公开至少一实施例的像素单元的工作时序图。在一些示例性实施方式中，如图18和图19所示，以第i行第j列像素单元的工作过程为例进行说明。第i行第j列像素单元的工作过程包括以下阶段。
在初始化阶段t1，第二复位线G(i-1)提供低电平信号，第十四晶体管T14导通，将初始信号线INT提供的初始电压提供至第五节点a，即将第四电容C4的第一极复位。第一扫描线G(i)、第一复位线G(i+1)和发光控制线EM(i)提供高电平信号，第九晶体管T9、第十一晶体管T11、第十二晶体管T12和第十四晶体管T14断开。
在资料写入及补偿阶段t2，第一扫描线G(i)提供低电平信号，第九晶体管T9和第十一晶体管T11导通。第九晶体管T9导通，使得数据线D(j)输出的数据电压提供至第五节点a，第五节点a的电位为数据电压Vdata。第十一晶体管T11导通，将第一电源线PL1提供的第一电源电压Vdd和第十晶体管T10的阈值电压Vth充入第六节点b，使得第六节点b的电位为Vdd+Vth。
在发光阶段t3，发光控制线EM(i)和第一复位线G(i+1)提供低电平信号，第十二晶体管T12和第十三晶体管T13导通。第五节点a的电位跳变为初始信号线INT提供的初始电压Vint，第六节点b的电位(即第十晶体管T10的控制极电位)跟着跳变为：Vb＝Vdd+Vth-(Vdata-Vint)。此时，第十晶体管T10处于饱和状态，第十晶体管T10的栅源电压差Vsg＝Vs-Vb＝Vdd-[Vdd+Vth-(Vdata-Vint)]＝Vdata-Vth-Vint。第十晶体管T10可以给主发光元件E1提供驱动电流。流经主发光元件E1的驱动电流可以为：
I＝K(Vgs-Vth) 2＝K(Vsg+Vth) 2＝K(Vdata-Vth-Vint+Vth) 2＝K(Vdata-Vint) 2；
其中，K为与驱动晶体管的工艺参数和几何尺寸有关的固定常数；Vdata为数据电压，Vint为初始信号线提供的初始电压。
由此可见，主发光元件E1的驱动电流与第十晶体管T10的阈值电压无关，从而可以确保主发光元件E1的稳定显示。本示例可以实现阈值电压的内部补偿。
在一些示例性实施方式中，在发光阶段，辅驱动电路22可以根据第七节点c的电位来给辅发光元件E2提供驱动电流，以便对主发光元件E1进行亮度补偿。在本示例中，检测电路23的检测结果可以控制辅发光元件E2的发光亮度，使得辅发光元件E2的发光亮度可以补偿由于温度升高造成的亮度损失。
关于本实施例的显示基板的制备过程可以参照前述实施例的说明，故于此不再赘述。
图20为本公开至少一实施例的显示基板的亮度补偿方法的流程图。如图20所示，本实施例的亮度补偿方法应用于如上所述的显示基板。所述亮度补偿方法包括以下步骤：
步骤801、补偿电路检测至少一个像素单元的亮度或温度；
步骤802、补偿电路控制所述至少一个像素单元的辅发光单元根据检测结果发光。
关于本实施例的亮度补偿方法可以参照前述实施例的说明，故于此不再赘述。
图21为本公开至少一实施例的显示装置的示意图。如图21所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板或者QLED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (18)

  1. 一种显示基板，包括：
    多个像素单元和至少一个补偿电路；
    至少一个像素单元包括：主发光单元和辅发光单元；所述至少一个补偿电路与至少一个像素单元的辅发光单元连接；
    所述至少一个补偿电路配置为检测所述至少一个像素单元的亮度或温度，并控制所述至少一个像素单元的辅发光单元根据检测结果发光。
  2. 根据权利要求1所述的显示基板，其中，所述补偿电路包括：补偿控制电路以及与所述补偿控制电路连接的至少一个检测电路；所述检测电路与一个像素单元的辅发光单元连接；
    所述检测电路配置为检测所连接的像素单元的亮度；
    所述补偿控制电路，配置为控制所述检测电路所连接的辅发光单元根据所述检测电路的检测结果发光。
  3. 根据权利要求2所述的显示基板，其中，所述补偿控制电路，包括：第一控制子电路和第二控制子电路；
    所述第一控制子电路，与第一扫描线、一个电压检测电路以及一个检测电路连接，配置为在所述第一扫描线的控制下，将所述检测电路的检测结果传输至所述电压检测电路，以使所述电压检测电路连接的外部控制电路根据所述检测结果更新补偿控制信号；
    所述第二控制子电路，与所述第一扫描线、补偿数据线、第二电源线以及至少一个检测电路连接，配置为在所述第一扫描线的控制下，将所述补偿数据线提供的所述补偿控制信号传输给所述至少一个检测电路，以控制所述至少一个检测电路将所述检测结果传输给对应的辅发光单元。
  4. 根据权利要求3所述的显示基板，其中，所述第一控制子电路包括：第七晶体管；所述第二控制子电路包括：第八晶体管和第二电容；
    所述第七晶体管的控制极与所述第一扫描线连接，所述第七晶体管的第一极与所述电压检测电路连接，所述第七晶体管的第二极与所述检测电路连 接；
    所述第八晶体管的控制极与所述第一扫描线连接，所述第八晶体管的第一极与所述补偿数据线连接，所述第八晶体管的第二极与所述第二电容的第二极连接，所述第二电容的第一极与所述第二电源线连接；
    所述第八晶体管的第二极与所述至少一个检测电路连接。
  5. 根据权利要求2至4中任一项所述的显示基板，其中，所述检测电路包括：检测元件、第五晶体管和第六晶体管；
    所述检测元件的第一极与所述第六晶体管的第二极连接，所述检测元件的第二极与第二电源线连接；所述第六晶体管的控制极和第一极与第一电源线连接；所述第五晶体管的控制极和所述补偿控制电路连接，所述第五晶体管的第一极与所述检测元件的第一极连接，所述第五晶体管的第二极与所述辅发光单元连接。
  6. 根据权利要求2至4中任一项所述的显示基板，其中，所述主发光单元包括：主发光元件以及与所述主发光元件连接的主驱动电路；
    所述主驱动电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容；所述第一晶体管的控制极与第一扫描线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述第二晶体管的控制极连接；所述第二晶体管的第一极与第一电源线连接，所述第二晶体管的第二极与所述第三晶体管的第一极连接；所述第三晶体管的控制极与第二扫描线连接，所述第三晶体管的第二极与电压检测电路连接；所述第一电容的第一极与所述第二晶体管的控制极连接，所述第一电容的第二极与所述第二晶体管的第二极连接；
    所述主发光元件的第一极与所述第二晶体管的第二极连接，所述主发光元件的第二极与第二电源线连接。
  7. 根据权利要求2至4中任一项所述的显示基板，其中，所述辅发光单元包括：辅发光元件以及与所述辅发光元件连接的辅驱动电路；
    所述辅驱动电路包括：第四晶体管；所述第四晶体管的控制极与所述检测电路连接，所述第四晶体管的第一极与第一电源线连接，所述第四晶体管 的第二极与所述辅发光元件的第一极连接；所述辅发光元件的第二极与第二电源线连接。
  8. 根据权利要求1所述的显示基板，其中，所述补偿电路包括：一个检测电路，所述检测电路与至少一个像素单元的辅发光单元连接；
    所述检测电路配置为检测所述至少一个像素单元的温度，并控制所述至少一个像素单元的辅发光单元根据检测结果发光。
  9. 根据权利要求8所述的显示基板，其中，所述检测电路包括：第一检测晶体管和第二检测晶体管；
    所述第一检测晶体管的控制极和第一极与第一电源线连接，所述第一检测晶体管的第二极与所述第二检测晶体管的第二极连接，并与至少一个像素单元的辅发光单元连接；所述第二检测晶体管的控制极和第一极与第二电源线连接；
    所述第一检测晶体管和第二检测晶体管的掺杂类型相反。
  10. 根据权利要求8或9所述的显示基板，其中，所述主发光单元包括：主发光元件以及与所述主发光元件连接的主驱动电路；
    所述主驱动电路包括：数据写入子电路、驱动子电路、阈值补偿子电路、存储子电路、初始化子电路和发光控制子电路；
    所述数据写入子电路，与第三扫描线、数据线和第五节点连接，配置为在所述第三扫描线的控制下，向所述存储子电路写入所述数据线提供的数据信号；
    所述存储子电路，与所述第五节点和第六节点连接；
    所述驱动子电路，与所述第六节点、第一电源线和所述主发光元件的第一极连接，配置为在所述第六节点的控制下，向所述主发光元件输出驱动电流；
    所述阈值补偿子电路，与所述第三扫描线、所述第六节点和所述主发光元件的第一极连接，配置为在所述第三扫描线的控制下，对所述驱动子电路的阈值电压进行补偿；
    所述初始化子电路，与所述第五节点、初始信号线、第一复位线、第二 复位线连接，配置为在所述第一复位线或第二复位线的控制下，对所述第五节点进行初始化；
    所述发光控制子电路，与发光控制线、第二电源线和所述主发光元件的第二极连接，配置为在所述发光控制线的控制下，导通所述主发光元件的第二极和所述第二电源线。
  11. 根据权利要求10所述的显示基板，其中，所述数据写入子电路，包括：第九晶体管；所述驱动子电路包括：第十晶体管；所述阈值补偿子电路包括：第十一晶体管；所述存储子电路包括：第四电容；
    所述发光控制子电路包括：第十二晶体管；
    所述初始化子电路包括：第十三晶体管和第十四晶体管；
    所述第九晶体管的控制极与第三扫描线连接，所述第九晶体管的第一极与数据线连接，所述第九晶体管的第二极与所述第五节点连接；
    所述第十晶体管的控制极与所述第五节点连接，所述第十晶体管的第一极与所述第一电源线连接，所述第十晶体管的第二极与所述主发光元件的第一极连接；
    所述第十一晶体管的控制极与所述第三扫描线连接，所述第十一晶体管的第一极与所述第六节点，所述第十一晶体管的第二极与所述第十晶体管的第二极连接；
    所述第十二晶体管的控制极与所述发光控制线连接，所述第十二晶体管的第一极与所述主发光元件的第二极连接，所述第十二晶体管的第二极与所述第二电源线连接；
    所述第十三晶体管的控制极与所述第一复位线连接，所述第十三晶体管的第一极与所述初始信号线连接，所述第十三晶体管的第二极与所述第五节点连接；
    所述第十四晶体管的控制极与所述第二复位线连接，所述第十四晶体管的第一极与所述初始信号线连接，所述第十四晶体管的第二极与所述第五节点连接；
    所述第四电容的第一极与所述第五节点连接，所述第四电容的第二极与 所述第六节点连接。
  12. 根据权利要求10所述的显示基板，其中，所述辅发光单元包括：辅发光元件以及与所述辅发光元件和主驱动电路连接的辅驱动电路；
    所述辅驱动电路包括：第十五晶体管；
    所述第十五晶体管的控制极与所述第六节点连接，所述第十五晶体管的第一极与所述检测电路连接，所述第十五晶体管的第二极与所述辅发光元件的第一极连接；
    所述辅发光元件的第二极与所述主发光元件的第二极连接。
  13. 根据权利要求1所述的显示基板，其中，所述主发光单元包括主发光元件和主驱动电路；所述辅发光单元包括辅发光元件和辅驱动电路；所述主发光元件和辅发光元件均为微发光元件；所述主发光元件的发光面积大于所述辅发光元件的发光面积。
  14. 根据权利要求13所述的显示基板，包括：衬底、设置在所述衬底上的电路结构层和多个发光二极管芯片；所述电路结构层包括：所述补偿电路以及所述像素单元的主驱动电路和辅驱动电路；至少一个发光二极管芯片包括：所述像素单元的主发光元件和辅发光元件；
    所述主发光元件和辅发光元件各自包括：依次层叠的第一半导体层、量子阱层和第二半导体层；所述第一半导体层和第二半导体层的掺杂类型不同；
    所述主发光元件和辅发光元件还各自包括：第一绑定电极和第二绑定电极中的至少一者；
    所述主发光元件的第一绑定电极与主发光元件的第一半导体层连接，所述主发光元件的第二绑定电极与主发光元件的第二半导体层连接；
    所述辅发光元件的第一绑定电极与辅发光元件的第一半导体层连接，所述辅发光元件的第二绑定电极与辅发光元件的第二半导体层连接。
  15. 根据权利要求14所述的显示基板，其中，所述主发光元件的第一半导体层和所述辅发光元件的第一半导体层为一体结构，并与同一个第一绑定电极连接。
  16. 根据权利要求14所述的显示基板，其中，所述发光二极管芯片还包 括基底，所述主发光元件和辅发光元件位于所述基底的同一侧。
  17. 一种显示装置，包括如权利要求1至16中任一项所述的显示基板。
  18. 一种显示基板的亮度补偿方法，应用于如权利要求1至16中任一项所述的显示基板，所述亮度补偿方法包括：
    补偿电路检测至少一个像素单元的亮度或温度；
    所述补偿电路控制所述至少一个像素单元的辅发光单元根据检测结果发光。
PCT/CN2022/104301 2021-07-20 2022-07-07 显示基板及其亮度补偿方法、显示装置 WO2023000989A1 (zh)

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