WO2023000823A1 - 一种功率半导体模块的新型封装结构 - Google Patents

一种功率半导体模块的新型封装结构 Download PDF

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Publication number
WO2023000823A1
WO2023000823A1 PCT/CN2022/095791 CN2022095791W WO2023000823A1 WO 2023000823 A1 WO2023000823 A1 WO 2023000823A1 CN 2022095791 W CN2022095791 W CN 2022095791W WO 2023000823 A1 WO2023000823 A1 WO 2023000823A1
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Prior art keywords
frame pin
conductive layer
metal conductive
chip unit
power semiconductor
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PCT/CN2022/095791
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English (en)
French (fr)
Inventor
封丹婷
房军军
Original Assignee
嘉兴斯达半导体股份有限公司
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Priority claimed from CN202110823796.0A external-priority patent/CN113517244A/zh
Priority claimed from CN202121660635.6U external-priority patent/CN215578525U/zh
Application filed by 嘉兴斯达半导体股份有限公司 filed Critical 嘉兴斯达半导体股份有限公司
Priority to DE112022000030.9T priority Critical patent/DE112022000030T5/de
Publication of WO2023000823A1 publication Critical patent/WO2023000823A1/zh

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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the invention relates to the field of power electronics, in particular to a novel package structure of a power semiconductor module.
  • field effect transistor modules are more and more widely used in the fields of frequency converters, welding machines, induction heating, uninterruptible power supplies, wind power generation and electric vehicles.
  • the packaging volume, power density, The requirements for reliability and other aspects are becoming more and more stringent.
  • the technical problem to be solved by the present invention is to provide a new packaging structure for power semiconductor modules to solve the problems of low heat dissipation efficiency, low power density, and large parasitic inductance and resistance in the prior art. .
  • a novel package structure of a power semiconductor module mainly includes an insulating heat sink and a metal lead frame unit and a chip unit arranged on the insulating heat sink.
  • the insulating heat sink includes The insulating layer and the inner metal conductive layer and the outer metal conductive layer respectively arranged on both sides of the insulating layer, the middle part of the inner metal conductive layer is a flat welding chip area, and the metal lead frame unit mainly includes the frame pin input part, The pin output part and the frame pin signal part, the frame pin input part is arranged on the upper side of the inner metal conductive layer by means of solder welding, and the chip unit is welded on the middle position of the inner metal conductive layer, and the The frame pin output part is provided with an inner concave part corresponding to the position of the chip unit and is welded and fixed to the chip unit through the outer end surface of the inner concave part, and the inner concave part corresponding to the position of the chip unit is connected to the chip through the outer
  • the signal part of the chip unit is connected to the signal part of the frame pins through ultrasonic bonding of the metal bonding wires; the insulating heat sink , the inner recesses on the chip unit and the pin output part of the frame are all covered by the plastic package, and the outer metal conductive layer of the insulating heat sink is exposed to the plastic package and flush with the outer wall of the plastic package.
  • the inner concave part is a groove formed by sinking or extrusion on the pin output part of the frame, the number, shape and size of the groove match the chip unit, and it can be arranged horizontally or vertically, And the outer surface of the groove is smooth and free of burrs; the grooves are all completely set on the wall surface of the frame pin output part or have one set on the upper side wall surface of the frame pin output part and form a concave gap.
  • the high-density metal bonding wires are used for ultrasonic welding, and the metal bonding wires are arranged as many as possible on the surface of the chip to achieve the maximum density that the chip can carry.
  • the frame pin output part is provided with a bent edge so that the output pin of the frame pin output part remains flush with the input pin of the frame pin input part, and the frame pin input part and the frame pin input part
  • the output parts of the frame pins are all provided with etching grooves or circular holes for reducing mechanical stress and increasing bonding force with injection molding materials.
  • the inner metal conductive layer of the insulating heat sink is etched with a channel for leading out electrical signals to the chip unit, and the signal part of the chip unit is bonded to the separate groove of the inner metal conductive layer through a metal bonding wire. On the track and jump to the frame pin signal part to lead out the chip signal.
  • the inner concave portion and the chip unit are soldered by reflow soldering, and the solder material is solder with a melting point higher than 260°C; the inner metal conductive layer and the chip unit are soldered by silver paste sintering or tin solder way of welding.
  • both the inner metal conductive layer and the outer metal conductive layer are made of aluminum or copper material whose surface is plated with gold; the metal bonding wire is made of aluminum or copper material.
  • the present invention provides a new packaging structure for power semiconductor modules, which optimizes the area of the chip loading area, increases the upper limit of the rated current of the package, and uses a metal sinking groove structure to double-sided the chip.
  • Welding increase heat capacity; improve overcurrent capability, use sheet metal lead frame structure in layout, maintain stacked upper and lower structure in circuit design, reduce parasitic inductance and resistance of modules, reduce voltage stress of chips, and use signal terminals Extremely close to the surface of the chip for electrical performance collection, reducing the signal interference caused by the induced electromotive force generated by the common terminal; greatly improving the output power, safety and reliability while ensuring heat dissipation efficiency.
  • FIG. 1 is a schematic diagram of the overall structure of the packaging structure of the present invention.
  • Fig. 2 is a side view structural schematic diagram of Fig. 1;
  • FIG. 3 is a structural schematic diagram of a metal lead frame multi-lead unit strip used in the packaging structure of the present invention
  • FIG. 4 is another structural schematic diagram of the packaging structure of the present invention.
  • Fig. 5 a 5 b is the structural representation when the groove of the present invention is laterally arranged
  • Fig. 6 is a scheme of different insulating fins of the scheme in Fig. 1 according to the present invention.
  • Fig. 7 is a schematic diagram of the internal structure of the power semiconductor module solution of the embodiment of the present invention, where the extension part of the metal lead frame is replaced by a metal bonding wire.
  • the novel packaging structure of a power semiconductor module mainly includes an insulating heat sink 1, a metal lead frame unit and a chip unit 2 arranged on the insulating heat sink, and the metal lead frame unit
  • the material is copper or copper alloy
  • the insulating heat sink adopts a double-sided metal layer with a ceramic layer in the middle, which includes an insulating layer 3 and an inner metal conductive layer 4 and an outer metal conductive layer respectively arranged on both sides of the insulating layer 3.
  • the middle part of the inner metal conductive layer 4 is a flat welding chip area
  • the metal lead frame unit mainly includes a frame pin input part 6, a frame pin output part 7 and a frame pin signal part 8, the frame lead
  • the pin input part 6 is arranged on the upper side of the inner metal conductive layer 4 by means of solder welding
  • the chip unit 2 is welded on the middle position of the inner metal conductive layer 4, and the frame pin output part 7 is provided with a
  • the inner concave part 9 corresponding to the position of the unit 2 is welded and fixed to the chip unit 2 through the outer end surface of the inner concave part 9, and the inner concave part 9 corresponding to the position of the chip unit is welded and fixed to the chip unit 2 through the outer end surface of the inner concave part 9
  • High-density metal bonding wires 14 can also be used for ultrasonic welding instead, and the signal part of the chip unit 2 is connected to the frame pin signal part 8 through the metal bonding wire 10 for ultrasonic bonding; the insul
  • the chip unit 2 of the present invention may be a silicon-based chip or a silicon carbide-based chip or a gallium nitride-based IGBT/DIODE/MOSFET chip.
  • Both the inner metal conductive layer 4 and the outer metal conductive layer 5 are made of aluminum or copper material whose surface is integrally plated with gold; the metal bonding wire 10 is made of aluminum or copper material.
  • the inner concave portion 9 is a groove formed by sinking or extruding the metal sheet extended on the frame pin output portion 7, and the number, shape and size of the groove are the same as those of the The chip units are matched, and the outer surface of the groove is smooth and free of burrs.
  • the arrangement of the grooves can be vertical, horizontal or other possible arrangements as shown in Figures 5a and 5b.
  • the grooves are all completely set on the wall surface of the frame pin output part 7 or one is set on the upper side wall surface of the frame pin output part 7 and forms a notch 12 .
  • the frame pin output part 7 is provided with a bent edge 13 so that the output pin of the frame pin output part 7 is flush with the input pin of the frame pin input part 6, and the frame pin input part Both the 6 and the frame pin output part 7 are provided with etching grooves or circular holes for reducing mechanical stress and increasing bonding force with injection molding materials.
  • the inner metal conductive layer 4 of the insulating heat sink 1 is etched with a channel for leading out electrical signals to the chip unit 2 , and the signal part of the chip unit 2 is bonded by a metal bonding wire 10 Go to the separate channel of the inner metal conductive layer 4 and jump to the frame pin signal part 8 to lead out the chip signal.
  • the inner concave part 9 and the chip unit 2 are welded by reflow soldering, and the solder material is solder with a melting point higher than 260°C; the inner metal conductive layer 4 and the chip unit 2 are sintered with silver paste or tin solder Welding is done by welding.
  • the present invention provides a new packaging structure for power semiconductor modules, which optimizes the area of the chip loading area, increases the upper limit of the rated current of the package, and uses a metal sinking groove structure to weld the chip on both sides to increase the heat capacity; Current capacity, the sheet metal lead frame structure is adopted in the layout, the upper and lower structure of the stack is maintained in the circuit design, the parasitic inductance and resistance of the module are reduced, and the voltage stress of the chip is reduced. Performance acquisition reduces the signal interference caused by the induced electromotive force generated by the common terminal; greatly improves the output power, safety and reliability while ensuring the heat dissipation efficiency.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了一种功率半导体模块的新型封装结构，主要包括绝缘散热片、金属引线框架单元和芯片单元，所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层，所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部，所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧，所述芯片单元焊接在内金属导电层的中间位置上，所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定，所述芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定也可采用高排布密度金属键合引线超声波焊接进行替代，芯片单元的信号部分通过金属键合引线与所述框架引脚信号部进行连接；所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆。

Description

一种功率半导体模块的新型封装结构 技术领域
本发明涉及电力电子学领域，具体涉及一种功率半导体模块的新型封装结构。
背景技术
目前场效应晶体管模块在变频器，焊机，感应加热，不间断电源，风力发电与电动汽车领域的应用越来越广泛，以上的各个领域对于功率半导体器件来说，封装的体积，功率密度，可靠性等各方面的要求也越来越严苛。
在传统的功率半导体模块封装中，为良好的可靠性和散热条件，以及功率密度之间平衡，功率半导体模块为更高的功率密度，体积不断趋于庞大，对于外部的散热器条件和安装要求也不断提高。传统封装的功率半导体模块在客户端安装中需要加装绝缘垫片或者涂覆导热材料，提升了封装的接触热阻，降低了封装的散热效率和芯片的抗冲击能力。传统封装的功率半导体模块内部多采用铜线或者铝线键合的方式进行电性能连接，且键合线密度取决于使用电流和成本考虑，键合线的数量较少导致键合铝线和功率端子形成的电路势必存在较大的寄生电感和电阻，在关断过程中会造成较大的电压应力施加在芯片上。
发明内容
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种功率半导体模块的新型封装结构，以解决现有技术情况下散热效率低，功率密度低，寄生电感和电阻大等问题。
本发明的目的是通过如下技术方案来完成的，一种功率半导体模块的新型封装结构，主要包括绝缘散热片及设置在该绝缘散热片上的金属引线框架单元和芯片单元，所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层，内金属导电层的中间部分为平整焊接芯片区域，所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部，所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧，所述芯片单元焊接在内金属导电层的中间位置上，所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定，所述芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定也可采用高排布密度金属键合引线超声波焊接进行替代，芯片单元的信号部分通过金属键合引线进行超声波键合与所述框架引脚信号部进行连接；所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆且所述绝缘散热片的外金属导电层外露于塑 封体并与塑封体的外壁齐平。
进一步地，所述内凹部为框架引脚输出部上通过打沉或挤压形成的凹槽，该凹槽的数量、形状及大小与所述芯片单元相匹配，可以横向设置也可以纵向设置，且所述凹槽的外表面光滑无毛刺；所述凹槽均完整设置在框架引脚输出部的壁面上或有一个设置在框架引脚输出部的上侧壁面上并形成凹缺口。
进一步地，所述采用高密度金属键合引线进行超声波焊接，金属键合引线采用在所述芯片的表面尽可能多的排列，以达到芯片能承载最大密度进行排布。
进一步地，所述框架引脚输出部上设置有弯折边以使得框架引脚输出部的输出引脚与框架引脚输入部的输入引脚保持齐平，且所述框架引脚输入部和框架引脚输出部上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
进一步地，所述绝缘散热片的内金属导电层上蚀刻有用于对芯片单元进行电信号引出的沟道，所述芯片单元的信号部分通过金属键合引线键合到内金属导电层的单独沟道上并跳点到框架引脚信号部进行芯片信号的引出。
进一步地，所述绝缘散热片的内金属导电层上蚀刻出的沟道可以为一条，可以为两条或者更多条，用于不用的芯片单元进行信号极的引出。
进一步地，所述内凹部与芯片单元之间通过回流焊接的方式进行焊接，焊接材料为熔点高于260℃的焊料；所述内金属导电层与芯片单元之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
进一步地，所述内金属导电层和外金属导电层均为铝或表面整体镀金的铜材料制成；所述金属键合引线为铝或铜材料制成。
本发明的有益技术效果在于：本发明提供了一种功率半导体模块的新型封装结构，对芯片装载区域面积优化，提高封装的额定电流上限，并使用金属打沉的凹槽结构对芯片进行双面焊接，增加热容；提升过电流能力，布局上采用片状金属引线框架结构，电路设计上保持叠层的上下结构，降低模块的寄生电感和电阻，减小芯片的电压应力，信号端子的采用极限的接近芯片表面来进行电性能采集，减少了公共端子产生的感应电动势造成信号的干扰；在保证散热效率的情况下大幅度提升输出功率、安全与可靠性。
附图说明
图1为本发明所述的封装结构整体结构示意图；
图2为图1的侧视结构示意图；
图3为本发明所述封装结构采用的金属引线框架多引线单元条带的结构示意图；
图4为本发明所述封装结构的另一种结构示意图；
图5a 5b为本发明所述凹槽横向布置时的结构示意图；
图6为本发明所述图1方案的不同绝缘散热片方案。
图7为本实用新型实施例的功率半导体模块方案中金属引线框延伸部分用金属键合引线代替的内部结构示意图。
具体实施方式
为使本领域的普通技术人员更加清楚地理解本发明的目的、技术方案和优点，以下结合附图和实施例对本发明做进一步的阐述。
在本发明的描述中，需要理解的是，“上”、“下”、“左”、“右”、“内”、“外”、“横向”、“竖向”等术语所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明，而不是指示或暗示所指的装置或原件必须具有特定的方位，因此不能理解为对本发明的限制。
如图1-7所示，本发明所述的一种功率半导体模块的新型封装结构，主要包括绝缘散热片1及设置在该绝缘散热片上的金属引线框架单元和芯片单元2，金属引线框架单元的材质为铜或铜合金，所述绝缘散热片采用双面金属层中间夹杂陶瓷层的结构，其包括绝缘层3及分别设置在该绝缘层3两侧的内金属导电层4和外金属导电层5，内金属导电层4的中间部分为平整焊接芯片区域，所述金属引线框架单元主要包括框架引脚输入部6、框架引脚输出部7及框架引脚信号部8，所述框架引脚输入部6通过焊料焊接的方式设置在内金属导电层4的上侧，所述芯片单元2焊接在内金属导电层4的中间位置上，所述框架引脚输出部7上设置有与芯片单元2位置对应的内凹部9并通过该内凹部9的外端面与芯片单元2进行焊接固定，述芯片单元位置对应的内凹部9并通过该内凹部9的外端面与芯片单元2进行焊接固定也可采用高密度金属键合引线14超声波焊接进行替代，芯片单元2的信号部分通过金属键合引线10进行超声波键合与所述框架引脚信号部8进行连接；所述绝缘散热片1、芯片单元2及框架引脚输出部7上的内凹部9均由塑封体11进行包覆且所述绝缘散热片1的外金属导电层5外露于塑封体11并与塑封体11的外壁齐平，外露的一面完全镀金或镀银且保持外露不被塑封体覆盖。
本发明所述芯片单元2可以为硅基芯片也可以为碳化硅基芯片或者氮化镓基的IGBT/DIODE/MOSFET芯片。所述内金属导电层4和外金属导电层5均为铝或表面整体镀金 的铜材料制成；所述金属键合引线10为铝或铜材料制成。整体模块制造完成后通过外包覆塑封体的方式进行相对位置的固定，从而有效提高了框架引脚输入部和框架引脚输出部对应金属引脚间的爬电距离与整体可靠性。
参照图1-5所示，所述内凹部9为在框架引脚输出部7上延展出的金属薄片通过打沉或挤压形成的凹槽，该凹槽的数量、形状及大小与所述芯片单元相匹配，且所述凹槽的外表面光滑无毛刺，凹槽排列可以为竖向，也可以为横向或其他可能的排列情况如图5a与5b。所述凹槽均完整设置在框架引脚输出部7的壁面上或有一个设置在框架引脚输出部7的上侧壁面上并形成凹缺口12。所述框架引脚输出部7上设置有弯折边13以使得框架引脚输出部7的输出引脚与框架引脚输入部6的输入引脚保持齐平，且所述框架引脚输入部6和框架引脚输出部7上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
参照图1所示，所述绝缘散热片1的内金属导电层4上蚀刻有用于对芯片单元2进行电信号引出的沟道，所述芯片单元2的信号部分通过金属键合引线10键合到内金属导电层4的单独沟道上并跳点到框架引脚信号部8进行芯片信号的引出。所述内凹部9与芯片单元2之间通过回流焊接的方式进行焊接，焊接材料为熔点高于260℃的焊料；所述内金属导电层4与芯片单元2之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
本发明提供了一种功率半导体模块的新型封装结构，对芯片装载区域面积优化，提高封装的额定电流上限，并使用金属打沉的凹槽结构对芯片进行双面焊接，增加热容；提升过电流能力，布局上采用片状金属引线框架结构，电路设计上保持叠层的上下结构，降低模块的寄生电感和电阻，减小芯片的电压应力，信号端子的采用极限的接近芯片表面来进行电性能采集，减少了公共端子产生的感应电动势造成信号的干扰；在保证散热效率的情况下大幅度提升输出功率、安全与可靠性。
本文中所描述的具体实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，但凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

  1. 一种功率半导体模块的新型封装结构，主要包括绝缘散热片及设置在该绝缘散热片上的金属引线框架单元和芯片单元，其特征在于：所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层，所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部，所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧，所述芯片单元焊接在内金属导电层的中间位置上，所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定，芯片单元的信号部分通过金属键合引线进行超声波键合与所述框架引脚信号部进行连接；所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆且所述绝缘散热片的外金属导电层外露于塑封体并与塑封体的外壁齐平。
  2. 根据权利要求1所述的功率半导体模块的新型封装结构，其特征在于：所述内凹部为框架引脚输出部上通过打沉或挤压形成的凹槽，该凹槽的数量、形状及大小与所述芯片单元相匹配，且所述凹槽的外表面光滑无毛刺；所述凹槽均完整设置在框架引脚输出部的壁面上或有一个设置在框架引脚输出部的上侧壁面上并形成凹缺口。
  3. 根据权利要求1所述的功率半导体模块的新型封装结构，其特征在于：所述框架引脚输出部上设置有与芯片单元位置对应的内凹部结构连接芯片部分可以使用高排布密度金属键合引线进行替代连接。
  4. 根据权利要求1或2所述的功率半导体模块的新型封装结构，其特征在于：所述框架引脚输出部上设置有弯折边以使得框架引脚输出部的输出引脚与框架引脚输入部的输入引脚保持齐平，且所述框架引脚输入部和框架引脚输出部上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
  5. 根据权利要求1所述的功率半导体模块的新型封装结构，其特征在于：所述绝缘散热片的内金属导电层上蚀刻有用于对芯片单元进行电信号引出的沟道，所述芯片单元的信号部分通过金属键合引线键合到内金属导电层的单独沟道上并跳点到框架引脚信号部进行芯片信号的引出。
  6. 根据权利要求1或2或5所述的功率半导体模块的新型封装结构，其特征在于：所述内凹部与芯片单元之间通过回流焊接的方式进行焊接，焊接材料为熔点高于260℃的焊料；所述内金属导电层与芯片单元之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
  7. 根据权利要求6所述的功率半导体模块的新型封装结构，其特征在于：所述内金属导电层和外金属导电层均为铝或表面整体镀金的铜材料制成；所述金属键合引线为铝或 铜材料制成。
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