CN215578525U - 一种功率半导体模块的新型封装结构 - Google Patents

一种功率半导体模块的新型封装结构 Download PDF

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CN215578525U
CN215578525U CN202121660635.6U CN202121660635U CN215578525U CN 215578525 U CN215578525 U CN 215578525U CN 202121660635 U CN202121660635 U CN 202121660635U CN 215578525 U CN215578525 U CN 215578525U
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封丹婷
房军军
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Star Semiconductor Co ltd
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STARPOWER SEMICONDUCTOR Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

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Abstract

本实用新型公开了一种功率半导体模块的新型封装结构,主要包括绝缘散热片、金属引线框架单元和芯片单元,所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层,所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部,所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧,所述芯片单元焊接在内金属导电层的中间位置上,所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定,芯片单元的信号部分通过金属键合引线与所述框架引脚信号部进行连接;所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆。

Description

一种功率半导体模块的新型封装结构
技术领域
本实用新型涉及电力电子学领域,具体涉及一种功率半导体模块的新型封装结构。
背景技术
目前场效应晶体管模块在变频器,焊机,感应加热,不间断电源,风力发电与电动汽车领域的应用越来越广泛,以上的各个领域对于功率半导体器件来说,封装的体积,功率密度,可靠性等各方面的要求也越来越严苛。
在传统的功率半导体模块封装中,为良好的可靠性和散热条件,以及功率密度之间平衡,功率半导体模块为更高的功率密度,体积不断趋于庞大,对于外部的散热器条件和安装要求也不断提高。传统封装的功率半导体模块在客户端安装中需要加装绝缘垫片或者涂覆导热材料,提升了封装的接触热阻,降低了封装的散热效率和芯片的抗冲击能力。传统封装的功率半导体模块内部多采用铜线或者铝线键合的方式进行电性能连接,键合铝线和功率端子形成的电路势必存在较大的寄生电感和电阻,在关断过程中会造成较大的电压应力施加在芯片上。
发明内容
本实用新型要解决的技术问题在于,针对现有技术的上述缺陷,提供一种功率半导体模块的新型封装结构,以解决现有技术情况下散热效率低,功率密度低,寄生电感和电阻大等问题。
本实用新型的目的是通过如下技术方案来完成的,一种功率半导体模块的新型封装结构,主要包括绝缘散热片及设置在该绝缘散热片上的金属引线框架单元和芯片单元,所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层,内金属导电层的中间部分为平整焊接芯片区域,所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部,所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧,所述芯片单元焊接在内金属导电层的中间位置上,所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定,芯片单元的信号部分通过金属键合引线进行超声波键合与所述框架引脚信号部进行连接;所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆且所述绝缘散热片的外金属导电层外露于塑封体并与塑封体的外壁齐平。
进一步地,所述内凹部为框架引脚输出部上通过打沉或挤压形成的凹槽,该凹槽的数量、形状及大小与所述芯片单元相匹配,可以横向设置也可以纵向设置,且所述凹槽的外表面光滑无毛刺;所述凹槽均完整设置在框架引脚输出部的壁面上或有一个设置在框架引脚输出部的上侧壁面上并形成凹缺口。
进一步地,所述框架引脚输出部上设置有弯折边以使得框架引脚输出部的输出引脚与框架引脚输入部的输入引脚保持齐平,且所述框架引脚输入部和框架引脚输出部上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
进一步地,所述绝缘散热片的内金属导电层上蚀刻有用于对芯片单元进行电信号引出的沟道,所述芯片单元的信号部分通过金属键合引线键合到内金属导电层的单独沟道上并跳点到框架引脚信号部进行芯片信号的引出。所述绝缘散热片的内金属导电层上蚀刻出的沟道可以为一条,可以为两条或者更多条,用于不用的芯片单元进行信号极的引出。
进一步地,所述内凹部与芯片单元之间通过回流焊接的方式进行焊接,焊接材料为熔点高于260℃的焊料;所述内金属导电层与芯片单元之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
进一步地,所述内金属导电层和外金属导电层均为铝或表面整体镀金的铜材料制成;所述金属键合引线为铝或铜材料制成。
本实用新型的有益技术效果在于:本实用新型提供了一种功率半导体模块的新型封装结构,对芯片装载区域面积优化,提高封装的额定电流上限,并使用金属打沉的凹槽结构对芯片进行双面焊接,增加热容;提升过电流能力,布局上采用片状金属引线框架结构,电路设计上保持叠层的上下结构,降低模块的寄生电感和电阻,减小芯片的电压应力,信号端子的采用极限的接近芯片表面来进行电性能采集,减少了公共端子产生的感应电动势造成信号的干扰;在保证散热效率的情况下大幅度提升输出功率、安全与可靠性。
附图说明
图1为本实用新型所述的封装结构整体结构示意图;
图2为图1的侧视结构示意图;
图3为本实用新型所述封装结构采用的金属引线框架多引线单元条带的结构示意图;
图4为本实用新型所述封装结构的另一种结构示意图;
图5为本实用新型所述凹槽横向布置时的结构示意图;
图6为本实用新型所述图1方案的不同绝缘散热片方案。
具体实施方式
为使本领域的普通技术人员更加清楚地理解本实用新型的目的、技术方案和优点,以下结合附图和实施例对本实用新型做进一步的阐述。
在本实用新型的描述中,需要理解的是,“上”、“下”、“左”、“右”、“内”、“外”、“横向”、“竖向”等术语所指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本实用新型,而不是指示或暗示所指的装置或原件必须具有特定的方位,因此不能理解为对本实用新型的限制。
如图1-6所示,本实用新型所述的一种功率半导体模块的新型封装结构,主要包括绝缘散热片1及设置在该绝缘散热片上的金属引线框架单元和芯片单元2,金属引线框架单元的材质为铜或铜合金,所述绝缘散热片采用双面金属层中间夹杂陶瓷层的结构,其包括绝缘层3及分别设置在该绝缘层3两侧的内金属导电层4和外金属导电层5,内金属导电层4的中间部分为平整焊接芯片区域,所述金属引线框架单元主要包括框架引脚输入部6、框架引脚输出部7及框架引脚信号部8,所述框架引脚输入部6通过焊料焊接的方式设置在内金属导电层4的上侧,所述芯片单元2焊接在内金属导电层4的中间位置上,所述框架引脚输出部7上设置有与芯片单元2位置对应的内凹部9并通过该内凹部9的外端面与芯片单元2进行焊接固定,芯片单元2的信号部分通过金属键合引线10进行超声波键合与所述框架引脚信号部8进行连接;所述绝缘散热片1、芯片单元2及框架引脚输出部7上的内凹部9均由塑封体11进行包覆且所述绝缘散热片1的外金属导电层5外露于塑封体11并与塑封体11的外壁齐平,外露的一面完全镀金或镀银且保持外露不被塑封体覆盖。
本实用新型所述芯片单元2可以为硅基芯片也可以为碳化硅基芯片或者氮化镓基的IGBT/DIODE/MOSFET芯片。所述内金属导电层4和外金属导电层5均为铝或表面整体镀金的铜材料制成;所述金属键合引线10为铝或铜材料制成。整体模块制造完成后通过外包覆塑封体的方式进行相对位置的固定,从而有效提高了框架引脚输入部和框架引脚输出部对应金属引脚间的爬电距离与整体可靠性。
参照图1-5所示,所述内凹部9为在框架引脚输出部7上延展出的金属薄片通过打沉或挤压形成的凹槽,该凹槽的数量、形状及大小与所述芯片单元相匹配,且所述凹槽的外表面光滑无毛刺,凹槽排列可以为竖向,也可以为横向或其他可能的排列情况。所述凹槽均完整设置在框架引脚输出部7的壁面上或有一个设置在框架引脚输出部7的上侧壁面上并形成凹缺口12。所述框架引脚输出部7上设置有弯折边13以使得框架引脚输出部7的输出引脚与框架引脚输入部6的输入引脚保持齐平,且所述框架引脚输入部6和框架引脚输出部7上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
参照图1所示,所述绝缘散热片1的内金属导电层4上蚀刻有用于对芯片单元2进行电信号引出的沟道,所述芯片单元2的信号部分通过金属键合引线10键合到内金属导电层4的单独沟道上并跳点到框架引脚信号部8进行芯片信号的引出。所述绝缘散热片的内金属导电层上蚀刻出的沟道可以为一条,可以为两条或者更多条,用于不用的芯片单元进行信号极的引出。所述内凹部9与芯片单元2之间通过回流焊接的方式进行焊接,焊接材料为熔点高于260℃的焊料;所述内金属导电层4与芯片单元2之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
本实用新型提供了一种功率半导体模块的新型封装结构,对芯片装载区域面积优化,提高封装的额定电流上限,并使用金属打沉的凹槽结构对芯片进行双面焊接,增加热容;提升过电流能力,布局上采用片状金属引线框架结构,电路设计上保持叠层的上下结构,降低模块的寄生电感和电阻,减小芯片的电压应力,信号端子的采用极限的接近芯片表面来进行电性能采集,减少了公共端子产生的感应电动势造成信号的干扰;在保证散热效率的情况下大幅度提升输出功率、安全与可靠性。
本文中所描述的具体实施例仅例示性说明本实用新型的原理及其功效,而非用于限制本实用新型。任何熟悉此技术的人士皆可在不违背本实用新型的精神及范畴下,对上述实施例进行修饰或改变。因此,但凡所属技术领域中具有通常知识者在未脱离本实用新型所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本实用新型的权利要求所涵盖。

Claims (6)

1.一种功率半导体模块的新型封装结构,主要包括绝缘散热片及设置在该绝缘散热片上的金属引线框架单元和芯片单元,其特征在于:所述绝缘散热片包括绝缘层及分别设置在该绝缘层两侧的内金属导电层和外金属导电层,所述金属引线框架单元主要包括框架引脚输入部、框架引脚输出部及框架引脚信号部,所述框架引脚输入部通过焊料焊接的方式设置在内金属导电层的上侧,所述芯片单元焊接在内金属导电层的中间位置上,所述框架引脚输出部上设置有与芯片单元位置对应的内凹部并通过该内凹部的外端面与芯片单元进行焊接固定,芯片单元的信号部分通过金属键合引线进行超声波键合与所述框架引脚信号部进行连接;所述绝缘散热片、芯片单元及框架引脚输出部上的内凹部均由塑封体进行包覆且所述绝缘散热片的外金属导电层外露于塑封体并与塑封体的外壁齐平。
2.根据权利要求1所述的功率半导体模块的新型封装结构,其特征在于:所述内凹部为框架引脚输出部上通过打沉或挤压形成的凹槽,该凹槽的数量、形状及大小与所述芯片单元相匹配,且所述凹槽的外表面光滑无毛刺;所述凹槽均完整设置在框架引脚输出部的壁面上或有一个设置在框架引脚输出部的上侧壁面上并形成凹缺口。
3.根据权利要求1或2所述的功率半导体模块的新型封装结构,其特征在于:所述框架引脚输出部上设置有弯折边以使得框架引脚输出部的输出引脚与框架引脚输入部的输入引脚保持齐平,且所述框架引脚输入部和框架引脚输出部上均设置有用于减少机械应力及增加与注塑料结合力的蚀刻槽或圆孔。
4.根据权利要求3所述的功率半导体模块的新型封装结构,其特征在于:所述绝缘散热片的内金属导电层上蚀刻有用于对芯片单元进行电信号引出的沟道,所述芯片单元的信号部分通过金属键合引线键合到内金属导电层的单独沟道上并跳点到框架引脚信号部进行芯片信号的引出。
5.根据权利要求1或2或4所述的功率半导体模块的新型封装结构,其特征在于:所述内凹部与芯片单元之间通过回流焊接的方式进行焊接,焊接材料为熔点高于260℃的焊料;所述内金属导电层与芯片单元之间通过银浆烧结或者锡焊料焊接的方式进行焊接。
6.根据权利要求5所述的功率半导体模块的新型封装结构,其特征在于:所述内金属导电层和外金属导电层均为铝或表面整体镀金的铜材料制成;所述金属键合引线为铝或铜材料制成。
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CN113517244A (zh) * 2021-07-21 2021-10-19 嘉兴斯达半导体股份有限公司 一种功率半导体模块的新型封装结构

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517244A (zh) * 2021-07-21 2021-10-19 嘉兴斯达半导体股份有限公司 一种功率半导体模块的新型封装结构

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