WO2023000655A1 - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- WO2023000655A1 WO2023000655A1 PCT/CN2022/076280 CN2022076280W WO2023000655A1 WO 2023000655 A1 WO2023000655 A1 WO 2023000655A1 CN 2022076280 W CN2022076280 W CN 2022076280W WO 2023000655 A1 WO2023000655 A1 WO 2023000655A1
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 that is Chemical compound 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a method for forming the same.
- Dynamic random access memory is a semiconductor structure commonly used in electronic equipment such as computers. It is composed of a plurality of storage units, and each storage unit usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored data can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
- DRAM Dynamic Random Access Memory
- NBTI Negative-bias temperature instability
- the present application provides a semiconductor structure and a forming method thereof, which are used to solve the problem that the PMOS device in the semiconductor structure is prone to NBTI effect, so as to improve the service life and performance reliability of the semiconductor structure.
- the present application provides a method for forming a semiconductor structure, comprising the following steps:
- a substrate comprising a first region for forming a first transistor and a second region for forming a second transistor
- first initial gate dielectric layer on the surface of the first region, and forming a second initial gate dielectric layer on the surface of the second region;
- the thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer The thickness of the dielectric layer.
- the present application also provides a semiconductor structure, which is formed by using any one of the methods for forming a semiconductor structure described above.
- the dopant element is implanted into the first initial gate dielectric layer and the second initial gate dielectric layer.
- the initial gate dielectric layer thin the first initial gate dielectric layer and the second initial gate dielectric layer, so as to ensure that the implanted doping elements are concentrated on the surface of the first gate dielectric layer and the The surface of the second gate dielectric layer effectively reduces the concentration of doping elements on the bottom surface of the first gate dielectric layer and the bottom surface of the second gate dielectric layer, improves the NBTI effect of the first transistor and the second transistor, and improves the semiconductor The service life and performance reliability of the structure.
- 2A-2I are schematic cross-sectional views of main processes in the process of forming a semiconductor structure according to specific embodiments of the present application.
- This specific embodiment provides a method for forming a semiconductor structure.
- Accompanying drawing 1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present application
- accompanying drawings 2A-2I are the process of forming the semiconductor structure in the specific embodiment of the present application. Schematic diagram of the main process section. As shown in Fig. 1, Fig. 2A-Fig. 2I, the formation method of described semiconductor structure comprises the following steps:
- Step S11 providing a substrate, the substrate includes a first region 21 for forming a first transistor and a second region 22 for forming a second transistor, as shown in FIG. 2A .
- the substrate may be, but not limited to, a silicon substrate, and this specific embodiment is described by taking the silicon substrate as an example for description.
- the substrate may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
- the substrate has the first region 21 and the second region 22, the first region 21 is isolated from the surrounding device regions by a shallow trench isolation structure 23, and the second region 22 is also separated by the The shallow trench isolation structure 23 is isolated from surrounding device regions.
- the material of the shallow trench isolation structure 23 may be but not limited to oxide material.
- the first region 21 and the second region 22 may be adjacent to each other, or may be separated by several device regions.
- the first transistor and the second transistor may be transistors with different threshold voltages, for example, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
- both the first transistor and the second transistor are PMOS transistors.
- Step S12 forming a first initial gate dielectric layer on the surface of the first region 21 , and forming a second initial gate dielectric layer on the surface of the second region 22 , as shown in FIG. 2F .
- the specific steps of forming a first initial gate dielectric layer on the surface of the first region 21 and forming a second initial gate dielectric layer on the surface of the second region 22 include:
- the specific steps of forming the first dielectric layer 24 on the surface of the first region 21 include:
- the first dielectric layer 24 covering the surface of the second region 22 is removed, as shown in FIG. 2E .
- the specific steps of removing the first dielectric layer 24 covering the surface of the second region 22 include:
- the barrier layer 25 covers the first dielectric layer 24 located on the surface of the first region 21, as shown in FIG. 2C;
- the blocking layer 25 is removed, as shown in FIG. 2E .
- the first dielectric layer 24 is formed on the surface of the first region 21 and the surface of the second region 22 of the substrate.
- the material of the first dielectric layer 24 may be, but not limited to, an oxide material, such as silicon dioxide.
- the thickness of the first dielectric layer 24 can be appropriately increased.
- the specific thickness of the first dielectric layer 24 can be adjusted according to actual needs, for example, according to the thickness of the first gate dielectric layer to be formed and the specific deposition process type used.
- the first dielectric layer 24 located on the second region 22 may be removed by using a dry etching process or a wet etching process, so that the surface of the second region 22 of the substrate is exposed, As shown in Figure 2D. After removing the barrier layer 25, a structure as shown in FIG. 2E is obtained.
- the second dielectric layer 26 can be used to deposit the second dielectric layer 26 on the surface of the second region 22 and the remaining surface of the first dielectric layer 24, as shown in FIG. Structure shown in 2F.
- the thickness of the second dielectric layer 26 can be appropriately increased.
- the specific thickness of the second dielectric layer 26 can be adjusted according to actual needs, for example, according to the thickness of the second gate dielectric layer to be formed and the specific deposition process type used.
- those skilled in the art may directly deposit the first dielectric layer 24 only on the surface of the first region 21 according to actual needs, so as to further simplify the formation process of the semiconductor structure.
- the material of the first dielectric layer 24 is the same as that of the second dielectric layer 26 .
- the materials of the first dielectric layer 24 and the second dielectric layer 26 are both oxide materials, such as silicon dioxide.
- the material of the first dielectric layer 24 may also be different from that of the second dielectric layer 26 .
- the thickness of the first dielectric layer 24 is greater than the thickness of the second dielectric layer 26 .
- Step S13 implanting doping elements into the first initial gate dielectric layer and the second initial gate dielectric layer.
- the implantation of the dopant element can reduce the leakage problem of the subsequently formed first gate and the second gate, and can effectively block the conduction in the first gate and the second gate. Particles diffuse into the substrate.
- the doping element may be but not limited to nitrogen.
- the specific step of implanting the doping element into the first initial gate dielectric layer and the second initial gate dielectric layer includes:
- Nitrogen is implanted into the first initial gate dielectric layer and the second initial gate dielectric layer by using a remote plasma nitriding (RPN) process.
- RPN remote plasma nitriding
- a remote plasma nitriding process can be used to form the top surface of the first initial gate dielectric layer (that is, the first initial gate dielectric layer is away from the substrate).
- bottom surface) and the top surface of the second initial gate dielectric layer (that is, the surface of the second initial gate dielectric layer away from the substrate) is implanted with nitrogen, that is, nitrogen is implanted onto the first region 21 In the first dielectric layer 24 and the second dielectric layer 26, nitrogen is implanted into the second dielectric layer 26 on the second region 22 to obtain the structure shown in FIG. 2G.
- Step S14 thinning the first initial gate dielectric layer and the second initial gate dielectric layer to form the first gate dielectric layer 27 and the second gate dielectric layer 28, the thickness of the first gate dielectric layer 27 is greater than the thickness of the second gate dielectric layer 28, as shown in FIG. 2H.
- the thicknesses of the first initial gate dielectric layer and the second initial gate dielectric layer formed before doping under the condition that the dopant element implantation depth and/or implantation amount remain unchanged , can reduce the bottom surface of the first initial gate dielectric layer (that is, the surface of the first initial gate dielectric layer in contact with the substrate) and the bottom surface of the second initial gate dielectric layer (that is, the second initial gate dielectric layer The concentration of the doping element on the surface of the dielectric layer in contact with the substrate), thereby reducing the NBTI effect.
- thinning the first initial gate dielectric layer and the second initial gate dielectric layer can make the first gate dielectric layer 27 reach a first preset thickness, and the second gate dielectric layer 28 have a thickness reaching The second predetermined thickness means that the thickness of the first gate dielectric layer 27 and the second gate dielectric layer 28 will not be increased.
- the specific steps of thinning the first initial gate dielectric layer and the second initial gate dielectric layer include:
- the specific steps of removing part of the first initial gate dielectric layer and part of the second initial gate dielectric layer using a wet etching process include:
- a wet etching process is used to remove part of the second dielectric layer 26 in the first initial gate dielectric layer and part of the second initial gate dielectric layer.
- a cleaning process may be used to remove part of the second dielectric layer in the first initial gate dielectric layer and part of the second initial gate dielectric layer, leaving the The first dielectric layer 24 and the second dielectric layer 26 together serve as the first gate dielectric layer 27 .
- the cleaning process removes part of the thickness of the second dielectric layer 26 above the second region 22, and the second dielectric layer 26 remaining above the second region 22 is used as the second gate dielectric layer. 28.
- the surface of the first gate dielectric layer 27 in contact with the substrate does not contain the doping element
- the surface of the second gate dielectric layer 28 in contact with the substrate does not contain the doping element.
- the surface of the finally formed first gate dielectric layer 27 in contact with the substrate does not have the doped
- the impurity element, the surface of the second gate dielectric layer 28 in contact with the substrate does not have the doping element, so as to further improve the reliability of the NBTI effect.
- the following steps are further included:
- a first gate 29 is formed on the surface of the first gate dielectric layer 27, and a second gate 30 is formed on the surface of the second gate dielectric layer 28.
- the specific steps of forming the first gate 29 on the surface of the first gate dielectric layer 27 and forming the second gate 30 on the surface of the second gate dielectric layer 30 include:
- a conductive material is deposited on the surface of the first gate dielectric layer 27 and the surface of the second gate dielectric layer 28 to form the first gate 29 and the second gate 30 at the same time.
- the conductive material may be but not limited to doped polysilicon material.
- the present application also provides a semiconductor structure, which is formed by using any one of the methods for forming a semiconductor structure described above.
- the first initial gate dielectric layer and the second initial gate dielectric layer are implanted with doping elements.
- the dielectric layer thin the first initial gate dielectric layer and the second initial gate dielectric layer, so as to ensure that the implanted doping elements are concentrated on the surface of the first gate dielectric layer and the second initial gate dielectric layer.
- the surface of the gate dielectric layer effectively reduces the concentration of doping elements on the bottom surface of the first gate dielectric layer and the bottom surface of the second gate dielectric layer, improves the NBTI effect of the first transistor and the second transistor, and improves the stability of the semiconductor structure. Longevity and performance reliability.
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
半导体结构的形成方法包括如下步骤:提供衬底,衬底包括第一区域和第二区域;形成第一初始栅介质层于第一区域、并形成第二初始栅介质层于第二区域;注入掺杂元素至第一初始栅介质层和第二初始栅介质层;减薄第一初始栅介质层和第二初始栅介质层,形成第一栅介质层和第二栅介质层,第一栅介质层的厚度大于第二栅介质层的厚度。本申请改善了第一晶体管和第二晶体管的NBTI效应。
Description
相关申请引用说明
本申请要求于2021年07月21日递交的中国专利申请号202110825385.5、申请名为“半导体结构及其形成方法”的优先权,其全部内容以引用的形式附录于此。
本申请涉及半导体制造技术领域,尤其涉及一种半导体结构及其形成方法。
动态随机存储器(Dynamic Random Access Memory,DRAM)是计算机等电子设备中常用的半导体结构,其由多个存储单元构成,每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接,字线上的字线电压能够控制晶体管的开启与关闭,从而通过位线能够读取存储在电容器中的数据信息,或者将数据信息写入到电容器中。
但是,对于动态随机存储器等半导体结构中的PMOS而言,随着集成电路特征尺寸的缩小,栅电场增加,PMOS器件的工作温度升高,器件参数(例如阈值电压、跨导和驱动电流)等会产生退化,导致负偏压温度不稳定(Negative-bias temperature instability,NBTI)效应的出现。NBTI效应会严重影响半导体结构的使用寿命以及性能可靠性。
因此,如何降低NBTI效应的影响,提高半导体结构的使用寿命和性能可靠性,是当前亟待解决的技术问题。
发明内容
本申请提供一种半导体结构及其形成方法,用于解决半导体结构中的PMOS器件易出现NBTI效应的问题,以提高半导体结构的使用寿命和性能可靠性。
根据一些实施例,本申请提供了一种半导体结构的形成方法,包括如下步骤:
提供衬底,所述衬底包括用于形成第一晶体管的第一区域和用于形成第二 晶体管的第二区域;
形成第一初始栅介质层于所述第一区域表面、并形成第二初始栅介质层于所述第二区域表面;
注入掺杂元素至所述第一初始栅介质层和所述第二初始栅介质层;
减薄所述第一初始栅介质层和所述第二初始栅介质层,形成第一栅介质层和所述第二栅介质层,所述第一栅介质层的厚度大于所述第二栅介质层的厚度。
根据一些实施例,本申请还提供了一种半导体结构,采用如上述任一项所述的半导体结构的形成方法形成。
本申请一些实施例中提供的半导体结构及其形成方法,通过增大第一初始栅介质层和第二初始栅介质层的厚度,在掺杂元素注入第一初始栅介质层和所述第二初始栅介质层之后,再减薄所述第一初始栅介质层和所述第二初始栅介质层,从而确保注入的所述掺杂元素集中于所述第一栅介质层的表面和所述第二栅介质层的表面,有效降低了所述第一栅介质层底面和所述第二栅介质层底面的掺杂元素浓度,改善了第一晶体管和第二晶体管的NBTI效应,提高了半导体结构的使用寿命和性能可靠性。
附图1是本申请具体实施方式中半导体结构的形成方法流程图;
附图2A-2I是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
下面结合附图对本申请提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法,附图1是本申请具体实施方式中半导体结构的形成方法流程图,附图2A-2I是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。如图1、图2A-图2I所示,所述半导体结构的形成方法,包括如下步骤:
步骤S11,提供衬底,所述衬底包括用于形成第一晶体管的第一区域21和用于形成第二晶体管的第二区域22,如图2A所示。
具体来说,所述衬底可以是但不限于硅衬底,本具体实施方式以所述衬底为硅衬底为例进行说明。在其他示例中,所述衬底可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底中具有所述第一区域21和所述第二区域22,所述第一区域21通过浅沟槽隔离结构23与周围的器件区域隔离,所述第二区域22也通过所述浅沟槽隔离结构23与周围的器件区域隔离。所述浅沟槽隔离结构23的材料可以是但不限于氧化物材料。所述第一区域21与所述第二区域22可以相邻,也可以间隔若干个器件区域。所述第一晶体管与所述第二晶体管可以是具有不同阈值电压的晶体管,例如所述第一晶体管的阈值电压大于所述第二晶体管的阈值电压。
在一些实施例中,所述第一晶体管和所述第二晶体管均为PMOS晶体管。
步骤S12,形成第一初始栅介质层于所述第一区域21表面、并形成第二初始栅介质层于所述第二区域22表面,如图2F所示。
在一些实施例中,形成第一初始栅介质层于所述第一区域21表面、并形成第二初始栅介质层于所述第二区域22表面的具体步骤包括:
形成第一介质层24于所述第一区域21表面;
形成第二介质层26于所述第一介质层24和所述第二区域22表面,所述第一介质层24和位于所述第一介质层24表面的所述第二介质26层共同作为第一初始栅介质层,位于所述第二区域22表面的所述第二介质层26作为第二初始栅介质层。
在一些实施例中,形成第一介质层24于所述第一区域21表面的具体步骤包括:
沉积第一介质材料于所述第一区域21和所述第二区域22表面,形成覆盖所述第一区域21和所述第二区域22的所述第一介质层24,如图2B所示;
去除覆盖于所述第二区域22表面的所述第一介质层24,如图2E所示。
在一些实施例中,去除覆盖于所述第二区域22表面的所述第一介质层24的具体步骤包括:
于所述衬底上形成阻挡层25,所述阻挡层25覆盖位于所述第一区域21表面的所述第一介质层24,如图2C所示;
去除覆盖于所述第二区域22表面的所述第一介质层24,如图2D所示;
去除所述阻挡层25,如图2E所示。
具体来说,在对所述衬底的所述第一区域21表面和所述第二区域22表面进行清洗之后,可以采用化学气相沉积、物理气相沉积、原子层沉积或者原位水汽生长(ISSG)工艺于所述第一区域21表面和所述第二区域22表面形成所述第一介质层24,如图2B所示。所述第一介质层24的材料可以是但不限于氧化物材料,例如二氧化硅。为了便于后续形成的第一栅介质层的厚度能够达到第一预设厚度,从而确保最终形成的所述第一晶体管的电性能不受影响,可以适当增大所述第一介质层24的厚度,所述第一介质层24的具体厚度可以根据实际需要进行调节,例如根据所需要形成的第一栅介质层的厚度以及所采用的具体沉积工艺类型。
之后,沉积光阻材料于所述第一区域21的所述第一介质层24之上,形成所述阻挡层25,使得位于所述第二区域22上的所述第一介质层24暴露,如图2C所示。接着,可以采用干法刻蚀工艺或者湿法刻蚀工艺,去除位于所述第二区域22上的所述第一介质层24,使得所述衬底的所述第二区域22的表面暴露,如图2D所示。去除所述阻挡层25之后,得到如图2E所示的结构。
之后,可以采用化学气相沉积、物理气相沉积、或者原子层沉积工艺,沉积所述第二介质层26于所述第二区域22的表面和残留的所述第一介质层24表面,得到如图2F所示的结构。为了便于后续形成的第二栅介质层的厚度能够达到第二预设厚度,从而确保最终形成的所述第二晶体管的电性能不受影响,可以适当增大所述第二介质层26的厚度,所述第二介质层26的具体厚度可以根据实际需要进行调节,例如根据所需要形成的第二栅介质层的厚度以及所采用的具体沉积工艺类型。
在其他实施例中,本领域技术人员也可以根据实际需要直接仅在所述第一区域21表面沉积所述第一介质层24,从而进一步简化所述半导体结构的形成工艺。
本具体实施方式是以在所述第二区域22的表面和残留的所述第一介质层24表面同时沉积所述第二介质层26为例进行说明。在其他实施例中,本领域技术人员还可以根据实际需要仅在所述第二区域22的表面沉积形成所述第二介质层26,此时,需要相应增大所述第一介质层24的厚度。
在一些实施例中,所述第一介质层24的材料与所述第二介质层26的材料相同。
在一些实施例中,所述第一介质层24和所述第二介质层26的材料均为氧化物材料,例如二氧化硅。
在其他实施例中,所述第一介质层24的材料也可以与所述第二介质层26的材料不同。
为了形成具有不同阈值电压的所述第一晶体管和所述第二晶体管,在一些实施例中,所述第一介质层24的厚度大于所述第二介质层26的厚度。
步骤S13,注入掺杂元素至所述第一初始栅介质层和所述第二初始栅介质层。
具体来说,所述掺杂元素的注入能够减小后续形成的第一栅极和第二栅极的漏电问题,并能够有效阻挡所述第一栅极和所述第二栅极中的导电粒子向所述衬底中扩散。所述掺杂元素可以是但不限于氮元素。
当所述掺杂元素为氮元素时,在一些实施例中,注入掺杂元素至所述第一初始栅介质层和所述第二初始栅介质层的具体步骤包括:
采用远距离等离子体渗氮(RPN)工艺注入氮元素至所述第一初始栅介质层和所述第二初始栅介质层。
具体来说,在形成如图2F所示的结构之后,可以采用远距离等离子体渗氮工艺自所述第一初始栅介质层的顶面(即所述第一初始栅介质层背离所述衬底的表面)和所述第二初始栅介质层的顶面(即所述第二初始栅介质层背离所述衬底的表面)注入氮元素,即注入氮元素至所述第一区域21上的所述第一介质层24和所述第二介质层26中、并注入氮元素至所述第二区域22上的所述第二介质层26中,得到如图2G所示的结构。
步骤S14,减薄所述第一初始栅介质层和所述第二初始栅介质层,形成第一栅介质层27和所述第二栅介质层28,所述第一栅介质层27的厚度大于所述第二栅介质层28的厚度,如图2H所示。
具体来说,通过增大掺杂前形成的所述第一初始栅介质层和所述第二初始栅介质层的厚度,在所述掺杂元素注入深度和/或注入量不变的条件下,能够减小所述第一初始栅介质层底面(即所述第一初始栅介质层与所述衬底接触的 表面)和所述第二初始栅介质层底面(即所述第二初始栅介质层与所述衬底接触的表面)的所述掺杂元素的浓度,从而降低NBTI效应。同时,减薄所述第一初始栅介质层和所述第二初始栅介质层,能够使得所述第一栅介质层27达到第一预设厚度、所述第二栅介质层28的厚度达到第二预设厚度,即不会造成所述第一栅介质层27和所述第二栅介质层28厚度的增加。
在一些实施例中,减薄所述第一初始栅介质层和所述第二初始栅介质层的具体步骤包括:
采用湿法刻蚀工艺去除部分所述第一初始栅介质层和部分所述第二初始栅介质层,形成具有第一厚度的第一栅介质层27和具有第二厚度的第二栅介质层28。
在一些实施例中,采用湿法刻蚀工艺去除部分所述第一初始栅介质层和部分所述第二初始栅介质层的具体步骤包括:
采用湿法刻蚀工艺去除所述第一初始栅介质层中的部分所述第二介质层26、以及部分所述第二初始栅介质层。
具体来说,可以采用清洗工艺去除所述第一初始栅介质层中的部分所述第二介质层、以及部分所述第二初始栅介质层,残留于所述第一区域21表面的所述第一介质层24和所述第二介质层26共同作为所述第一栅介质层27。同时,所述清洗工艺去除所述第二区域22上方部分厚度的所述第二介质层26,残留于所述第二区域22上方的所述第二介质层26作为所述第二栅介质层28。
在一些实施例中,所述第一栅介质层27与所述衬底接触的表面不具有所述掺杂元素;
所述第二栅介质层28与所述衬底接触的表面不具有所述掺杂元素。
具体来说,通过调整所述第一介质层24和所述第二介质层26的厚度,可以使得最终形成的所述第一栅介质层27与所述衬底接触的表面不具有所述掺杂元素,所述第二栅介质层28与所述衬底接触的表面不具有所述掺杂元素,从而进一步改善NBTI效应的可靠性。
在一些实施例中,形成第一栅介质层27和所述第二栅介质层28之后,还包括如下步骤:
形成第一栅极29于所述第一栅介质层27表面、并形成第二栅极30于所 述第二栅介质层28表面。
在一些实施例中,形成第一栅极29于所述第一栅介质层27表面、并形成第二栅极30于所述第二栅介质层30表面的具体步骤包括:
沉积导电材料于所述第一栅介质层27表面和所述第二栅介质层28表面,同时形成所述第一栅极29和所述第二栅极30。
其中,所述导电材料可以是但不限于掺杂的多晶硅材料。
根据一些实施例,本申请还提供了一种半导体结构,采用如上述任一项所述的半导体结构的形成方法形成。
本具体实施方式提供的半导体结构及其形成方法,通过增大第一初始栅介质层和第二初始栅介质层的厚度,在掺杂元素注入第一初始栅介质层和所述第二初始栅介质层之后,再减薄所述第一初始栅介质层和所述第二初始栅介质层,从而确保注入的所述掺杂元素集中于所述第一栅介质层的表面和所述第二栅介质层的表面,有效降低了所述第一栅介质层底面和所述第二栅介质层底面的掺杂元素浓度,改善了第一晶体管和第二晶体管的NBTI效应,提高了半导体结构的使用寿命和性能可靠性。
以上所述仅是本申请的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本申请的保护范围。
Claims (15)
- 一种半导体结构的形成方法,包括如下步骤:提供衬底,所述衬底包括用于形成第一晶体管的第一区域和用于形成第二晶体管的第二区域;形成第一初始栅介质层于所述第一区域表面、并形成第二初始栅介质层于所述第二区域表面;注入掺杂元素至所述第一初始栅介质层和所述第二初始栅介质层;减薄所述第一初始栅介质层和所述第二初始栅介质层,形成第一栅介质层和所述第二栅介质层,所述第一栅介质层的厚度大于所述第二栅介质层的厚度。
- 根据权利要求1所述的半导体结构的形成方法,其中,形成第一初始栅介质层于所述第一区域表面、并形成第二初始栅介质层于所述第二区域表面的具体步骤包括:形成第一介质层于所述第一区域表面;形成第二介质层于所述第一介质层和所述第二区域表面,所述第一介质层和位于所述第一介质层表面的所述第二介质层共同作为第一初始栅介质层,位于所述第二区域表面的所述第二介质层作为第二初始栅介质层。
- 根据权利要求2所述的半导体结构的形成方法,其中,形成第一介质层于所述第一区域表面的具体步骤包括:沉积第一介质材料于所述第一区域和所述第二区域表面,形成覆盖所述第一区域和所述第二区域的所述第一介质层;去除覆盖于所述第二区域表面的所述第一介质层。
- 根据权利要求3所述的半导体结构的形成方法,其中,去除覆盖于所述第二区域表面的所述第一介质层的具体步骤包括:于所述衬底上形成阻挡层,所述阻挡层覆盖位于所述第一区域表面的所述第一介质层;去除覆盖于所述第二区域表面的所述第一介质层;去除所述阻挡层。
- 根据权利要求2所述的半导体结构的形成方法,其中,所述第一介质层的 材料与所述第二介质层的材料相同。
- 根据权利要求2所述的半导体结构的形成方法,其中,所述第一介质层和所述第二介质层的材料均为氧化物材料。
- 根据权利要求2所述的半导体结构的形成方法,其中,所述第一介质层的厚度大于所述第二介质层的厚度。
- 根据权利要求1所述的半导体结构的形成方法,其中,注入掺杂元素至所述第一初始栅介质层和所述第二初始栅介质层的具体步骤包括:采用远距离等离子体渗氮工艺注入氮元素至所述第一初始栅介质层和所述第二初始栅介质层。
- 根据权利要求1所述的半导体结构的形成方法,其中,减薄所述第一初始栅介质层和所述第二初始栅介质层的具体步骤包括:采用湿法刻蚀工艺去除部分所述第一初始栅介质层和部分所述第二初始栅介质层,形成具有第一厚度的第一栅介质层和具有第二厚度的第二栅介质层。
- 根据权利要求9所述的半导体结构的形成方法,其中,采用湿法刻蚀工艺去除部分所述第一初始栅介质层和部分所述第二初始栅介质层的具体步骤包括:采用湿法刻蚀工艺去除所述第一初始栅介质层中的部分所述第二介质层、以及部分所述第二初始栅介质层。
- 根据权利要求1所述的半导体结构的形成方法,其中,所述第一栅介质层与所述衬底接触的表面不具有所述掺杂元素;所述第二栅介质层与所述衬底接触的表面不具有所述掺杂元素。
- 根据权利要求1所述的半导体结构的形成方法,其中,形成第一栅介质层和所述第二栅介质层之后,还包括如下步骤:形成第一栅极于所述第一栅介质层表面、并形成第二栅极于所述第二栅介质层表面。
- 根据权利要求12所述的半导体结构的形成方法,其中,形成第一栅极于所述第一栅介质层表面、并形成第二栅极于所述第二栅介质层表面的具体步 骤包括:沉积导电材料于所述第一栅介质层表面和所述第二栅介质层表面,同时形成所述第一栅极和所述第二栅极。
- 根据权利要求1所述的半导体结构的形成方法,其中,所述第一晶体管和所述第二晶体管均为PMOS晶体管。
- 一种半导体结构,采用如权利要求1-14中任一项所述的半导体结构的形成方法形成。
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