WO2023000378A1 - 热传导结构及其形成方法、芯片及芯片堆叠结构 - Google Patents

热传导结构及其形成方法、芯片及芯片堆叠结构 Download PDF

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WO2023000378A1
WO2023000378A1 PCT/CN2021/110135 CN2021110135W WO2023000378A1 WO 2023000378 A1 WO2023000378 A1 WO 2023000378A1 CN 2021110135 W CN2021110135 W CN 2021110135W WO 2023000378 A1 WO2023000378 A1 WO 2023000378A1
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substrate
blind
layer
silicon
silicon via
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PCT/CN2021/110135
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/515,783 priority Critical patent/US20230024555A1/en
Publication of WO2023000378A1 publication Critical patent/WO2023000378A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to the technical field of semiconductors, and relate to, but are not limited to, a heat conduction structure and a forming method thereof, a chip and a chip stacking structure.
  • DRAM Dynamic Random Access Memory
  • TSV Silicon Via
  • Embodiments of the present disclosure provide a heat conduction structure and a method for forming the same, a chip and a chip stack structure.
  • an embodiment of the present disclosure provides a method for forming a heat conduction structure, the method comprising: providing a substrate; wherein at least a dielectric layer is formed on the substrate;
  • Forming a through-silicon via and at least one blind silicon via wherein the at least one blind silicon via is located on at least one side of the through-silicon via; the through-silicon via penetrates the substrate and the dielectric layer; each The blind silicon vias do not penetrate through the substrate.
  • an embodiment of the present disclosure provides a heat conduction structure, including:
  • an embodiment of the present disclosure provides a chip, and the chip at least includes the above-mentioned heat conduction structure.
  • an embodiment of the present disclosure provides a chip stack structure, including: at least two chips;
  • Each of the at least two chips includes the above-mentioned heat conduction structure
  • pads located on the first side of each of the chips, wherein the pads are connected to through-silicon vias in the heat conduction structure;
  • the pads on the first side of the first chip of the at least two chips are electrically connected to the bonding pads on the second side of the second chip of the at least two chips.
  • the forming method of the heat conduction structure includes: providing a substrate on which at least a dielectric layer is formed; forming through silicon vias and at least one blind silicon hole; The silicon blind hole is located on at least one side of the through silicon hole, and the through silicon hole penetrates the substrate and the dielectric layer; each blind silicon hole does not penetrate the substrate.
  • the forming method of the heat conduction structure includes: providing a substrate on which at least a dielectric layer is formed; forming through silicon vias and at least one blind silicon hole; The silicon blind hole is located on at least one side of the through silicon hole, and the through silicon hole penetrates the substrate and the dielectric layer; each blind silicon hole does not penetrate the substrate.
  • FIG. 1A is a schematic flow diagram of a method for forming a heat conduction structure provided by an embodiment of the present disclosure
  • FIG. 1B to FIG. 1E are top views of the positional relationship between blind vias and TSVs provided by embodiments of the present disclosure.
  • FIGS. 2A to 4B are flowcharts of forming a heat conduction structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a chip provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a chip stack structure provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a heat conduction structure and a method for forming the same, a chip and a chip stack structure.
  • FIG. 1A is a schematic flowchart of a method for forming a heat conduction structure provided by an embodiment of the present disclosure. As shown in FIG. 1A , the method includes:
  • Step S101 providing a substrate; wherein at least a dielectric layer is formed on the substrate.
  • the substrate may be a silicon substrate, and the dielectric layer is formed on the surface of the substrate to protect the silicon substrate.
  • the material used for the dielectric layer may be silicon dioxide (SiO 2 ) or other insulating materials.
  • the dielectric layer can be formed by the following methods: chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) or atomic layer deposition (Atomic Layer Deposition, ALD).
  • Step S102 forming a through-silicon via and at least one blind silicon via; wherein, the at least one blind silicon via is located on at least one side of the through-silicon via; the through-silicon via penetrates through the substrate and the dielectric layer; Each of the blind silicon vias does not penetrate through the substrate.
  • the through-silicon vias are used for signal transmission, and the blind silicon vias are used for heat transmission.
  • the thickness of the substrate can be 40 ⁇ m to 70 ⁇ m; the purpose of setting the substrate thickness to 40 ⁇ m to 70 ⁇ m is to make the total thickness of the subsequent substrate meet the packaging requirements. If the thickness of the initially provided substrate is too large, then Substrate thinning is required, and substrate thinning can be achieved by mechanical grinding, chemical mechanical polishing (CMP) and wet etching.
  • CMP chemical mechanical polishing
  • a dielectric layer, a shallow trench isolation layer and a metal layer may be sequentially formed on the substrate, and the TSV penetrates through the substrate, the dielectric layer and the shallow trench isolation layer and lands on the metal layer.
  • an insulating layer, a barrier layer, a seed layer, and a conductive layer are sequentially formed in the through-silicon via and each of the blind silicon vias; wherein, the thickness of the insulating layer can be to
  • the at least one blind via is located on at least one side of the TSV, and may at least include the following situations:
  • Case 1 When the number of blind silicon vias is one, the blind silicon vias are arranged on any side of the TSVs, for example, any one of the front side, the back side, the left side and the right side. As shown in FIG. 1B , the blind silicon vias 12 are arranged on the left side of the TSVs 11 .
  • Case 2 When the number of blind silicon vias is two, the two blind silicon vias can be arranged on either side of the TSV, or can be arranged on any two sides of the TSV, such as left and right sides, front and rear Sides, front and left, etc.
  • the two blind silicon vias When the two blind silicon vias are arranged on any side of the through silicon vias, the two blind silicon vias and the through silicon vias can be arranged uniformly or non-uniformly in a straight line. As shown in Figure 1C, two blind silicon vias 12 are arranged in a straight line on the right side of the through silicon via 11; side.
  • the heat generated by the through-silicon via can be dissipated to the substrate through the surrounding blind silicon via.
  • the outside of the bottom improves the reliability and stability of the through-silicon vias; at the same time, it avoids the problems of reducing area efficiency and increasing process complexity caused by additional heat transfer lines.
  • FIGS. 2A to 4B are flow charts of the method for forming the heat conduction structure provided by the embodiment of the present disclosure. Next, please refer to FIGS. 2A to 4B to further describe the method of forming the heat conduction structure provided by the embodiment of the present disclosure in detail.
  • An embodiment of the present disclosure also provides a method for forming a heat conduction structure, the method including:
  • Step S201 providing a substrate; wherein, at least a dielectric layer is formed on a first surface of the substrate.
  • Step S202 using the second surface of the substrate as an etching starting point, etching the substrate and the dielectric layer to form through-silicon vias penetrating through the substrate and the dielectric layer.
  • the second surface of the substrate is a surface opposite to the first surface of the substrate in the thickness direction of the substrate.
  • Step S203 using the second surface of the substrate as an etching starting point, etching the substrate to form at least one silicon blind hole that does not penetrate the substrate.
  • the etching process in step S203 and the etching process in step S202 can be implemented in a similar manner or in a different manner.
  • the layers included may be the same or different.
  • blind silicon vias are formed around the TSVs, and the blind silicon vias are filled with an insulating layer, a barrier layer, a seed layer, and a conductive layer, and a simple process can be used to improve the heat dissipation of the heat generated in the TSVs. effect, thereby improving the reliability and stability of TSVs.
  • step S202 may be formed by the following steps:
  • Step S2021a forming a first photoresist layer on the second surface of the substrate.
  • the first photoresist layer can be formed on the second surface of the silicon substrate by any suitable deposition process, and the material of the first photoresist layer can be composed of Novolac resin plus a photosensitive naphthoquinone diazo compound such as di
  • the photoresist composed of Diazo Naphtho Quinone (DNQ) and solvents and additives for adjusting viscosity and other physical and chemical properties can also be a chemically amplified photoresist (Chemically ampiification Photoresist, CAMP) system photoresist material, also It may be a chemically amplified photoresist.
  • Step S2022a patterning the first photoresist layer to form a first window; wherein, the first window exposes the position corresponding to the TSV.
  • the first photoresist layer may be patterned through steps such as exposure and development to form the first window.
  • the mask plate and the substrate are aligned to expose the first photoresist layer to obtain the first window, and the finally formed TSV is located at a preset position.
  • Step S2023a through the first window, and using the second surface of the substrate as an etching starting point, etch the substrate and the dielectric layer to form via holes.
  • the through hole may be formed by etching the substrate and the dielectric layer by a dry etching process or a wet etching process.
  • the dry etching process can be a plasma etching process, a reactive ion etching process or an ion milling process; deep reactive ion etching (Deep Reactive Ion Etching, DRIE) can also be used to etch the substrate and the medium layer to get vias.
  • DRIE Deep Reactive Ion Etching
  • the DRIE technology combines the deposition of the polymer passivation layer and the etching of the single crystal silicon, which are cycled alternately, so as to avoid the mutual influence between deposition and etching, and ensure the passivation layer.
  • the most typical deep reactive ion etching method is the method called "Bosch (Bosch)" process.
  • the specific process is to first use sulfur hexafluoride (SF 6 ) to etch the silicon (Si) surface, and then on the sidewall A layer of polyfluorocarbon ((CF) n ) polymer passivation film is deposited, and then SF 6 is injected to etch the passivation film, and then the Si substrate is etched.
  • SF 6 sulfur hexafluoride
  • CF polyfluorocarbon
  • Step S2024a sequentially forming an insulating layer, a barrier layer, a seed layer and a conductive layer in the through hole to obtain the through silicon hole.
  • the insulating layer is used to block the conduction between the filling metal and silicon Si and protect the substrate from being damaged;
  • the insulating layer material can be silicon oxide, silicon nitride and polymer, etc., and different insulating layer materials require Using different deposition techniques, thermal oxidation technology (Thermal Oxidation) can be used to deposit silicon dioxide materials, and plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) technology can be used to deposit silicon dioxide materials and silicon nitride (Si 3 N 4 ) material, p-xylene material can be deposited by vacuum vapor deposition technology.
  • thermal Oxidation Thermal Oxidation
  • PECVD plasma enhanced chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the barrier layer is used to prevent the diffusion of the conductive material subsequently filled in the TSV;
  • the material of the barrier layer can be metal tantalum, tantalum nitride or titanium nitride, etc., and can be deposited by any suitable process to form the barrier layer.
  • the seed layer is used to provide a bridging function for the subsequent formation of the conductive layer in the TSV.
  • the material of the seed layer can be any conductive material, for example, tungsten, cobalt, copper, aluminum or any combination thereof.
  • the material of the conductive layer can be any conductive metal, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or In any combination, the conductive material and the seed material can be the same or different.
  • the material of the conductive layer is copper metal, and the formation of the copper conductive layer can first deposit a seed layer by physical vapor deposition (Physical Vapor Deposition, PVD), as the cathode of electroplating, and electroplating by electrochemical plating (Electro Chemical Plating, ECP). A layer of copper is deposited to form the conductive layer.
  • Step S2021a to step S2024a refer to FIG. 2A to FIG. 2D respectively.
  • a dielectric layer 202 is formed on the first surface of the substrate 201 (surface A shown in FIG. 2A ).
  • a first photoresist layer 203 is formed on the second surface of the substrate 201 (such as the B surface in FIG. 2B), and the first photoresist layer 203 is patterned to form a first window 203a.
  • the first window 203a exposes the corresponding position of the TSV.
  • the substrate 201 and the dielectric layer 202 are etched through the first window 203 a to obtain a through hole 204 .
  • FIG. 2A a dielectric layer 202 is formed on the first surface of the substrate 201 (surface A shown in FIG. 2A ).
  • a first photoresist layer 203 is formed on the second surface of the substrate 201 (such as the B surface in FIG. 2B), and the first photoresist layer 203 is patterned to form a first
  • an insulating layer 205 a , a barrier layer 205 b , a seed layer 205 c and a conductive layer 205 d are sequentially formed on the inner wall of the through hole 204 to form a through silicon hole 205 penetrating the substrate.
  • step S203 can be referred to in FIG. 2E .
  • the position corresponding to the silicon blind hole 206 is exposed on the second surface of the substrate, and the substrate 201 is etched to finally obtain a The silicon blind via 206 of the substrate 201 is described above.
  • Steps S2021a to S2024a are applicable to the following situations:
  • step S2021a there is no other layer on the dielectric layer.
  • other layers on the dielectric layer may be shallow trench isolation layers and/or metal layers. In practice, other layers are formed after the vias are formed.
  • step S2021a other layers are formed on the dielectric layer, and the other layers are formed before the via holes are formed.
  • the through hole may first penetrate through the dielectric layer and then through the substrate, that is, step S202 may include step S2021b to step S2023b, wherein: step S2021b, forming a second hole on the first surface of the substrate A photoresist layer; step S2022b, patterning the first photoresist layer to form a first window, the first window exposing the position corresponding to the through-silicon via; step S2023b, passing through the first window, using the The first surface of the substrate is an etching starting point, and the dielectric layer and the substrate are etched to form through holes.
  • Steps S2021b to S2023b are applicable to the above case 1: that is, at step S2021b, there is no other layer on the dielectric layer.
  • other layers on the dielectric layer may be shallow trench isolation layers and/or metal layers. In practice, other layers are formed after the vias are formed.
  • the method for forming the heat conduction structure further includes: removing the first photoresist layer.
  • the first photoresist layer can be removed by wet etching process or dry etching process.
  • the insulating layer, the barrier layer and the seed layer are formed in the TSV, the insulating layer, the barrier layer and the seed layer are also formed on the second surface of the substrate at the same time, Therefore, before forming the silicon blind hole, it is necessary to perform chemical mechanical polishing on the second surface of the substrate to remove the insulating layer, the barrier layer and the seed layer on the second surface of the substrate, and expose the second surface of the silicon substrate.
  • an embodiment of the present disclosure also provides a heat conduction structure, including:
  • the substrate 201 further includes a metal layer 207 formed on the dielectric layer 202 , and the TSV 205 lands on the metal layer 207 .
  • the material of the metal layer may be copper.
  • the structure further includes: a metal layer 207 formed on the dielectric layer 202 ; and the TSV 205 lands on the metal layer 207 .
  • An embodiment of the present disclosure also provides a method for forming a heat conduction structure, including:
  • Step S301 providing a substrate; wherein at least a dielectric layer is formed on the substrate, and the substrate further includes a metal layer formed on the dielectric layer; the TSVs land on the metal layer.
  • Step S302 taking the second surface of the substrate as an etching starting point, etching the substrate to form at least two blind holes that do not penetrate the substrate.
  • the metal layer is closer to the first surface of the substrate, and the second surface of the substrate means that it is opposite to the first surface of the substrate in the thickness direction of the substrate. face.
  • Step S303 continue to etch one of the at least two blind holes to form the TSV.
  • Step S304 forming a silicon blind via in each of the remaining blind vias of the at least two blind vias.
  • step S302 may be formed by the following steps:
  • Step S3021 forming a second photoresist layer on the second surface of the substrate.
  • the second photoresist layer may be formed on the second surface of the silicon substrate by any suitable deposition process; the material of the second photoresist layer may be the same as or different from that of the first photoresist layer.
  • Step S3022 patterning the second photoresist layer to form a second window and a third window.
  • the second window exposes the position corresponding to the TSV
  • the third window exposes the position corresponding to the blind silicon via.
  • the second photoresist layer may be patterned through steps such as exposure and development to form the second window and the third window.
  • a second photoresist layer 208 is formed on the second side of the substrate 201 (like B side in FIG. 3A ), and the second photoresist layer 208 is patterned to form a second window 208a and a third window 208a.
  • window 208b, the second window 208a and the third window 208b expose the second surface of the substrate 201, the second window 208a exposes the position corresponding to the TSV, and the third window 208b exposes the The position corresponding to the silicon blind via.
  • Step S3023 etching the substrate through the second window and the third window to form at least two blind holes that do not penetrate the substrate.
  • the substrate 201 is etched through the second window 208a and the third window 208b to form at least two blind holes 209 that do not penetrate the substrate 201, wherein the blind holes have a first Depth, the first depth is less than the thickness of the substrate.
  • step S303 includes: continuing to etch the blind hole located in the middle of the substrate among the at least two blind holes to form the through-silicon via.
  • the blind hole located in the middle of the substrate may be a blind hole located in the middle of the substrate among the blind holes arranged in a straight line, or a plurality of blind holes arranged in a ring form A blind via in the center of the substrate.
  • step S303 may be implemented through the following steps:
  • Step S3031 forming a protective layer on each of the remaining blind holes
  • the protective layer is used to protect each of the remaining blind holes from being etched, and the material used for the protective layer can be photoresist, or silicon oxide, silicon oxynitride, silicon carbide and combinations thereof, and And/or other suitable materials, the protective layer can be formed by any suitable deposition process.
  • Step S3032 etching away the substrate and the dielectric layer in the blind hole corresponding to the TSV to form a through hole
  • Step S3033 sequentially forming an insulating layer, a barrier layer, a seed layer and a conductive layer in the through hole to obtain the through silicon hole;
  • Step S3034 removing the protection layer.
  • Step S3031 to step S3034 refer to FIG. 3C to FIG. 3D respectively.
  • a protective layer 210 is formed on each of the remaining blind holes 209, and the substrate 201 and the dielectric layer 202 in the blind holes 209 are etched with the second surface of the substrate 201 as the etching starting point. , forming a via hole 204 .
  • an insulating layer 205 a , a barrier layer 205 b , a seed layer 205 c and a conductive layer 205 d are sequentially formed in the through hole 204 to obtain the through silicon hole 205 ; and the protection layer 210 is removed.
  • step S304 can be implemented by the following steps: sequentially forming an insulating layer 206a, a barrier layer 206b, a seed layer 206c and a conductive layer 206d in each of the remaining blind holes 209 , to obtain a blind silicon via 206 .
  • the layers included in the blind silicon vias may be different from or the same as the layers included in the through-silicon vias.
  • the layers included in the blind silicon via are the same as the layers included in the through silicon via
  • step S3034 can be directly performed after step S3032, and materials of each layer are deposited in the through hole and the remaining blind holes at the same time, Forming different layers, such as depositing an insulating layer, a barrier layer, a seed layer, and a conductive layer, respectively forming through-silicon vias and blind vias without depositing an insulating layer, a barrier layer, a seed layer, and Conductive layer, so as to achieve the effect of simplifying the process.
  • the method includes sequentially forming an insulating layer, a barrier layer, a seed layer, and a conductive layer in the through-silicon vias and each of the blind silicon vias; here, the thickness of the insulating layer is to
  • the distance between the insulating layer of adjacent TSVs and the insulating layer of a blind silicon via, and/or, the insulating layers of two adjacent blind silicon vias is 1.5 ⁇ m.
  • the thickness of the insulating layer in the TSV is greater than the thickness of the insulating layer in the BSV.
  • An embodiment of the present disclosure also provides a method for forming a heat conduction structure, the method including:
  • Step S401 providing a substrate.
  • Step S402 sequentially forming the shallow trench isolation layer, the dielectric layer and the metal layer on the substrate.
  • step S401 and step S402 the shallow trench isolation layer 211 , the dielectric layer 202 and the metal layer 207 are sequentially formed on the first surface of the substrate 201 .
  • Step S403 forming a through-silicon via and at least one blind silicon via, wherein the at least one blind silicon via is located on at least one side of the through-silicon via; the through-silicon via penetrates through the substrate and the dielectric layer; Each of the blind silicon vias does not penetrate through the substrate.
  • Step S404 forming a redistribution layer interconnected with the at least one blind silicon via and the through-silicon via on the second surface of the substrate, wherein the shallow trench isolation layer is on the second surface of the substrate.
  • the substrate is formed on one side, and the second surface of the substrate is a surface opposite to the first surface of the substrate in the thickness direction of the substrate.
  • a redistribution layer 212 interconnected with the at least one blind silicon via 206 and the through silicon via 205 is formed on the second surface of the substrate 201 .
  • RDL redistribution Layer
  • the shallow trench isolation layer is formed by shallow trench isolation technology (Shallow Trench Isolation, STI), specifically by using a silicon nitride mask to form a groove after depositing, patterning, and etching silicon. And deposit oxide is filled in the trench for isolation from silicon.
  • shallow trench isolation technology Shallow Trench Isolation, STI
  • the step S403 of forming a through-silicon via and at least one blind silicon via can be implemented through the steps S202 and S203 or steps S302 to S304.
  • an embodiment of the present disclosure also provides a heat conduction structure, including:
  • a substrate 201 a shallow trench isolation layer 211 located between the substrate 201 and the dielectric layer 202, and a metal layer 207 located on the dielectric layer 202;
  • At least one blind silicon via 206 located on at least one side of the through-silicon via 205, each of the blind silicon vias 206 does not penetrate through the substrate 201;
  • the diameter of the TSV and the at least one blind silicon via is 2 ⁇ m to 10 ⁇ m; the depth of the TSV is 40 ⁇ m to 100 ⁇ m, and the depth of the at least one blind silicon via is 5 ⁇ m to 10 ⁇ m. 67 ⁇ m.
  • plating voids will be formed when copper plating is formed by uniform electroplating process, so the "bottom-up" electroplating in related technologies can be used
  • the process uses special electroplating accelerators and inhibitors to accelerate the deposition rate inside the through hole and inhibit the deposition rate on the outer surface of the through hole. By adjusting the ratio of the accelerator and the inhibitor, the two are balanced to prevent the formation of electroplating voids. produce.
  • the distance on the substrate not penetrated by the at least one blind silicon via is 3 ⁇ m to 65 ⁇ m.
  • an embodiment of the present disclosure further provides a chip, and the chip at least includes the above-mentioned heat conduction structure.
  • the chip 50 at least includes a heat conduction structure
  • the heat conduction junction includes: a substrate 501 ; a dielectric layer 502 formed on the substrate 501 ; and the through-silicon via 503 of the dielectric layer 502 ; at least one blind silicon via 504 located on at least one side of the through-silicon via 503 , each of the blind silicon vias 504 does not penetrate the substrate 501 .
  • the heat conduction structure can be seen in FIG. 2F , FIG. 3E or FIG. 4B .
  • the heat conduction structure in the chip in the embodiment of the present disclosure is similar to the formation method of the heat conduction structure in the above embodiment.
  • the technical features not disclosed in detail in the embodiment of the present disclosure please refer to the above embodiment for understanding.
  • an embodiment of the present disclosure also provides a chip stacking structure, including:
  • each of the at least two chips includes the above-mentioned heat conduction structure
  • the bonding pad located on the second surface of the chip, wherein the bonding pad is connected to the metal layer connected to the through-silicon via; the second surface of the chip is connected to the first surface of the chip on the Opposite faces in the thickness of the chip;
  • the bonding pads on the first surface of the first chip among the at least two chips are electrically connected to the bonding pads on the second surface of the second chip among the at least two chips.
  • the chip stack structure includes: two chips 60; each of the chips 60 in the two chips includes the above-mentioned heat conduction structure;
  • the bonding pads 601 on the first surface of the first chip among the two chips 60 are electrically connected to the bonding pads 602 on the second surface of the second chip among the two chips 60 .
  • the heat conduction structure may refer to FIG. 2E , FIG. 2F , FIG. 3E or FIG. 4B .
  • the at least two chips may be four, six, eight or other numbers.
  • the heat conduction structure in the chip in the embodiment of the present disclosure is similar to the formation method of the heat conduction structure in the above embodiment.
  • the technical features not disclosed in detail in the embodiment of the present disclosure please refer to the above embodiment for understanding.
  • the features disclosed in several method or device embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

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Abstract

本公开实施例提供一种热传导结构及其形成方法、芯片及芯片堆叠结构，其中，热传导结构的形成方法包括：提供衬底；其中，所述衬底上至少形成有介质层；形成硅通孔和至少一个硅盲孔，其中，所述至少一个硅盲孔位于所述硅通孔的至少一侧；所述硅通孔贯穿所述衬底和所述介质层；每一所述硅盲孔未贯穿所述衬底。

Description

热传导结构及其形成方法、芯片及芯片堆叠结构
相关申请的交叉引用
本公开基于申请号为202110821367.X、申请日为2021年07月20日、申请名称为“热传导结构及其形成方法、芯片及芯片堆叠结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开实施例涉及半导体技术领域，涉及但不限于一种热传导结构及其形成方法、芯片及芯片堆叠结构。
背景技术
传统动态随机存取存储器(Dynamic Random Access Memory，DRAM)硅通孔(Through Silicon Via，TSV)技术堆叠4X/8X DRAM芯片，适用于高速和宽带应用。
相关技术中，一方面，由于硅通孔将多层芯片堆叠在一起，高密度TSV间距和堆叠芯片消耗大量功率，导致功耗密度急剧上升，较高的发热量和较差的散热性使得芯片的工作温度上升，但是只有第一层芯片与热沉相邻，散热非常困难，造成芯片内部热密度过高，严重困扰着硅通孔的可靠性和稳定性，因而，热传递成为芯片性能的关键问题；另一方面，额外的热传输线(Thermal Transmission Line，TTL)会降低面积效率并增加工艺复杂性。
发明内容
本公开实施例提供一种热传导结构及其形成方法、芯片及芯片堆叠结构。
第一方面，本公开实施例提供一种热传导结构的形成方法，所述方法包括：提供衬底；其中，所述衬底上至少形成有介质层；
形成硅通孔和至少一个硅盲孔，其中，所述至少一个硅盲孔位于所述硅通孔的至少一侧；所述硅通孔贯穿所述衬底和所述介质层；每一所述硅盲孔未贯穿所述衬底。
第二方面，本公开实施例提供一种热传导结构，包括：
衬底；
在所述衬底上形成的介质层；
贯穿所述衬底和所述介质层的硅通孔；
位于所述硅通孔至少一侧的至少一个硅盲孔，每一所述硅盲孔未贯穿所述衬底。
第三方面，本公开实施例提供一种芯片，所述芯片至少包括上述的热传导结构。
第四方面，本公开实施例提供一种芯片堆叠结构，包括：至少两个芯片；
所述至少两个芯片中的每一所述芯片包括上述的热传导结构；
位于每一所述芯片的第一面的焊盘，其中，所述焊盘与所述热传导结构中的硅通孔连接；
位于所述芯片的第二面的键合焊盘，其中，所述键合焊盘与所述硅通孔相连的金属层连接；所述芯片的第二面是与所述芯片的第一面在所述芯片厚度上相对的面；
所述至少两个芯片中第一芯片的第一面的所述焊盘与所述至少两个芯片中的第二芯片的第二面的所述键合焊盘电连接。
本公开实施例提供的热传导结构及其形成方法、芯片及芯片堆叠结构，其中，热传导结构的形成方法包括：提供衬底，衬底上至少形成有介质层；形成硅通孔和至少一个硅盲孔，硅盲孔位于硅通孔的至少一侧，硅通孔贯穿衬底和介质层；每一硅盲孔未贯穿衬底。本公开实施例中由于形成位于硅通孔至少一侧的硅盲孔，可以实现将热量通过硅盲孔传输到衬底外，使热传导效率变高，提高了硅通孔的可靠性和稳定性；另外，由于没有形成额外的热传输线，因此不会降低面积效率，同时简化了工艺。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1A为本公开实施例提供的热传导结构形成方法的一种流程示意图；
图1B至图1E为本公开实施例提供的盲孔位和硅通孔位置关系俯视图。
图2A至图4B为本公开实施例提供的形成热传导结构的流程图；
图5为本公开实施例提供的芯片中的一种结构示意图；
图6为本公开实施例提供的芯片堆叠结构中的一种结构示意图；
附图标记说明如下：
201/501—衬底；202/502—介质层；203—第一光阻层；203a—第一窗口；204—通孔；11/205/503—硅通孔；205a/206a—绝缘层；205b/206b—阻挡层；205c/205c—种子层；205d/206d—导电层；206/12/504—硅盲孔；207/505—金属层；208—第二光阻层；208a—第二窗口；208b—第三窗口；209—盲孔；210—保护层；211/506—浅沟槽隔离层；212/507—再分布层；50/60—芯片；601—焊盘；602—键合焊盘。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开的具体技术方案做进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
本公开实施例提供一种热传导结构及其形成方法、芯片及芯片堆叠结构。
下面通过附图及具体实施例对本公开做进一步的详细说明。
图1A为本公开实施例提供的一种热传导结构的形成方法的一种的流程示意图，如图1A所示，所述方法包括：
步骤S101、提供衬底；其中，所述衬底上至少形成有介质层。
本公开实施例中，所述衬底可以是硅衬底，所述介质层形成于衬底的表面，用于保护硅衬底。所述介质层采用的材料可以是二氧化硅(SiO 2)或者其它绝缘材料。可以采用以下方法形成介质层：化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)。
步骤S102、形成硅通孔和至少一个硅盲孔；其中，所述至少一个硅盲孔位于所述硅通孔的至少一侧；所述硅通孔贯穿所述衬底和所述介质层；每一所述硅盲孔未贯穿所述衬底。
这里，硅通孔用来实现信号的传输，硅盲孔用于进行热传输。
在一些实施例中，所述衬底的厚度可以为40μm至70μm；设置衬底厚度为40μm至70μm的目的是使后续衬底总厚度满足封装要求，若初始提供的衬底厚度过大，则需要进行衬底减薄，可以采用机械磨削、化学机械抛光(Chemical Mechanical Polishing，CMP)和湿法腐蚀等来实现衬底减薄。
在一些实施例中，所述衬底上还可以依次形成有介质层、浅沟槽隔离层和金属层，硅通孔贯穿衬底、介质层和浅沟槽隔离层，着陆于金属层。
在一些实施例中，在所述硅通孔和每一所述硅盲孔内包括依次形成的绝缘层、阻挡层、种子层和导电层；其中，所述绝缘层的厚度可以为
Figure PCTCN2021110135-appb-000001
至
Figure PCTCN2021110135-appb-000002
在实际应用中，本公开实施例中，所述硅盲孔可以是一个，也可以是两个、三个甚至多个。为了使热传导效果更佳，所述硅盲孔可以是两个以上，可以均匀分布在硅通孔的周围。
在一些实施例中，所述至少一个盲孔位于所述硅通孔的至少一侧，至少可以包括以下情况：
情况一：硅盲孔的数量为一个时，硅盲孔排布在硅通孔的任意一侧，例如前侧、后侧、左侧和右侧中任意一侧。如图1B所示，硅盲孔12排布在硅通孔11的左侧。
情况二：硅盲孔的数量为两个时，两个硅盲孔可以排布在硅通孔的任意一侧，也可以分别排布在硅通孔的任意两侧，例如左右两侧、前后两侧、前侧和左侧等等。当两个硅盲孔排布在硅通孔的任意一侧时，两个硅盲孔与硅通孔三者之间可以以直线形式均匀地排布或非均匀地排布。如图1C所示，两个硅盲孔12以直线形式排布在硅通孔11的右侧；再如图1D所示，两个硅盲孔12分别排布在硅通孔11的左右两侧。
情况三：硅盲孔的数量为三个以上时，三个以上的硅盲孔以环状形式排布在硅通孔的周围，也可以以直线形式排布在硅通孔的一侧或两侧。如图1E所示，四个硅盲孔12以环状形式排布在硅通孔11的周围。
本公开实施例提供的热传导结构的形成方法，由于硅通孔的至少一侧形成有包括硅盲孔的热传导结构，如此，能够使得硅通孔产生的热量能够通过周围的硅盲孔散发至衬底外部，提高了硅通孔的可靠性和稳定性；同时，避免了因额外设置热传输线引起的降低面积效率并增加工艺复杂性的问题。
图2A至图4B为本公开实施例提供的形成热传导结构形成方法的流程图，接下来请参考图2A至图4B对本公开实施例提供的热传导结构的形成方法进一步地详细说明。
本公开实施例还提供一种热传导结构的形成方法，所述方法包括：
步骤S201、提供衬底；其中，所述衬底的第一面上至少形成有介质层。
步骤S202、以所述衬底的第二面为刻蚀起点，刻蚀所述衬底和所述介质层，形成贯穿所述衬底和所述介质层的硅通孔。
这里，其中，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的面。
步骤S203、以所述衬底的第二面为刻蚀起点，刻蚀所述衬底，形成未贯穿所述衬底的至少一个硅盲孔。
在一些实施例中，步骤S203中的刻蚀过程与步骤S202的刻蚀过程可以采用类似的方式或不同的方式实现，步骤S203中硅盲孔内包括的各层与步骤S202中硅通孔内包括的各层可以相同，也可以不同。
在本实施例中，在硅通孔的周围形成硅盲孔，硅盲孔中填充有绝缘层、阻挡层、种子层和导电层，能够使用简单的工艺提高硅通孔内产生的热量的散热效果，从而提高硅 通孔的可靠性和稳定性。
在一些实施例中，步骤S202可以通过以下步骤形成：
步骤S2021a、在所述衬底的第二面形成第一光阻层。
这里，可以通过任意一种合适的沉积工艺在硅衬底的第二面形成第一光阻层，所述第一光阻层的材料可以由Novolac树脂加上感光性萘醌重氮化合物如二氮萘醌(Diazo Naphtho Quinone，DNQ)和调整黏度及其他物理化学性质的溶剂和添加剂组成的光刻胶，也可以是化学增幅型光阻剂(Chemically ampiification Photoresist，CAMP)系统光阻材料，也可以是化学放大的光刻胶。
步骤S2022a、图形化所述第一光阻层，形成第一窗口；其中，所述第一窗口暴露出所述硅通孔对应的位置。
在一些实施例中，可以通过曝光、显影等步骤来图形化第一光阻层，形成所述第一窗口。在实际应用中，对准掩膜版和衬底，使第一光阻层曝光，得到第一窗口，最终形成的硅通孔位于预设的位置。
步骤S2023a、通过第一窗口，以所述衬底的第二面为刻蚀起点，刻蚀所述衬底和介质层，形成通孔。
在一些实施例中，可以通过干法刻蚀工艺或者湿法刻蚀工艺刻蚀衬底和介质层，形成所述通孔。其中，所述干法刻蚀工艺可以是等离子体刻蚀工艺，反应离子刻蚀工艺或者离子铣工艺；还可以采用深反应离子刻蚀(Deep Reactive Ion Etching，DRIE)来刻蚀衬底和介质层，来得到通孔。其中DRIE技术是将聚合物钝化层的沉积和对单晶硅的刻蚀这两种工艺过程组合在一起循环交替进行，这样可以避免沉积和刻蚀之间相互影响，保证了钝化层的稳定可靠，从而形成侧壁陡直的高深宽比扇贝结构。最典型的深反应离子刻蚀方法是被称为“博世(Bosch)”工艺的方法，具体过程是，先用六氟化硫(SF 6)刻蚀硅(Si)表面，然后在侧壁上沉积一层聚氟化碳((CF) n)高分子钝化膜，再通入SF 6刻蚀掉钝化膜，接着进行Si基材的刻蚀。
步骤S2024a、在所述通孔内依次形成绝缘层、阻挡层、种子层和导电层，得到所述硅通孔。
在一些实施例中，绝缘层用于隔断填充金属与硅Si之间的电导并且保护衬底不被破坏；绝缘层材料可以采用硅氧化物、硅氮化物和聚合物等，不同绝缘层材料需要用不同的沉积技术，可以采用热氧化技术(Thermal Oxidation)沉积二氧化硅材料，可以采 用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)技术沉积二氧化硅材料和氮化硅(Si 3N 4)材料，可以采用真空气相沉积技术沉积对二甲苯材料。
在一些实施例中，阻挡层用于防止后续填充在硅通孔中的导电材料的扩散；阻挡层的材料可以是金属钽、氮化钽或者氮化钛等，可以通过任意一种合适的沉积工艺形成所述阻挡层。
在一些实施例中，种子层用于为后续在硅通孔中形成导电层，提供衔接作用。种子层的材料可以是任意一种导电材料，例如，钨、钴、铜、铝或其任何组合。
在一些实施例中，导电层的材料可以是任意一种导电金属，例如，钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合，所述导电材料与所述种子材料可以相同，也可以不同。一般来说，导电层的材料采用铜金属，形成铜导电层可以先通过物理气相沉积(Physical Vapor Deposition，PVD)沉积种子层，作为电镀的阴极，通过电化学镀膜(Electro Chemical Plating，ECP)电镀淀积一层铜形成导电层。
步骤S2021a至步骤S2024a分别参见图2A至图2D。如图2A所示，在衬底201的第一面(如图2A中示出的A面)形成有介质层202。如图2B所示，在衬底201的第二面(如图2B中的B面)形成第一光阻层203，图形化第一光阻层203形成第一窗口203a，所述第一窗口203a暴露出所述硅通孔对应的位置。如图2C所示，通过第一窗口203a，刻蚀所述衬底201和介质层202，得到通孔204。如图2D所示，在通孔204的内壁依次形成绝缘层205a、阻挡层205b、种子层205c和导电层205d，形成贯穿所述衬底的硅通孔205。
基于图2A至图2D提供的流程，步骤S203的实现过程可以参见图2E，在衬底的第二面暴露出所述硅盲孔206对应的位置，刻蚀衬底201，最终得到没有贯穿所述衬底201的硅盲孔206。
步骤S2021a至步骤S2024a适用于以下情况：
情况一：在步骤S2021a时，所述介质层上没有其他层。
其中，介质层上的其他层可以是浅沟道隔离层和/或金属层。在实施时，在形成通孔之后再形成其他层。
情况二：在步骤S2021a时，所述介质层上形成有其他层，该其他层是在形成通孔之前形成的。
在一些实施例中，所述通孔也可以是先贯穿介质层，后贯穿衬底，即步骤S202可以包括步骤S2021b至步骤S2023b，其中：步骤S2021b，在所述衬底的第一面形成第一光阻层；步骤S2022b，图形化所述第一光阻层，形成第一窗口，所述第一窗口暴露出所述硅通孔对应的位置；步骤S2023b，通过第一窗口，以所述衬底的第一面为刻蚀起点，刻蚀所述介质层和所述衬底，形成通孔。
步骤S2021b至步骤S2023b适用于上述情况一：即在步骤S2021b时，所述介质层上没有其他层。其中，介质层上的其他层可以是浅沟道隔离层和/或金属层。在实施时，在形成通孔之后再形成其他层。
在一些实施例中，在通过所述第一光阻层中的第一窗口形成通孔后，所述热传导结构的形成方法还包括：去除所述第一光阻层。在实际应用中，可以通过湿法刻蚀工艺或者干法刻蚀工艺去除所述第一光阻层。
在一些实施例中，在硅通孔中形成绝缘层、阻挡层和种子层时，在所述衬底的第二面同时也形成有所述绝缘层、所述阻挡层和所述种子层，因此在形成硅盲孔之前需要对衬底的第二面进行化学机械抛光处理，去除衬底第二面的绝缘层、阻挡层和种子层，暴露出硅衬底的第二面。
基于图2E，本公开实施例还提供一种热传导结构，包括：
衬底201；
在所述衬底201上形成的介质层202；
贯穿所述衬底201和所述介质层202的硅通孔205；
位于所述硅通孔205至少一侧的至少一个硅盲孔206，每一所述硅盲孔206未贯穿所述衬底201。
在一些实施例中，如图2F所示，所述衬底201还包括在所述介质层202上形成的金属层207，所述硅通孔205着陆于所述金属层207。其中，金属层的材料可以是铜。基于图2F，所述结构还包括：在所述介质层202上形成的金属层207；所述硅通孔205着陆于所述金属层207。
本公开实施例还提供一种热传导结构的形成方法，包括：
步骤S301、提供衬底；其中，所述衬底上至少形成有介质层，所述衬底还包括在所述介质层上形成的金属层；所述硅通孔着陆于所述金属层。
步骤S302、以所述衬底的第二面为刻蚀起点，刻蚀所述衬底，形成未贯穿所述衬 底的至少两个盲孔。
其中，与所述衬底的第二面相比，所述金属层靠近所述衬底的第一面，所述衬底的第二面是指在衬底厚度方向上与衬底第一面相对的面。
步骤S303、继续刻蚀所述至少两个盲孔中的一所述盲孔，形成所述硅通孔。
步骤S304、在所述至少两个盲孔的其余每一所述盲孔中形成一所述硅盲孔。
在一些实施例中，步骤S302可以通过以下步骤形成：
步骤S3021、在所述衬底的第二面形成第二光阻层。
这里，可以通过任意一种合适的沉积工艺在硅衬底的第二面形成第二光阻层；所述第二光阻层的材料可以与第一光阻层的材料相同，也可以不同。
步骤S3022、图形化所述第二光阻层，形成第二窗口和第三窗口。
这里，所述第二窗口暴露出所述硅通孔对应的位置，所述第三窗口暴露出所述硅盲孔对应的位置。
在一些实施例中，可以通过曝光、显影等步骤来图形化第二光阻层，形成所述第二窗口和第三窗口。
步骤S3021和步骤S3022参见图3A，在衬底201的第二面(如图3A中的B面)形成第二光阻层208，图形化第二光阻层208形成第二窗口208a和第三窗口208b，所述第二窗口208a和第三窗口208b暴露出衬底201的第二面，所述第二窗口208a暴露出所述硅通孔对应的位置，所述第三窗口208b暴露出所述硅盲孔对应的位置。
步骤S3023、通过第二窗口和第三窗口，刻蚀所述衬底，形成未贯穿所述衬底的至少两个盲孔。
步骤S3021参见图3B，通过第二窗口208a和第三窗口208b，刻蚀所述衬底201，形成未贯穿所述衬底201的至少两个盲孔209，其中，所述盲孔具有第一深度，所述第一深度小于所述衬底的厚度。
在一些实施例中，步骤S303包括：继续刻蚀所述至少两个盲孔中位于所述衬底中间的所述盲孔，形成所述硅通孔。其中，位于所述衬底中间的所述盲孔可以是以直线形式排布的多个盲孔中位于所述衬底中间的盲孔，也可以是以环状形式排布的多个盲孔中的位于衬底中央的盲孔。
在一些实施例中，所述步骤S303可以通过以下步骤来实现：
步骤S3031、在所述其余每一所述盲孔上形成保护层；
其中，保护层用于保护所述其余每一所述盲孔不被刻蚀，保护层所采用的材料可以是光刻胶，也可以是氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料，可以通过任意一种合适的沉积工艺形成保护层。
步骤S3032、刻蚀掉所述硅通孔对应的盲孔内的所述衬底和所述介质层，形成通孔；
步骤S3033、在所述通孔内依次形成绝缘层、阻挡层、种子层和导电层，得到所述硅通孔；
步骤S3034、去除所述保护层。
步骤S3031至步骤S3034分别参见图3C至图3D。如图3C所示，在所述其余每一所述盲孔209上形成保护层210，以衬底201的第二面为刻蚀起点，刻蚀盲孔209内的衬底201和介质层202，形成通孔204。如图3D所示，在所述通孔204内依次形成绝缘层205a、阻挡层205b、种子层205c和导电层205d，得到所述硅通孔205；去掉保护层210。
在一些实施例中，如图3E所示，步骤S304可以通过以下步骤来实现：在所述其余每一所述盲孔209内依次形成绝缘层206a、阻挡层206b、种子层206c和导电层206d，得到一所述硅盲孔206。
在一些实施例中，所述硅盲孔包括的各层可以与所述硅通孔包括的各层不同，也可以相同。在实际应用中，所述硅盲孔包括的各层与所述硅通孔包括的各层相同，可以在步骤S3032后直接进行步骤S3034，同时在通孔和其余盲孔中沉积各层材料，形成不同层，例如沉积绝缘层、阻挡层、种子层和导电层，分别形成硅通孔和硅盲孔，无需分两次在通孔和其余盲孔内沉积绝缘层、阻挡层、种子层和导电层，从而达到简化工艺的效果。
在一些实施例中，所述方法在所述硅通孔和每一所述硅盲孔内包括依次形成的绝缘层、阻挡层、种子层和导电层；这里，所述绝缘层的厚度为
Figure PCTCN2021110135-appb-000003
至
Figure PCTCN2021110135-appb-000004
在一些实施例中，相邻的所述硅通孔的所述绝缘层和一所述硅盲孔的所述绝缘层之间，和/或，相邻的两个所述硅盲孔的所述绝缘层之间的距离为1.5μm，通过设置上述距离参数可以提高热传导效率，进一步提高硅通孔的可靠性和稳定性，同时还可以降低接地噪声。
在一些实施例中，所述硅通孔中的所述绝缘层的厚度大于所述硅盲孔中的所述绝缘层的厚度。
本公开实施例还提供一种热传导结构的形成方法，所述方法包括：
步骤S401、提供衬底。
步骤S402、在所述衬底上依次形成所述浅沟槽隔离层、所述介质层和所述金属层。
步骤S401和步骤S402参见图4A，衬底201的第一面依次形成所述浅沟槽隔离层211、所述介质层202和所述金属层207。
步骤S403、形成硅通孔和至少一个硅盲孔，其中，所述至少一个硅盲孔位于所述硅通孔的至少一侧；所述硅通孔贯穿所述衬底和所述介质层；每一所述硅盲孔未贯穿所述衬底。
步骤S404、在所述衬底的第二面形成与所述至少一个硅盲孔和所述硅通孔互连的再分布层，其中，所述浅沟槽隔离层在所述衬底的第一面上形成，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的面。
如图4B所示，在衬底201的第二面形成与所述至少一个硅盲孔206和所述硅通孔205互连的再分布层212。
在本实施例中，所有硅盲孔和硅通孔都与衬底的第二面的再分布层(Redistribution Layer，RDL)连接，热量在最短距离内传到再分布层中的金属线上，以实现效率热梯度，提高热传输效果；同时RDL接地可以屏蔽基板噪声。
在实际应用中，所述浅沟槽隔离层是通过浅槽隔离技术(Shallow Trench Isolation，STI)形成的，具体通过利用氮化硅掩膜经过淀积、图形化、刻蚀硅后形成槽，并在槽中填充淀积氧化物，用于与硅隔离。
在一些实施例中，所述步骤S403形成硅通孔和至少一个硅盲孔的过程可以通过所述步骤S202和步骤S203实现或者步骤S302至步骤S304实现。
基于图4B，本公开实施例还提供一种热传导结构，包括：
衬底201；位于所述衬底201上与介质层202之间的浅沟槽隔离层211，位于所述介质层202上的金属层207；
贯穿所述衬底201、所述浅沟槽隔离层211和所述介质层202，着陆与所述金属层207的硅通孔205；
位于所述硅通孔205至少一侧的至少一个硅盲孔206，每一所述硅盲孔206未贯穿所述衬底201；
位于所述衬底201的第二面的与所述至少一个硅盲孔206和所述硅通孔205互连的 再分布层212；其中，所述浅沟槽隔离层211位于所述衬底201的第一面上；所述衬底201的第二面是与所述衬底201的第一面在所述衬底201的厚度方向上相对的面。
在一些实施例中，所述硅通孔和所述至少一个硅盲孔的直径为2μm至10μm；所述硅通孔的深度为40μm至100μm，所述至少一个硅盲孔的深度为5μm至67μm。
在实际应用中，由于硅通孔孔径较小，深度较大，深宽比较高，采用均匀电镀工艺镀铜形成的时候会形成电镀空洞，因此可以采用相关技术中的“自底向上”的电镀工艺，利用特殊的电镀促进剂和抑制剂来加速通孔内部的沉积速率和抑制通孔外表面的沉积速率，通过调整促进剂和抑制剂的比例，使二者相互平衡，从而防止电镀空洞的产生。
在一些实施例中，所述衬底上未被所述至少一个硅盲孔贯穿的距离为3μm至65μm。
除此之外，本公开实施例还提供一种芯片，所述芯片至少包括上述热传导结构。
在一些实施例中，如图5所示，所述芯片50至少包括热传导结构，所述热传导结包括：衬底501；在所述衬底501上形成的介质层502；贯穿所述衬底501和所述介质层502的硅通孔503；位于所述硅通孔503至少一侧的至少一个硅盲孔504，每一所述硅盲孔504未贯穿所述衬底501。
在一些实施例中，热传导结构可以参见图2F、图3E或者图4B。
本公开实施例中芯片中的热传导结构与上述实施例中的热传导结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解。
另外，本公开实施例还提供一种芯片堆叠结构，包括：
至少两个芯片；所述至少两个芯片中的每一所述芯片包括上述的热传导结构；
位于每一所述芯片第一面的焊盘，其中，所述焊盘与所述热传导结构中的硅通孔连接；
位于所述芯片第二面的键合焊盘，其中，所述键合焊盘与所述硅通孔相连的金属层连接；所述芯片第二面是与所述芯片第一面在所述芯片厚度上相对的面；
所述至少两个芯片中第一芯片第一面的所述焊盘与所述至少两个芯片中的第二芯片第二面的所述键合焊盘电连接。
在一些实施例中，所述芯片为两个，如图6所示，所述芯片堆叠结构包括：两个芯片60；所述两个芯片中的每一所述芯片60包括上述的热传导结构；
位于每一所述芯片60的第一面(如图6所示的C面)的焊盘601，其中，所述焊盘601与所述热传导结构中的硅通孔连接；
位于所述芯片60的第二面(如图6所示的D面)的键合焊盘602，其中，所述键 合焊盘602与所述硅通孔相连的金属层连接；所述芯片60的第二面是与所述芯片60的第一面在所述芯片60的厚度上相对的面；
所述两个芯片60中第一芯片的第一面的所述焊盘601与所述两个芯片60中的第二芯片的第二面的所述键合焊盘602电连接。
其中，热传导结构可以参见图2E、图2F、图3E或者图4B。
在一些实施例中，所述至少两个芯片可以是四个、六个、八个或者其他数量。
本公开实施例中芯片中的热传导结构与上述实施例中的热传导结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种热传导结构形成方法，所述方法包括：
    提供衬底；其中，所述衬底上至少形成有介质层；
    形成硅通孔和至少一个硅盲孔，其中，所述至少一个硅盲孔位于所述硅通孔的至少一侧；所述硅通孔贯穿所述衬底和所述介质层；每一所述硅盲孔未贯穿所述衬底。
  2. 根据权利要求1所述的方法，其中，所述衬底还包括在所述介质层上形成的金属层；所述硅通孔着陆于所述金属层。
  3. 根据权利要求2所述的方法，其中，所述介质层在所述衬底的第一面上形成；
    所述形成硅通孔和至少一个硅盲孔，包括：
    以所述衬底的第二面为刻蚀起点，刻蚀所述衬底和所述介质层，形成贯穿所述衬底和所述介质层的硅通孔；其中，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的面；
    以所述衬底的第二面为刻蚀起点，刻蚀所述衬底，形成未贯穿所述衬底的至少一个硅盲孔。
  4. 根据权利要求2所述的方法，其中，所述介质层在所述衬底的第一面上形成；所述形成硅通孔和至少一个硅盲孔，包括：
    以所述衬底的第二面为刻蚀起点，刻蚀所述衬底，形成未贯穿所述衬底的至少两个盲孔，其中，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的；
    继续刻蚀所述至少两个盲孔中的一所述盲孔，形成所述硅通孔；
    在所述至少两个盲孔的其余每一所述盲孔中形成一所述硅盲孔。
  5. 根据权利要求4所述的方法，其中，所述继续刻蚀所述至少两个盲孔中的一所述盲孔，形成所述硅通孔，包括：
    继续刻蚀所述至少两个盲孔中位于所述衬底中间的所述盲孔，形成所述硅通孔。
  6. 根据权利要求4所述的方法，其中，所述继续刻蚀所述至少两个盲孔中的一所述盲孔，形成所述硅通孔，包括：
    在所述其余每一所述盲孔上形成阻挡层；
    刻蚀掉所述硅通孔对应的盲孔内的所述衬底和所述介质层，形成所述硅通孔；
    去除所述阻挡层。
  7. 根据权利要求6述的方法，其中，所述刻蚀掉所述硅通孔对应的盲孔内的所述衬底和所述介质层，形成所述硅通孔，包括：刻蚀掉所述盲孔内的所述衬底和所述介质层，形成通孔；在所述通孔内依次形成绝缘层、阻挡层、种子层和导电层，得到所述硅通孔；
    所述在所述至少两个盲孔的其余每一所述盲孔中形成一所述硅盲孔，包括：在所述其余每一所述盲孔内依次形成绝缘层、阻挡层、种子层和导电层，得到一所述硅盲孔。
  8. 根据权利要求1至6任一项所述的方法，其中，在所述硅通孔和每一所述硅盲孔内包括依次形成的绝缘层、阻挡层、种子层和导电层；
    其中，所述绝缘层的厚度为
    Figure PCTCN2021110135-appb-100001
    至
    Figure PCTCN2021110135-appb-100002
  9. 根据权利要求8所述的方法，其中，相邻的所述硅通孔的所述绝缘层和一所述硅盲孔的所述绝缘层之间，和/或，相邻的两个所述硅盲孔的所述绝缘层之间的距离为1.5μm。
  10. 根据权利要求8所述的方法，其中，所述硅通孔中的所述绝缘层的厚度大于所述硅盲孔中的所述绝缘层的厚度。
  11. 根据权利要求1至7任一项所述的方法，其中，所述介质层在所述衬底的第一面上形成；还包括：
    在所述衬底的第二面形成与所述至少一个硅盲孔和所述硅通孔互连的再分布层，其中，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的面。
  12. 根据权利要求1至7任一项所述的方法，其中，还包括：
    提供一衬底；
    在所述衬底上依次形成所述浅沟槽隔离层、所述介质层和所述金属层。
  13. 根据权利要求1至7任一项所述的方法，其中，还包括：
    所述衬底的厚度为40μm至70μm；
    所述硅通孔和所述至少一个硅盲孔的直径为2μm至10μm；
    所述硅通孔的深度为40μm至100μm，所述至少一个硅盲孔的深度为5μm至67μm。
  14. 根据权利要求1至7任一项所述的方法，其中，所述衬底上未被所述至少一个硅盲孔贯穿的距离为3μm至65μm。
  15. 一种热传导结构，包括：
    衬底；
    在所述衬底上形成的介质层；
    贯穿所述衬底和所述介质层的硅通孔；
    位于所述硅通孔至少一侧的至少一个硅盲孔，每一所述硅盲孔未贯穿所述衬底。
  16. 根据权利要求15所述的热传导结构，其中，还包括：在所述介质层上形成的金属层；所述硅通孔着陆于所述金属层。
  17. 根据权利要求16所述的热传导结构，其中，还包括：
    所述硅通孔位于所述至少一个硅盲孔的中间。
  18. 根据权利要求15至17任一项所述的结构，其中，所述硅通孔和每一所述硅盲孔内包括绝缘层、阻挡层、种子层和导电层；
    其中，所述绝缘层的厚度为
    Figure PCTCN2021110135-appb-100003
    至
    Figure PCTCN2021110135-appb-100004
  19. 根据权利要求18所述的结构，其中，相邻的所述硅通孔的所述绝缘层和一所述硅盲孔的所述绝缘层之间，和/或，相邻的两个所述硅盲孔的所述绝缘层之间的距离为1.5μm。
  20. 根据权利要求18所述的结构，其中，所述硅通孔中的所述绝缘层的厚度大于所述硅盲孔中的所述绝缘层的厚度。
  21. 根据权利要求15至17任一项所述的结构，其中，所述介质层位于所述衬底的第一面上；还包括：位于所述衬底的第二面的与所述至少一个硅盲孔和所述硅通孔互连的再分布层；其中，所述衬底的第二面是与所述衬底的第一面在所述衬底的厚度方向上相对的面。
  22. 根据权利要求15至17任一项所述的结构，其中，还包括：
    位于所述衬底与所述介质层之间的浅沟槽隔离层；
    位于所述介质层上的金属层。
  23. 根据权利要求15至17任一项所述的结构，其中，所述衬底的厚度为40μm至70μm；
    所述硅通孔和所述硅盲孔的直径为2μm至10μm；
    所述硅通孔的深度为40μm至100μm，所述硅盲孔的深度为5μm至67μm。
  24. 根据权利要求15至17所述的结构，其中，所述衬底上未被所述硅盲孔贯穿的距离为3μm至65μm。
  25. 一种芯片，所述芯片至少包括所述权利要求15至24任一项所述的热传导结构。
  26. 一种芯片的堆叠结构，包括：至少两个芯片；
    所述至少两个芯片中的每一所述芯片包括权利要求15至25任一项所述的热传导结 构；
    位于每一所述芯片第一面的焊盘，其中，所述焊盘与所述热传导结构中的硅通孔连接；
    位于所述芯片第二面的键合焊盘，其中，所述键合焊盘与所述硅通孔相连的金属层连接；所述芯片第二面是与所述芯片第一面在所述芯片厚度上相对的面；
    所述至少两个芯片中第一芯片第一面的所述焊盘与所述至少两个芯片中的第二芯片第二面的所述键合焊盘电连接。
PCT/CN2021/110135 2021-07-20 2021-08-02 热传导结构及其形成方法、芯片及芯片堆叠结构 WO2023000378A1 (zh)

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