WO2022270309A1 - 半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器 - Google Patents

半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器 Download PDF

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Publication number
WO2022270309A1
WO2022270309A1 PCT/JP2022/023088 JP2022023088W WO2022270309A1 WO 2022270309 A1 WO2022270309 A1 WO 2022270309A1 JP 2022023088 W JP2022023088 W JP 2022023088W WO 2022270309 A1 WO2022270309 A1 WO 2022270309A1
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Prior art keywords
semiconductor
semiconductor device
manufacturing
substrate
main substrate
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PCT/JP2022/023088
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English (en)
French (fr)
Japanese (ja)
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賢太郎 村川
剛 神川
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Kyocera Corp
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Kyocera Corp
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Priority to KR1020237043617A priority Critical patent/KR20240010014A/ko
Priority to JP2023529812A priority patent/JP7637237B2/ja
Priority to EP22828226.5A priority patent/EP4362115A1/en
Priority to US18/572,005 priority patent/US20240313151A1/en
Publication of WO2022270309A1 publication Critical patent/WO2022270309A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/04—Pattern deposit, e.g. by using masks
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/817—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H10P14/272—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using mask materials other than SiO2 or SiN
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/276—Lateral overgrowth
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2904—Silicon carbide
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations

Definitions

  • the present disclosure relates to a method of manufacturing a semiconductor device and the like.
  • Patent Literature 1 discloses a method of forming through holes in a sapphire substrate and a GaN buffer layer grown thereon, and extracting an electrode in contact with a GaN contact layer through the through holes to the lower side of the sapphire substrate.
  • a method of manufacturing a semiconductor device includes steps of preparing a template substrate having a main substrate and a mask pattern located above the main substrate and including a mask portion and an opening, and employing an ELO method. removing a portion of the main substrate overlapping the opening in plan view; and removing the opening in plan view of the first semiconductor part. and removing the portion that overlaps the portion.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment;
  • FIG. It is a flow chart which shows an example of a manufacturing method of a semiconductor device concerning this embodiment. It is a sectional view showing an example of a manufacturing method of a semiconductor device concerning this embodiment.
  • 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment;
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to Example 1;
  • FIG. 1 is a cross-sectional view showing the configuration of an electronic device according to Example 1;
  • FIG. 4 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
  • FIG. 4 is a cross-sectional view showing another example of the method for manufacturing the semiconductor device according to Example 1;
  • FIG. 11 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device according to Example 2; 10 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 3; FIG. 11 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 3;
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment.
  • a semiconductor device 20 includes a first semiconductor portion 8 and a second semiconductor portion 9 located in an upper layer (above) than the first semiconductor portion 8 and including an active layer.
  • the first semiconductor section 8 may be a first semiconductor layer containing a nitride semiconductor (for example, a GaN-based semiconductor), and the second semiconductor section 9 may be a second semiconductor layer containing a nitride semiconductor.
  • the first semiconductor portion 8 includes an upper surface 8a that is the (0001) plane and a lower surface 8b that is the (000-1) plane.
  • the length of the upper surface 8a in the ⁇ 11-20> direction can be longer than the length of the lower surface 8b in the ⁇ 11-20> direction. This facilitates the manufacturing process of the semiconductor device 20 .
  • FIG. 2 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to this embodiment. 2 and 3, after the step of preparing a template substrate (ELO growth substrate) 7, an ELO film is formed on the template substrate 7 including the mask portion 5 and the mask pattern 6 including the opening K. A first semiconductor portion 8 is formed using a method. Next, a step of forming the second semiconductor portion 9 is performed. After that, the main substrate 1 is etched from its back surface to remove the portion of the main substrate 1 that overlaps the opening K of the mask pattern 6 in plan view.
  • a step of removing the portion of the first semiconductor portion 8 that overlaps the opening K of the mask pattern 6 in plan view is performed. This makes it easier to separate the semiconductor device from the template substrate 7 .
  • "two members overlap in plan view” means that "at least a part of one member overlaps the other in plan view (including transparent plan view) viewed in the normal direction of the main substrate 1". is.
  • FIG. 4 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment.
  • the formation unit 72 may include a MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and memory.
  • the control unit 74 may be configured to control the forming unit 72 and the processing unit 73 by executing a program stored in an internal memory, a communicable communication device, or an accessible network, for example.
  • the above program and a recording medium storing the above program are also included in this embodiment.
  • FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.
  • a semiconductor device 20 according to Example 1 includes a first semiconductor portion 8, and is positioned on the first semiconductor portion 8 and includes an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P.
  • a first electrode E1 located on the p-type semiconductor layer 9P; and a second electrode E2 located on the first semiconductor part 8.
  • the active layer 9E is, for example, a light emitting layer.
  • the first electrode E1 is the anode.
  • the second semiconductor portion 9 is provided on the first semiconductor portion 8, but the second semiconductor portion 9 is not formed above a portion of the first semiconductor portion 8, and the portion of the first semiconductor portion 8 is not formed above the portion of the first semiconductor portion 8.
  • a second electrode E2 which is a cathode, may be provided so as to be in contact with the .
  • the first semiconductor portion 8 includes a nitride semiconductor (eg, GaN-based semiconductor).
  • a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
  • GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N)
  • the ⁇ 0001> direction (thickness direction, c-axis direction) of the GaN-based semiconductor is the Z direction
  • the ⁇ 11-20> direction (a-axis direction) of the GaN-based semiconductor is the X-direction
  • the ⁇ 1- 100> direction (m-axis direction) can be the Y direction.
  • the first semiconductor portion 8 can be formed by an ELO (Epitaxial Lateral Overgrowth) method.
  • the first semiconductor section 8 may contain an n-type dopant such as Si.
  • the first semiconductor portion 8 includes an upper surface 8a that is the (0001) plane and a lower surface 8b that is the (000-1) plane.
  • the second semiconductor portion 9 includes an upper surface 9a that is the (0001) plane and a lower surface 9b that is the (000-1) plane.
  • the length of the upper surface 8a of the first semiconductor portion 8 in the ⁇ 11-20> direction (X direction) may be longer than the length of the lower surface 8b in the ⁇ 11-20> direction (X direction).
  • the length of the ⁇ 11-20> direction (X direction) of the upper surface 9a of the second semiconductor portion 9 is less than the length of the lower surface 9b of the second semiconductor portion 9 (n-type semiconductor layer 9N).
  • 11-20> direction (X direction) This facilitates the manufacturing process of the semiconductor device 20 (described later).
  • semiconductor device 20 include light emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, transistors (including power transistors and high electron mobility transistors), and the like.
  • LEDs light emitting diodes
  • semiconductor lasers semiconductor lasers
  • Schottky diodes Schottky diodes
  • photodiodes transistors (including power transistors and high electron mobility transistors), and the like.
  • FIG. 6 is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
  • a micro LED display 30 (electronic device) includes the semiconductor device 20 described above fabricated as a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B.
  • the micro LED display 30 also includes a drive board 23 on which these semiconductor devices 20 are mounted, a control circuit 25 that controls the drive board 23, and a driver circuit 29 that drives the semiconductor devices 20.
  • the red micro-LED 20R, the green micro-LED 20G, and the blue micro-LED 20B are mounted on the plurality of pixel circuits 27 of the drive substrate 23 with conductive resin (for example, anisotropic conductive resin) or the like.
  • conductive resin for example, anisotropic conductive resin
  • a portion of the driver circuit 29 may be included in the drive substrate 23 .
  • examples of electronic devices include display devices, laser emitting devices (including Fabry-Perot type and surface emitting type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like. can be done.
  • FIG. 7 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 8 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1.
  • FIG. 9 and 10 are plan views showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
  • a step of preparing a template substrate (ELO growth substrate) 7 is performed.
  • the template substrate 7 includes the main substrate 1, the underlying portion 4, and the mask pattern 6 in this order, and the mask pattern 6 includes the mask portion 5 and the opening portion K.
  • the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
  • a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed. Thereby, the semiconductor substrate 10 is formed.
  • etching deep etching
  • a step of removing the portion of the main substrate 1 overlapping the opening K of the mask pattern 6 in plan view is performed.
  • the thickness of the main substrate 1 may be reduced by polishing the back surface of the main substrate 1 or the like. By doing so, the etching depth is reduced and the etching accuracy is improved.
  • the portions of the underlying portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlap with the opening portion K of the mask pattern 6 in plan view are removed.
  • a step of forming trenches TY extending in the direction is performed.
  • the connecting portion between the base portion 4 (seed portion 3) and the first semiconductor portion 8 is removed.
  • the partial removal of the first semiconductor section 8 may be followed (continuously) by the partial removal of the second semiconductor section 9 .
  • Etching in this step may be dry etching or wet etching. In the case of dry etching, side etching can be suppressed. For wet etching, phosphoric acid or a mixed solution of phosphoric acid can be used.
  • a GaN-based semiconductor has an N face (bottom face) and a Ga face (top face), which are polar faces, in the c-axis direction. It has a characteristic that the etching rate from the N surface ((000-1) surface), which is the lower surface, is higher. Etching (especially, dry etching) from the rear surface (lower surface) of the first semiconductor section 8 can increase the etching speed and accuracy.
  • the back surface (lower surface) of the first semiconductor portion 8 is not limited to a polar surface. It may be a semipolar plane inclined from the c-plane. A combination surface of a polar surface and a semi-polar surface may be used.
  • the trench TY extending in the Y direction is formed, but as shown in FIG. 10, the trench TX extending in the X direction may be formed in the same process as the formation of the trench TY.
  • a step of separating the template substrate 7 and the first semiconductor portion 8 is performed. Since the adhesive force between the mask portion 5 and the first semiconductor portion 8 is weak (mainly due to von der Waals force), for example, the first and second semiconductor portions 8 and 9 are adhered to a flexible adhesive sheet. In this state, the first semiconductor section 8 can be peeled off from the mask section 5 . That is, it is easy to separate the template substrate 7 and the first semiconductor portion 8 . As a result, the first and second semiconductor parts 8 and 9, etc. are singulated, and a plurality of semiconductor devices 20 are formed.
  • trench TY has a tapered shape that tapers upward (in the direction from main substrate 1 to mask pattern 6)
  • the ⁇ 11-20> direction (X direction) of first semiconductor portion upper surface 8a ) is longer than the length of the first semiconductor portion lower surface 8b in the ⁇ 11-20> direction (X direction).
  • the length of the second semiconductor portion upper surface 9a in the ⁇ 11-20> direction (X direction) is longer than the length of the second semiconductor portion lower surface 9b in the ⁇ 11-20> direction (X direction).
  • FIG. 11 and 12 are cross-sectional views showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
  • the step of removing the portion of the first semiconductor portion 8 that overlaps with the opening K of the mask pattern 6 in plan view may be performed in a state where the main substrate 1 is positioned vertically upward, as shown in FIG.
  • an anchor film AF for example, an inorganic film such as a silicon oxide film, a silicon nitride film, etc.
  • insulating film may be formed. This reduces the risk that the first semiconductor portion 8 will drop from the mask pattern 6 when the joint portion between the first semiconductor portion 8 and the underlying portion 4 is removed.
  • FIG. 13 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1.
  • the first and second electrodes E1 and E2 are arranged in the X direction in FIGS. 8 and 9, etc., the arrangement is not limited to this.
  • the first and second electrodes E1 and E2 may be arranged in the Y direction.
  • the area of the first electrode E1 may be larger than that of the second electrode E2.
  • a heterosubstrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1 .
  • hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC, silicon carbide) substrates, and the like.
  • the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate. These are just examples, and any main substrate and plane orientation may be used as long as the first semiconductor portion 8 can be grown by the ELO method.
  • the main substrate 1 is not limited to a heterosubstrate, and may be a GaN substrate (bulk).
  • the base portion 4 As the base portion 4, as shown in FIG. 8, the buffer portion 2 and the seed portion 3 can be provided in order from the main substrate 1 side.
  • the base portion 4 may be a base layer.
  • the buffer section 2 may be a buffer layer.
  • the seed portion 3 may be a seed layer.
  • the buffer section 2 has, for example, a function of reducing the direct contact between the main substrate 1 and the seed section 3 and the mutual melting. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, both (the main substrate and the seed layer) melt together. By providing a buffer portion 2 containing one side, melting is reduced.
  • An AlN layer which is an example of the buffer section 2, can be formed to a thickness of about 10 nm to about 5 ⁇ m using, for example, an MOCVD apparatus.
  • the buffer portion 2 may have at least one of the effect of increasing the crystallinity of the seed portion 3 and the effect of relieving the internal stress of the first semiconductor portion 8 (relieving the warp of the semiconductor substrate 10).
  • a configuration without the buffer portion 2 is also possible.
  • At least one of the buffer portion 2 (eg, aluminum nitride) and the seed portion 3 (eg, GaN-based semiconductor) can be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).
  • PLD pulse sputter deposition
  • PLD pulse laser deposition
  • the opening K of the mask pattern 6 exposes the seed portion 3 and functions as a growth start hole for starting the growth of the first semiconductor portion 8.
  • the mask portion 5 allows the first semiconductor portion 8 to grow laterally. It has the function of a mask for selective growth that allows Mask pattern 6 may be mask layer 6 .
  • the opening K may be a portion without the mask portion 5 , and the opening K may not be surrounded by the mask portion 5 .
  • SiOx silicon oxide film
  • TiN titanium nitride film
  • SiNx silicon nitride film
  • SiON silicon oxynitride film
  • metal film having a high melting point for example, 1000° C. or higher.
  • a silicon oxide film having a thickness of about 100 nm to 4 ⁇ m (preferably about 150 nm to 2 ⁇ m) is formed on the underlying portion 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film.
  • the resist is patterned by photolithography to form a resist having a plurality of striped openings.
  • a part of the silicon oxide film is removed with a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including K), and the resist is removed by organic cleaning to form a mask.
  • a pattern 6 is formed.
  • the openings K have a longitudinal shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor portion 8 .
  • the width of the opening K is about 0.1 ⁇ m to 20 ⁇ m. The smaller the width of each opening K, the smaller the number of threading dislocations propagating from each opening K to the first semiconductor portion 8 . Also, the low-defect portion in the first semiconductor portion 8 can be enlarged.
  • the silicon oxide film decomposes and evaporates in small amounts during the film formation of the first semiconductor part 8, and may be incorporated into the first semiconductor part 8.
  • the silicon nitride film and the silicon oxynitride film decompose at high temperatures. , has the advantage of being difficult to evaporate.
  • the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4.
  • 4 may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order, or a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on an underlying layer.
  • a good mask pattern 6 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method.
  • the seed portion 3 of the base portion 4 is formed by a first layer of Al 0.6 Ga 0.4 N layer (for example, 300 nm) and a second layer of GaN layer (for example, 1 to 2 ⁇ m), which are formed in this order. and graded layer.
  • a layered body in which a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5 .
  • the thickness of the silicon oxide film is, for example, 0.3 ⁇ m, and the thickness of the silicon nitride film is, for example, 70 nm.
  • a plasma-enhanced chemical vapor deposition (CVD) method was used to form each of the silicon oxide film and the silicon nitride film.
  • the first semiconductor portion 8 is formed by an ELO (Epitaxial Lateral Overgrowth) method, overlaps the mask portion 5 in plan view, and includes a low dislocation portion SD with relatively few threading dislocations and an opening K of the mask pattern 6 in plan view. and includes a high dislocation portion HD having relatively more threading dislocations than a low dislocation portion (see FIG. 8).
  • the threading dislocation density of the low dislocation portion SD may be 1 ⁇ 5 or less of the threading dislocation density of the high dislocation portion HD.
  • the threading dislocation density of the low dislocation portion SD may be 5 ⁇ 10 6 /cm 2 or less. In the low dislocation portion SD, the non-threading dislocation density may be higher than the threading dislocation density.
  • Threading dislocations are dislocations (defects) that extend from the lower surface or inside of the first semiconductor part 8 to its surface or superficial layer along the thickness direction (Z direction) of the first semiconductor part 8 . Threading dislocations can be observed by performing CL (Cathode Luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8 .
  • Non-threading dislocations are dislocations that are CL-measured in a cross section along a plane (eg, m-plane) parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.
  • the luminous efficiency of the active layer 9E can be increased by overlapping the light emitting region (the portion under the anode) of the active layer 9E with the low dislocation portion SD in plan view. This is because the portion of the second semiconductor portion 9 that overlaps the low dislocation portion SD in plan view inherits the low dislocation property of the first semiconductor portion 8 .
  • the first semiconductor portion 8 was a GaN layer, and an ELO film of gallium nitride (GaN) was formed on the template substrate 7 using the MOCVD apparatus provided in the formation portion 72 .
  • the first semiconductor portion 8 is selectively grown (vertically grown) on the seed portion 3 (the GaN layer that is the second layer) exposed in the opening K, and subsequently grown laterally on the mask portion 5 . . Then, the lateral growth was stopped before the first semiconductor portion 8 growing laterally from both sides of the mask portion 5 joined together.
  • the width Wm of the mask portion 5 is 50 ⁇ m
  • the width of the opening K is 5 ⁇ m
  • the width of the first semiconductor portion 8 is 53 ⁇ m
  • the width of the low defect portion (size in the X direction) is 24 ⁇ m
  • the layer thickness of the first semiconductor portion 8 is was 5 ⁇ m.
  • the lateral film formation rate is increased.
  • a technique for increasing the lateral film formation rate is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
  • the second semiconductor section 9 includes an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P in order from the lower layer side.
  • the active layer 9E is, for example, an MQW (Multi-Quantum Well) structure and contains, for example, InGaN or GaN.
  • the n-type semiconductor layer 9N is, for example, an AlGaN layer.
  • the p-type semiconductor layer 9P is, for example, a p-type GaN layer.
  • a first electrode E1, which is an anode, is arranged so as to be in contact with the p-type semiconductor layer 9P.
  • the first and second semiconductor parts 8 and 9 may be continuously formed by the same apparatus (for example, MOCVD apparatus), or after the formation of the first semiconductor part 8, the substrate is once removed from the apparatus and the surface of the first semiconductor part 8 is removed.
  • the second semiconductor section 9 may be formed after performing polishing or the like.
  • a sputtering apparatus in addition to the MOCVD apparatus, a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, or the like can be used. Since the remote plasma CVD apparatus and the PSD apparatus do not use hydrogen as a carrier gas, a p-type GaN-based semiconductor with low resistance can be formed.
  • the MQW structure of the active layer 9E can be, for example, a structure of 5 to 6 cycles of InGaN/GaN.
  • the In composition differs depending on the target emission wavelength. For blue (around 450 nm), the In concentration can be about 15-20%, and for green (about 530 nm), the In concentration can be about 30%.
  • An electron blocking layer eg, AlGaN layer
  • the surface (about 10 nm) of the p-type semiconductor layer 9P may be a p-type highly doped layer.
  • the first and second electrodes E1 and E2 have, for example, a single layer structure containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn and In, or It may have a multilayer structure.
  • FIG. 14 and 15 are cross-sectional views showing another example of the semiconductor device manufacturing method according to the first embodiment.
  • the underlying portion 4 is formed entirely on the main substrate 1, but the present invention is not limited to this.
  • the underlying portion 4 can also be locally formed so as to overlap with the opening portion K of the mask pattern 6 in plan view.
  • FIG. 15 by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H—SiC substrate as the main substrate 1, the base portion 4 is not provided, and the upper surface of the main substrate 1 is used as a seed.
  • One semiconductor portion 8 can also be grown.
  • the template substrate 7 including the main substrate 1 and the mask pattern 6 on the main substrate 1 may be used.
  • the template substrate 7 may have a growth suppression region (for example, a region for suppressing crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening K.
  • a growth suppression region and a seed region can be formed on the main substrate 1, and the first semiconductor section 8 can be formed on the growth suppression region and the seed region using the ELO method.
  • FIG. 16 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
  • 17A and 17B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
  • a step of preparing a template substrate (ELO growth substrate) 7 is performed.
  • the template substrate includes a main substrate 1, an underlying portion 4 and a mask pattern 6 in this order, and the mask pattern 6 includes the mask portion 5 and the opening K.
  • the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
  • a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed.
  • a step of removing the entire main substrate 1 and a step of removing the entire base portion 4 are performed.
  • the mask portion 5, which is a selective growth mask, is used (made to function) as an etching mask, and the portions of the first and second semiconductor portions 8 and 9 overlapping the opening portion K of the mask pattern 6 in plan view are removed. carry out the process.
  • a step of removing the mask portion 5 using hydrogen fluoride (HF) is performed.
  • HF hydrogen fluoride
  • FIG. 18 and 19 are cross-sectional views showing another example of the semiconductor device manufacturing method according to the second embodiment.
  • the underlying portion 4 is formed entirely on the main substrate 1, but it is not limited to this.
  • the underlying portion 4 can also be locally formed so as to overlap with the opening portion K of the mask pattern 6 in plan view.
  • FIG. 19 by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H—SiC substrate as the main substrate 1, the base portion 4 is not provided, and the upper surface of the main substrate 1 is used as a seed.
  • One semiconductor portion 8 can also be grown.
  • FIG. 20 is a flow chart showing another example of the semiconductor device manufacturing method according to the second embodiment.
  • FIG. 21 is a cross-sectional view showing another example of the semiconductor device manufacturing method according to the second embodiment.
  • 20 and 21 after the semiconductor substrate 10 including the first and second semiconductor portions 8 and 9 is formed, the support substrate FK is bonded to the opposite side of the main substrate 1. As shown in FIG. As a result, the first and second semiconductor parts 8 and 9 and the first and second electrodes E and E2 are held by the support substrate FK. After that, the entire main substrate 1 is removed. This facilitates handling after the main substrate 1 is removed. In this case, the mounting process can be omitted by using the support substrate FK as a mounting substrate (sub-mount substrate or driving substrate). Note that the first and second semiconductor parts 8 and 9 may be transferred from the support substrate FK to another mounting substrate.
  • FIG. 22 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the third embodiment.
  • 23A and 23B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.
  • a step of preparing a template substrate (ELO growth substrate) 7 is performed.
  • the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
  • a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed.
  • the main substrate 1 is etched (deep etching) from its back surface to remove the portion of the main substrate 1 that overlaps the opening K of the mask pattern 6 in plan view.
  • the portions of the underlying portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlap with the opening portion K of the mask pattern 6 in plan view are removed. Then, a step of forming trenches TY extending in the direction is performed. Thereafter, a step of removing the entire main substrate 1 and a step of separating the first semiconductor portion 8 from the mask pattern 6 are performed.

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PCT/JP2022/023088 2021-06-21 2022-06-08 半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器 Ceased WO2022270309A1 (ja)

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