WO2022267025A1

WO2022267025A1 - Capacitor, integrated circuit, radio frequency circuit and electronic device

Info

Publication number: WO2022267025A1
Application number: PCT/CN2021/102445
Authority: WO
Inventors: 王邦麟; 王生荣; 童庆强
Original assignee: 华为技术有限公司
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2022-12-29
Also published as: CN117501430A

Abstract

The embodiments of the present application relate to the technical field of semiconductors, and are used for improving a Q value of a capacitor, such that the performance of an impedance matching network having the capacitor is also improved. Provided are a capacitor, an integrated circuit, a radio frequency circuit and an electronic device. A capacitor in an impedance matching network of the integrated circuit comprises an electrode structure and a capacitor substrate. The electrode structure comprises a plurality of first finger electrodes, which are electrically connected, and a plurality of second finger electrodes, which are electrically connected, wherein the first finger electrodes and the second finger electrodes are arranged in a staggered manner. An N-type well is arranged on a semiconductor substrate, and the first finger electrodes and the second finger electrodes are arranged above the N-type well. The N-well is floating in the electric potential.

Description

A capacitor, integrated circuit, radio frequency circuit and electronic equipment

technical field

The present application relates to the technical field of semiconductors, and in particular to a capacitor, an integrated circuit, a radio frequency circuit and electronic equipment.

Background technique

With the development of wireless communication technology, in order to improve the efficiency of electronic equipment transmission signal, an impedance matching network (impedance matching network) can be set on the signal transmission line in the electronic equipment. Through the impedance matching network, impedance conjugate matching can be achieved between the signal source and the load connected at both ends of the transmission line, referred to as impedance matching. In this way, almost all high-frequency signals radiated by the signal source can be transmitted to the load after passing through the transmission line, so as to reduce the probability of the signal being reflected back to the signal source.

However, at present, due to the limited Q value of the capacitor, the above-mentioned high-frequency signal will be greatly attenuated after passing through the above-mentioned impedance matching network, which leads to the performance degradation of the impedance matching network.

Contents of the invention

Embodiments of the present application provide a capacitor, an integrated circuit, a radio frequency circuit, and an electronic device, which are used to increase the Q value of the capacitor, thereby also improving the performance of an impedance matching network having the capacitor.

In order to achieve the above object, the application adopts the following technical solutions:

The first aspect of the embodiments of the present application provides an integrated circuit, which can be manufactured in a chip. The integrated circuit includes an impedance matching network. The impedance matching network may include a capacitor and an inductor electrically connected to the capacitor. Wherein, the capacitor may include an electrode structure and a capacitor substrate for carrying the electrode structure. The electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes; the first finger electrodes and the second finger electrodes are arranged alternately. The capacitor substrate includes an N-type well. The N-type well is arranged on the semiconductor substrate of the integrated circuit, and the above-mentioned first finger electrode and the second finger electrode are arranged on the N-type well. In addition, the N-type well is at potential floating.

It can be seen from the above that, between the first finger electrode and the semiconductor substrate, there is an N-type well at a floating potential. In this way, there may be a parasitic capacitance between the first finger electrode and the N-type well. In addition, there is a parasitic capacitance between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, between the second finger electrode and the semiconductor substrate, an N-type well at a floating potential is provided. There may be a parasitic capacitance between the second finger electrode and the N-type well. There is a parasitic capacitance between the N-type well under the second finger electrode and the semiconductor substrate. In this case, two parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the solutions of the embodiments of the present application, the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate. Similarly, two parasitic capacitors are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and finally achieve The purpose of reducing the parasitic capacitance between the entire capacitor and the semiconductor substrate is conducive to improving the Q value of the capacitor. Based on this, on the one hand, when the above-mentioned capacitor is used in the impedance matching network, since the capacitor has a higher Q value, the attenuation of the high-frequency circuit signal by the capacitor is smaller, which is conducive to improving the performance of the impedance matching network and reducing the load. The reflection of the terminal signal improves the conversion rate of the electrical signal. On the other hand, since the signal reflected by the load end is reduced, the heat converted by the reflected signal will be correspondingly reduced, thereby effectively reducing the probability of temperature rise of the electronic device and improving the life of the electronic device.

Optionally, the capacitor substrate further includes a P-type well. It is arranged between the electrode structure and the N-type well. The P-type well is in potential floating. In this case, an N-type well and a P-type well in a floating state are arranged between the first finger electrode and the semiconductor substrate. In this way, there may be a parasitic capacitance between the first finger electrode and the P-type well. In addition, there is a parasitic capacitance between the P-type well below the first finger electrode and the N-type well below the first finger electrode. There is a parasitic capacitance between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate. In this way, there may be a parasitic capacitance between the second finger electrode and the P-type well. In addition, there is a parasitic capacitance between the P-type well under the second finger electrode and the N-type well under the second finger electrode. There is a parasitic capacitance between the N-type well under the second finger electrode and the semiconductor substrate. In this case, three parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the solutions of the embodiments of the present application, the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate. Similarly, there are three parasitic capacitors connected in series between the second finger electrode and the semiconductor substrate. Similarly, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and ultimately reduce the entire capacitance and the semiconductor substrate. The purpose of the parasitic capacitance between the substrates is to improve the Q value of the capacitor, thereby also improving the performance of the impedance matching network with the capacitor.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the N-type well is located. In this way, it is beneficial to increase the relative area between the first finger electrode and the N-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the N-type well. Similarly, it is beneficial to increase the relative area between the second finger electrode and the N-type well in the electrode structure, making it easier to form parasitic capacitance between the second finger electrode and the N-type well.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located. In this way, it is beneficial to increase the relative area between the first finger electrode and the P-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the P-type well. Similarly, it is beneficial to increase the relative area between the second finger electrode and the P-type well in the electrode structure, making it easier to form parasitic capacitance between the second finger electrode and the P-type well.

Optionally, the capacitor also includes an interconnection structure. One end of the interconnect structure is in contact with the semiconductor substrate, and the other end of the interconnect structure is used for grounding. In this way, the semiconductor substrate can be grounded through the interconnect structure.

Optionally, the interconnection structure includes a P-type semiconductor doped part, a first through hole and a metal part. Wherein, the P-type semiconductor doped part is disposed on the semiconductor substrate. The P-type semiconductor doping part is used to improve the conductivity between the semiconductor substrate and the first through hole, which is beneficial to signal transmission. The first through hole penetrates through the dielectric layer, and the first end of the first through hole is electrically connected with the P-type semiconductor doped part. The metal part is arranged on the surface of the dielectric layer away from the semiconductor substrate, electrically connected to the second end of the first through hole, and the metal part is used for grounding. The P-type semiconductor doped part is used as one end of the interconnection structure for connecting with the semiconductor substrate. As the other end of the interconnection structure, the metal part is used for grounding. The metal part is made of metal material and has good conductivity, and is used to improve the conductivity of the entire interconnection structure, so that the grounding performance of the semiconductor substrate is good.

Optionally, the interconnection structure is arranged around a circle of the N-type well and connected end to end. In this way, all parts of the semiconductor substrate can be evenly grounded, so that the performance of the capacitor is stable, which is beneficial to provide the Q value of the capacitor, thereby also improving the performance of the impedance matching network with the capacitor.

On this basis, the material of the metal portion is the same as that of the first finger electrode or the second finger electrode. In this way, the fabrication of the metal part can be completed while fabricating the first finger electrode or the second finger electrode, so as to achieve the purpose of briefly describing the fabrication process.

Optionally, the electrode structure further includes a first interconnect electrode and a second interconnect electrode. A plurality of first finger electrodes and the first interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure. A plurality of second finger electrodes and the second interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure. The first finger electrode and the second finger electrode are arranged in the same layer and in parallel. In this case, the plurality of first finger electrodes, the plurality of second finger electrodes, the first interconnection electrodes and the second interconnection electrodes may be of the same layer and of the same material. In this way, the first finger electrode, the second finger electrode, the first interconnection electrode and the second interconnection electrode can be formed simultaneously by using the above-mentioned one-time communication process.

Optionally, the electrode structure further includes a first interconnect electrode and a second interconnect electrode. A plurality of first finger electrodes and the first interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure. A plurality of second finger electrodes and the second interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure. The first finger electrode and the second finger electrode are arranged vertically in different layers. A capacitor can also be formed between the first finger-shaped electrode and the second finger-shaped electrode by using different layers.

Optionally, the capacitor further includes an insulating layer and a plurality of electrode structures, and the plurality of electrode structures are stacked. The electrode structure is disposed in the insulating layer. The capacitor also includes a second through hole and a third through hole penetrating through at least a part of the insulating layer. The first finger electrodes in the plurality of electrode structures are all electrically connected to the second through holes. The second finger electrodes in the plurality of electrode structures are all electrically connected to the third through holes. In this way, by providing a multi-layer stacked electrode structure, and the multiple first finger electrodes in the electrode structures of different layers are all electrically connected to the second through hole, and the multiple second finger electrodes are all connected to the first through hole. The three through holes are electrically connected to increase the capacitance of the capacitor.

Optionally, the impedance matching network is an L-type matching network, a π-type matching network, or a T-type matching network. Those skilled in the art can select the type of the impedance matching network according to needs.

A second aspect of the embodiments of the present application provides a radio frequency circuit. The radio frequency circuit includes a radio frequency transceiver. A radio frequency transceiver is used for electrical connection with the antenna. In addition, the radio frequency circuit also includes any one of the above-mentioned integrated circuits. The impedance matching network in the integrated circuit is electrically connected between the radio frequency transceiver and the antenna. The radio frequency circuit has the same technical effect as that of the impedance matching network provided by the foregoing embodiments, which will not be repeated here.

Optionally, the radio frequency circuit further includes a field effect transistor. The field effect transistor is integrated in the integrated circuit. In this way, at the same time as manufacturing the above-mentioned field effect transistor, the preparation of the above-mentioned capacitance part structure can be completed, thereby facilitating the simplification of the manufacturing process.

Optionally, the radio frequency circuit further includes a power amplifier, at least one of the output end of the power amplifier and the input end of the power amplifier is electrically connected to the impedance matching network. The above-mentioned field effect transistor is arranged in the power amplifier, and at least a part of the field effect transistor and at least a part of the capacitor substrate are of the same layer and material. In this way, at the same time as the above-mentioned field effect transistor is manufactured, the preparation of a part of the structure of the capacitor substrate can be completed, thereby facilitating the simplification of the manufacturing process.

Optionally, the radio frequency circuit further includes a low noise amplifier, at least one of the output terminal of the low noise amplifier and the input terminal of the low noise amplifier is electrically connected to the impedance matching network. The above-mentioned field effect transistor is arranged in the low noise amplifier, at least a part of the field effect transistor and at least a part of the capacitor substrate are in the same layer and material. In this way, at the same time as the above-mentioned field effect transistor is manufactured, the preparation of a part of the structure of the capacitor substrate can be completed, thereby facilitating the simplification of the manufacturing process.

Optionally, the capacitor substrate further includes a P-type well. The P-type well is located above the N-type well, the surface of the P-type well close to the electrode structure is flush with the first surface, and the rest of the surface is surrounded by the N-type well. The P-type well is in potential floating. Wherein, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located. In this case, the field effect transistor includes: a P-type transistor substrate on a semiconductor substrate, an N-type source region, and an N-type drain region. The semiconductor substrate and the semiconductor substrate have the same layer and the same material, and have an integrated structure. In this way, the above-mentioned capacitor and field effect transistor can be fabricated in different regions on the same semiconductor substrate. In addition, the P-type transistor substrate is disposed on the semiconductor substrate, and has the same layer and the same material as the P-type well. In this way, in the semiconductor substrate, the above-mentioned P-type doping process can be used to form a P-type well at the position corresponding to the capacitor, and at the same time, the above-mentioned P-type doping process can be used to form a P-type transistor substrate at the position corresponding to the field effect transistor. , so as to achieve the purpose of simplifying the manufacturing process. In addition, both the N-type source region and the N-type drain region of the field effect transistor are disposed on the substrate of the P-type transistor. Moreover, the N-type source region and the N-type drain region are arranged at intervals. In this case, after the above-mentioned P-type transistor substrate is fabricated, the above-mentioned N-type doping process may be used to form an N-type source region and an N-type drain region on the P-type transistor substrate. Next, metal can be used to form the gate, source, and drain of the field effect transistor. In this case, the field effect transistor is an N-type transistor.

Optionally, the capacitor substrate further includes a P-type well. The P-type well is located above the N-type well, the surface of the P-type well close to the electrode structure is flush with the first surface, and the rest of the surface is surrounded by the N-type well. The P-type well is in potential floating. Wherein, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located. In this case, the field effect transistor includes: an N-type transistor substrate, a P-type source region and a P-type drain region on the semiconductor substrate. In this way, in the semiconductor substrate, the N-type well can be formed by using the above-mentioned N-type doping process at the position corresponding to the capacitor, and at the same time, the N-type transistor substrate can be formed by the above-mentioned N-type doping process at the position corresponding to the field effect transistor. , so as to achieve the purpose of simplifying the manufacturing process. In addition, the P-type source region and the P-type drain region of the field effect transistor are both arranged on the substrate of the N-type transistor. In this way, while using the above-mentioned P-type doping process to form a P-type well on the N-type well of the capacitor, a P-type source region and a P-type drain can be formed on the N-type transistor substrate of the field effect transistor. polar region. Wherein, the P-type source region and the P-type drain region are arranged at intervals. Next, metal can be used to form the gate, source, and drain of the field effect transistor. In this case, the field effect transistor is a P-type transistor.

A third aspect of the embodiments of the present application provides an electronic device, including a main board and any radio frequency circuit as described above, at least a part of the radio frequency circuit is disposed on the main board. The electronic device has the same technical effect as that of the radio frequency circuit provided by the foregoing embodiments, which will not be repeated here.

According to a fourth aspect of the embodiments of the present application, a capacitor is provided, and the capacitor may include an electrode structure and a capacitor substrate for carrying the electrode structure. The electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes. The first finger electrodes and the second finger electrodes are alternately arranged. The capacitor substrate includes an N-type well. The N-type well is arranged on the semiconductor substrate of the integrated circuit, and the above-mentioned first finger electrode and the second finger electrode are arranged on the N-type well. In addition, the N-type well is at potential floating.

It can be seen from the above that, between the first finger electrode and the semiconductor substrate, there is an N-type well at a floating potential. In this way, there may be a parasitic capacitance between the first finger electrode and the N-type well. In addition, there is a parasitic capacitance between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, between the second finger electrode and the semiconductor substrate, an N-type well at a floating potential is provided. There may be a parasitic capacitance between the second finger electrode and the N-type well. There is a parasitic capacitance between the N-type well under the second finger electrode and the semiconductor substrate. In this case, two parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the solutions of the embodiments of the present application, the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate. Similarly, two parasitic capacitors are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and finally achieve The purpose of reducing the parasitic capacitance between the entire capacitor and the semiconductor substrate is conducive to improving the Q value of the capacitor.

Optionally, the capacitor substrate further includes a P-type well. It is arranged between the electrode structure and the N-type well. The P-type well is in potential floating. In this case, an N-type well and a P-type well in a floating state are arranged between the first finger electrode and the semiconductor substrate. In this way, there may be a parasitic capacitance between the first finger electrode and the P-type well. In addition, there is a parasitic capacitance between the P-type well below the first finger electrode and the N-type well below the first finger electrode. There is a parasitic capacitance between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate. In this way, there may be a parasitic capacitance between the second finger electrode and the P-type well. In addition, there is a parasitic capacitance between the P-type well under the second finger electrode and the N-type well under the second finger electrode. There is a parasitic capacitance between the N-type well under the second finger electrode and the semiconductor substrate. In this case, three parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the solutions of the embodiments of the present application, the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate. Similarly, there are three parasitic capacitors connected in series between the second finger electrode and the semiconductor substrate. Similarly, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and ultimately reduce the entire capacitance and the semiconductor substrate. The purpose of the parasitic capacitance between the substrates is beneficial to improve the Q value of the capacitor.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the N-type well is located. In this way, it is beneficial to increase the relative area between the first finger electrode and the N-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the N-type well. Similarly, it is beneficial to increase the relative area between the second finger electrode and the N-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the N-type well.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located. In this way, it is beneficial to increase the relative area between the first finger electrode and the P-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the P-type well. Similarly, it is beneficial to increase the relative area between the second finger electrode and the P-type well in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode and the P-type well.

Optionally, the interconnection structure is arranged around a circle of the N-type well and connected end to end. In this way, all parts of the semiconductor substrate can be evenly grounded, so that the performance of the capacitor is stable, which is beneficial to provide the Q value of the capacitor.

On this basis, the material of the metal portion is the same as that of the first finger electrode or the second finger electrode. In this way, the fabrication of the metal part can be completed while fabricating the first finger-shaped electrode or the second finger-shaped electrode, so as to achieve the purpose of briefly describing the fabrication process.

Description of drawings

Fig. 1 is a kind of structural representation of the electronic equipment of the present application;

Fig. 2 is a kind of structural representation of the radio frequency circuit in Fig. 1;

Fig. 3 is another schematic structural diagram of the radio frequency circuit in Fig. 1;

FIG. 4A is a schematic structural diagram of the impedance matching network in FIG. 2 or FIG. 3;

Fig. 4B is another schematic structural diagram of the impedance matching network in Fig. 2 or Fig. 3;

Fig. 4C is another schematic structural diagram of the impedance matching network in Fig. 2 or Fig. 3;

FIG. 5A is a schematic structural diagram of a capacitor provided in an embodiment of the present application;

FIG. 5B is a structural schematic diagram of a battery structure in a capacitor provided in an embodiment of the present application;

Figure 5C is a cross-sectional view obtained by cutting along the dotted line O-O in Figure 5B;

FIG. 6 is a schematic structural view of the electrode structure in the battery structure provided in the embodiment of the present application;

FIG. 7A is another structural schematic diagram of a capacitor provided in the embodiment of the present application;

Figure 7B is a cross-sectional view obtained by cutting along the dotted line F-F in Figure 7A;

Figure 7C is a top view obtained along the B direction in Figure 7B;

FIG. 8A is a schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application;

FIG. 8B is another schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application;

FIG. 9A is another schematic structural diagram of a capacitor provided in the embodiment of the present application;

Fig. 9B is a cross-sectional view obtained by cutting along the dotted line E-E in Fig. 9A;

Figure 9C is a top view obtained along the D direction in Figure 9B;

FIG. 10 is another schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application;

FIG. 11A is a graph of the capacitance value of a capacitor according to the variation of the signal frequency according to the embodiment of the present application;

FIG. 11B is a graph showing the Q value of a capacitor changing with the signal frequency according to the embodiment of the present application;

FIG. 12 is a schematic structural diagram of an electrical connection between a power amplifier and an impedance matching network provided in an embodiment of the present application;

FIG. 13A is a schematic structural diagram of at least a part of the MOS in FIG. 12 and at least a part of the capacitance in the impedance matching network being arranged on the same layer;

FIG. 13B is a schematic structural diagram of the MOS shown in FIG. 12 being arranged on the same layer as at least a part of the capacitance in the impedance matching network.

Reference signs:

01-electronic equipment; 10-display module; 11-middle frame; 12-back shell; 13-main board; 20-radio frequency circuit; 02-antenna; 200-radio frequency transmitter; 201-receiving channel; 211-LNA; 212-PA; 30-impedance matching network; 41-capacitor substrate; 400-insulating layer; 401-electrode structure; 4011-first finger electrode; 4012-second finger electrode; 402-first Interconnection electrode; 403-second interconnection electrode; 404-second through hole; 405-third through hole; 42-dielectric layer; 410-semiconductor substrate; 411-N-type well; 43-interconnection structure; 431 -P-type semiconductor doping part; 432-first through hole; 433-metal part; 412-P-type well; 52-P-type transistor substrate; 53-N-type source region; 54-N-type drain region; 55-through hole; 56-N-type transistor substrate; 57-P-type source region; 58-P-type drain region.

detailed description

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature.

In addition, in this application, orientation terms such as "upper" and "lower" may include, but are not limited to, definitions relative to the schematic placement orientations of components in the drawings. It should be understood that these directional terms may be relative concepts, They are used for description and clarification relative to, which may change accordingly according to changes in the orientation in which parts of the figures are placed in the figures.

In this application, unless otherwise specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediary.

An embodiment of the present application provides an electronic device, which may include a tablet computer (pad), a notebook (for example, ultra-thin or portable), a mobile phone (mobile phone), a smart watch, a wireless charging electric vehicle, a wireless charging household small Electrical appliances (such as soybean milk machines, sweeping robots), etc., electronic products with wireless signal transmission function. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device. For the convenience of description, the electronic device 01 is a mobile phone as shown in FIG. 1 as an example.

The above-mentioned electronic device 01 , as shown in FIG. 1 , mainly but not limited to includes a display module 10 , a middle frame 11 , a rear case 12 and a main board 13 . Wherein, the main board 13 may be a printed circuit board (printed circuit board, PCB). The above-mentioned display module 10 may include a display screen. For example, the display screen may be a liquid crystal display (liquid crystal display, LCD) screen, or may be an organic light emitting diode (organic light emitting diode, OLED) display screen, or may be a micro LED display screen, or may be a The mini LED display is not limited in this application. The display module 10 and the casing 12 are respectively located on two sides of the middle frame 11 . The main board 13 is disposed on the surface of the middle frame 11 near the housing 12 . After the middle frame 11 and the rear case 12 are fastened together, an accommodating cavity for accommodating internal components such as the motherboard 13 and the antenna can be formed.

Based on this, in order to enable the above-mentioned electronic device 01 to transmit and receive high-frequency signals through the antenna, the electronic device 01 may also include a radio frequency circuit 20 as shown in FIG. 02 electrical connections. The embodiment of the present application does not limit the type and arrangement of the antenna 02 . For example, it can be arranged around the main board 13 , or a part of the middle frame 11 can also be shared as the antenna 02 .

In some embodiments of the present application, the radio frequency circuit 20 may include a radio frequency transmitter 200 as shown in FIG. 2 . There may be a receiving path 201 and a transmitting path 202 between the radio frequency transmitter 200 and the antenna 02 . Wherein, when the electronic device 01 receives a signal, the antenna 02 can convert the electromagnetic wave sent by the base station into a weak AC signal, and after filtering and high-frequency amplification by the above-mentioned receiving channel 201, send it to the radio frequency transmitter 200 for demodulation, To get the receiving baseband information.

In addition, when the electronic device 01 transmits a signal, the radio frequency transmitter 200 can modulate and convert the transmitted baseband information into a high-frequency signal, which is amplified by the transmission path 202 and then transferred to the electromagnetic board by the antenna 02 for radiation. In addition, there is an antenna switch between the receiving path 201 , the transmitting path 202 and the antenna 02 , and the antenna switch is used to control the transmission and interruption of signals between the above-mentioned signal path and the antenna.

As can be seen from the above, both the receiving path 201 and the transmitting path 202 need to amplify the signal, therefore, the receiving path 201 can include a low noise amplifier (low noise amplifier, LNA) 211 as shown in Figure 2, and the transmitting path 202 can include such as The power amplifier (power amplifier, PA) 212 shown in FIG. 2 is used to amplify and process signals.

Based on this, in some embodiments of the present application, in order to improve the signal transmission efficiency between the input end and the output end in the transmission path 202, the transmission path 202 may include an integrated circuit, and the integrated circuit may include at least one The impedance matching network 30 is shown. The above-mentioned impedance matching network 30 can be electrically connected to the output terminal a1 of the PA 212 , that is, the impedance matching network 30 is electrically connected between the PA 212 and the antenna 02 . Alternatively, as shown in FIG. 3 , the above-mentioned impedance matching network 30 can be electrically connected to the input terminal a1 of the PA212 . Alternatively, both the input end a1 and the output end b1 of the PA212 are electrically connected to the above-mentioned impedance matching network 30 , which is not limited in this application.

Similarly, in order to improve the signal transmission efficiency between the input end and the output end in the receiving path 201, the receiving path 201 may include at least one impedance matching network 30 as shown in FIG. 2 . The above-mentioned impedance matching network 30 can be electrically connected to the output end of the LNA 211 , that is, the impedance matching network 30 is electrically connected between the PA 212 and the antenna 02 . Alternatively, as shown in FIG. 3 , the above-mentioned impedance matching network 30 may be electrically connected to the input terminal a2 of the LNA 211 . Alternatively, both the input end a2 and the output end b2 of the LNA 211 are electrically connected to the above-mentioned impedance matching network 30 , which is not limited in this application.

It should be noted that, the above is to set the impedance matching network 30 on at least one of the output terminal a1 of the PA212 and the input terminal b1 of the PA212. The description will be given as an example in which the impedance matching network 30 is provided at least one of the output end a2 of the LNA 211 and the input end b2 of the LNA 211 . In other embodiments of the present application, the above-mentioned radio frequency transmitter 200 may also include a filter, and the filter may be set in at least one of the receiving path 201 and the transmitting path 202, or the filter may be set in the above-mentioned antenna Between the switch and the antenna 02. In this case, at least one of the input end and the output end of the filter may be electrically connected to the impedance matching network 30 .

The above-mentioned impedance matching network 30 may include a capacitor and an inductor electrically connected to the capacitor. The present application does not limit the electrical connection manner of the capacitor and the inductor, and the quantity of the capacitor and the inductor. For example, as shown in FIG. 4A , the impedance matching network 30 may include a capacitor C and an inductor L. As shown in FIG. Wherein, the capacitor C is connected in series with the inductor L. At this time, the impedance matching network 30 can be called an L-type matching network.

Or, for another example, as shown in FIG. 4B , the impedance matching network 30 may include two capacitors, namely C1 and C2 , and an inductor L. Wherein, the capacitor C1 and the capacitor C2 are connected in parallel, and the inductor L is electrically connected between the capacitor C1 and the capacitor C2. At this time, the impedance matching network 30 may be called a π-type matching network.

Or, for another example, as shown in FIG. 4C , the impedance matching network 30 may include two inductors, namely L1 and L2 , and a capacitor C. Wherein, the inductor L1 and the inductor L2 are connected in parallel, and the capacitor C is electrically connected between the inductor L1 and the inductor L2. At this time, the impedance matching network 30 may be called a T-type matching network.

It should be noted that the above-mentioned impedance matching network 30 may also include a signal source resistor R _opt and a load resistor _RL as shown in FIG. 4A , FIG. 4B and FIG. 4C . For example, when the impedance matching network 30 is electrically connected to the output terminal a1 of the PA 212, the signal source resistance R _opt may be the resistance of the radio frequency transceiver 200, and the load resistance _RL may be the resistance of the antenna. In addition, the above is an illustration of the quantity and connection mode of the capacitors and inductors in the impedance matching network 30 , and other configuration methods of the capacitors and inductors will not be repeated here. The present application does not limit the structure of the impedance matching network 30 , as long as the impedance matching network 30 can be guaranteed to have capacitance, those skilled in the art can select the type of the impedance matching network 30 according to needs.

The Q value of the above capacitor will affect the impedance matching performance of the impedance matching network 30 , and further affect the conversion rate of the electrical signal when the electronic device 01 transmits the signal. For example, the higher the Q value of the capacitor in the impedance matching network 30, the smaller the attenuation of the high-frequency circuit signal by the capacitor, which is beneficial to improve the performance of the impedance matching network, reduce the reflection of the signal at the load end, and improve the conversion rate of the electrical signal. Conversely, the lower the Q value of the capacitor in the impedance matching network 30, the greater the attenuation of the high-frequency circuit signal by the capacitor, which will reduce the performance of the impedance matching network, increase the reflection of the signal at the load end, and reduce the conversion rate of the electrical signal. The embodiment of the present application provides a capacitor, and the capacitor may have a relatively high Q value. The structure of the capacitor will be described in detail below with an example.

In some embodiments of the present application, the capacitors in the impedance matching network 30 may use metal-oxide-metal (metal oxide metal, MOM) capacitors with relatively high capacitance density. The MOM capacitor C (hereinafter referred to as capacitor C) may include an electrode structure 401 and a capacitor substrate 41 as shown in FIG. 5A . Wherein, the electrode structure 401 is disposed above the capacitor substrate 41 .

Specifically, the above capacitor may further include an insulating layer 400 . The above-mentioned electrode structure 401 is disposed in the insulating layer 400 , and the electrode structure 401 may include a plurality of electrically connected first finger electrodes 4011 and a plurality of electrically connected second finger electrodes 4012 . The first finger electrodes 4011 and the second finger electrodes 4012 are alternately arranged, and adjacent first finger electrodes 4011 and second finger electrodes 4012 are separated by part of the material of the insulating layer 400, so that the first The finger electrodes 4011 and the second finger electrodes 4012 are insulated. The capacitance value in the MOM capacitor may be the sum of the capacitance values formed between every adjacent first finger electrode 4011 and second finger electrode 4012 in the same layer.

In addition, in some embodiments of the present application, as shown in FIG. 5A , the first finger electrode 4011 and the second finger electrode 4012 may be on the same layer and arranged in parallel. Arranging the first finger electrodes 4011 and the second finger electrodes 4012 in parallel means that the strip-shaped first finger electrodes 4011 and the strip-shaped second finger electrodes 4012 may extend in the same direction, for example, both extend along the X direction.

It should be noted that the "same-layer arrangement" in the embodiment of the present application refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process. Depending on the specific pattern, the same patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.

Based on this, in order to electrically connect the plurality of first finger electrodes 4011 and electrically connect the plurality of second finger electrodes 4012, the electrode structure 401 further includes a first interconnection electrode 402 and a second interconnection electrode 402 as shown in FIG. 5A. Two interconnect electrodes 403 . In this case, the plurality of first finger electrodes 4011 may be arranged vertically on the same layer as the first interconnect electrodes 402 . For example, the first finger electrodes 4011 may extend along the X direction, and the first interconnect electrodes 402 may extend along the Y direction. The above-mentioned X direction and Y direction are perpendicular, and the plane where the X direction and Y direction lie may be parallel to the bearing surface of the capacitor substrate 41 facing the electrode structure 401 . Moreover, the multiple first finger electrodes 4011 are connected to the first interconnect electrodes 402 as an integral structure, so that the first interconnect electrodes 402 can be directly electrically connected to the multiple first finger electrodes 4011 .

Similarly, a plurality of second finger electrodes 4012 and the second interconnect electrodes 403 are arranged vertically on the same layer. For example, the second finger electrodes 4012 may extend along the X direction, and the second interconnect electrodes 403 may extend along the Y direction. Moreover, the multiple second finger electrodes 4012 are connected with the second interconnection electrodes 403 as an integral structure, so that the second interconnection electrodes 403 can be directly electrically connected to the multiple second finger electrodes 4012 .

In this case, in the electrode structure 401 shown in FIG. 5A , multiple first finger electrodes 4011, multiple second finger electrodes 4012, first interconnect electrodes 402, and second interconnect electrodes 403 may be in the same layer. Material. In this way, the first finger electrode 4011 , the second finger electrode 4012 , the first interconnection electrode 402 and the second interconnection electrode 403 can be formed simultaneously by using the above-mentioned one-time communication process.

In addition, in some embodiments of the present application, in order to increase the capacitance value of the capacitor C, the capacitor C may include a plurality of electrode structures 401 as shown in FIG. 5B . The plurality of electrode structures 401 can be stacked. In this case, in order to enable the first finger electrodes 4011 of different layers to be electrically connected, and the second finger electrodes 4012 of multiple different layers to be electrically connected, the above-mentioned capacitance C may also include As shown in the cross-sectional view obtained by cutting along the dotted line O-O), at least a part of the second through hole 404 and the third through hole 405 penetrate through the insulating layer 400 .

Wherein, the first finger electrodes 4011 in the plurality of electrode structures 401 are all electrically connected to the second through holes 404 . The second finger electrodes 4012 in the plurality of electrode structures are all electrically connected to the third through holes 405 . In this way, by providing multiple layers of the above-mentioned electrode structure 401, and electrically connecting the first finger electrodes 4011 of different layers through the second through holes 404, and electrically connecting the second finger electrodes 4012 of different layers through the third through holes 405. The connection can increase the overlapping area between the two plates in the capacitor C, thereby achieving the purpose of increasing the capacitance value of the capacitor C. As an example, the manufacturing process of the second through hole 404 and the third through hole 405 may be: etching the insulating layer 400 to form a via hole, and then filling the via hole with a metal material through electroplating or other processes, and finally forming a via hole with The second through hole 404 and the third through hole 405 are electrically conductive.

Alternatively, in some embodiments of the present application, as shown in FIG. 6 , the first finger electrode 4011 and the second finger electrode 4012 may be in different layers and arranged vertically. The perpendicular arrangement of the first finger-shaped electrodes 4011 and the second finger-shaped electrodes 4012 means that the extending directions of the strip-shaped first finger-shaped electrodes 4011 and the strip-shaped second finger-shaped electrodes 4012 may be different. For example, the first finger electrodes 4011 may extend along the X direction, and the second finger electrodes 4012 may extend along the Y direction.

It should be noted that the arrangement of the first finger electrode 4011 and the second finger electrode 4012 in different layers means that the first finger electrode 4011 and the second finger electrode 4012 respectively adopt two manufacturing processes (each manufacturing process may include film forming process and patterning process).

Based on this, similarly, in order to electrically connect the plurality of first finger electrodes 4011 and electrically connect the plurality of second finger electrodes 4012, as shown in FIG. An interconnection electrode 402 is arranged vertically on the same layer and connected to form an integrated structure. A plurality of second finger electrodes 4012 and the electrodes of the second interconnection 403 are arranged vertically on the same layer, and are connected to form an integrated structure.

It should be noted that when the capacitor C can be provided with multiple layers of electrode structures 401 as shown in FIG. The electrical connection between the second finger electrodes 4012 is the same as that described above, and will not be repeated here. For the convenience of description, the following descriptions are made by taking the capacitor C including a layer of electrode structure 401 as shown in FIG. 5A as an example.

In addition, in some embodiments of the present application, the capacitor C may further include a dielectric layer 42 as shown in FIG. 7A . The dielectric layer 42 may be located between the electrode structure 401 and the semiconductor substrate 410 . Moreover, the dielectric layer 42 may be in contact with the electrode structure 401 and the first surface A of the semiconductor substrate 410 , thereby separating the electrode structure 401 from the semiconductor substrate 410 . The structure of the capacitor substrate 41 will be illustrated in detail below.

Exemplarily, in some embodiments of the present application, as shown in FIG. 7A , the capacitor substrate 41 may include an N-type well 411 . Wherein, the material constituting the semiconductor substrate 410 may be silicon (Si), in this case, the semiconductor substrate 410 may be called a silicon substrate. The above-mentioned semiconductor substrate 410 has a first surface A, and the electrode structure 401 may be disposed on a side where the first surface A is located.

In addition, an N-type well 411 is disposed on the semiconductor substrate 410 . For example, as shown in FIG. 7B (the cross-sectional view obtained by cutting along the dotted line F-F in FIG. 7A ), the surface of the N-type well 411 close to the electrode structure 401 can be flush with the first surface A, and the rest of the surface is covered by the semiconductor substrate. 410 , at this time, the N-type well 411 is located between the semiconductor substrate 410 and the electrode structure 401 .

Moreover, as shown in FIG. 7C (the top view taken along the B direction in FIG. 7B ), the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located within the range where the N-type well 411 is located. In this way, it is beneficial to increase the relative area between the first finger electrode 4011 and the N-type well 411 in the electrode structure 401 , making it easier to form parasitic capacitance between the first finger electrode 4011 and the N-type well 411 . Similarly, it is beneficial to increase the relative area between the second finger electrode 4012 and the N-type well 411 in the electrode structure 401 , making it easier to form parasitic capacitance between the second finger electrode 4012 and the N-type well 411 .

As an example of the manufacturing process of the N-type well 411, a pentavalent dielectric element (hereinafter referred to as the N-type doping process), such as phosphorus or arsenic, can be doped on the semiconductor substrate 410 corresponding to the ion doping process, and the above-mentioned N-type well 411 . Then, in the process of making the above-mentioned electrode structure 401 on the capacitor substrate 41, the electrode structure 401 can be formed directly above the N-type well 411, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located at the N-type well 410. within the range where the type well 411 is located.

On this basis, the N-type well 411 may be in a floating potential, that is, the N-type well 411 is not connected to a potential. In addition, the semiconductor substrate may be grounded 410 . For example, in order to ground the semiconductor substrate 410 , the capacitor C may further include an interconnection structure 43 as shown in FIG. 7C . One end of the interconnection structure 43 may be in contact with the semiconductor substrate 410 , and the other end of the interconnection structure 43 is used for grounding.

Specifically, as shown in FIG. 7B , the interconnection structure 43 may include a P-type semiconductor doped part 431 , a first through hole 432 and a metal part 433 connected in sequence. In this case, the P-type semiconductor doped part 431 may be located on the semiconductor substrate 410 to serve as one end of the interconnection structure 43 for contacting the semiconductor substrate 410 .

Wherein, the P-type semiconductor doped part 431 may be located on the semiconductor substrate 410 means that the surface of the P-type semiconductor doped part 431 close to the electrode structure 401 is flush with the first surface A, and the remaining surfaces are surrounded by the semiconductor substrate 410 . As an example of the manufacturing process of the P-type semiconductor doped part 431, a trivalent dielectric element (hereinafter referred to as the P-type doping process), such as boron or gallium, can be doped on the semiconductor substrate 410 correspondingly through an ion doping process. The aforementioned P-type semiconductor doped portion 431 is formed.

In addition, the first through hole 432 may penetrate through the dielectric layer 42 . A first end of the first through hole 432 close to the P-type semiconductor doped portion 431 is in contact with the P-type semiconductor doped portion 431 to be electrically connected to the P-type semiconductor doped portion 431 . Wherein, the manufacturing method of the first through hole 432 is similar to the manufacturing method of the second through hole 404 and the third through hole 405 mentioned above, and will not be repeated here.

In addition, the metal part 433 may be disposed on a surface of the dielectric layer 42 away from the semiconductor substrate 410 . The metal portion 433 may be electrically connected to the second end of the first through hole 432 away from the P-type semiconductor doped portion 431 . The metal portion 433 is used as a conductor for grounding, so that the semiconductor substrate 410 can be grounded through the interconnection structure 43 . In some embodiments of the present application, the metal part 433 may be in the same layer and material as the first finger electrode 4011 and the second finger electrode 4012 (as shown in FIG. 5A ) in the electrode structure 401 . In this way, the same patterning process can be used to complete the preparation of the metal part 433 while manufacturing the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401 , thereby simplifying the manufacturing process.

In some embodiments of the present application, as shown in FIG. 7C , the interconnection structure 43 may be arranged around the N-type well 411 and connected end to end. In this way, all parts of the semiconductor substrate 410 can be evenly grounded, so that the performance of the capacitor C is stable, which is beneficial to provide the Q value of the capacitor C.

In summary, the capacitor C in the impedance matching network 30 provided by the embodiment of the present application may include a capacitor substrate 41 and an electrode structure 401 disposed above the capacitor substrate 41 as shown in FIG. 5A . The capacitor substrate includes an N-type well 411 on the semiconductor substrate 410 . Wherein, the N-type well 411 is at a floating potential, and the semiconductor substrate 410 may be grounded. In addition, the vertical projection of the electrode structure 401 on the semiconductor substrate 410 in the electrode structure 401 is located within the range where the N-type well 411 is located.

It can be seen from the above that the electrode structure 401 may include a first finger electrode 4011 and a second finger electrode 4012, so an N-type electrode in a floating state is provided between the first finger electrode 4011 and the grounded semiconductor substrate 410. Well 411. In this way, there may be a parasitic capacitance C11 between the first finger electrode 4011 and the N-type well 411 as shown in FIG. 8A . In addition, there is a parasitic capacitance C12 between the N-type well 411 below the first finger electrode 4011 and the semiconductor substrate 410 . Similarly, an N-type well 411 in a floating state is provided between the second finger electrode 4012 and the grounded semiconductor substrate 410 . There may be a parasitic capacitance C21 between the second finger electrode 4012 and the N-type well 411 as shown in FIG. 8A . There is a parasitic capacitance C22 between the N-type well 411 below the second finger electrode 4012 and the semiconductor substrate 410 .

In this case, a parasitic capacitance C11 and a parasitic capacitance C12 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410 . If the above-mentioned N-type well 411 is grounded, then the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitors connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitor between the first finger electrode 4011 and the semiconductor substrate 410. value.

Similarly, as shown in FIG. 8A , a parasitic capacitance C21 and a parasitic capacitance C22 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410 . If the above-mentioned N-type well 411 is grounded, then the second finger electrode 4012 and the semiconductor substrate 410 have only one parasitic capacitance C20 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrodes 4012 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitances between the second finger electrodes 4012 and the semiconductor substrate 410. Finally, the purpose of reducing the parasitic capacitance between the entire capacitor C and the semiconductor substrate 410 is achieved, thereby improving the Q value of the capacitor C.

Based on this, on the one hand, when the above-mentioned capacitor C is used in the impedance matching network 30, since the capacitor C has a higher Q value, the attenuation of the high-frequency circuit signal by the capacitor C is smaller, which is conducive to improving the performance of the impedance matching network 30. Performance, reduce the reflection of the signal at the load end, and improve the conversion rate of the electrical signal. On the other hand, since the signal reflected by the load end is reduced, the heat converted by the reflected signal will be correspondingly reduced, thereby effectively reducing the probability of temperature rise of the electronic device and improving the life of the electronic device.

It should be noted that the capacitance Cm in FIG. 8A is the capacitance formed between the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401 . The resistance Rm is the equivalent resistance of the first finger electrode 4011 and the second finger electrode 4012 . The inductance Lm is the equivalent inductance of the first finger electrode 4011 and the second finger electrode 4012 . The resistance R11 is an equivalent resistance between the N-type well 411 under the first finger electrode 4011 and the semiconductor substrate 410 . The resistance R21 is an equivalent resistance between the N-type well 411 under the second finger electrode 4012 and the semiconductor substrate 410 .

The above is that in the electrode structure 401, between the first finger electrode 4011 and the grounded semiconductor substrate 410, an N-type well 411 in a floating state is provided, and between the second finger electrode 4012 and the grounded semiconductor substrate 410 In between, an N-type well 411 in a floating state is provided as an example to illustrate the structure of the capacitor C above.

In other embodiments of the present application, the structure of the capacitor substrate 41 may be as shown in FIG. 9A , and the capacitor substrate 41 includes a semiconductor substrate 410 and an N-type well 411 . Wherein, the arrangement manner of the semiconductor substrate 410 and the N-type well 411 is the same as that described above, and will not be repeated here. In addition, the capacitor substrate 41 may further include a P-type well 412 .

As shown in FIG. 9A , the P-type well 412 may be disposed between the electrode structure 401 and the N-type well 411 . For example, as shown in FIG. 9B (the cross-sectional view obtained by cutting along the dotted line E-E in FIG. 9A ), the surface of the P-type well 412 close to the electrode structure 401 is flush with the first surface A, and the remaining surfaces are surrounded by the N-type well 411. . Moreover, as shown in FIG. 9C (the top view taken along the D direction in FIG. 9B ), the vertical projection of the electrode structure on the semiconductor substrate 410 may be located within the range where the P-type well 412 is located.

For example, on the N-type well 411 , corresponding to doping a trivalent dielectric element, such as boron element or gallium element, through an ion doping process, the above-mentioned P-type well 412 can be formed. Then, in the process of making the above-mentioned electrode structure 401 on the capacitor substrate 41, the electrode structure 401 can be formed directly above the P-type well 412, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located at the P-type well 412. within the range where the type well 412 is located. In this way, it is beneficial to increase the relative area between the first finger electrode 4011 and the P-type well 412 in the electrode structure, making it easier to form parasitic capacitance between the first finger electrode 4011 and the P-type well 412 . Similarly, it is beneficial to increase the relative area between the second finger electrode 4012 and the P-type well 412 in the electrode structure 401 , making it easier to form parasitic capacitance between the second finger electrode 4012 and the P-type well 412 .

It should be noted that, as can be seen from the above, the P-type well 412 may be located above the N-type well 411 , and the surface of the P-type well 412 close to the electrode structure 401 is flush with the first surface A, and the rest of the surface is surrounded by the N-type well 411 . Therefore, along the direction perpendicular to the capacitor substrate 41 , the thickness of the P-type well 412 is smaller than that of the N-type well 411 , so the N-type well 411 can also be called an N-type deep well.

On this basis, the grounding method of the semiconductor substrate 410 through the interconnection structure 43 is the same as that described above, and will not be repeated here. In addition, the above-mentioned P-type well 412 is in a floating potential. In this case, an N-type well 411 and a P-type well 412 in a floating state are disposed between the first finger electrode 4011 and the grounded semiconductor substrate 410 . In this way, there may be a parasitic capacitance C31 as shown in FIG. 10 between the first finger electrode 4011 and the P-type well 412 . In addition, there is a parasitic capacitance C32 between the P-type well 412 below the first finger electrode 4011 and the N-type well 411 below the first finger electrode 4011 . There is a parasitic capacitance C33 between the N-type well 411 below the first finger electrode 4011 and the semiconductor substrate 410 . Wherein, the resistor R31 is an equivalent resistance between the P-type well 412 below the first finger electrode 4011 and the N-type well 411 below the first finger electrode 4011 . The resistance R32 is an equivalent resistance between the P-type well 412 under the first finger electrode 4011 and the semiconductor substrate 410 .

Similarly, an N-type well 411 and a P-type well 412 in a floating state are disposed between the second finger electrode 4012 and the grounded semiconductor substrate 410 . In this way, there may be a parasitic capacitance C41 as shown in FIG. 10 between the second finger electrode 4012 and the P-type well 412 . In addition, there is a parasitic capacitance C42 between the P-type well 412 below the second finger electrode 4012 and the N-type well 411 below the second finger electrode 4012 . There is a parasitic capacitance C43 between the N-type well 411 below the second finger electrode 4012 and the semiconductor substrate 410 . Wherein, the resistor R41 is an equivalent resistance between the P-type well 412 below the second finger electrode 4012 and the N-type well 411 below the second finger electrode 4012 . The resistance R42 is an equivalent resistance between the P-type well 412 under the second finger electrode 4012 and the semiconductor substrate 410 .

In this case, as shown in FIG. 10 , a parasitic capacitance C31 , a parasitic capacitance C32 and a parasitic capacitance C33 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410 . It can be seen from the above that if the above-mentioned N-type well 411 is grounded, then the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitors connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitor between the first finger electrode 4011 and the semiconductor substrate 410. value.

Similarly, as shown in FIG. 10 , a parasitic capacitance C41 , a parasitic capacitance C42 and a parasitic capacitance C43 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410 . Similarly, the number of parasitic capacitances connected in series between the second finger electrodes 4012 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitances between the second finger electrodes 4012 and the semiconductor substrate 410, and finally reduce The purpose of the parasitic capacitance between the entire capacitor C and the semiconductor substrate 410 is to improve the Q value of the capacitor C.

As an example, FIG. 11A is a curve of the capacitance value of the capacitor C varying with the frequency of the signal. It can be seen that the capacitance value of the capacitor will vary with the frequency of the signal. Wherein, the embodiment of the present application adopts the capacitance shown in FIG. 9A , which overlaps with the above-mentioned curve of the capacitance C shown in FIG. 8B which connects the above-mentioned N-type well 411 to ground. In this case, the capacitance values of the above two capacitors C are the same. For example, at the node m1, the capacitance values of the above two types of capacitors C may both be 5 GHz.

On this basis, as shown in FIG. 11B , the curve ① is the variation curve of the Q value of the capacitor C shown in FIG. 9A with the signal frequency according to the embodiment of the present application. Curve ② is the variation curve of the capacitance C that grounds the above-mentioned N-type well 411 with the signal frequency shown in FIG. 8B . It can be seen that curve ① is above curve ②. For example, at the node m2 with a signal frequency of 5 GHz, the Q value corresponding to the curve ① is increased by about 10% compared with the Q value corresponding to the curve ②. Therefore, in the embodiment of the present application, the capacitor C shown in FIG. 9A has a higher Q value.

In addition, it can be seen from the above that the capacitor C provided by the present application only needs to improve the structure of the capacitor substrate 41 in the capacitor C to achieve the purpose of increasing the Q value of the capacitor C, so it does not increase the difficulty of the manufacturing process. Ease of mass production of products.

It can be seen from the above that in the radio frequency circuit 20 , the impedance matching network 30 having the capacitance C above can be electrically connected to the PA212 or the LNA211 . Wherein, the above-mentioned PA212 or LNA211 is provided with a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, at least a part of the field effect transistor and at least a part of the capacitor substrate 41 in the capacitor C may be in the same layer and material. Therefore, at least a part of the structure of the capacitor substrate 41 can be prepared while the above-mentioned field effect transistor is prepared by the semiconductor manufacturing process, so as to simplify the process and improve the production efficiency.

Exemplarily, as shown in FIG. 12 , the PA212 may include a MOS, an isolation DC capacitor Cb, a ground capacitor Cg, and a resistor R connected to the working voltage Vdc. The gate (gate, g) of the MOS is electrically connected to the power supply Vin, the first pole a (source area or drain area) of the MOS is used to receive the input electrical signal, and the second pole b (drain area or source area) of the MOS area) is used to electrically connect with the impedance matching network 30 through the isolation DC capacitor Cb.

The above-mentioned PA212 can use the amplification state of the MOS to amplify the input electrical signal, and transmit it to the impedance matching network 30 through the isolation DC capacitor Cb. An example will be given below to explain how a part of the MOS is arranged in the same layer and with the same material as part of the structure of the capacitor substrate 41 in the capacitor C.

Specifically, as shown in FIG. 13A, the MOS may include a P-type transistor substrate 52, an N-type source (source, s) region 53 and an N-type drain (drain, d) region disposed on the semiconductor substrate 410. 54. In this way, the above-mentioned capacitor C and MOS can be fabricated in different regions on the same semiconductor substrate, so as to integrate the above-mentioned MOS into an integrated circuit.

In addition, the P-type transistor substrate 52 is disposed on the semiconductor substrate 410 and has the same layer and material as the P-type well 412 in the capacitor substrate 41 of the capacitor C. In this way, in the semiconductor substrate 410, the P-type well 412 can be formed by using the above-mentioned P-type doping process at the position corresponding to the capacitor C, and at the same time, the P-type transistor lining can be formed at the position corresponding to the MOS by using the above-mentioned P-type doping process. Bottom 52, so as to achieve the purpose of simplifying the manufacturing process.

In addition, as shown in FIG. 13A , both the N-type source region 53 and the N-type drain region 54 of the MOS are disposed on the P-type transistor substrate 52 . Moreover, the N-type source region 53 and the N-type drain region 54 are arranged at intervals. In this case, after the above-mentioned P-type transistor substrate 52 is manufactured, the above-mentioned N-type doping process can be used to form an N-type source region 53 and an N-type drain region 54 on the P-type transistor substrate 52 . Next, metal can be used to form the gate g, source s, and drain d of the MOS. In this case, the MOS is an N-type transistor.

Wherein, in order to simplify the manufacturing process, the via hole 55 used to electrically connect the source s and the drain d to the N-type source region 53 and the N-type drain region 54 in the MOS can be used to connect the capacitor C The first through hole 432 of the interconnection structure 43 is formed by the same patterning process.

The above is an example where the MOS is an N-type transistor, and at least a part of the field effect transistor can be in the same layer and material as at least a part of the capacitor substrate 41 in the capacitor C. In other embodiments of the present application, the above-mentioned MOS may also be a P-type transistor.

Exemplarily, as shown in FIG. 13B , the field effect transistor includes an N-type transistor substrate 56 , a P-type source region 57 and a P-type drain region 58 disposed on a semiconductor substrate 410 . The N-type transistor substrate 56 is disposed on the semiconductor substrate 410 and has the same layer and material as the N-type well 411 in the capacitor substrate 41 of the capacitor C. In this way, in the semiconductor substrate 410, such as a Si substrate, the N-type well 411 can be formed by using the above-mentioned N-type doping process at the position corresponding to the capacitor C, and at the same time, the above-mentioned N-type doping process can be used at the position corresponding to the MOS. An N-type transistor substrate 56 is formed to achieve the purpose of simplifying the manufacturing process.

In addition, as shown in FIG. 13B , both the P-type source region 57 and the P-type drain region 58 of the MOS are disposed on the N-type transistor substrate 56 . In this way, while the P-type well 412 is formed on the N-type well 411 of the capacitor C by using the above-mentioned P-type doping process, a P-type source region 57 and a P-type source region 57 can be formed on the N-type transistor substrate 56 of the MOS. type drain region 58 . Wherein, the P-type source region 57 and the P-type drain region 58 are arranged at intervals.

In the same way, next, metal can be used to form the gate g, source s, and drain d of the MOS. In this case, the MOS is a P-type transistor.

It should be noted that, the above description is based on an example that at least a part of the field effect transistor in the PA212 and at least a part of the capacitor substrate 41 in the capacitor C can be of the same layer and material. The fabrication method of at least a part of the field effect transistor in the LNA 211 in the radio frequency circuit 20 and at least a part of the capacitor substrate 41 in the capacitor C is the same as that described above, and will not be repeated here.

In addition, the above description is made by taking the capacitor C in the impedance matching network 30 as an example. The capacitor C provided in the embodiment of the present application can be applied not only to the impedance matching network 30 but also to other circuit structures in the radio frequency circuit 20, such as a digital-to-analog converter, an analog-to-digital converter, and the like. Or it can also be applied to other circuits with capacitance.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

An integrated circuit is characterized in that it includes an impedance matching network, and the impedance matching network includes a capacitor and an inductor electrically connected to the capacitor; the capacitor includes:

An electrode structure; the electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes; the first finger electrodes and the second finger electrodes are alternately arranged;

The capacitor substrate includes an N-type well; the N-type well is arranged on the semiconductor substrate; the first finger electrode and the second finger electrode are arranged on the N-type well; the N-type The type well is at potential floating.
The integrated circuit according to claim 1, wherein the capacitor substrate further comprises:

A P-type well is arranged between the electrode structure and the N-type well; the P-type well is in a floating potential.
The integrated circuit according to claim 1 or 2, wherein the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the N-type well is located.
The integrated circuit according to claim 2, wherein the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located.
The integrated circuit according to any one of claims 1-4, wherein the capacitor further comprises:

An interconnection structure, one end of the interconnection structure is in contact with the semiconductor substrate, and the other end of the interconnection structure is used for grounding.
The integrated circuit according to claim 5, wherein the interconnect structure comprises:

a P-type semiconductor doped portion disposed on the semiconductor substrate;

a first through hole, penetrating through the dielectric layer, and the first end is electrically connected to the P-type semiconductor doped part;

The metal portion is disposed on a surface of the dielectric layer away from the semiconductor substrate, electrically connected to the second end of the first through hole, and the metal portion is used for grounding.
The integrated circuit according to claim 5 or 6, wherein the interconnection structure is arranged around the circumference of the N-type well and connected end to end.
The integrated circuit according to any one of claims 5-7, wherein the material of the metal portion is the same as that of the first finger electrode or the second finger electrode.
The integrated circuit according to any one of claims 1-8, wherein the impedance matching network is an L-type matching network, a π-type matching network, or a T-type matching network.
A radio frequency circuit, characterized in that the radio frequency circuit includes a radio frequency transceiver for electrical connection with the antenna; the radio frequency circuit also includes the integrated circuit according to any one of claims 1-9; the integrated circuit The impedance matching network in is electrically connected between the radio frequency transceiver and the antenna.
The radio frequency circuit according to claim 10, characterized in that, the radio frequency circuit further comprises a field effect transistor, and the field effect transistor is integrated in the integrated circuit.
An electronic device, characterized by comprising a main board and the radio frequency circuit according to claim 10 or 11, at least a part of the radio frequency circuit is arranged on the main board.