CN116093084A - Switching plate structure and forming method thereof - Google Patents

Switching plate structure and forming method thereof Download PDF

Info

Publication number
CN116093084A
CN116093084A CN202310083152.1A CN202310083152A CN116093084A CN 116093084 A CN116093084 A CN 116093084A CN 202310083152 A CN202310083152 A CN 202310083152A CN 116093084 A CN116093084 A CN 116093084A
Authority
CN
China
Prior art keywords
capacitor
substrate
forming
inductor
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310083152.1A
Other languages
Chinese (zh)
Inventor
殷翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd, Shanghai Xianfang Semiconductor Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN202310083152.1A priority Critical patent/CN116093084A/en
Publication of CN116093084A publication Critical patent/CN116093084A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The invention relates to an adapter plate structure, which comprises two bonded first adapter plates, wherein the first adapter plates comprise: a substrate; a plurality of interconnected trench capacitor structures located on a front side of the substrate, wherein the trench capacitor structures comprise: a plurality of trenches located on the front side of the substrate; a capacitor lower electrode covering an inner wall of the trench; the capacitor medium is positioned on one side surface of the capacitor lower electrode, which is away from the inner wall of the groove; the capacitor upper electrode is positioned on one side surface of the capacitor medium, which is away from the capacitor lower electrode; and the inductor is positioned on the back surface of the substrate and is electrically connected with the groove capacitor structure. The capacitor is integrated in the adapter plate, the inductor is integrated on the surface of the adapter plate, the occupied space of two devices is greatly reduced, the distance between the inductor and the groove capacitor structure is far, the isolation degree is high, the interference between the inductor and the groove capacitor structure is reduced, the dielectric loss is reduced, and the Q value of the inductor is improved; and the trench capacitor structure is used, so that the capacitor density is improved, and the capacitance value can be effectively improved.

Description

Switching plate structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor packaging technology, and in particular, to an interposer structure and a method for forming the same.
Background
In recent years, with the rapid development of the wireless communication market, the demand for low-cost and high-performance on-chip radio frequency devices is increasing, and in order to meet the requirements of low loss and high integration, on-chip integrated inductors have become important elements in many communication modules such as voltage-controlled oscillators, low-noise amplifiers, mixers, filters and the like. The capacitor is an indispensable element in the microwave radio frequency circuit and has the functions of direct current isolation, filtering, coupling, tuning, rectification and the like. As the operating frequency of integrated circuits is higher and faster, the noise problem of circuit power supply networks in electronic systems is also more and more serious, and the need for decoupling of capacitors is also rapidly increasing.
Conventional ipd capacitors are mainly implemented in the form of M-M by two layers of planar metal electrodes, but such capacitor structures often cannot achieve large capacitance values due to limited planar space. In the prior art, the transfer plate comprises an inductor and a capacitor in an M I M mode, the capacitor and the inductor are generally integrated together, the distance between the capacitor and the inductor is relatively short, the capacitor and the inductor have relatively large interference, the inductor has dielectric loss, and the performance of the inductor is limited.
Disclosure of Invention
To solve at least some of the above problems in the prior art, the present invention provides an interposer structure comprising two bonded first interposer boards, wherein the first interposer board comprises:
a substrate;
a plurality of interconnected trench capacitor structures located on a front side of the substrate, wherein the trench capacitor structures comprise: a plurality of trenches located at a front side of the substrate; a capacitor bottom electrode covering an inner wall of the trench; the capacitor medium is positioned on one side surface of the capacitor lower electrode, which is away from the inner wall of the groove; the capacitor upper electrode is positioned on one side surface of the capacitor medium, which is away from the capacitor lower electrode;
and the inductor is positioned on the back surface of the substrate and is electrically connected with the groove capacitor structure.
Further, the method further comprises the following steps:
the conductive piece is positioned on the side surface of the groove capacitor structure and is spaced from the groove capacitor structure;
a first rewiring layer electrically connecting the conductive member and the trench capacitor structure;
and the second rewiring layer is electrically connected with the conductive piece and the inductor.
Further, the substrate has a via, and the conductive member is located in the via.
Further, the method further comprises the following steps:
the first insulating layer is positioned between the capacitor lower electrode and the inner wall of the groove;
the second insulating layer is positioned on one side surface of the upper electrode of the capacitor, which is away from the capacitor medium;
a third insulating layer located between the inner wall of the through hole and the conductive member;
and a fourth insulating layer located on the back surface of the substrate.
Further, the capacitor lower electrode extends to an upper surface of the first insulating layer away from the substrate; the capacitor lower electrodes of the trench capacitor structures are electrically connected;
the first rewiring layer is electrically connected with the capacitor lower electrode.
Further, the first rewiring layers of the two first adapter plates are bonded, so that the two first adapter plates are bonded to form an adapter plate structure.
The invention also provides a method for forming the adapter plate structure, which comprises the following steps: first adapter plates are formed, and then two first adapter plates are bonded to form an adapter plate structure, wherein forming the first adapter plates comprises:
forming a trench on the front surface of the substrate;
forming a capacitor lower electrode on the inner wall of the groove;
forming a capacitance medium on the surface of one side of the lower electrode of the capacitance, which is away from the inner wall of the groove;
forming a capacitor upper electrode on the surface of one side of the capacitor medium, which is away from the capacitor lower electrode;
forming a through hole on the front surface of the substrate;
forming a conductive member in the via hole;
forming a first rewiring layer on the front surface of the substrate, wherein the first rewiring layer is used for connecting the conductive piece and the lower electrode of the capacitor;
thinning the back of the substrate to expose the conductive member;
and arranging an inductor and a second redistribution layer on the back surface of the substrate to finally obtain the first adapter plate.
Further, the method further comprises the following steps:
forming a first insulating layer on the front surface of the substrate and the inner wall of the groove before forming the capacitor lower electrode on the inner wall of the groove;
before forming a through hole on the front surface of the substrate, forming a second insulating layer on the surface of one side of the upper electrode of the capacitor, which is away from the capacitor medium;
a third insulating layer is formed on the inner wall of the via hole before the conductive member is formed in the via hole.
Further, the interposer structure is obtained by bonding the first rewiring layers of the two first interposer boards.
Further, a fourth insulating layer is formed on the back surface of the substrate, the fourth insulating layer is etched to form an inductance pattern and a rerouting pattern, and then metal is filled in the inductance pattern and the rerouting pattern to form an inductance and a second rerouting layer, wherein the inductance and the second rerouting layer are integrally formed.
The invention has at least the following beneficial effects: according to the adapter plate structure and the forming method thereof disclosed by the invention, the capacitor is integrated in the adapter plate structure, the inductor is integrated on the surface of the adapter plate, so that the space occupied by two devices is greatly reduced, the distance between the inductor and the groove capacitor structure is far, the isolation degree is high, the interference between the inductor and the groove capacitor structure is reduced, the dielectric loss is reduced, and the Q value of the inductor is improved; compared with a common plane M I M capacitor, the trench capacitor structure is used, so that the capacitor density is improved, and the capacitance value can be effectively improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 shows a schematic cross-sectional view of an interposer structure according to one embodiment of the present invention; and
fig. 2A to 2N are schematic cross-sectional views illustrating a process of forming a interposer structure according to an embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention.
It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as limiting or implying any relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and not for limiting the order of the steps, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
At present, the integration of the capacitor and the inductor structure mainly comprises the following modes:
1. the integration is realized by using the on-chip capacitance element, the capacitance used in the mode is mostly plane capacitance in an M I M mode, and an M I M capacitance structure is formed by sandwiching a capacitance medium layer between two metal electrode plates in the horizontal direction.
2. The on-chip inductance element is used for realizing integration, the plane spiral inductance structure with more inductance used in the mode is formed by using a rewiring layer with the thickness below 10um as an inductance metal coil, capacitance and inductance are integrated together in an adapter plate in the prior art, the distance between the capacitance and the inductance is relatively short, relatively large interference exists between the capacitance and the inductance, dielectric loss exists in the inductance, and the performance of the inductance is limited.
The capacitor is limited by area cost in the integrated mode of the capacitor and the inductor structure, the capacitance is limited, the capacitor density is low, and the capacitor and the inductor occupy larger plane area cost when being integrated.
The invention provides a transfer plate structure and a forming method thereof, wherein a groove capacitor structure array is formed in a substrate, a capacitor is formed by a conductor on the side wall of the groove, a high-K value medium and a middle conductor, an inductor is formed on the back surface of the transfer plate, and a capacitor lower electrode and the inductor are led out by a plurality of rewiring layers above the transfer plate to construct a series/parallel capacitor and inductor structure. The capacitor is integrated in the adapter plate, the inductor is integrated on the surface of the adapter plate, the occupied space of two devices is greatly reduced, the distance between the inductor and the groove capacitor structure is far, the isolation degree is high, the interference between the inductor and the groove capacitor structure is reduced, the dielectric loss is reduced, and the Q value of the inductor is improved; compared with a common plane M I M capacitor, the trench capacitor structure is used, so that the capacitor density is improved, and the capacitance value can be effectively improved.
The adaptor plate structure is described below in connection with specific embodiments.
Fig. 1A shows a schematic cross-sectional view of an interposer structure according to an embodiment of the present invention. Fig. 1B shows a schematic top view of a interposer structure according to an embodiment of the present invention.
As shown in fig. 1A and 1B, a interposer structure includes two bonded first interposer, wherein the first interposer includes a substrate 101, a trench capacitor structure, an inductor 105, a conductive element 106, a first redistribution layer 107, and a second redistribution layer 108.
A plurality of interconnected trench capacitor structures located on the front side of the substrate 101. The trench capacitor structure includes a plurality of trenches located on the front side of the substrate 101; a capacitance lower electrode 102 covering an inner wall of the trench; a capacitance medium 103, which is located on one side surface of the capacitance lower electrode 102 facing away from the inner wall of the trench; a capacitive upper electrode 104 located on a side surface of the capacitive medium 103 facing away from the capacitive lower electrode 102. The capacitor lower electrodes 102 of the plurality of trench capacitor structures are electrically connected to each other so that the plurality of trench capacitor structures are connected in series. A plurality of interconnected trench capacitor structures form a capacitor array.
An inductor 105 located on the back side of the substrate 101. The inductor 105 is electrically connected to the trench capacitor structure.
And a conductive member 106 located at a side of the trench capacitor structure and spaced apart from the trench capacitor structure. The conductive member 106 penetrates the substrate 101. The substrate 101 has a through hole, and the conductive member 106 is located in the through hole. The via penetrates through the substrate 101, is located at a side surface of the trench capacitor structure, and is spaced from the trench capacitor structure.
A first redistribution layer 107 electrically connecting the conductive element 106 and the trench capacitor structure. The first re-wiring layer 107 is electrically connected to the capacitor lower electrode 102 of the trench capacitor structure. The first redistribution layer 107 is located on the front side of the substrate 101.
A second redistribution layer 108 electrically connecting the conductive element 106 and the inductor 105. The second redistribution layer 108 is located on the back side of the substrate 101. The second redistribution layer 108 is integrally formed with the inductor 105.
The above-mentioned keysets structure still includes: a first insulating layer 109 located between the capacitor lower electrode 102 and the trench inner wall; a second insulating layer 110 located on a surface of the capacitor upper electrode 104 facing away from the capacitor medium 103; a third insulating layer 111 located between the inner wall of the via hole and the conductive member 106; a fourth insulating layer 112 located on the back side of the substrate 101. The fourth insulating layer 112 surrounds the second redistribution layer 108.
The first insulating layer 109 covers the front surface of the substrate 101 and the inner walls of the trench.
The capacitive lower electrode 102 extends to an upper surface of the first insulating layer facing away from the substrate 101.
The first redistribution layers 107 of the two first interposer boards are bonded such that the two first interposer boards are bonded to form a interposer board structure. The two first transfer plates are bonded face to face.
The upper inductor and the lower inductor in the adapter plate structure are connected in parallel to form a three-dimensional inductor, and the upper capacitor array and the lower capacitor array are connected in parallel. According to the adapter plate structure, the capacitor structure is integrated in the adapter plate, the inductor is integrated on the surface of the adapter plate, the occupied space of two devices is greatly reduced, the distance between the inductor and the groove capacitor structure is far, the isolation degree is high, the interference between the inductor and the groove capacitor structure is reduced, the dielectric loss is reduced, and the Q value is improved. Compared with a common plane M I M capacitor, the trench capacitor structure is used, so that the capacitor density is improved, the capacitor value can be effectively improved, the capacitor can be freely placed near a required circuit, and the power quality can be effectively optimized. When the adapter plate structure is used, the chip can be flexibly integrated on the adapter plate structure.
Fig. 2A to 2N are schematic cross-sectional views illustrating a process of forming a interposer structure according to an embodiment of the present invention.
First, forming a first adapter plate, and then bonding the two first adapter plates to form an adapter plate structure.
The process of forming the first adapter plate is as follows:
in step 1.1, as shown in fig. 2A, a trench 202 is formed on the front side of the substrate 201 by etching.
In step 1.2, as shown in fig. 2B, a first insulating layer 203 is formed on the front surface of the substrate 201 and the inner wall of the trench 202. The first insulating layer 203 is formed, for example, by deposition.
In step 1.3, as shown in fig. 2C, a capacitor bottom electrode 204 is formed on the inner wall of the trench 202. The capacitor bottom electrode is formed, for example, by electroplating a metal layer on the inner walls of the trench 202. The capacitor bottom electrode 204 also extends to the upper surface of the substrate 201, away from the substrate 201, of the first insulating layer on the front side of the substrate 201.
In step 1.4, as shown in fig. 2D, a capacitance medium 205 is formed on a surface of a side of the capacitance lower electrode 204 facing away from the inner wall of the trench 202. The capacitive medium 205 is formed, for example, by deposition.
In step 1.5, as shown in fig. 2E, a capacitor upper electrode 206 is formed on a surface of the capacitor medium 205 facing away from the capacitor lower electrode 204. The capacitor bottom electrode 206 is formed, for example, by electroplating a metal layer on a surface of the capacitor dielectric 205 facing away from the capacitor bottom electrode 204. The capacitor bottom electrode 204, the capacitor dielectric 205 and the capacitor bottom electrode 206 in each trench 202 form a trench capacitor structure, and the capacitor bottom electrodes between each trench capacitor structure are electrically connected so as to be connected in series between the plurality of trench capacitor structures.
In step 1.6, as shown in fig. 2F, a second insulating layer 207 is formed on a surface of the capacitor upper electrode 206 facing away from the capacitor medium 205. The second insulating layer 207 is formed, for example, by deposition.
In step 1.7, as shown in fig. 2G, a via 208 is formed in the front side of the substrate 201. The via 208 is located on a side of the trench 202 and is spaced apart from the trench 202. The depth of the via 208 is greater than the depth of the trench 202.
In step 1.8, as shown in fig. 2H, a third insulating layer 209 is formed on the inner wall of the via 208.
In step 1.9, as shown in fig. 2I, a conductive member 210 is formed in the via 208.
In step 1.10, as shown in fig. 2J, a first redistribution layer 211 is formed on the front surface of the substrate 201 to connect the conductive element 210 and the capacitor bottom electrode 204.
In step 1.11, as shown in fig. 2K, the back surface of the substrate 201 is thinned, exposing the conductive element 210.
In step 1.12, as shown in fig. 2L and 2M, an inductor 212 and a second redistribution layer 213 are disposed on the back surface of the substrate 201, and finally a first interposer is obtained. Wherein the inductor 212 and the second redistribution layer 213 are integrally formed. The second redistribution layer 213 electrically connects the inductor 212 and the conductive element 210. First, a fourth insulating layer 214 is formed on the back surface of the substrate 201, and the fourth insulating layer 214 is etched to form an inductance pattern and a rerouting pattern, and then, the inductance pattern and the line pattern are filled with a metal to form an inductance 212 and a second rerouting layer 213.
Step 2, as shown in fig. 2N, the front sides of the two first adapter plates are bonded to obtain the adapter plate structure. The first redistribution layers 211 of the two first interposer boards are bonded such that the two first interposer boards are bonded to form a interposer board structure. And bonding the two first conversion plates to further improve the capacitance value and the inductance Q value.
While certain embodiments of the present invention have been described herein, those skilled in the art will appreciate that these embodiments are shown by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the present teachings without departing from the scope of the invention. The appended claims are intended to define the scope of the invention and to cover such methods and structures within the scope of these claims themselves and their equivalents.

Claims (10)

1. An interposer structure comprising two bonded first interposer boards, wherein the first interposer boards comprise:
a substrate;
a plurality of interconnected trench capacitor structures located on a front side of the substrate, wherein the trench capacitor structures comprise: a plurality of trenches located at a front side of the substrate; a capacitor bottom electrode covering an inner wall of the trench; the capacitor medium is positioned on one side surface of the capacitor lower electrode, which is away from the inner wall of the groove; the capacitor upper electrode is positioned on one side surface of the capacitor medium, which is away from the capacitor lower electrode;
and the inductor is positioned on the back surface of the substrate and is electrically connected with the groove capacitor structure.
2. The adaptor plate structure of claim 1, further comprising:
the conductive piece is positioned on the side surface of the groove capacitor structure and is spaced from the groove capacitor structure;
a first rewiring layer electrically connecting the conductive member and the trench capacitor structure;
and the second rewiring layer is electrically connected with the conductive piece and the inductor.
3. The interposer board structure of claim 2 wherein the substrate has a through hole, the conductive element being located in the through hole.
4. The adaptor plate structure of claim 3, further comprising:
the first insulating layer is positioned between the capacitor lower electrode and the inner wall of the groove;
the second insulating layer is positioned on one side surface of the upper electrode of the capacitor, which is away from the capacitor medium;
a third insulating layer located between the inner wall of the through hole and the conductive member;
and a fourth insulating layer located on the back surface of the substrate.
5. The interposer structure of claim 2 wherein the capacitor bottom electrode extends to an upper surface of the first insulating layer facing away from the substrate; the capacitor lower electrodes of the trench capacitor structures are electrically connected;
the first rewiring layer is electrically connected with the capacitor lower electrode.
6. The interposer board structure of claim 5 wherein the first rewiring layers of the two first interposer boards are bonded such that the two first interposer boards are bonded to form the interposer board structure.
7. A method of forming a interposer structure, comprising: first adapter plates are formed, and then two first adapter plates are bonded to form an adapter plate structure, wherein forming the first adapter plates comprises:
forming a trench on the front surface of the substrate;
forming a capacitor lower electrode on the inner wall of the groove;
forming a capacitance medium on the surface of one side of the lower electrode of the capacitance, which is away from the inner wall of the groove;
forming a capacitor upper electrode on the surface of one side of the capacitor medium, which is away from the capacitor lower electrode;
forming a through hole on the front surface of the substrate;
forming a conductive member in the via hole;
forming a first rewiring layer on the front surface of the substrate, wherein the first rewiring layer is used for connecting the conductive piece and the lower electrode of the capacitor;
thinning the back of the substrate to expose the conductive member;
and arranging an inductor and a second redistribution layer on the back surface of the substrate to finally obtain the first adapter plate.
8. The method of forming a interposer structure of claim 7, further comprising:
forming a first insulating layer on the front surface of the substrate and the inner wall of the groove before forming the capacitor lower electrode on the inner wall of the groove;
before forming a through hole on the front surface of the substrate, forming a second insulating layer on the surface of one side of the upper electrode of the capacitor, which is away from the capacitor medium;
a third insulating layer is formed on the inner wall of the via hole before the conductive member is formed in the via hole.
9. The method of claim 7, wherein the interposer structure is obtained by bonding the first redistribution layers of the two first interposer plates.
10. The method of forming a interposer structure as claimed in claim 7, wherein a fourth insulating layer is formed on the back surface of the substrate, the fourth insulating layer is etched to form an inductor pattern and a redistribution pattern, and then metal is filled in the inductor pattern and the redistribution pattern to form an inductor and a second redistribution layer, wherein the inductor and the second redistribution layer are integrally formed.
CN202310083152.1A 2023-02-08 2023-02-08 Switching plate structure and forming method thereof Pending CN116093084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310083152.1A CN116093084A (en) 2023-02-08 2023-02-08 Switching plate structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310083152.1A CN116093084A (en) 2023-02-08 2023-02-08 Switching plate structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116093084A true CN116093084A (en) 2023-05-09

Family

ID=86186712

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310083152.1A Pending CN116093084A (en) 2023-02-08 2023-02-08 Switching plate structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116093084A (en)

Similar Documents

Publication Publication Date Title
KR100917508B1 (en) High-frequency module board device
US6800936B2 (en) High-frequency module device
CN1663120B (en) Electronic component comprising a multilayer substrate
US6633005B2 (en) Multilayer RF amplifier module
US7884458B2 (en) Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package
US20070236900A1 (en) Chip carrier and fabrication method
WO2007131967A1 (en) Integrated low-loss capacitor-arrray structure
US20100052099A1 (en) Capacitor device and method for manufacturing the same
CN110959197B (en) Distributed LC filter structure
CN111564426A (en) Radio frequency front-end module, radio frequency communication device and electronic equipment
CN103367269A (en) Separation mixed substrate for radio frequency application
US12058814B2 (en) Power module and manufacturing method thereof
CN113380772B (en) Chip packaging structure and packaging method thereof
CN110087391B (en) LTCC local vibration source module and preparation method thereof
CN212113714U (en) Radio frequency front-end module, radio frequency communication device and electronic equipment
US20080169883A1 (en) LC resonant circuit
WO2024114183A1 (en) Heterogeneous package substrate and module
WO2023232050A1 (en) Wafer-level power module and manufacturing method therefor
WO2024087535A1 (en) Adapter board structure and preparation method therefor
CN116093084A (en) Switching plate structure and forming method thereof
KR101696644B1 (en) Rf stacked module using three dimension vertical interconnection and arrangement method thereof
US11387182B2 (en) Module structure and method for manufacturing the module structure
CN115050716A (en) High-frequency high-power-density module power supply and manufacturing method thereof
CN114093852A (en) Three-dimensional stacked capacitor integrated structure and manufacturing method thereof
CN114285387B (en) Small LC filter and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination