CN218867104U - Heterogeneous packaging substrate and module - Google Patents
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- CN218867104U CN218867104U CN202223259905.XU CN202223259905U CN218867104U CN 218867104 U CN218867104 U CN 218867104U CN 202223259905 U CN202223259905 U CN 202223259905U CN 218867104 U CN218867104 U CN 218867104U
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- 239000000758 substrate Substances 0.000 title claims abstract description 107
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 117
- 229910052751 metal Inorganic materials 0.000 claims abstract description 117
- 239000011521 glass Substances 0.000 claims abstract description 36
- 239000003989 dielectric material Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000000149 penetrating effect Effects 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 78
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000007530 organic bases Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model provides a heterogeneous packaging substrate and a module, wherein the heterogeneous packaging substrate comprises a glass substrate, a heterogeneous layer, a metal column, a back metal wiring layer and a containing hole which simultaneously penetrates through the glass substrate and the heterogeneous layer; the heterogeneous layer comprises a dielectric material layer and metal wires, and the metal wires form metal wiring and passive devices in the dielectric material layer; the metal wiring comprises N layers, wherein N is a positive integer and meets the requirement, and N is more than or equal to 2; the passive device is made of metal wires by an integrated passive device process; the back metal wiring layer at least partially covers the accommodating hole; the back metal wiring layer is provided with a plurality of metal bumps which are manufactured by an etching process and are used for realizing the electric connection with pins of an external chip accommodated in the accommodating hole; the back metal wiring layer is connected with the metal wiring through the metal column, and the passive device is electrically connected with the metal bump after sequentially passing through the metal wiring and the metal column. The technical scheme of the utility model whole thickness is little, and the radiating effect is good and the reliability is high.
Description
Technical Field
The utility model relates to an encapsulation technology field especially relates to a heterogeneous encapsulation base plate and module.
Background
At present, the development of mobile communication technology, coming in the 5G era, greatly increases the complexity and the transmission power of the radio frequency chip of the wireless terminal represented by a mobile phone.
In the related art, a radio frequency module using a core device is formed by welding a chip, a capacitor, an inductor, a resistor and the like on a substrate. The related art substrate is generally an organic-based substrate.
However, the related art organic base substrate is generally a multilayer substrate. The 5G radio frequency module has the defects of 6 layers, about 250um substrate thickness and longer heat dissipation path. The transmission power of the radio frequency power amplifier in the radio frequency chip is larger and larger, the generated heat is larger and larger, and along with the improvement of the complexity of the modulation mode of the signal, the radio frequency power amplifier needs to work in a deeper and deeper back-off area, so that the efficiency of the radio frequency power amplifier is lower and lower, and the generated heat is more and more. Combining the above factors, the problem of heat dissipation of the rf power amplifier is becoming more and more severe. The improvement of the working temperature of the radio frequency power amplifier can bring about the problems of performance degradation, poor reliability and the like. How to reduce the problem of heat dissipation of the rf power amplifier through the substrate is a technical problem to be solved. In addition, the thickness of the chip in the radio frequency module is generally 150 microns-200 microns, and the thickness of the chip and the substrate stacked is generally 700 microns, so that the whole thickness of the radio frequency module is large, and the radio frequency module is not suitable for being assembled and used in wearable terminals, smart watches and the like.
Therefore, it is desirable to provide a substrate and a module that solve the above problems.
SUMMERY OF THE UTILITY MODEL
Not enough to above prior art, the utility model provides a whole thickness is little, and the radiating effect is good and the heterogeneous packaging substrate and the module that the reliability is high.
In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a heterogeneous package substrate, which includes a glass substrate, a heterogeneous layer extending from one side of the glass substrate, a metal pillar penetrating through the glass substrate, a back metal wiring layer disposed on one side of the glass substrate away from the heterogeneous layer, and a receiving hole penetrating through both the glass substrate and the heterogeneous layer; the heterogeneous layer comprises a dielectric material layer extending from the glass substrate and metal wires arranged in the dielectric material layer, and the metal wires form metal wiring and passive devices in the dielectric material layer; the metal wiring comprises N layers, N is a positive integer and satisfies the requirement, and N is more than or equal to 2; the passive device is formed by integrating the metal wire through a passive device process; the back metal wiring layer at least partially covers the accommodating hole; the back metal wiring layer is provided with a plurality of metal lugs manufactured by an etching process and used for realizing electric connection with pins of an external chip accommodated in the accommodating hole; the back metal wiring layer is connected with the metal wiring through the metal column, and the passive device is electrically connected with the metal bump through the metal wiring and the metal column in sequence.
Preferably, the accommodating holes include a plurality of metal bumps, each of the metal bumps covers one of the accommodating holes, and the metal bumps are matched with the pins of the external chip accommodated in the corresponding accommodating hole.
Preferably, the dielectric material layer comprises a plurality of dielectric layers which are sequentially stacked; the metal wiring and the passive device are formed in a plurality of the dielectric layers.
Preferably, the heterogeneous layer is provided with a plurality of bonding pads on one side of the dielectric material layer away from the glass substrate, and the bonding pads are used for being respectively welded with pins and external connecting wires of other external chips; the pad is electrically connected to the metal wiring.
Preferably, the pad is formed in one of the dielectric layers farthest from the glass substrate and exposed to the dielectric layer.
Preferably, the passive device comprises one or more of a capacitor, an inductor and a resistor.
Preferably, at least two of the capacitor, the inductor and the resistor are connected in the dielectric material layer to form a circuit functional module, and the circuit functional module comprises one or more of a radio frequency filter, an impedance matching circuit and a power supply decoupling circuit.
Preferably, the back metal wiring layer includes at least one layer.
Preferably, the metal bump is a solid copper pillar.
In a second aspect, the embodiment of the present invention further provides a module, which includes a chip and the above-mentioned heterogeneous package substrate provided by the embodiment of the present invention, the pin of the chip is electrically connected to the metal bump.
Compared with the prior art, the utility model discloses a heterogeneous packaging substrate and module set up an isomorphism layer and back metal wiring layer respectively through the both sides at the glass substrate through heterogeneous packaging substrate to the setting runs through simultaneously the glass substrate with the accommodating hole on isomorphism layer. And at least partially covering the accommodating hole with the back metal wiring layer, wherein the back metal wiring layer is provided with a plurality of metal bumps, and the metal bumps are electrically connected with pins of the external chip accommodated in the accommodating hole. The structure enables heat generated by an external chip to be directly radiated through the back metal wiring layer, so that a radiating path is greatly shortened, and the thermal stability and reliability of the module are improved. In addition, the external chip is accommodated in the accommodating hole, and compared with the related art, the thickness of the external chip is not required to be superposed with that of the heterogeneous packaging substrate, so that the module is small in overall thickness and easy to apply. In addition, the heterogeneous layer includes a dielectric material layer and a metal line, and a metal wiring and a passive device are formed in the dielectric material layer through the metal line. The utility model discloses a heterogeneous packaging substrate forms passive matching components such as electric capacity, inductance, resistance in that the glass substrate is inside, more saves space. Wherein, heterogeneous packaging substrate can realize integrated electric capacity, high Q's inductance and resistance through passive device, and rethread metal wiring electricity is connected, thereby integrated IPD filter in the dielectric material layer and impedance matching circuit, radio frequency filter and the power decoupling circuit who realizes the radio frequency circuit the inside satisfy miniaturized modular design, and the device occupies that the substrate area is little, thereby makes the utility model discloses a high and small of integrated level of heterogeneous packaging substrate and module.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings:
fig. 1 is a schematic structural diagram of a heterogeneous package substrate according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a heterogeneous package substrate according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a module according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a module according to a fourth embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.
The description of the embodiments/examples set forth herein is provided to illustrate the principles of the invention and is intended to be exemplary and explanatory only and should not be construed as limiting the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
(embodiment one)
The utility model provides a heterogeneous packaging substrate 100. Referring to fig. 1, fig. 1 is a schematic structural diagram of a heterogeneous package substrate 100 according to a first embodiment of the present invention.
The heterogeneous packaging substrate 100 comprises a glass substrate 1, a heterogeneous layer 2 extending from one side of the glass substrate 1, a metal column 3 penetrating through the glass substrate 1, a back metal wiring layer 4 arranged on one side of the glass substrate 1 far away from the heterogeneous layer 2, and a containing hole 10 penetrating through the glass substrate 1 and the heterogeneous layer 2.
The heterogeneous layer 2 includes a dielectric material layer 21 extended from the glass substrate 1 and a metal line 22 disposed within the dielectric material layer 21.
The dielectric material layer 21 includes a plurality of dielectric layers stacked in sequence.
The metal lines 22 form metal wiring 5 and passive devices 6 within the dielectric material layer 21.
The metal wiring 5 is formed in a plurality of the dielectric layers. The metal wiring 5 comprises N layers, N is a positive integer and satisfies, and N is more than or equal to 2.
The passive devices 6 are formed in a plurality of the dielectric layers. The passive device 6 is made by an integrated passive device process for the metal line 22. The passive device 6 comprises one or more of a capacitor 61, an inductor 62 and a resistor (not shown).
Wherein the capacitor 61 is a MIM capacitor formed by integrating the metal lines 22 on the glass substrate 1 by a passive device process. The MIM capacitor utilizes the capacitance between upper and lower layers of metal, namely a plate capacitor, the lower plate is Mn, the upper plate is Mn +1, and the conventional organic base material substrate cannot realize the capacitor because common Mn and Mn +1 are far away from an oxide layer in a three-dimensional space, so that the capacitance of the manufactured capacitor is not large and cannot be applied. And the capacitance of the MIM capacitor is larger, so that the SMD device welded on the substrate can be replaced.
This exampleIn one embodiment, at least two of the capacitor 61, the inductor 62 and the resistor are connected within the dielectric material layer 21 to form a circuit functional module 8, and the circuit functional module 8 includes one or more of a radio frequency filter 81, an impedance matching circuit 82 and a power decoupling circuit (not shown). The size of the passive device is fixed relative to the passive device soldered on the substrate in the related art, namely, the passive device is a capacitor or an inductor resistor. For example, 01005 capacitors commonly used in a module have a size of 0.4 x 0.2mm, and a layout area of one capacitor on a substrate is 0.08mm 2 Whereas the capacitance density that can be achieved in a plurality of said dielectric layers is 600pF/mm2. If we want to realize a common capacitance value, such as 2pF, the layout area of the surface mount device (SMD device) in the related art on the substrate is 0.08mm 2 In the first embodiment, the realization is only 1/300mm2. The traditional SMD placement requires the requirement of space and cannot be close to each other, so that a plurality of SMD devices are placed, the space is calculated, and the layout area is larger; the pitch of the passive device in the first embodiment can be as small as 10um, and the layout area is very compact. Preferably, the passive device in the first embodiment may be disposed below the external chip. Thereby make the utility model discloses a heterogeneous packaging substrate 100's integrated level is high and small.
Each of the passive devices 6 is electrically connected through the metal wiring 5.
The back metal wiring layer 4 is connected to the metal wiring 5 through the metal posts 3. The back metal wiring layer 4 is arranged on the outer surface of the heterogeneous layer 2, so that space can be reasonably utilized, the heterogeneous packaging substrate 100 can be reasonably distributed, and the whole product is small in size.
The back metal wiring layer 4 includes at least one layer. In this embodiment, the back metal wiring layer 4 is a single layer. Of course, without being limited thereto, the back metal wiring layer 4 may be designed to be multi-layered according to design requirements.
The back metal wiring layer 4 at least partially covers the receiving hole 10. The back metal wiring layer 4 is provided with a plurality of metal bumps 7 made by an etching process. The metal bumps 7 are used for electrically connecting with pins of an external chip 11 accommodated in the accommodating hole 10. The passive device 6 is electrically connected to the metal bump 7 through the metal wiring 5 and the metal pillar 3 in this order. It is a plurality of metal bump 7 makes the heat that outside chip 11 produced directly dispel the heat through back metal wiring layer 4, has shortened heat dissipation path greatly to improve the use the utility model discloses a thermal stability and the reliability of heterogeneous packaging substrate 100's module.
In the first embodiment, the metal bump 7 is a solid copper pillar formed by a deposition process. Of course, without limitation, other structures may be employed to facilitate electrical connection with the pins of the external chip 11.
In this embodiment, the receiving hole 10 may be a through hole or a strip-shaped slot. Of course, the external chip 11 may be accommodated in the accommodating hole 10 in any shape. Compared with the related art, the structure of accommodating hole 10 makes the thickness of outside chip 11 not need with the utility model discloses a heterogeneous packaging substrate 100's thickness stack to make and use the utility model discloses a whole thickness of heterogeneous packaging substrate 100's module is little and easily use.
In the first embodiment, the heterogeneous layer 2 is further provided with a plurality of pads 9 on a side of the dielectric material layer 21 away from the glass substrate 1. The bonding pads 9 are used for bonding with pins of other external chips 11 and external wires, respectively. The pad 9 is electrically connected to the metal wiring 5. The pad 9 is formed in and exposed to one of the dielectric layers farthest from the glass substrate 1. And the pins of the external chip 11 and the bonding pads 9 are welded through a wire bonding process or a flip chip packaging process. The arrangement of the bonding pads 9 is beneficial to the assembly and application of the heterogeneous packaging substrate 100. The user is according to using the utility model discloses a thickness requirement of heterogeneous package substrate 100's module will not outside chip 11 with pad 9 welding to realize the little requirement of this module thickness.
Example two
The utility model also provides a heterogeneous packaging substrate 200. Referring to fig. 2, fig. 2 is a schematic structural diagram of a heterogeneous package substrate 200 according to a second embodiment of the present invention.
The heterogeneous package substrate 200 of the second embodiment is substantially the same as the heterogeneous package substrate 100 of the first embodiment, except that: the housing hole 10 includes a plurality of. Each receiving hole 10 can receive a corresponding external chip 11, and the plurality of metal bumps 7 in the back metal wiring layer 4 respectively covering each receiving hole 10 are matched with the pins of the external chip 11 received in the corresponding receiving hole 10.
In addition, the heterogeneous package substrate 200 of the second embodiment may be provided with a plurality of pads 9 or without a plurality of pads 9. In the second embodiment, the heterogeneous package substrate 200 is not provided with the plurality of pads 9. This structure can be so that a plurality of outside chip 11 accept respectively with in the difference in accommodate hole 10 in, thereby make and use the utility model discloses a heterogeneous packaging substrate 200's module's whole thickness is little.
The second heterogeneous package substrate 200 of this embodiment can implement various implementation manners and corresponding beneficial effects in the first heterogeneous package substrate 100 of this embodiment, and for avoiding repetition, details are not repeated here.
(third embodiment)
The third embodiment provides a module 300, which further includes a chip 11 and the heterogeneous package substrate 100.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a module 300 according to a third embodiment of the present invention.
The chip 11 includes a plurality of chips. In the third embodiment, the chip 11 includes a gaas chip 111 and a si-based chip 112. The gaas chip 111 is housed in the housing hole 10, which is beneficial to effectively dissipate heat generated by the gaas chip 111 through the backside metal wiring layer 4. The silicon-based chip 112 is soldered to the pad 9, thereby simplifying the manufacturing process and improving the efficiency and reliability of the manufacturing process.
The utility model discloses a module 300 is integrated to a encapsulation with the semiconductor device of different materials in, thereby makes the utility model discloses a module 300 integrated level is high, the size is little, economic nature is good, the flexibility is high, system performance is better.
The module 300 of the third embodiment can implement various implementation manners and corresponding beneficial effects in the first embodiment of the heterogeneous package substrate 100, and for avoiding repetition, details are not repeated here.
(example four)
The fourth embodiment provides a module 400, where the module 400 further includes a chip 11a and the heterogeneous package substrate 200.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a module 400 according to a third embodiment of the present invention.
The chip 11a includes a plurality of chips. In the third embodiment, the chip 11a includes a gaas chip 111a and a si-based chip 112a. The gaas chip 111a and the si-based chip 112a are both housed in the housing hole 10, which is beneficial to effectively dissipate heat generated by the gaas chip 111a and the si-based chip 112a through the backside metal wiring layer 4. Meanwhile, the thickness of the module 400 does not need to be the thickness of the stacked chip 11a, and the thickness of the module 400 is the thickness of the heterogeneous package substrate 200, so that the overall thickness of the module 400 is small and easy to apply.
The utility model discloses a module 400 is integrated to an encapsulation with the semiconductor device of different materials in, thereby makes the utility model discloses a module 400's integrated level is high, the size is little, economic nature is good, the flexibility is high, system performance is better.
The module 400 of the fourth embodiment can implement various implementation manners and corresponding beneficial effects in the embodiment of the heterogeneous package substrate 200 of the second embodiment, and for avoiding repetition, details are not repeated here.
It should be pointed out that the utility model discloses a relevant glass substrate, dielectric material layer upon layer and metal wire are the material commonly used in the field, have index and parameter and adjust according to practical application, here, do not describe in detail.
Compared with the prior art, the utility model discloses a heterogeneous packaging substrate and module pass through heterogeneous packaging substrate and set up an isomorphism layer and back metal wiring layer respectively through the both sides at the glass substrate to the setting runs through simultaneously the glass substrate with the hole of acceping on isomorphism layer. And at least partially covering the accommodating hole with the back metal wiring layer, wherein the back metal wiring layer is provided with a plurality of metal bumps, and the metal bumps are electrically connected with pins of an external chip accommodated in the accommodating hole. The structure enables heat generated by an external chip to be directly radiated through the back metal wiring layer, so that a radiating path is greatly shortened, and the thermal stability and reliability of the module are improved. In addition, the external chip is accommodated in the accommodating hole, and compared with the related art, the thickness of the external chip does not need to be superposed with that of a heterogeneous packaging substrate, so that the whole thickness of the module is small and the module is easy to apply. In addition, the heterogeneous layer includes a dielectric material layer and a metal line, and a metal wiring and a passive device are formed in the dielectric material layer through the metal line. The utility model discloses a heterogeneous packaging substrate is with passive matching components such as electric capacity, inductance, resistance at the inside formation of glass substrate, more province space. Wherein, heterogeneous packaging substrate can realize integrated capacitance, high Q's inductance and resistance through passive device, and rethread metal wiring electricity is connected, thereby dielectric material layer in situ integrated IPD wave filter and the impedance matching circuit, the radio frequency filter and the power decoupling circuit that realize the radio frequency circuit the inside satisfy miniaturized module design, and the device occupies that the base plate area is little, thereby makes the utility model discloses a heterogeneous packaging substrate and the integrated level of module are high and small.
It should be noted that the above embodiments described with reference to the drawings are only used for illustrating the present invention and not for limiting the scope of the present invention, and those skilled in the art should understand that modifications or equivalent substitutions made on the present invention without departing from the spirit and scope of the present invention should be included in the scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (10)
1. The heterogeneous packaging substrate is characterized by comprising a glass substrate, a heterogeneous layer extending from one side of the glass substrate, a metal column penetrating through the glass substrate, a back metal wiring layer arranged on one side of the glass substrate far away from the heterogeneous layer, and a containing hole penetrating through the glass substrate and the heterogeneous layer simultaneously;
the heterogeneous layer comprises a dielectric material layer extending from the glass substrate and metal wires arranged in the dielectric material layer, and the metal wires form metal wiring and passive devices in the dielectric material layer;
the metal wiring comprises N layers, N is a positive integer and satisfies the requirement, and N is more than or equal to 2;
the passive device is formed by integrating the metal wire through a passive device process;
the back metal wiring layer at least partially covers the accommodating hole; the back metal wiring layer is provided with a plurality of metal lugs manufactured by an etching process and used for realizing electric connection with pins of an external chip accommodated in the accommodating hole;
the back metal wiring layer is connected with the metal wiring through the metal column, and the passive device is electrically connected with the metal bump through the metal wiring and the metal column in sequence.
2. The package substrate of claim 1, wherein the receiving holes comprise a plurality of receiving holes, each receiving hole can receive a corresponding external chip, and the metal bumps of the back metal wiring layer respectively covering each receiving hole are matched with pins of the external chip received in the corresponding receiving hole.
3. The heterogeneous packaging substrate of claim 1, wherein the dielectric material layer comprises a plurality of dielectric layers stacked in sequence; the metal wiring and the passive device are formed in a plurality of the dielectric layers.
4. The heterogeneous packaging substrate according to claim 3, wherein the heterogeneous layer is provided with a plurality of bonding pads on one side of the dielectric material layer away from the glass substrate, and the bonding pads are used for being respectively welded with pins and external wires of other external chips; the pad is electrically connected to the metal wiring.
5. The heterogeneous package substrate of claim 4, wherein the pad is formed in and exposed to one of the dielectric layers that is farthest from the glass substrate.
6. The heterogeneous package substrate of claim 1, wherein the passive devices comprise one or more of capacitors, inductors, and resistors.
7. The heterogeneous package substrate of claim 6, wherein at least two of the capacitor, the inductor, and the resistor are connected within the layer of dielectric material to form a circuit functional module comprising one or more of a radio frequency filter, an impedance matching circuit, and a power decoupling circuit.
8. The heterogeneous package substrate of claim 1, wherein the backside metal routing layer comprises at least one layer.
9. The package substrate of claim 1, wherein the metal bump is a solid copper pillar.
10. A module comprising a chip, characterized in that it further comprises the heterogeneous package substrate of any one of claims 1 to 9, the pins of the chip being electrically connected to the metal bumps.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223259905.XU CN218867104U (en) | 2022-11-30 | 2022-11-30 | Heterogeneous packaging substrate and module |
| PCT/CN2023/126192 WO2024114183A1 (en) | 2022-11-30 | 2023-10-24 | Heterogeneous package substrate and module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223259905.XU CN218867104U (en) | 2022-11-30 | 2022-11-30 | Heterogeneous packaging substrate and module |
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|---|---|
| CN218867104U true CN218867104U (en) | 2023-04-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202223259905.XU Active CN218867104U (en) | 2022-11-30 | 2022-11-30 | Heterogeneous packaging substrate and module |
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| Country | Link |
|---|---|
| CN (1) | CN218867104U (en) |
| WO (1) | WO2024114183A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114183A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100524706C (en) * | 2002-05-31 | 2009-08-05 | 富士通微电子株式会社 | Semiconductor device manufacturing method |
| TWI239603B (en) * | 2003-09-12 | 2005-09-11 | Advanced Semiconductor Eng | Cavity down type semiconductor package |
| KR101845150B1 (en) * | 2016-04-20 | 2018-04-04 | 전자부품연구원 | Semiconductor package and method for manufacturing the same |
| CN110299329A (en) * | 2018-03-21 | 2019-10-01 | 华为技术有限公司 | A kind of encapsulating structure and preparation method thereof, electronic equipment |
| CN211208440U (en) * | 2019-12-30 | 2020-08-07 | 厦门云天半导体科技有限公司 | Three-dimensional packaging structure integrating chip and antenna |
| CN212517170U (en) * | 2020-05-30 | 2021-02-09 | 华为技术有限公司 | A chip packaging structure and electronic equipment |
| CN215342505U (en) * | 2021-06-28 | 2021-12-28 | 盛合晶微半导体(江阴)有限公司 | Wafer-level ASIC 3D integrated substrate and packaging device |
| CN113990763A (en) * | 2021-10-28 | 2022-01-28 | 上海航天电子通讯设备研究所 | A chip packaging structure and packaging method based on electroforming technology |
| CN114566489A (en) * | 2022-04-27 | 2022-05-31 | 珠海市人民医院 | Fan-out type packaging structure with electromagnetic shielding function and packaging method |
| CN218867104U (en) * | 2022-11-30 | 2023-04-14 | 深圳飞骧科技股份有限公司 | Heterogeneous packaging substrate and module |
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2022
- 2022-11-30 CN CN202223259905.XU patent/CN218867104U/en active Active
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2023
- 2023-10-24 WO PCT/CN2023/126192 patent/WO2024114183A1/en not_active Ceased
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114183A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and module |
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| Publication number | Publication date |
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| WO2024114183A1 (en) | 2024-06-06 |
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