WO2022267025A1 - Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique - Google Patents

Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique Download PDF

Info

Publication number
WO2022267025A1
WO2022267025A1 PCT/CN2021/102445 CN2021102445W WO2022267025A1 WO 2022267025 A1 WO2022267025 A1 WO 2022267025A1 CN 2021102445 W CN2021102445 W CN 2021102445W WO 2022267025 A1 WO2022267025 A1 WO 2022267025A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
type well
semiconductor substrate
electrode
type
Prior art date
Application number
PCT/CN2021/102445
Other languages
English (en)
Chinese (zh)
Inventor
王邦麟
王生荣
童庆强
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/102445 priority Critical patent/WO2022267025A1/fr
Priority to CN202180099523.4A priority patent/CN117501430A/zh
Publication of WO2022267025A1 publication Critical patent/WO2022267025A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology

Definitions

  • the present application relates to the technical field of semiconductors, and in particular to a capacitor, an integrated circuit, a radio frequency circuit and electronic equipment.
  • an impedance matching network (impedance matching network) can be set on the signal transmission line in the electronic equipment.
  • impedance matching network impedance conjugate matching can be achieved between the signal source and the load connected at both ends of the transmission line, referred to as impedance matching.
  • impedance matching impedance conjugate matching
  • the above-mentioned high-frequency signal will be greatly attenuated after passing through the above-mentioned impedance matching network, which leads to the performance degradation of the impedance matching network.
  • Embodiments of the present application provide a capacitor, an integrated circuit, a radio frequency circuit, and an electronic device, which are used to increase the Q value of the capacitor, thereby also improving the performance of an impedance matching network having the capacitor.
  • the first aspect of the embodiments of the present application provides an integrated circuit, which can be manufactured in a chip.
  • the integrated circuit includes an impedance matching network.
  • the impedance matching network may include a capacitor and an inductor electrically connected to the capacitor.
  • the capacitor may include an electrode structure and a capacitor substrate for carrying the electrode structure.
  • the electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes; the first finger electrodes and the second finger electrodes are arranged alternately.
  • the capacitor substrate includes an N-type well.
  • the N-type well is arranged on the semiconductor substrate of the integrated circuit, and the above-mentioned first finger electrode and the second finger electrode are arranged on the N-type well.
  • the N-type well is at potential floating.
  • the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate.
  • two parasitic capacitors are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and finally achieve The purpose of reducing the parasitic capacitance between the entire capacitor and the semiconductor substrate is conducive to improving the Q value of the capacitor.
  • the capacitor has a higher Q value, the attenuation of the high-frequency circuit signal by the capacitor is smaller, which is conducive to improving the performance of the impedance matching network and reducing the load.
  • the reflection of the terminal signal improves the conversion rate of the electrical signal.
  • the heat converted by the reflected signal will be correspondingly reduced, thereby effectively reducing the probability of temperature rise of the electronic device and improving the life of the electronic device.
  • the capacitor substrate further includes a P-type well. It is arranged between the electrode structure and the N-type well.
  • the P-type well is in potential floating.
  • an N-type well and a P-type well in a floating state are arranged between the first finger electrode and the semiconductor substrate.
  • an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate.
  • the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate.
  • the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and ultimately reduce the entire capacitance and the semiconductor substrate.
  • the purpose of the parasitic capacitance between the substrates is to improve the Q value of the capacitor, thereby also improving the performance of the impedance matching network with the capacitor.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the N-type well is located.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located.
  • the capacitor also includes an interconnection structure.
  • One end of the interconnect structure is in contact with the semiconductor substrate, and the other end of the interconnect structure is used for grounding. In this way, the semiconductor substrate can be grounded through the interconnect structure.
  • the interconnection structure includes a P-type semiconductor doped part, a first through hole and a metal part.
  • the P-type semiconductor doped part is disposed on the semiconductor substrate.
  • the P-type semiconductor doping part is used to improve the conductivity between the semiconductor substrate and the first through hole, which is beneficial to signal transmission.
  • the first through hole penetrates through the dielectric layer, and the first end of the first through hole is electrically connected with the P-type semiconductor doped part.
  • the metal part is arranged on the surface of the dielectric layer away from the semiconductor substrate, electrically connected to the second end of the first through hole, and the metal part is used for grounding.
  • the P-type semiconductor doped part is used as one end of the interconnection structure for connecting with the semiconductor substrate. As the other end of the interconnection structure, the metal part is used for grounding.
  • the metal part is made of metal material and has good conductivity, and is used to improve the conductivity of the entire interconnection structure, so that the grounding performance of the semiconductor substrate is good.
  • the interconnection structure is arranged around a circle of the N-type well and connected end to end. In this way, all parts of the semiconductor substrate can be evenly grounded, so that the performance of the capacitor is stable, which is beneficial to provide the Q value of the capacitor, thereby also improving the performance of the impedance matching network with the capacitor.
  • the material of the metal portion is the same as that of the first finger electrode or the second finger electrode. In this way, the fabrication of the metal part can be completed while fabricating the first finger electrode or the second finger electrode, so as to achieve the purpose of briefly describing the fabrication process.
  • the electrode structure further includes a first interconnect electrode and a second interconnect electrode.
  • a plurality of first finger electrodes and the first interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure.
  • a plurality of second finger electrodes and the second interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure.
  • the first finger electrode and the second finger electrode are arranged in the same layer and in parallel.
  • the plurality of first finger electrodes, the plurality of second finger electrodes, the first interconnection electrodes and the second interconnection electrodes may be of the same layer and of the same material. In this way, the first finger electrode, the second finger electrode, the first interconnection electrode and the second interconnection electrode can be formed simultaneously by using the above-mentioned one-time communication process.
  • the electrode structure further includes a first interconnect electrode and a second interconnect electrode.
  • a plurality of first finger electrodes and the first interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure.
  • a plurality of second finger electrodes and the second interconnection electrodes are arranged vertically on the same layer and connected to form an integral structure.
  • the first finger electrode and the second finger electrode are arranged vertically in different layers.
  • a capacitor can also be formed between the first finger-shaped electrode and the second finger-shaped electrode by using different layers.
  • the capacitor further includes an insulating layer and a plurality of electrode structures, and the plurality of electrode structures are stacked.
  • the electrode structure is disposed in the insulating layer.
  • the capacitor also includes a second through hole and a third through hole penetrating through at least a part of the insulating layer.
  • the first finger electrodes in the plurality of electrode structures are all electrically connected to the second through holes.
  • the second finger electrodes in the plurality of electrode structures are all electrically connected to the third through holes.
  • the three through holes are electrically connected to increase the capacitance of the capacitor.
  • the impedance matching network is an L-type matching network, a ⁇ -type matching network, or a T-type matching network.
  • L-type matching network a ⁇ -type matching network
  • T-type matching network a ⁇ -type matching network
  • Those skilled in the art can select the type of the impedance matching network according to needs.
  • a second aspect of the embodiments of the present application provides a radio frequency circuit.
  • the radio frequency circuit includes a radio frequency transceiver.
  • a radio frequency transceiver is used for electrical connection with the antenna.
  • the radio frequency circuit also includes any one of the above-mentioned integrated circuits.
  • the impedance matching network in the integrated circuit is electrically connected between the radio frequency transceiver and the antenna.
  • the radio frequency circuit has the same technical effect as that of the impedance matching network provided by the foregoing embodiments, which will not be repeated here.
  • the radio frequency circuit further includes a field effect transistor.
  • the field effect transistor is integrated in the integrated circuit. In this way, at the same time as manufacturing the above-mentioned field effect transistor, the preparation of the above-mentioned capacitance part structure can be completed, thereby facilitating the simplification of the manufacturing process.
  • the radio frequency circuit further includes a power amplifier, at least one of the output end of the power amplifier and the input end of the power amplifier is electrically connected to the impedance matching network.
  • the above-mentioned field effect transistor is arranged in the power amplifier, and at least a part of the field effect transistor and at least a part of the capacitor substrate are of the same layer and material. In this way, at the same time as the above-mentioned field effect transistor is manufactured, the preparation of a part of the structure of the capacitor substrate can be completed, thereby facilitating the simplification of the manufacturing process.
  • the radio frequency circuit further includes a low noise amplifier, at least one of the output terminal of the low noise amplifier and the input terminal of the low noise amplifier is electrically connected to the impedance matching network.
  • the above-mentioned field effect transistor is arranged in the low noise amplifier, at least a part of the field effect transistor and at least a part of the capacitor substrate are in the same layer and material. In this way, at the same time as the above-mentioned field effect transistor is manufactured, the preparation of a part of the structure of the capacitor substrate can be completed, thereby facilitating the simplification of the manufacturing process.
  • the capacitor substrate further includes a P-type well.
  • the P-type well is located above the N-type well, the surface of the P-type well close to the electrode structure is flush with the first surface, and the rest of the surface is surrounded by the N-type well.
  • the P-type well is in potential floating.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located.
  • the field effect transistor includes: a P-type transistor substrate on a semiconductor substrate, an N-type source region, and an N-type drain region.
  • the semiconductor substrate and the semiconductor substrate have the same layer and the same material, and have an integrated structure. In this way, the above-mentioned capacitor and field effect transistor can be fabricated in different regions on the same semiconductor substrate.
  • the P-type transistor substrate is disposed on the semiconductor substrate, and has the same layer and the same material as the P-type well.
  • the above-mentioned P-type doping process can be used to form a P-type well at the position corresponding to the capacitor, and at the same time, the above-mentioned P-type doping process can be used to form a P-type transistor substrate at the position corresponding to the field effect transistor. , so as to achieve the purpose of simplifying the manufacturing process.
  • both the N-type source region and the N-type drain region of the field effect transistor are disposed on the substrate of the P-type transistor.
  • the N-type source region and the N-type drain region are arranged at intervals.
  • the above-mentioned N-type doping process may be used to form an N-type source region and an N-type drain region on the P-type transistor substrate.
  • metal can be used to form the gate, source, and drain of the field effect transistor.
  • the field effect transistor is an N-type transistor.
  • the capacitor substrate further includes a P-type well.
  • the P-type well is located above the N-type well, the surface of the P-type well close to the electrode structure is flush with the first surface, and the rest of the surface is surrounded by the N-type well.
  • the P-type well is in potential floating.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located.
  • the field effect transistor includes: an N-type transistor substrate, a P-type source region and a P-type drain region on the semiconductor substrate.
  • the N-type well can be formed by using the above-mentioned N-type doping process at the position corresponding to the capacitor, and at the same time, the N-type transistor substrate can be formed by the above-mentioned N-type doping process at the position corresponding to the field effect transistor. , so as to achieve the purpose of simplifying the manufacturing process.
  • the P-type source region and the P-type drain region of the field effect transistor are both arranged on the substrate of the N-type transistor.
  • a P-type source region and a P-type drain can be formed on the N-type transistor substrate of the field effect transistor.
  • polar region wherein, the P-type source region and the P-type drain region are arranged at intervals.
  • metal can be used to form the gate, source, and drain of the field effect transistor.
  • the field effect transistor is a P-type transistor.
  • a third aspect of the embodiments of the present application provides an electronic device, including a main board and any radio frequency circuit as described above, at least a part of the radio frequency circuit is disposed on the main board.
  • the electronic device has the same technical effect as that of the radio frequency circuit provided by the foregoing embodiments, which will not be repeated here.
  • a capacitor may include an electrode structure and a capacitor substrate for carrying the electrode structure.
  • the electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes.
  • the first finger electrodes and the second finger electrodes are alternately arranged.
  • the capacitor substrate includes an N-type well.
  • the N-type well is arranged on the semiconductor substrate of the integrated circuit, and the above-mentioned first finger electrode and the second finger electrode are arranged on the N-type well.
  • the N-type well is at potential floating.
  • the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate.
  • two parasitic capacitors are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and finally achieve The purpose of reducing the parasitic capacitance between the entire capacitor and the semiconductor substrate is conducive to improving the Q value of the capacitor.
  • the capacitor substrate further includes a P-type well. It is arranged between the electrode structure and the N-type well.
  • the P-type well is in potential floating.
  • an N-type well and a P-type well in a floating state are arranged between the first finger electrode and the semiconductor substrate.
  • an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate.
  • the number of parasitic capacitances connected in series between the first finger electrodes and the semiconductor substrate is increased to reduce the value of the parasitic capacitances between the first finger electrodes and the semiconductor substrate.
  • the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased to reduce the capacitance of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and ultimately reduce the entire capacitance and the semiconductor substrate.
  • the purpose of the parasitic capacitance between the substrates is beneficial to improve the Q value of the capacitor.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the N-type well is located.
  • the vertical projection of the electrode structure on the semiconductor substrate is located within the range where the P-type well is located.
  • the capacitor also includes an interconnection structure.
  • One end of the interconnect structure is in contact with the semiconductor substrate, and the other end of the interconnect structure is used for grounding. In this way, the semiconductor substrate can be grounded through the interconnect structure.
  • the interconnection structure includes a P-type semiconductor doped part, a first through hole and a metal part.
  • the P-type semiconductor doped part is disposed on the semiconductor substrate.
  • the P-type semiconductor doping part is used to improve the conductivity between the semiconductor substrate and the first through hole, which is beneficial to signal transmission.
  • the first through hole penetrates through the dielectric layer, and the first end of the first through hole is electrically connected with the P-type semiconductor doped part.
  • the metal part is arranged on the surface of the dielectric layer away from the semiconductor substrate, electrically connected to the second end of the first through hole, and the metal part is used for grounding.
  • the P-type semiconductor doped part is used as one end of the interconnection structure for connecting with the semiconductor substrate. As the other end of the interconnection structure, the metal part is used for grounding.
  • the metal part is made of metal material and has good conductivity, and is used to improve the conductivity of the entire interconnection structure, so that the grounding performance of the semiconductor substrate is good.
  • the interconnection structure is arranged around a circle of the N-type well and connected end to end. In this way, all parts of the semiconductor substrate can be evenly grounded, so that the performance of the capacitor is stable, which is beneficial to provide the Q value of the capacitor.
  • the material of the metal portion is the same as that of the first finger electrode or the second finger electrode. In this way, the fabrication of the metal part can be completed while fabricating the first finger-shaped electrode or the second finger-shaped electrode, so as to achieve the purpose of briefly describing the fabrication process.
  • Fig. 1 is a kind of structural representation of the electronic equipment of the present application
  • Fig. 2 is a kind of structural representation of the radio frequency circuit in Fig. 1;
  • Fig. 3 is another schematic structural diagram of the radio frequency circuit in Fig. 1;
  • FIG. 4A is a schematic structural diagram of the impedance matching network in FIG. 2 or FIG. 3;
  • Fig. 4B is another schematic structural diagram of the impedance matching network in Fig. 2 or Fig. 3;
  • Fig. 4C is another schematic structural diagram of the impedance matching network in Fig. 2 or Fig. 3;
  • FIG. 5A is a schematic structural diagram of a capacitor provided in an embodiment of the present application.
  • FIG. 5B is a structural schematic diagram of a battery structure in a capacitor provided in an embodiment of the present application.
  • Figure 5C is a cross-sectional view obtained by cutting along the dotted line O-O in Figure 5B;
  • FIG. 6 is a schematic structural view of the electrode structure in the battery structure provided in the embodiment of the present application.
  • FIG. 7A is another structural schematic diagram of a capacitor provided in the embodiment of the present application.
  • Figure 7B is a cross-sectional view obtained by cutting along the dotted line F-F in Figure 7A;
  • Figure 7C is a top view obtained along the B direction in Figure 7B;
  • FIG. 8A is a schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application.
  • FIG. 8B is another schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application.
  • FIG. 9A is another schematic structural diagram of a capacitor provided in the embodiment of the present application.
  • Fig. 9B is a cross-sectional view obtained by cutting along the dotted line E-E in Fig. 9A;
  • Figure 9C is a top view obtained along the D direction in Figure 9B;
  • FIG. 10 is another schematic diagram of a parasitic capacitance in a capacitor provided by an embodiment of the present application.
  • FIG. 11A is a graph of the capacitance value of a capacitor according to the variation of the signal frequency according to the embodiment of the present application.
  • FIG. 11B is a graph showing the Q value of a capacitor changing with the signal frequency according to the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an electrical connection between a power amplifier and an impedance matching network provided in an embodiment of the present application
  • FIG. 13A is a schematic structural diagram of at least a part of the MOS in FIG. 12 and at least a part of the capacitance in the impedance matching network being arranged on the same layer;
  • FIG. 13B is a schematic structural diagram of the MOS shown in FIG. 12 being arranged on the same layer as at least a part of the capacitance in the impedance matching network.
  • first”, second, etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • orientation terms such as “upper” and “lower” may include, but are not limited to, definitions relative to the schematic placement orientations of components in the drawings. It should be understood that these directional terms may be relative concepts, They are used for description and clarification relative to, which may change accordingly according to changes in the orientation in which parts of the figures are placed in the figures.
  • connection should be understood in a broad sense, for example, “connection” can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • An embodiment of the present application provides an electronic device, which may include a tablet computer (pad), a notebook (for example, ultra-thin or portable), a mobile phone (mobile phone), a smart watch, a wireless charging electric vehicle, a wireless charging household small Electrical appliances (such as soybean milk machines, sweeping robots), etc., electronic products with wireless signal transmission function.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • the electronic device 01 is a mobile phone as shown in FIG. 1 as an example.
  • the above-mentioned electronic device 01 mainly but not limited to includes a display module 10 , a middle frame 11 , a rear case 12 and a main board 13 .
  • the main board 13 may be a printed circuit board (printed circuit board, PCB).
  • the above-mentioned display module 10 may include a display screen.
  • the display screen may be a liquid crystal display (liquid crystal display, LCD) screen, or may be an organic light emitting diode (organic light emitting diode, OLED) display screen, or may be a micro LED display screen, or may be a
  • the mini LED display is not limited in this application.
  • the display module 10 and the casing 12 are respectively located on two sides of the middle frame 11 .
  • the main board 13 is disposed on the surface of the middle frame 11 near the housing 12 . After the middle frame 11 and the rear case 12 are fastened together, an accommodating cavity for accommodating internal components such as the motherboard 13 and the antenna can be formed.
  • the electronic device 01 may also include a radio frequency circuit 20 as shown in FIG. 02 electrical connections.
  • the embodiment of the present application does not limit the type and arrangement of the antenna 02 .
  • it can be arranged around the main board 13 , or a part of the middle frame 11 can also be shared as the antenna 02 .
  • the radio frequency circuit 20 may include a radio frequency transmitter 200 as shown in FIG. 2 .
  • the antenna 02 can convert the electromagnetic wave sent by the base station into a weak AC signal, and after filtering and high-frequency amplification by the above-mentioned receiving channel 201, send it to the radio frequency transmitter 200 for demodulation, To get the receiving baseband information.
  • the radio frequency transmitter 200 can modulate and convert the transmitted baseband information into a high-frequency signal, which is amplified by the transmission path 202 and then transferred to the electromagnetic board by the antenna 02 for radiation.
  • the receiving path 201 can include a low noise amplifier (low noise amplifier, LNA) 211 as shown in Figure 2, and the transmitting path 202 can include such as
  • the power amplifier (power amplifier, PA) 212 shown in FIG. 2 is used to amplify and process signals.
  • the transmission path 202 may include an integrated circuit, and the integrated circuit may include at least one The impedance matching network 30 is shown.
  • the above-mentioned impedance matching network 30 can be electrically connected to the output terminal a1 of the PA 212 , that is, the impedance matching network 30 is electrically connected between the PA 212 and the antenna 02 .
  • the above-mentioned impedance matching network 30 can be electrically connected to the input terminal a1 of the PA212 .
  • both the input end a1 and the output end b1 of the PA212 are electrically connected to the above-mentioned impedance matching network 30 , which is not limited in this application.
  • the receiving path 201 may include at least one impedance matching network 30 as shown in FIG. 2 .
  • the above-mentioned impedance matching network 30 can be electrically connected to the output end of the LNA 211 , that is, the impedance matching network 30 is electrically connected between the PA 212 and the antenna 02 .
  • the above-mentioned impedance matching network 30 may be electrically connected to the input terminal a2 of the LNA 211 .
  • both the input end a2 and the output end b2 of the LNA 211 are electrically connected to the above-mentioned impedance matching network 30 , which is not limited in this application.
  • the above is to set the impedance matching network 30 on at least one of the output terminal a1 of the PA212 and the input terminal b1 of the PA212.
  • the description will be given as an example in which the impedance matching network 30 is provided at least one of the output end a2 of the LNA 211 and the input end b2 of the LNA 211 .
  • the above-mentioned radio frequency transmitter 200 may also include a filter, and the filter may be set in at least one of the receiving path 201 and the transmitting path 202, or the filter may be set in the above-mentioned antenna Between the switch and the antenna 02. In this case, at least one of the input end and the output end of the filter may be electrically connected to the impedance matching network 30 .
  • the above-mentioned impedance matching network 30 may include a capacitor and an inductor electrically connected to the capacitor.
  • the present application does not limit the electrical connection manner of the capacitor and the inductor, and the quantity of the capacitor and the inductor.
  • the impedance matching network 30 may include a capacitor C and an inductor L. As shown in FIG. Wherein, the capacitor C is connected in series with the inductor L. At this time, the impedance matching network 30 can be called an L-type matching network.
  • the impedance matching network 30 may include two capacitors, namely C1 and C2 , and an inductor L. Wherein, the capacitor C1 and the capacitor C2 are connected in parallel, and the inductor L is electrically connected between the capacitor C1 and the capacitor C2. At this time, the impedance matching network 30 may be called a ⁇ -type matching network.
  • the impedance matching network 30 may include two inductors, namely L1 and L2 , and a capacitor C. Wherein, the inductor L1 and the inductor L2 are connected in parallel, and the capacitor C is electrically connected between the inductor L1 and the inductor L2. At this time, the impedance matching network 30 may be called a T-type matching network.
  • the above-mentioned impedance matching network 30 may also include a signal source resistor R opt and a load resistor RL as shown in FIG. 4A , FIG. 4B and FIG. 4C .
  • the signal source resistance R opt may be the resistance of the radio frequency transceiver 200
  • the load resistance RL may be the resistance of the antenna.
  • the above is an illustration of the quantity and connection mode of the capacitors and inductors in the impedance matching network 30 , and other configuration methods of the capacitors and inductors will not be repeated here.
  • the present application does not limit the structure of the impedance matching network 30 , as long as the impedance matching network 30 can be guaranteed to have capacitance, those skilled in the art can select the type of the impedance matching network 30 according to needs.
  • the Q value of the above capacitor will affect the impedance matching performance of the impedance matching network 30 , and further affect the conversion rate of the electrical signal when the electronic device 01 transmits the signal.
  • the lower the Q value of the capacitor in the impedance matching network 30 the greater the attenuation of the high-frequency circuit signal by the capacitor, which will reduce the performance of the impedance matching network, increase the reflection of the signal at the load end, and reduce the conversion rate of the electrical signal.
  • the embodiment of the present application provides a capacitor, and the capacitor may have a relatively high Q value. The structure of the capacitor will be described in detail below with an example.
  • the capacitors in the impedance matching network 30 may use metal-oxide-metal (metal oxide metal, MOM) capacitors with relatively high capacitance density.
  • MOM capacitor C (hereinafter referred to as capacitor C) may include an electrode structure 401 and a capacitor substrate 41 as shown in FIG. 5A . Wherein, the electrode structure 401 is disposed above the capacitor substrate 41 .
  • the above capacitor may further include an insulating layer 400 .
  • the above-mentioned electrode structure 401 is disposed in the insulating layer 400 , and the electrode structure 401 may include a plurality of electrically connected first finger electrodes 4011 and a plurality of electrically connected second finger electrodes 4012 .
  • the first finger electrodes 4011 and the second finger electrodes 4012 are alternately arranged, and adjacent first finger electrodes 4011 and second finger electrodes 4012 are separated by part of the material of the insulating layer 400, so that the first The finger electrodes 4011 and the second finger electrodes 4012 are insulated.
  • the capacitance value in the MOM capacitor may be the sum of the capacitance values formed between every adjacent first finger electrode 4011 and second finger electrode 4012 in the same layer.
  • the first finger electrode 4011 and the second finger electrode 4012 may be on the same layer and arranged in parallel. Arranging the first finger electrodes 4011 and the second finger electrodes 4012 in parallel means that the strip-shaped first finger electrodes 4011 and the strip-shaped second finger electrodes 4012 may extend in the same direction, for example, both extend along the X direction.
  • the "same-layer arrangement" in the embodiment of the present application refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the electrode structure 401 further includes a first interconnection electrode 402 and a second interconnection electrode 402 as shown in FIG. 5A.
  • Two interconnect electrodes 403 the plurality of first finger electrodes 4011 may be arranged vertically on the same layer as the first interconnect electrodes 402 .
  • the first finger electrodes 4011 may extend along the X direction
  • the first interconnect electrodes 402 may extend along the Y direction.
  • the above-mentioned X direction and Y direction are perpendicular, and the plane where the X direction and Y direction lie may be parallel to the bearing surface of the capacitor substrate 41 facing the electrode structure 401 .
  • the multiple first finger electrodes 4011 are connected to the first interconnect electrodes 402 as an integral structure, so that the first interconnect electrodes 402 can be directly electrically connected to the multiple first finger electrodes 4011 .
  • a plurality of second finger electrodes 4012 and the second interconnect electrodes 403 are arranged vertically on the same layer.
  • the second finger electrodes 4012 may extend along the X direction
  • the second interconnect electrodes 403 may extend along the Y direction.
  • the multiple second finger electrodes 4012 are connected with the second interconnection electrodes 403 as an integral structure, so that the second interconnection electrodes 403 can be directly electrically connected to the multiple second finger electrodes 4012 .
  • first finger electrodes 4011, multiple second finger electrodes 4012, first interconnect electrodes 402, and second interconnect electrodes 403 may be in the same layer. Material.
  • the first finger electrode 4011 , the second finger electrode 4012 , the first interconnection electrode 402 and the second interconnection electrode 403 can be formed simultaneously by using the above-mentioned one-time communication process.
  • the capacitor C in order to increase the capacitance value of the capacitor C, may include a plurality of electrode structures 401 as shown in FIG. 5B .
  • the plurality of electrode structures 401 can be stacked.
  • the above-mentioned capacitance C may also include As shown in the cross-sectional view obtained by cutting along the dotted line O-O), at least a part of the second through hole 404 and the third through hole 405 penetrate through the insulating layer 400 .
  • the first finger electrodes 4011 in the plurality of electrode structures 401 are all electrically connected to the second through holes 404 .
  • the second finger electrodes 4012 in the plurality of electrode structures are all electrically connected to the third through holes 405 .
  • the connection can increase the overlapping area between the two plates in the capacitor C, thereby achieving the purpose of increasing the capacitance value of the capacitor C.
  • the manufacturing process of the second through hole 404 and the third through hole 405 may be: etching the insulating layer 400 to form a via hole, and then filling the via hole with a metal material through electroplating or other processes, and finally forming a via hole with The second through hole 404 and the third through hole 405 are electrically conductive.
  • the first finger electrode 4011 and the second finger electrode 4012 may be in different layers and arranged vertically.
  • the perpendicular arrangement of the first finger-shaped electrodes 4011 and the second finger-shaped electrodes 4012 means that the extending directions of the strip-shaped first finger-shaped electrodes 4011 and the strip-shaped second finger-shaped electrodes 4012 may be different.
  • the first finger electrodes 4011 may extend along the X direction
  • the second finger electrodes 4012 may extend along the Y direction.
  • first finger electrode 4011 and the second finger electrode 4012 in different layers means that the first finger electrode 4011 and the second finger electrode 4012 respectively adopt two manufacturing processes (each manufacturing process may include film forming process and patterning process).
  • An interconnection electrode 402 is arranged vertically on the same layer and connected to form an integrated structure.
  • a plurality of second finger electrodes 4012 and the electrodes of the second interconnection 403 are arranged vertically on the same layer, and are connected to form an integrated structure.
  • the capacitor C can be provided with multiple layers of electrode structures 401 as shown in FIG.
  • the electrical connection between the second finger electrodes 4012 is the same as that described above, and will not be repeated here.
  • the following descriptions are made by taking the capacitor C including a layer of electrode structure 401 as shown in FIG. 5A as an example.
  • the capacitor C may further include a dielectric layer 42 as shown in FIG. 7A .
  • the dielectric layer 42 may be located between the electrode structure 401 and the semiconductor substrate 410 .
  • the dielectric layer 42 may be in contact with the electrode structure 401 and the first surface A of the semiconductor substrate 410 , thereby separating the electrode structure 401 from the semiconductor substrate 410 .
  • the structure of the capacitor substrate 41 will be illustrated in detail below.
  • the capacitor substrate 41 may include an N-type well 411 .
  • the material constituting the semiconductor substrate 410 may be silicon (Si), in this case, the semiconductor substrate 410 may be called a silicon substrate.
  • the above-mentioned semiconductor substrate 410 has a first surface A, and the electrode structure 401 may be disposed on a side where the first surface A is located.
  • an N-type well 411 is disposed on the semiconductor substrate 410 .
  • the surface of the N-type well 411 close to the electrode structure 401 can be flush with the first surface A, and the rest of the surface is covered by the semiconductor substrate. 410 , at this time, the N-type well 411 is located between the semiconductor substrate 410 and the electrode structure 401 .
  • the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located within the range where the N-type well 411 is located.
  • it is beneficial to increase the relative area between the first finger electrode 4011 and the N-type well 411 in the electrode structure 401 making it easier to form parasitic capacitance between the first finger electrode 4011 and the N-type well 411 .
  • it is beneficial to increase the relative area between the second finger electrode 4012 and the N-type well 411 in the electrode structure 401 making it easier to form parasitic capacitance between the second finger electrode 4012 and the N-type well 411 .
  • a pentavalent dielectric element such as phosphorus or arsenic
  • the N-type doping process can be doped on the semiconductor substrate 410 corresponding to the ion doping process, and the above-mentioned N-type well 411 .
  • the electrode structure 401 can be formed directly above the N-type well 411, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located at the N-type well 410. within the range where the type well 411 is located.
  • the N-type well 411 may be in a floating potential, that is, the N-type well 411 is not connected to a potential.
  • the semiconductor substrate may be grounded 410 .
  • the capacitor C may further include an interconnection structure 43 as shown in FIG. 7C . One end of the interconnection structure 43 may be in contact with the semiconductor substrate 410 , and the other end of the interconnection structure 43 is used for grounding.
  • the interconnection structure 43 may include a P-type semiconductor doped part 431 , a first through hole 432 and a metal part 433 connected in sequence.
  • the P-type semiconductor doped part 431 may be located on the semiconductor substrate 410 to serve as one end of the interconnection structure 43 for contacting the semiconductor substrate 410 .
  • the P-type semiconductor doped part 431 may be located on the semiconductor substrate 410 means that the surface of the P-type semiconductor doped part 431 close to the electrode structure 401 is flush with the first surface A, and the remaining surfaces are surrounded by the semiconductor substrate 410 .
  • a trivalent dielectric element hereinafter referred to as the P-type doping process
  • boron or gallium can be doped on the semiconductor substrate 410 correspondingly through an ion doping process.
  • the aforementioned P-type semiconductor doped portion 431 is formed.
  • the first through hole 432 may penetrate through the dielectric layer 42 .
  • a first end of the first through hole 432 close to the P-type semiconductor doped portion 431 is in contact with the P-type semiconductor doped portion 431 to be electrically connected to the P-type semiconductor doped portion 431 .
  • the manufacturing method of the first through hole 432 is similar to the manufacturing method of the second through hole 404 and the third through hole 405 mentioned above, and will not be repeated here.
  • the metal part 433 may be disposed on a surface of the dielectric layer 42 away from the semiconductor substrate 410 .
  • the metal portion 433 may be electrically connected to the second end of the first through hole 432 away from the P-type semiconductor doped portion 431 .
  • the metal portion 433 is used as a conductor for grounding, so that the semiconductor substrate 410 can be grounded through the interconnection structure 43 .
  • the metal part 433 may be in the same layer and material as the first finger electrode 4011 and the second finger electrode 4012 (as shown in FIG. 5A ) in the electrode structure 401 . In this way, the same patterning process can be used to complete the preparation of the metal part 433 while manufacturing the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401 , thereby simplifying the manufacturing process.
  • the interconnection structure 43 may be arranged around the N-type well 411 and connected end to end. In this way, all parts of the semiconductor substrate 410 can be evenly grounded, so that the performance of the capacitor C is stable, which is beneficial to provide the Q value of the capacitor C.
  • the capacitor C in the impedance matching network 30 may include a capacitor substrate 41 and an electrode structure 401 disposed above the capacitor substrate 41 as shown in FIG. 5A .
  • the capacitor substrate includes an N-type well 411 on the semiconductor substrate 410 .
  • the N-type well 411 is at a floating potential, and the semiconductor substrate 410 may be grounded.
  • the vertical projection of the electrode structure 401 on the semiconductor substrate 410 in the electrode structure 401 is located within the range where the N-type well 411 is located.
  • the electrode structure 401 may include a first finger electrode 4011 and a second finger electrode 4012, so an N-type electrode in a floating state is provided between the first finger electrode 4011 and the grounded semiconductor substrate 410.
  • Well 411 there may be a parasitic capacitance C11 between the first finger electrode 4011 and the N-type well 411 as shown in FIG. 8A .
  • C12 there is a parasitic capacitance C12 between the N-type well 411 below the first finger electrode 4011 and the semiconductor substrate 410 .
  • an N-type well 411 in a floating state is provided between the second finger electrode 4012 and the grounded semiconductor substrate 410 .
  • parasitic capacitance C21 between the second finger electrode 4012 and the N-type well 411 as shown in FIG. 8A .
  • parasitic capacitance C22 between the N-type well 411 below the second finger electrode 4012 and the semiconductor substrate 410 .
  • a parasitic capacitance C11 and a parasitic capacitance C12 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410 . If the above-mentioned N-type well 411 is grounded, then the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitors connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitor between the first finger electrode 4011 and the semiconductor substrate 410. value.
  • a parasitic capacitance C21 and a parasitic capacitance C22 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410 . If the above-mentioned N-type well 411 is grounded, then the second finger electrode 4012 and the semiconductor substrate 410 have only one parasitic capacitance C20 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrodes 4012 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitances between the second finger electrodes 4012 and the semiconductor substrate 410. Finally, the purpose of reducing the parasitic capacitance between the entire capacitor C and the semiconductor substrate 410 is achieved, thereby improving the Q value of the capacitor C.
  • the capacitor C when the above-mentioned capacitor C is used in the impedance matching network 30, since the capacitor C has a higher Q value, the attenuation of the high-frequency circuit signal by the capacitor C is smaller, which is conducive to improving the performance of the impedance matching network 30. Performance, reduce the reflection of the signal at the load end, and improve the conversion rate of the electrical signal. On the other hand, since the signal reflected by the load end is reduced, the heat converted by the reflected signal will be correspondingly reduced, thereby effectively reducing the probability of temperature rise of the electronic device and improving the life of the electronic device.
  • the capacitance Cm in FIG. 8A is the capacitance formed between the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401 .
  • the resistance Rm is the equivalent resistance of the first finger electrode 4011 and the second finger electrode 4012 .
  • the inductance Lm is the equivalent inductance of the first finger electrode 4011 and the second finger electrode 4012 .
  • the resistance R11 is an equivalent resistance between the N-type well 411 under the first finger electrode 4011 and the semiconductor substrate 410 .
  • the resistance R21 is an equivalent resistance between the N-type well 411 under the second finger electrode 4012 and the semiconductor substrate 410 .
  • an N-type well 411 in a floating state is provided, and between the second finger electrode 4012 and the grounded semiconductor substrate 410 In between, an N-type well 411 in a floating state is provided as an example to illustrate the structure of the capacitor C above.
  • the structure of the capacitor substrate 41 may be as shown in FIG. 9A , and the capacitor substrate 41 includes a semiconductor substrate 410 and an N-type well 411 . Wherein, the arrangement manner of the semiconductor substrate 410 and the N-type well 411 is the same as that described above, and will not be repeated here.
  • the capacitor substrate 41 may further include a P-type well 412 .
  • the P-type well 412 may be disposed between the electrode structure 401 and the N-type well 411 .
  • FIG. 9B the cross-sectional view obtained by cutting along the dotted line E-E in FIG. 9A
  • the surface of the P-type well 412 close to the electrode structure 401 is flush with the first surface A, and the remaining surfaces are surrounded by the N-type well 411.
  • FIG. 9C the top view taken along the D direction in FIG. 9B
  • the vertical projection of the electrode structure on the semiconductor substrate 410 may be located within the range where the P-type well 412 is located.
  • the above-mentioned P-type well 412 can be formed on the N-type well 411 .
  • the electrode structure 401 can be formed directly above the P-type well 412, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located at the P-type well 412. within the range where the type well 412 is located.
  • the P-type well 412 may be located above the N-type well 411 , and the surface of the P-type well 412 close to the electrode structure 401 is flush with the first surface A, and the rest of the surface is surrounded by the N-type well 411 . Therefore, along the direction perpendicular to the capacitor substrate 41 , the thickness of the P-type well 412 is smaller than that of the N-type well 411 , so the N-type well 411 can also be called an N-type deep well.
  • the grounding method of the semiconductor substrate 410 through the interconnection structure 43 is the same as that described above, and will not be repeated here.
  • the above-mentioned P-type well 412 is in a floating potential.
  • an N-type well 411 and a P-type well 412 in a floating state are disposed between the first finger electrode 4011 and the grounded semiconductor substrate 410 .
  • the resistor R31 is an equivalent resistance between the P-type well 412 below the first finger electrode 4011 and the N-type well 411 below the first finger electrode 4011 .
  • the resistance R32 is an equivalent resistance between the P-type well 412 under the first finger electrode 4011 and the semiconductor substrate 410 .
  • an N-type well 411 and a P-type well 412 in a floating state are disposed between the second finger electrode 4012 and the grounded semiconductor substrate 410 .
  • the resistor R41 is an equivalent resistance between the P-type well 412 below the second finger electrode 4012 and the N-type well 411 below the second finger electrode 4012 .
  • the resistance R42 is an equivalent resistance between the P-type well 412 under the second finger electrode 4012 and the semiconductor substrate 410 .
  • a parasitic capacitance C31 , a parasitic capacitance C32 and a parasitic capacitance C33 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410 . It can be seen from the above that if the above-mentioned N-type well 411 is grounded, then the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in FIG. 8B . Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitors connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitor between the first finger electrode 4011 and the semiconductor substrate 410. value.
  • a parasitic capacitance C41 , a parasitic capacitance C42 and a parasitic capacitance C43 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410 .
  • the number of parasitic capacitances connected in series between the second finger electrodes 4012 and the semiconductor substrate 410 is increased to reduce the capacitance of the parasitic capacitances between the second finger electrodes 4012 and the semiconductor substrate 410, and finally reduce The purpose of the parasitic capacitance between the entire capacitor C and the semiconductor substrate 410 is to improve the Q value of the capacitor C.
  • FIG. 11A is a curve of the capacitance value of the capacitor C varying with the frequency of the signal. It can be seen that the capacitance value of the capacitor will vary with the frequency of the signal.
  • the embodiment of the present application adopts the capacitance shown in FIG. 9A , which overlaps with the above-mentioned curve of the capacitance C shown in FIG. 8B which connects the above-mentioned N-type well 411 to ground.
  • the capacitance values of the above two capacitors C are the same.
  • the capacitance values of the above two types of capacitors C may both be 5 GHz.
  • the curve 1 is the variation curve of the Q value of the capacitor C shown in FIG. 9A with the signal frequency according to the embodiment of the present application.
  • Curve 2 is the variation curve of the capacitance C that grounds the above-mentioned N-type well 411 with the signal frequency shown in FIG. 8B . It can be seen that curve 1 is above curve 2. For example, at the node m2 with a signal frequency of 5 GHz, the Q value corresponding to the curve 1 is increased by about 10% compared with the Q value corresponding to the curve 2. Therefore, in the embodiment of the present application, the capacitor C shown in FIG. 9A has a higher Q value.
  • the capacitor C provided by the present application only needs to improve the structure of the capacitor substrate 41 in the capacitor C to achieve the purpose of increasing the Q value of the capacitor C, so it does not increase the difficulty of the manufacturing process. Ease of mass production of products.
  • the impedance matching network 30 having the capacitance C above can be electrically connected to the PA212 or the LNA211 .
  • the above-mentioned PA212 or LNA211 is provided with a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • at least a part of the field effect transistor and at least a part of the capacitor substrate 41 in the capacitor C may be in the same layer and material. Therefore, at least a part of the structure of the capacitor substrate 41 can be prepared while the above-mentioned field effect transistor is prepared by the semiconductor manufacturing process, so as to simplify the process and improve the production efficiency.
  • the PA212 may include a MOS, an isolation DC capacitor Cb, a ground capacitor Cg, and a resistor R connected to the working voltage Vdc.
  • the gate (gate, g) of the MOS is electrically connected to the power supply Vin
  • the first pole a (source area or drain area) of the MOS is used to receive the input electrical signal
  • the second pole b (drain area or source area) of the MOS area) is used to electrically connect with the impedance matching network 30 through the isolation DC capacitor Cb.
  • the above-mentioned PA212 can use the amplification state of the MOS to amplify the input electrical signal, and transmit it to the impedance matching network 30 through the isolation DC capacitor Cb.
  • An example will be given below to explain how a part of the MOS is arranged in the same layer and with the same material as part of the structure of the capacitor substrate 41 in the capacitor C.
  • the MOS may include a P-type transistor substrate 52, an N-type source (source, s) region 53 and an N-type drain (drain, d) region disposed on the semiconductor substrate 410. 54.
  • the above-mentioned capacitor C and MOS can be fabricated in different regions on the same semiconductor substrate, so as to integrate the above-mentioned MOS into an integrated circuit.
  • the P-type transistor substrate 52 is disposed on the semiconductor substrate 410 and has the same layer and material as the P-type well 412 in the capacitor substrate 41 of the capacitor C.
  • the P-type well 412 can be formed by using the above-mentioned P-type doping process at the position corresponding to the capacitor C, and at the same time, the P-type transistor lining can be formed at the position corresponding to the MOS by using the above-mentioned P-type doping process. Bottom 52, so as to achieve the purpose of simplifying the manufacturing process.
  • both the N-type source region 53 and the N-type drain region 54 of the MOS are disposed on the P-type transistor substrate 52 .
  • the N-type source region 53 and the N-type drain region 54 are arranged at intervals.
  • the above-mentioned N-type doping process can be used to form an N-type source region 53 and an N-type drain region 54 on the P-type transistor substrate 52 .
  • metal can be used to form the gate g, source s, and drain d of the MOS.
  • the MOS is an N-type transistor.
  • the via hole 55 used to electrically connect the source s and the drain d to the N-type source region 53 and the N-type drain region 54 in the MOS can be used to connect the capacitor C
  • the first through hole 432 of the interconnection structure 43 is formed by the same patterning process.
  • the MOS is an N-type transistor, and at least a part of the field effect transistor can be in the same layer and material as at least a part of the capacitor substrate 41 in the capacitor C.
  • the above-mentioned MOS may also be a P-type transistor.
  • the field effect transistor includes an N-type transistor substrate 56 , a P-type source region 57 and a P-type drain region 58 disposed on a semiconductor substrate 410 .
  • the N-type transistor substrate 56 is disposed on the semiconductor substrate 410 and has the same layer and material as the N-type well 411 in the capacitor substrate 41 of the capacitor C.
  • the semiconductor substrate 410 such as a Si substrate
  • the N-type well 411 can be formed by using the above-mentioned N-type doping process at the position corresponding to the capacitor C, and at the same time, the above-mentioned N-type doping process can be used at the position corresponding to the MOS.
  • An N-type transistor substrate 56 is formed to achieve the purpose of simplifying the manufacturing process.
  • both the P-type source region 57 and the P-type drain region 58 of the MOS are disposed on the N-type transistor substrate 56 .
  • the P-type well 412 is formed on the N-type well 411 of the capacitor C by using the above-mentioned P-type doping process
  • a P-type source region 57 and a P-type source region 57 can be formed on the N-type transistor substrate 56 of the MOS. type drain region 58 .
  • the P-type source region 57 and the P-type drain region 58 are arranged at intervals.
  • MOS is a P-type transistor.
  • the above description is based on an example that at least a part of the field effect transistor in the PA212 and at least a part of the capacitor substrate 41 in the capacitor C can be of the same layer and material.
  • the fabrication method of at least a part of the field effect transistor in the LNA 211 in the radio frequency circuit 20 and at least a part of the capacitor substrate 41 in the capacitor C is the same as that described above, and will not be repeated here.
  • the above description is made by taking the capacitor C in the impedance matching network 30 as an example.
  • the capacitor C provided in the embodiment of the present application can be applied not only to the impedance matching network 30 but also to other circuit structures in the radio frequency circuit 20, such as a digital-to-analog converter, an analog-to-digital converter, and the like. Or it can also be applied to other circuits with capacitance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Les modes de réalisation selon la présente invention se rapportent au champ technique des semi-conducteurs, et servent à améliorer une valeur Q d'un condensateur, de sorte que la performance d'un réseau de concordance d'impédance ayant le condensateur est également améliorée. L'invention concerne un condensateur, un circuit intégré, un circuit à radiofréquence et un dispositif électronique. Un condensateur dans un réseau de concordance d'impédance du circuit intégré comprend une structure d'électrodes et un substrat de condensateur. La structure d'électrodes comprend une pluralité de premières électrodes-doigts, lesquelles sont connectées électriquement, et une pluralité de deuxièmes électrodes-doigts, lesquelles sont connectées électriquement. Les premières électrodes-doigts et les deuxièmes électrodes-doigts sont agencées en quinconce. Un puits de type n est agencé sur un substrat semi-conducteur, et les premières électrodes-doigts et les deuxièmes électrodes-doigts sont agencées au-dessus du puits de type n. Le puits de type n est flottant dans le potentiel électrique.
PCT/CN2021/102445 2021-06-25 2021-06-25 Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique WO2022267025A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/102445 WO2022267025A1 (fr) 2021-06-25 2021-06-25 Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique
CN202180099523.4A CN117501430A (zh) 2021-06-25 2021-06-25 一种电容、集成电路、射频电路以及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/102445 WO2022267025A1 (fr) 2021-06-25 2021-06-25 Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique

Publications (1)

Publication Number Publication Date
WO2022267025A1 true WO2022267025A1 (fr) 2022-12-29

Family

ID=84545085

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/102445 WO2022267025A1 (fr) 2021-06-25 2021-06-25 Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique

Country Status (2)

Country Link
CN (1) CN117501430A (fr)
WO (1) WO2022267025A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080111598A1 (en) * 2006-11-14 2008-05-15 Nec Electronics Corporation Charge pump circuit with reduced parasitic capacitance
CN105632889A (zh) * 2014-11-04 2016-06-01 北大方正集团有限公司 电容的制作方法、电容和电容组件
CN106411136A (zh) * 2016-08-25 2017-02-15 浙江大学 一种隔离型功率变换器基于高压电容耦合的控制芯片

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080111598A1 (en) * 2006-11-14 2008-05-15 Nec Electronics Corporation Charge pump circuit with reduced parasitic capacitance
CN105632889A (zh) * 2014-11-04 2016-06-01 北大方正集团有限公司 电容的制作方法、电容和电容组件
CN106411136A (zh) * 2016-08-25 2017-02-15 浙江大学 一种隔离型功率变换器基于高压电容耦合的控制芯片

Also Published As

Publication number Publication date
CN117501430A (zh) 2024-02-02

Similar Documents

Publication Publication Date Title
US10269729B2 (en) Semiconductor packages having wire bond wall to reduce coupling
JP5812234B1 (ja) 可変容量デバイス
US9401342B2 (en) Semiconductor package having wire bond wall to reduce coupling
US8581799B2 (en) Ground radiation antenna
US11862834B2 (en) Distributed LC filter structure
US9281557B2 (en) Multi bandwidth balun and circuit structure thereof
US10916938B2 (en) ESD-protective surface-mount composite component
CN101499785A (zh) 设置有功率放大器的高频模块
US20140202750A1 (en) Multilayer substrate module
CN1605135A (zh) 滤波电路
JP2015133660A (ja) 集積回路及び送受信装置
CN105141262A (zh) 一种适用于f类或逆f类功率放大器的放大模块
US6392298B1 (en) Functional lid for RF power package
WO2022267025A1 (fr) Condensateur, circuit intégré, circuit à radiofréquence et dispositif électronique
KR100887140B1 (ko) 캐패시터 내장형 다층 세라믹 기판
CN103138705A (zh) 一种带通滤波器
CN106329052A (zh) 一种功率分配器
JP2000049554A (ja) ローパスフィルタおよび回路基板
JP2008263077A (ja) 半導体装置および電子装置
CN218867104U (zh) 异构封装基板和模组
US20220254717A1 (en) Semiconductor Device And Manufacturing Method Therefor
CN110752195A (zh) 射频功率芯片封装结构
CN116093084A (zh) 一种转接板结构及其形成方法
KR20210096623A (ko) 고주파 파워 트랜지스터 및 고주파 파워 앰프
TW202332128A (zh) 可攜式電子裝置及其具有發光功能的天線模組

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21946518

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180099523.4

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE