CN117501430A

CN117501430A - Capacitor, integrated circuit, radio frequency circuit and electronic equipment

Info

Publication number: CN117501430A
Application number: CN202180099523.4A
Authority: CN
Inventors: 王邦麟; 王生荣; 童庆强
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2024-02-02
Also published as: WO2022267025A1

Abstract

The embodiment of the application provides a capacitor, an integrated circuit, a radio frequency circuit and electronic equipment, relates to the technical field of semiconductors, and is used for improving the Q value of the capacitor, so that the performance of an impedance matching network with the capacitor can be improved. The capacitor in the impedance matching network of the integrated circuit includes an electrode structure and a capacitor substrate. The electrode structure comprises a plurality of first finger electrodes which are electrically connected and a plurality of second finger electrodes which are electrically connected, and the first finger electrodes and the second finger electrodes are arranged in a staggered mode. The N-type well is arranged on the semiconductor substrate, and the first finger electrode and the second finger electrode are arranged on the N-type well. The N-type well is at potential float.

Description

Capacitor, integrated circuit, radio frequency circuit and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a capacitor, an integrated circuit, a radio frequency circuit, and an electronic device.

Background

With the development of wireless communication technology, in order to improve the efficiency of signal transmission of electronic devices, an impedance matching network (impedance matching network) may be disposed on a signal transmission line in the electronic device. Through the impedance matching network, impedance conjugate matching, short for impedance matching, can be achieved between the signal sources connected to the two ends of the transmission line and the load. Therefore, the high-frequency signals radiated by the signal source can be almost transmitted to the load after passing through the transmission line, so that the probability of reflecting the signals back to the signal source is reduced.

However, at present, due to the limited Q value of the capacitor, the high-frequency signal is greatly attenuated after passing through the impedance matching network, so that the performance of the impedance matching network is reduced.

Disclosure of Invention

The embodiment of the application provides a capacitor, an integrated circuit, a radio frequency circuit and electronic equipment, which are used for improving the Q value of the capacitor, so that the performance of an impedance matching network with the capacitor can be improved.

In order to achieve the above purpose, the present application adopts the following technical scheme:

in a first aspect of embodiments of the present application, an integrated circuit is provided that may be fabricated within a chip. The integrated circuit includes an impedance matching network. The impedance matching network may include a capacitor and an inductor electrically connected to the capacitor. The capacitor may include an electrode structure and a capacitor substrate for carrying the electrode structure. The electrode structure comprises a plurality of first finger electrodes electrically connected and a plurality of second finger electrodes electrically connected; the first finger electrodes and the second finger electrodes are staggered. The capacitive substrate includes an N-type well. The N-type well is arranged on the semiconductor substrate of the integrated circuit, and the first finger electrode and the second finger electrode are arranged on the N-type well. In addition, the N-type well is at potential float.

As described above, an N-type well in which the potential floats is provided between the first finger electrode and the semiconductor substrate. Thus, the first finger electrode may have a parasitic capacitance with the N-well. In addition, a parasitic capacitance is provided between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well having a floating potential is provided between the second finger electrode and the semiconductor substrate. The second finger electrode may have a parasitic capacitance with the N-type well. Parasitic capacitance is arranged between the N-type well below the second finger electrode and the semiconductor substrate. In this case, two parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the quantity of the parasitic capacitance connected in series between the first finger electrode and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the first finger electrode and the semiconductor substrate is reduced. Similarly, two parasitic capacitances are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the number of the parasitic capacitances connected in series between the second finger electrodes and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the second finger electrodes and the semiconductor substrate is reduced, and finally the purpose of reducing the parasitic capacitance between the whole capacitance and the semiconductor substrate is achieved, thereby being beneficial to improving the Q value of the capacitance. On the one hand, when the capacitor is adopted in the impedance matching network, the capacitor has a higher Q value, so that the smaller the attenuation of the capacitor to the high-frequency circuit signal is, the performance of the impedance matching network is improved, the reflection of the load-end signal is reduced, and the conversion rate of the electric signal is improved. On the other hand, as the signal reflected by the load end is reduced, the heat converted by the reflected signal is correspondingly reduced, so that the probability of temperature rise of the electronic equipment can be effectively reduced, and the service life of the electronic equipment is prolonged.

Optionally, the capacitive substrate further includes a P-well. Is disposed between the electrode structure and the N-well. The P-type well is at potential float. In this case, an N-type well and a P-type well in a floating state are provided between the first finger electrode and the semiconductor substrate. Thus, the first finger electrode may have a parasitic capacitance with the P-well. In addition, parasitic capacitance exists between the P-type well below the first finger electrode and the N-type well below the first finger electrode. A parasitic capacitance is provided between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate. Thus, the second finger electrode may have a parasitic capacitance with the P-well. In addition, parasitic capacitance exists between the P-type well below the second finger electrode and the N-type well below the second finger electrode. Parasitic capacitance is arranged between the N-type well below the second finger electrode and the semiconductor substrate. In this case, three parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the quantity of the parasitic capacitance connected in series between the first finger electrode and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the first finger electrode and the semiconductor substrate is reduced. Similarly, three parasitic capacitances are connected in series between the second finger electrode and the semiconductor substrate. The number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate is increased in a similar way, so that the capacitance value of the parasitic capacitance between the second finger electrode and the semiconductor substrate is reduced, and finally the purpose of reducing the parasitic capacitance between the whole capacitance and the semiconductor substrate is achieved, thereby being beneficial to improving the Q value of the capacitance, and further improving the performance of an impedance matching network with the capacitance.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range of the N-type well. In this way, the relative area between the first finger electrode and the N-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the N-type well. Similarly, the relative area between the second finger electrode and the N-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the second finger electrode and the N-type well.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located in the range of the P-type well. In this way, the relative area between the first finger electrode and the P-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the P-type well. Similarly, the relative area between the second finger electrode and the P-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the second finger electrode and the P-type well.

Optionally, the capacitor further comprises an interconnect structure. One end of the interconnection structure is contacted with the semiconductor substrate, and the other end of the interconnection structure is used for grounding. In this way, the semiconductor substrate may be grounded through the interconnect structure.

Optionally, the interconnection structure includes a P-type semiconductor doped portion, a first via, and a metal portion. The P-type semiconductor doping part is arranged on the semiconductor substrate. The P-type semiconductor doping part is used for improving the conductivity of the semiconductor substrate and the first through hole, and is beneficial to signal transmission. The first end of the first through hole penetrates through the dielectric layer and is electrically connected with the P-type semiconductor doping part. The metal part is arranged on one side surface of the dielectric layer, which is far away from the semiconductor substrate, and is electrically connected with the second end of the first through hole, and the metal part is used for grounding. The P-type semiconductor doped part is used as one end of the interconnection structure for being connected with the semiconductor substrate. The metal part is used as the other end of the interconnection structure for grounding, and is made of metal materials and has good conductivity, so that the conductivity of the whole interconnection structure is improved, and the grounding performance of the semiconductor substrate is good.

Optionally, the interconnection structure is arranged around the circumference of the N-type well and connected end to end. Therefore, the semiconductor substrate can be uniformly grounded everywhere, so that the performance of the capacitor is stable, the Q value of the capacitor is favorably provided, and the performance of the impedance matching network with the capacitor can be improved.

On this basis, the metal part is the same as the first finger electrode or the second finger electrode. Thus, the first finger electrode or the second finger electrode can be manufactured simultaneously, and the metal part can be manufactured simultaneously, so that the purpose of simplifying the manufacturing process is achieved.

Optionally, the electrode structure further comprises a first interconnect electrode and a second interconnect electrode. The plurality of first finger electrodes and the first interconnection electrode are arranged in the same layer and vertically, and are connected into an integral structure. The plurality of second finger electrodes and the second interconnection electrode are arranged in the same layer and vertically, and are connected into an integral structure. The first finger electrode and the second finger electrode are arranged in the same layer and parallel. In this case, the plurality of first finger electrodes, the plurality of second finger electrodes, the first interconnection electrode, and the second interconnection electrode may be the same layer and the same material. Thus, the first finger electrode, the second finger electrode, the first interconnection electrode and the second interconnection electrode can be simultaneously formed by the one-time communication process.

Optionally, the electrode structure further comprises a first interconnect electrode and a second interconnect electrode. The plurality of first finger electrodes and the first interconnection electrode are arranged in the same layer and vertically, and are connected into an integral structure. The plurality of second finger electrodes and the second interconnection electrode are arranged in the same layer and vertically, and are connected into an integral structure. The first finger electrode and the second finger electrode are arranged in different layers and are perpendicular to each other. The first finger electrode and the second finger electrode are also layered to form a capacitance therebetween.

Optionally, the capacitor further includes an insulating layer and a plurality of electrode structures, and the plurality of electrode structures are stacked. The electrode structure is arranged in the insulating layer. The capacitor further includes a second via and a third via extending through at least a portion of the insulating layer. The first finger electrodes in the plurality of electrode structures are electrically connected with the second through holes. The second finger electrodes in the plurality of electrode structures are all electrically connected with the third through holes. In this way, by providing the electrode structure in which the plurality of layers are stacked, and the plurality of first finger electrodes in the electrode structure of different layers are electrically connected to the second through holes, the plurality of second finger electrodes are electrically connected to the third through holes, the capacitance value of the capacitor can be increased.

Optionally, the impedance matching network is an L-type matching network, pi-type matching network, or T-type matching network. The type of impedance matching network may be selected as desired by those skilled in the art.

In a second aspect of embodiments of the present application, a radio frequency circuit is provided. The radio frequency circuit includes a radio frequency transceiver. The radio frequency transceiver is configured to electrically connect with the antenna. The radio frequency circuit further comprises any of the integrated circuits described above. An impedance matching network in the integrated circuit is electrically connected between the radio frequency transceiver and the antenna. The rf circuit has the same technical effects as the impedance matching network provided in the foregoing embodiments, and will not be described herein.

Optionally, the radio frequency circuit further comprises a field effect transistor. The field effect transistor is integrated in the integrated circuit. Thus, the manufacturing of the capacitor part structure can be completed while manufacturing the field effect transistor, thereby being beneficial to simplifying the manufacturing process.

Optionally, the radio frequency circuit further comprises a power amplifier, at least one of an output of the power amplifier and an input of the power amplifier being electrically connected to the impedance matching network. The field effect transistor is arranged in the power amplifier, and at least one part of the field effect transistor and at least one part of the capacitor substrate are made of the same material. Therefore, the manufacturing of the capacitor substrate part structure can be completed while manufacturing the field effect transistor, so that the manufacturing process is facilitated to be simplified.

Optionally, the radio frequency circuit further comprises a low noise amplifier, at least one of an output of the low noise amplifier and an input of the low noise amplifier being electrically connected to the impedance matching network. The field effect transistor is arranged in the low noise amplifier, and at least one part of the field effect transistor and at least one part of the capacitor substrate are made of the same material. Therefore, the manufacturing of the capacitor substrate part structure can be completed while manufacturing the field effect transistor, so that the manufacturing process is facilitated to be simplified.

Optionally, the capacitive substrate further includes a P-well. The P-type well is positioned above the N-type well, the surface of the P-type well, which is close to the electrode structure, is flush with the first surface, and the rest surfaces are surrounded by the N-type well. The P-type well is at potential float. The vertical projection of the electrode structure on the semiconductor substrate is positioned in the range of the P-type well. In this case, the field effect transistor includes: a P-type transistor substrate, an N-type source region, and an N-type drain region on the semiconductor substrate. The semiconductor substrate and the semiconductor substrate are made of the same material and are of an integral structure. Thus, the capacitor and the field effect transistor can be manufactured in different areas on the same semiconductor substrate. In addition, the P-type transistor substrate is arranged on the semiconductor substrate and is made of the same material as the P-type well. Therefore, the P-type doping process is adopted at the position corresponding to the capacitor in the semiconductor substrate to form the P-type well, and the P-type doping process is adopted at the position corresponding to the field effect transistor to form the P-type transistor substrate, so that the purpose of simplifying the manufacturing process is achieved. In addition, the N-type source electrode region and the N-type drain electrode region of the field effect transistor are arranged on the P-type transistor substrate. And the N-type source electrode region and the N-type drain electrode region are arranged at intervals. In this case, after the P-type transistor substrate is fabricated, the N-type source region and the N-type drain region may be formed on the P-type transistor substrate using the N-type doping process. Next, a gate, a source, and a drain of the field effect transistor may be formed using a metal. In this case, the field effect transistor is an N-type transistor.

Optionally, the capacitive substrate further includes a P-well. The P-type well is positioned above the N-type well, the surface of the P-type well, which is close to the electrode structure, is flush with the first surface, and the rest surfaces are surrounded by the N-type well. The P-type well is at potential float. The vertical projection of the electrode structure on the semiconductor substrate is positioned in the range of the P-type well. In this case, the field effect transistor includes: an N-type transistor substrate P-type source region and a P-type drain region are located on the semiconductor substrate. Therefore, the N-type well can be formed in the semiconductor substrate by adopting the N-type doping process at the position corresponding to the capacitor, and the N-type transistor substrate can be formed by adopting the N-type doping process at the position corresponding to the field effect transistor, so that the purpose of simplifying the manufacturing process is achieved. In addition, the P-type source electrode region and the P-type drain electrode region of the field effect transistor are arranged on the N-type transistor substrate. Thus, by adopting the P-type doping process, the P-type source region and the P-type drain region can be formed on the N-type transistor substrate of the field effect transistor while the P-type well is formed on the N-type well of the capacitor. The P-type source electrode region and the P-type drain electrode region are arranged at intervals. Next, a gate, a source, and a drain of the field effect transistor may be formed using a metal. In this case, the field effect transistor is a P-type transistor.

In a third aspect of the embodiments of the present application, an electronic device is provided, including a motherboard and any of the radio frequency circuits described above, where at least a portion of the radio frequency circuits is disposed on the motherboard. The electronic device has the same technical effects as the radio frequency circuit provided in the foregoing embodiment, and will not be described herein.

In a fourth aspect of embodiments of the present application, a capacitor is provided that includes a capacitor substrate that may include an electrode structure and a capacitor for carrying the electrode structure. The electrode structure includes a plurality of electrically connected first finger electrodes and a plurality of electrically connected second finger electrodes. The first finger electrodes and the second finger electrodes are staggered. The capacitive substrate includes an N-type well. The N-type well is arranged on the semiconductor substrate of the integrated circuit, and the first finger electrode and the second finger electrode are arranged on the N-type well. In addition, the N-type well is at potential float.

As described above, an N-type well in which the potential floats is provided between the first finger electrode and the semiconductor substrate. Thus, the first finger electrode may have a parasitic capacitance with the N-well. In addition, a parasitic capacitance is provided between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well having a floating potential is provided between the second finger electrode and the semiconductor substrate. The second finger electrode may have a parasitic capacitance with the N-type well. Parasitic capacitance is arranged between the N-type well below the second finger electrode and the semiconductor substrate. In this case, two parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the quantity of the parasitic capacitance connected in series between the first finger electrode and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the first finger electrode and the semiconductor substrate is reduced. Similarly, two parasitic capacitances are connected in series between the second finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the number of the parasitic capacitances connected in series between the second finger electrodes and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the second finger electrodes and the semiconductor substrate is reduced, and finally the purpose of reducing the parasitic capacitance between the whole capacitance and the semiconductor substrate is achieved, thereby being beneficial to improving the Q value of the capacitance.

Optionally, the capacitive substrate further includes a P-well. Is disposed between the electrode structure and the N-well. The P-type well is at potential float. In this case, an N-type well and a P-type well in a floating state are provided between the first finger electrode and the semiconductor substrate. Thus, the first finger electrode may have a parasitic capacitance with the P-well. In addition, parasitic capacitance exists between the P-type well below the first finger electrode and the N-type well below the first finger electrode. A parasitic capacitance is provided between the N-type well under the first finger electrode and the semiconductor substrate. Similarly, an N-type well and a P-type well in a floating state are arranged between the second finger electrode and the semiconductor substrate. Thus, the second finger electrode may have a parasitic capacitance with the P-well. In addition, parasitic capacitance exists between the P-type well below the second finger electrode and the N-type well below the second finger electrode. Parasitic capacitance is arranged between the N-type well below the second finger electrode and the semiconductor substrate. In this case, three parasitic capacitances are connected in series between the first finger electrode and the semiconductor substrate. Therefore, in the scheme of the embodiment of the application, the quantity of the parasitic capacitance connected in series between the first finger electrode and the semiconductor substrate is increased, so that the capacitance value of the parasitic capacitance between the first finger electrode and the semiconductor substrate is reduced. Similarly, three parasitic capacitances are connected in series between the second finger electrode and the semiconductor substrate. The same way increases the number of parasitic capacitances connected in series between the second finger electrode and the semiconductor substrate, so as to reduce the capacitance value of the parasitic capacitance between the second finger electrode and the semiconductor substrate, and finally achieve the purpose of reducing the parasitic capacitance between the whole capacitance and the semiconductor substrate, thereby being beneficial to improving the Q value of the capacitance.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located within the range of the N-type well. In this way, the relative area between the first finger electrode and the N-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the N-type well. Similarly, the relative area between the second finger electrode and the N-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the N-type well.

Optionally, the vertical projection of the electrode structure on the semiconductor substrate is located in the range of the P-type well. In this way, the relative area between the first finger electrode and the P-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the P-type well. Similarly, the relative area between the second finger electrode and the P-type well in the electrode structure is increased, so that parasitic capacitance is easier to form between the first finger electrode and the P-type well.

Optionally, the interconnection structure is arranged around the circumference of the N-type well and connected end to end. Therefore, the semiconductor substrate can be uniformly grounded everywhere, the performance of the capacitor is stable, and the Q value of the capacitor is favorably provided.

Drawings

FIG. 1 is a schematic structural diagram of an electronic device of the present application;

FIG. 2 is a schematic diagram of the RF circuit of FIG. 1;

FIG. 3 is a schematic diagram of another configuration of the RF circuit of FIG. 1;

FIG. 4A is a schematic diagram of the impedance matching network in FIG. 2 or FIG. 3;

FIG. 4B is a schematic diagram of another structure of the impedance matching network in FIG. 2 or FIG. 3;

FIG. 4C is a schematic diagram of another structure of the impedance matching network in FIG. 2 or FIG. 3;

fig. 5A is a schematic structural diagram of a capacitor according to an embodiment of the present disclosure;

fig. 5B is a schematic structural diagram of a battery structure in a capacitor according to an embodiment of the present disclosure;

FIG. 5C is a cross-sectional view taken along the dashed line O-O in FIG. 5B;

fig. 6 is a schematic structural view of an electrode structure in a battery structure according to an embodiment of the present disclosure;

fig. 7A is a schematic structural diagram of a capacitor according to an embodiment of the present disclosure;

FIG. 7B is a cross-sectional view taken along the dashed line F-F in FIG. 7A;

FIG. 7C is a top view taken along the direction B in FIG. 7B;

FIG. 8A is a schematic diagram of parasitic capacitance in a capacitor according to an embodiment of the present disclosure;

FIG. 8B is a schematic diagram of a parasitic capacitor in a capacitor according to an embodiment of the present disclosure;

Fig. 9A is a schematic diagram of another structure of a capacitor according to an embodiment of the present disclosure;

FIG. 9B is a cross-sectional view taken along the line E-E in FIG. 9A;

FIG. 9C is a top view taken along the direction D in FIG. 9B;

FIG. 10 is another schematic diagram of parasitic capacitance in a capacitor according to an embodiment of the present disclosure;

FIG. 11A is a graph showing a capacitance value of a capacitor according to a signal frequency variation according to an embodiment of the present disclosure;

FIG. 11B is a graph showing the Q value of a capacitor according to the frequency variation of a signal according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electrical connection between a power amplifier and an impedance matching network according to an embodiment of the present disclosure;

FIG. 13A is a schematic diagram of a structure in which at least a portion of the capacitors in the MOS and impedance matching networks of FIG. 12 are co-layered;

fig. 13B is a schematic structural diagram of at least a portion of the capacitors in the MOS and impedance matching network of fig. 12 in a layered arrangement.

Reference numerals:

01-an electronic device; 10-a display module; 11-a middle frame; 12-a rear shell; 13-a main board; 20-radio frequency circuits; 02-an antenna; 200-radio frequency transmitters; 201-receive path; 202-a transmit path; 211-LNA;212-PA; 30-an impedance matching network; 41-a capacitive substrate; 400-an insulating layer; 401-electrode structure; 4011-a first finger electrode; 4012-a second finger electrode; 402-a first interconnect electrode; 403-second interconnect electrode; 404-a second through hole; 405-a third via; 42-a dielectric layer; 410-a semiconductor substrate; 411-N type well; a 43-interconnect structure; 431-P type semiconductor doping part; 432-first through holes; 433-metal part; 412-P-well; a 52-P type transistor substrate; a 53-N type source region; a 54-N type drain region; 55-through holes; a 56-N type transistor substrate; a 57-P type source region; 58-P type drain region.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature.

Furthermore, in this application, directional terms "upper", "lower", etc. may be defined as including, but not limited to, the orientation in which the components are schematically disposed with respect to one another, and it should be understood that these directional terms may be relative terms, which are used for descriptive and clarity with respect to one another, and which may be correspondingly altered with respect to the orientation in which the components are illustrated in the drawings.

In the present application, unless explicitly specified and limited otherwise, the term "coupled" is to be construed broadly, and for example, "coupled" may be either fixedly coupled, detachably coupled, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "electrically connected" may be a direct electrical connection or an indirect electrical connection via an intermediary.

The embodiment of the application provides an electronic device, which may include a tablet personal computer (pad), a notebook (for example, ultrathin or portable), a mobile phone (mobile phone), a smart watch, a wireless charging electric automobile, a wireless charging household small-sized electrical appliance (for example, a soymilk machine, a sweeping robot) and the like, and an electronic product with a wireless signal transmission function. The embodiment of the application does not particularly limit the specific form of the electronic device. For convenience of explanation, the electronic device 01 will be described by taking a mobile phone as shown in fig. 1 as an example.

As shown in fig. 1, the electronic device 01 mainly includes, but is not limited to, a display module 10, a middle frame 11, a rear case 12, and a main board 13. The motherboard 13 may be a printed circuit board (printed circuit board, PCB). The display module 10 may include a display screen. The display screen may be a liquid crystal display (liquid crystal display, LCD) screen, or may be an organic light emitting diode (organic light emitting diode, OLED) display screen, or may be a micro LED display screen, or may be a mini LED display screen, which is not limited in this application. The display module 10 and the housing 12 are respectively located at two sides of the middle frame 11. The main board 13 is disposed on a surface of the middle frame 11 near the side of the housing 12. After the middle frame 11 and the rear case 12 are fastened, a housing cavity for housing internal components such as the motherboard 13 and the antenna may be formed.

Based on this, in order to enable the above-described electronic apparatus 01 to transmit and receive a high-frequency signal through an antenna, the electronic apparatus 01 may further include a radio frequency circuit 20 as shown in fig. 1, and the radio frequency circuit 20 may be electrically connected to the antenna 02 as shown in fig. 2. The type and arrangement of the antenna 02 are not limited in this embodiment. For example, the antenna may be provided around the main board 13, or a part of the center 11 may be shared as the antenna 02.

In some embodiments of the present application, the radio frequency circuit 20 may include a radio frequency transmitter 200 as shown in fig. 2. The radio frequency transmitter 200 may have a receive path 201 and a transmit path 202 between the antenna 02. When the electronic device 01 receives a signal, the antenna 02 may convert an electromagnetic wave sent from the base station into a weak ac signal, filter and amplify the weak ac signal by the receiving path 201, and send the weak ac signal to the radio frequency transmitter 200 for demodulation, so as to obtain receiving baseband information.

In addition, when the electronic device 01 sends a signal, the radio frequency transmitter 200 may modulate and convert the transmitted baseband information into a high frequency signal, amplify the high frequency signal through the above-mentioned transmission path 202, and convert the amplified high frequency signal into an electromagnetic plate by the antenna 02 to radiate the electromagnetic plate. Further, an antenna switch for controlling the transmission and interruption of signals between the signal path and the antenna is provided between the reception path 201, the transmission path 202, and the antenna 02.

As can be seen from the foregoing, the receiving path 201 and the transmitting path 202 need to amplify signals, so the receiving path 201 may include a low noise amplifier (low noise amplifier, LNA) 211 as shown in fig. 2, and the transmitting path 202 may include a Power Amplifier (PA) 212 as shown in fig. 2 to amplify signals.

Based on this, in some embodiments of the present application, to improve the signal transmission efficiency between the input and output terminals in the transmit path 202, the transmit path 202 may include an integrated circuit, which may include at least one impedance matching network 30 as shown in fig. 2. The impedance matching network 30 may be electrically connected to the output a1 of the PA212, i.e., the impedance matching network 30 is electrically connected between the PA212 and the antenna 02. Alternatively, as shown in fig. 3, the impedance matching network 30 may be electrically connected to the input terminal a1 of the PA 212. Alternatively, the impedance matching network 30 may be electrically connected to the input terminal a1 and the output terminal b1 of the PA212, which is not limited in this application.

Similarly, to increase the efficiency of signal transmission between the input and output terminals in the receive path 201, the receive path 201 may include at least one impedance matching network 30 as shown in fig. 2. The impedance matching network 30 may be electrically connected to the output of the LNA211, i.e. the impedance matching network 30 is electrically connected between the PA212 and the antenna 02. Alternatively, as shown in fig. 3, the impedance matching network 30 may be electrically connected to the input terminal a2 of the LNA 211. Alternatively, the impedance matching network 30 is electrically connected to both the input terminal a2 and the output terminal b2 of the LNA211, which is not limited in this application.

It should be noted that, the impedance matching network 30 is disposed at least one of the output terminal a1 of the PA212 and the input terminal b1 of the PA 212. The description is given taking, as an example, the impedance matching network 30 provided at least one of the output terminal a2 of the LNA211 and the input terminal b2 of the LNA 211. In other embodiments of the present application, the radio frequency transmitter 200 may further include a filter, which may be disposed in at least one of the receiving path 201 and the transmitting path 202, or the filter may be disposed between the antenna switch and the antenna 02. In this case, at least one of the input terminal and the output terminal of the filter may be electrically connected to the impedance matching network 30.

The impedance matching network 30 may include a capacitor and an inductor electrically connected to the capacitor. The electrical connection manner of the capacitor and the inductor, and the number of the capacitor and the inductor are not limited. For example, as shown in fig. 4A, the impedance matching network 30 may include a capacitor C and an inductance L. Wherein, the capacitor C is connected in series with the inductor L. At this time, the impedance matching network 30 may be referred to as an L-type matching network.

Alternatively, and as shown in fig. 4B, for example, the impedance matching network 30 may include two capacitors, C1 and C2, and an inductance L. The capacitor C1 and the capacitor C2 are connected in parallel, and are electrically connected between the capacitor C1 and the capacitor C2 with the inductor L. At this time, the impedance matching network 30 may be referred to as pi-type matching network.

Alternatively, as shown in fig. 4C, for another example, the impedance matching network 30 may include two inductors, i.e., L1 and L2, and a capacitor C. The inductor L1 is connected in parallel with the inductor L2, and is electrically connected between the inductor L1 and the inductor L2 with the capacitor C. At this time, the impedance matching network 30 may be referred to as a T-type matching network.

It should be noted that the impedance matching network 30 may further include a signal source resistor R as shown in fig. 4A, 4B, and 4C _opt And a load resistor R _L . For example, in the case where the impedance matching network 30 is electrically connected to the output terminal a1 of the PA212, the signal source resistor R _opt May be the resistance of the radio frequency transceiver 200, the load resistance R _L May be the resistance of the antenna. In addition, the foregoing is an illustration of the number of capacitors and inductors in the impedance matching network 30 and the connection manner, and other arrangement manners of the capacitors and the inductors are not described herein. The structure of the impedance matching network 30 is not limited in this application, as long as the impedance matching network 30 can be ensured to have a capacitor, and a person skilled in the art can select the type of the impedance matching network 30 according to the need.

The Q value of the capacitor affects the impedance matching performance of the impedance matching network 30, and thus affects the conversion rate of the electrical signal when the electronic device 01 transmits a signal. For example, the higher the Q value of the capacitor in the impedance matching network 30, the smaller the attenuation of the capacitor to the high-frequency circuit signal, which is beneficial to improving the performance of the impedance matching network, reducing the reflection of the load-side signal and improving the conversion rate of the electric signal. Conversely, the lower the Q value of the capacitor in the impedance matching network 30, the greater the attenuation of the capacitor to the high frequency circuit signal, which reduces the performance of the impedance matching network, increases the reflection of the load end signal, and reduces the conversion rate of the electrical signal. The embodiment of the application provides a capacitor, which can have a higher Q value. The structure of this capacitor is illustrated in detail below.

In some embodiments of the present application, the capacitance in the impedance matching network 30 may be a metal-oxide-metal (metal oxide metal, MOM) capacitance having a higher capacitance density. The MOM capacitor C (hereinafter referred to as capacitor C) may include an electrode structure 401 and a capacitor substrate 41 as shown in fig. 5A. Wherein the electrode structure 401 is disposed above the capacitive substrate 41.

Specifically, the capacitor may further include an insulating layer 400. The electrode structure 401 is disposed in the insulating layer 400, and the electrode structure 401 may include a plurality of electrically connected first finger electrodes 4011 and a plurality of electrically connected second finger electrodes 4012. The first finger electrodes 4011 and the second finger electrodes 4012 are alternately arranged with adjacent first finger electrodes 4011 and second finger electrodes 4012 being spaced apart from each other by a portion of the material of the insulating layer 400 so as to insulate the first finger electrodes 4011 and the second finger electrodes 4012. The capacitance value in the MOM capacitance may be a sum of capacitance values formed between each adjacent first finger electrode 4011 and second finger electrode 4012 in the same layer.

Further, in some embodiments of the present application, as shown in fig. 5A, the first finger electrodes 4011 may be in the same layer as the second finger electrodes 4012 and disposed in parallel. The first finger electrodes 4011 and the second finger electrodes 4012 are arranged in parallel means that the extending directions of the first finger electrodes 4011 and the second finger electrodes 4012 may be the same, for example, each extending in the X direction.

It should be noted that, the "same layer setting" in the embodiment of the present application refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then using the same mask plate through a one-time patterning process. Depending on the particular pattern, the same patterning process may include multiple exposure, development, or etching processes, and the particular patterns in the formed layer structure may be continuous or discontinuous, and may be at different heights or have different thicknesses.

On this account, in order to electrically connect the plurality of first finger electrodes 4011 and electrically connect the plurality of second finger electrodes 4012, the electrode structure 401 further includes a first interconnect electrode 402 and a second interconnect electrode 403 as shown in fig. 5A. In this case, the plurality of first finger electrodes 4011 may be arranged in the same layer as the first interconnection electrode 402, vertically. For example, the first finger electrode 4011 may extend in the X direction, and the first interconnect electrode 402 may extend in the Y direction. The X direction and the Y direction are perpendicular, and a plane where the X direction and the Y direction are located may be parallel to a carrying surface of the capacitor substrate 41 facing the electrode structure 401. Also, the plurality of first finger electrodes 4011 are connected with the first interconnect electrode 402 as a unitary structure so that the first interconnect electrode 402 can be directly electrically connected with the plurality of first finger electrodes 4011.

Similarly, a plurality of second finger electrodes 4012 are arranged in the same layer as and perpendicular to the second interconnection electrode 403. For example, the second finger electrode 4012 may extend in the X direction, and the second interconnection electrode 403 may extend in the Y direction. And, the plurality of second finger electrodes 4012 are connected to the second interconnection electrode 403 as a unitary structure so that the second interconnection electrode 403 can be directly electrically connected to the plurality of second finger electrodes 4012.

In this case, in the electrode structure 401 shown in fig. 5A, the plurality of first finger electrodes 4011, the plurality of second finger electrodes 4012, the first interconnect electrode 402, and the second interconnect electrode 403 may be the same material. Thus, the first finger electrode 4011, the second finger electrode 4012, the first interconnection electrode 402, and the second interconnection electrode 403 can be simultaneously formed by the one-time communication process.

Furthermore, in some embodiments of the present application, in order to increase the capacitance value of the capacitor C, the capacitor C may include a plurality of the electrode structures 401 as shown in fig. 5B. The plurality of electrode structures 401 may be stacked. In this case, in order to enable the first finger electrodes 4011 of the different layers to be electrically connected, the second finger electrodes 4012 of the plurality of different layers may be electrically connected, and the capacitor C may further include a second through hole 404 and a third through hole 405 penetrating at least a portion of the insulating layer 400 as shown in fig. 5C (a cross-sectional view taken along a broken line O-O in fig. 5B).

Wherein, the first finger electrodes 4011 in the plurality of electrode structures 401 are all electrically connected with the second through holes 404. The second finger electrodes 4012 in the plurality of electrode structures are all electrically connected to the third through hole 405. In this way, by providing the electrode structure 401 in multiple layers, and electrically connecting the first finger electrodes 4011 in different layers through the second through holes 404 and electrically connecting the second finger electrodes 4012 in different layers through the third through holes 405, the overlapping area between the two electrode plates in the capacitor C can be increased, and the purpose of increasing the capacitance value of the capacitor C can be achieved. For example, the manufacturing process of the second through hole 404 and the third through hole 405 may be: a via hole is etched on the insulating layer 400, and then a metal material is filled in the via hole by electroplating or other processes, to finally form a second via hole 404 and a third via hole 405 having conductive properties.

Alternatively, in some embodiments of the present application, as shown in fig. 6, the first finger electrode 4011 may be different from the second finger electrode 4012 in layer and disposed vertically. The first finger electrode 4011 and the second finger electrode 4012 are arranged vertically, which means that the extending directions of the first finger electrode 4011 and the second finger electrode 4012 may be different. For example, the first finger electrode 4011 may extend in the X direction, and the second finger electrode 4012 may extend in the Y direction.

The different layer arrangement of the first finger electrode 4011 and the second finger electrode 4012 means that the first finger electrode 4011 and the second finger electrode 4012 are manufactured by two processes (each process may include a film forming process and a patterning process).

In this regard, similarly, in order to electrically connect the plurality of first finger electrodes 4011 and electrically connect the plurality of second finger electrodes 4012, as shown in fig. 6, the plurality of first finger electrodes 4011 may be arranged in the same layer as the first interconnection electrode 402, vertically, and integrally connected. The plurality of second finger electrodes 4012 are arranged in the same layer as the electrodes of the second interconnect 403, vertically, and are connected as an integral structure.

It should be noted that, when a plurality of layers of electrode structures 401 as shown in fig. 6 may be disposed in the capacitor C, the electrical connection manner between the plurality of first finger electrodes 4011 in the different electrode structures 401 and the electrical connection manner between the plurality of second finger electrodes 4012 in the different electrode structures 401 are the same as described above, and will not be repeated here. For convenience of description, the capacitor C includes a layer of electrode structure 401 as shown in fig. 5A.

In addition, in some embodiments of the present application, the capacitor C may further include a dielectric layer 42 as shown in fig. 7A. The dielectric layer 42 may be located between the electrode structure 401 and the semiconductor substrate 410. Also, the dielectric layer 42 may be in contact with the electrode structure 401 and the first surface a of the semiconductor substrate 410, thereby spacing the electrode structure 401 from the semiconductor substrate 410. The structure of the capacitor substrate 41 will be described in detail below.

For example, in some embodiments of the present application, as shown in fig. 7A, the capacitive substrate 41 may include an N-well 411. The material constituting the semiconductor substrate 410 may be silicon (Si), in which case the semiconductor substrate 410 may be referred to as a silicon substrate. The semiconductor substrate 410 has a first surface a, and the electrode structure 401 may be disposed on a side of the first surface a.

In addition, an N-type well 411 is disposed over the semiconductor substrate 410. As illustrated in fig. 7B (a cross-sectional view taken along a broken line F-F in fig. 7A), a surface of the N-well 411 adjacent to the electrode structure 401 may be flush with the first surface a, and the remaining surface is surrounded by the semiconductor substrate 410, at which time the N-well 411 is located between the semiconductor substrate 410 and the electrode structure 401.

As shown in fig. 7C (a plan view taken along direction B in fig. 7B), the electrode structure 401 is vertically projected on the semiconductor substrate 410 within the N-well 411. In this way, the relative area between the first finger electrode 4011 and the N-well 411 in the electrode structure 401 is advantageously increased, so that parasitic capacitance is more easily formed between the first finger electrode 4011 and the N-well 411. Similarly, the relative area between the second finger electrode 4012 and the N-well 411 in the electrode structure 401 is advantageously increased, so that parasitic capacitance is more easily formed between the second finger electrode 4012 and the N-well 411.

The N-type well 411 may be formed on the semiconductor substrate 410 by doping a pentavalent dielectric element (hereinafter, referred to as an N-type doping process), such as a phosphorus element or an arsenic element, through an ion doping process. Then, in the process of manufacturing the electrode structure 401 on the capacitor substrate 41, the electrode structure 401 may be formed directly above the N-type well 411, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located in the range where the N-type well 411 is located.

On this basis, the N-well 411 may be floating, i.e., the N-well 411 is not connected to a potential. In addition, the semiconductor substrate 410 may be grounded. For example, to ground the semiconductor substrate 410, the capacitor C may further include an interconnect structure 43 as shown in fig. 7C. One end of the interconnect structure 43 may be in contact with the semiconductor substrate 410, and the other end of the interconnect structure 43 is for grounding.

Specifically, as shown in fig. 7B, the interconnection structure 43 may include a P-type semiconductor doped portion 431, a first via 432, and a metal portion 433 that are sequentially connected. In this case, the P-type semiconductor doping portion 431 may be located over the semiconductor substrate 410 as an end of the interconnection structure 43 for contacting with the semiconductor substrate 410.

The P-type semiconductor doped portion 431 may be located on the semiconductor substrate 410, which means that a surface of the P-type semiconductor doped portion 431 close to the electrode structure 401 is flush with the first surface a, and the remaining surfaces are surrounded by the semiconductor substrate 410. The P-type semiconductor doping portion 431 may be formed on the semiconductor substrate 410 by doping a trivalent dielectric element (hereinafter referred to as a P-type doping process), such as boron or gallium, by an ion doping process.

In addition, the first via 432 may penetrate the dielectric layer 42. The first end of the first through hole 432, which is close to the P-type semiconductor doped portion 431, contacts the P-type semiconductor doped portion 431 to be electrically connected with the P-type semiconductor doped portion 431. The manufacturing method of the first through hole 432 is the same as the manufacturing method of the second through hole 404 and the third through hole 405, and will not be described herein.

In addition, the metal portion 433 may be disposed on a surface of the dielectric layer 42 away from the semiconductor substrate 410. The metal portion 433 may be electrically connected to a second end of the first via 432 remote from the P-type semiconductor doping portion 431. The metal portion 433 serves as a conductor for grounding, so that the semiconductor substrate 410 can be grounded through the interconnect structure 43. In some embodiments of the present application, the metal portion 433 may be the same material as the first finger electrode 4011 and the second finger electrode 4012 (shown in fig. 5A) in the electrode structure 401. Thus, the same patterning process can be used to manufacture the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401, and the metal portion 433 can be manufactured at the same time, thereby simplifying the manufacturing process.

In some embodiments of the present application, the interconnect structure 43 may be disposed around a perimeter of the N-well 411 and connected end-to-end as shown in fig. 7C. In this way, the semiconductor substrate 410 can be grounded uniformly, so that the performance of the capacitor C is stable, and the Q value of the capacitor C is advantageously provided.

In summary, as shown in fig. 5A, the capacitor C in the impedance matching network 30 provided in the embodiment of the present application may include a capacitor substrate 41 and an electrode structure 401 disposed above the capacitor substrate 41. The capacitor substrate includes an N-well 411 over the semiconductor substrate 410. Wherein the N-well 411 is at a floating potential, the semiconductor substrate 410 may be grounded. In addition, the vertical projection of the electrode structure 401 in the electrode structure 401 on the semiconductor substrate 410 is located in the range where the N-well 411 is located.

As can be seen from the above, the electrode structure 401 may include the first finger electrode 4011 and the second finger electrode 4012, and thus the N-type well 411 in a floating state is provided between the first finger electrode 4011 and the grounded semiconductor substrate 410. Thus, the first finger electrode 4011 may have a parasitic capacitance C11 with the N-type well 411 as shown in fig. 8A. In addition, a parasitic capacitance C12 is provided between the N-type well 411 under the first finger electrode 4011 and the semiconductor substrate 410. Similarly, an N-well 411 in a floating state is provided between the second finger electrode 4012 and the grounded semiconductor substrate 410. The second finger electrode 4012 may have a parasitic capacitance C21 with the N-type well 411 as shown in fig. 8A. A parasitic capacitance C22 is provided between the N-well 411 under the second finger electrode 4012 and the semiconductor substrate 410.

In this case, a parasitic capacitance C11 and a parasitic capacitance C12 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410. If the N-well 411 is grounded, the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in fig. 8B. The number of parasitic capacitances connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased in the scheme of the embodiment of the present application, so as to reduce the capacitance value of the parasitic capacitance between the first finger electrode 4011 and the semiconductor substrate 410.

Similarly, as shown in fig. 8A, a parasitic capacitance C21 and a parasitic capacitance C22 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410. If the N-well 411 is grounded, the second finger 4012 and the semiconductor substrate 410 have only one parasitic capacitance C20 as shown in fig. 8B. Therefore, in the solution of the embodiment of the present application, the number of parasitic capacitances connected in series between the second finger electrode 4012 and the semiconductor substrate 410 is increased, so as to reduce the capacitance value of the parasitic capacitance between the second finger electrode 4012 and the semiconductor substrate 410, and finally achieve the purpose of reducing the parasitic capacitance between the whole capacitance C and the semiconductor substrate 410, thereby being beneficial to improving the Q value of the capacitance C.

Based on this, on the one hand, when the above-mentioned capacitor C is adopted in the impedance matching network 30, since the capacitor C has a higher Q value, the smaller the attenuation of the capacitor C to the high-frequency circuit signal, the performance of the impedance matching network 30 is facilitated to be improved, the reflection of the load-side signal is reduced, and the conversion rate of the electrical signal is improved. On the other hand, as the signal reflected by the load end is reduced, the heat converted by the reflected signal is correspondingly reduced, so that the probability of temperature rise of the electronic equipment can be effectively reduced, and the service life of the electronic equipment is prolonged.

Note that, in fig. 8A, the capacitance Cm is a capacitance formed between the first finger electrode 4011 and the second finger electrode 4012 in the electrode structure 401. The resistance Rm is the equivalent resistance of the first finger 4011 and the second finger 4012. The inductance Lm is an equivalent inductance of the first finger 4011 and the second finger 4012. The resistor R11 is an equivalent resistance between the N-well 411 under the first finger electrode 4011 and the semiconductor substrate 410. The resistor R21 is an equivalent resistance between the N-well 411 under the second finger electrode 4012 and the semiconductor substrate 410.

The structure of the capacitor C is exemplified by the electrode structure 401 in which the N-type well 411 in a floating state is provided between the first finger electrode 4011 and the grounded semiconductor substrate 410, and the N-type well 411 in a floating state is provided between the second finger electrode 4012 and the grounded semiconductor substrate 410.

In other embodiments of the present application, the structure of the capacitor substrate 41 may be as shown in fig. 9A, and the capacitor substrate 41 includes a semiconductor substrate 410 and an N-type well 411. The semiconductor substrate 410 and the N-well 411 are disposed in the same manner as described above, and will not be described herein again. In addition, the capacitive substrate 41 may also include a P-type well 412.

As shown in fig. 9A, the P-type well 412 may be disposed between the electrode structure 401 and the N-type well 411. By way of example, as shown in fig. 9B (a cross-sectional view taken along dashed line E-E in fig. 9A), a surface of P-type well 412 adjacent electrode structure 401 is level with first surface a, and the remaining surface is surrounded by N-type well 411. As shown in fig. 9C (a plan view taken along direction D in fig. 9B), the vertical projection of the electrode structure on the semiconductor substrate 410 may be located within the range where the P-type well 412 is located.

For example, the P-type well 412 may be formed on the N-type well 411 corresponding to doping a trivalent dielectric element, such as boron or gallium, through an ion doping process. Then, in the process of fabricating the electrode structure 401 on the capacitor substrate 41, the electrode structure 401 may be formed directly above the P-type well 412, so that the vertical projection of the electrode structure 401 on the semiconductor substrate 410 is located in the range where the P-type well 412 is located. In this way, the relative area between the first finger electrode 4011 and the P-type well 412 in the electrode structure is advantageously increased, so that parasitic capacitance is more easily formed between the first finger electrode 4011 and the P-type well 412. Similarly, the relative area between the second finger 4012 and the P-type well 412 in the electrode structure 401 is advantageously increased, so that parasitic capacitance is more easily formed between the second finger 4012 and the P-type well 412.

It should be noted that, as described above, the P-type well 412 may be located above the N-type well 411, and the surface of the P-type well 412 near the electrode structure 401 is level with the first surface a, and the remaining surfaces are surrounded by the N-type well 411. Accordingly, the thickness of the P-type well 412 is smaller than that of the N-type well 411 in a direction perpendicular to the capacitor substrate 41, and thus the N-type well 411 may also be referred to as an N-type deep well.

On this basis, the manner in which the semiconductor substrate 410 is grounded through the interconnect structure 43 is as described above, and will not be described here again. The P-well 412 is at a floating potential. In this case, an N-type well 411 and a P-type well 412 in a floating state are provided between the first finger electrode 4011 and the grounded semiconductor substrate 410. Thus, the first finger electrode 4011 may have a parasitic capacitance C31 as shown in fig. 10 with the P-type well 412. In addition, a parasitic capacitance C32 is provided between the P-type well 412 under the first finger electrode 4011 and the N-type well 411 under the first finger electrode 4011. A parasitic capacitance C33 is provided between the N-type well 411 under the first finger electrode 4011 and the semiconductor substrate 410. The resistor R31 is an equivalent resistor between the P-well 412 under the first finger electrode 4011 and the N-well 411 under the first finger electrode 4011. Resistor R32 is the equivalent resistance between P-well 412 under first finger 4011 and semiconductor substrate 410.

Similarly, an N-type well 411 and a P-type well 412 in a floating state are provided between the second finger electrode 4012 and the grounded semiconductor substrate 410. Thus, the second finger 4012 has a parasitic capacitance C41 as shown in fig. 10 with the P-type well 412. In addition, a parasitic capacitance C42 is provided between the P-well 412 under the second finger 4012 and the N-well 411 under the second finger 4012. A parasitic capacitance C43 is provided between the N-well 411 under the second finger electrode 4012 and the semiconductor substrate 410. The resistor R41 is an equivalent resistor between the P-well 412 under the second finger 4012 and the N-well 411 under the second finger 4012. Resistor R42 is the equivalent resistance between P-well 412 under second finger 4012 and semiconductor substrate 410.

In this case, as shown in fig. 10, a parasitic capacitance C31, a parasitic capacitance C32, and a parasitic capacitance C33 are connected in series between the first finger electrode 4011 and the semiconductor substrate 410. As can be seen from the above, if the N-well 411 is grounded, the first finger electrode 4011 and the semiconductor substrate 410 have only one parasitic capacitance C10 as shown in fig. 8B. The number of parasitic capacitances connected in series between the first finger electrode 4011 and the semiconductor substrate 410 is increased in the scheme of the embodiment of the present application, so as to reduce the capacitance value of the parasitic capacitance between the first finger electrode 4011 and the semiconductor substrate 410.

Similarly, as shown in fig. 10, a parasitic capacitance C41, a parasitic capacitance C42, and a parasitic capacitance C43 are connected in series between the second finger electrode 4012 and the semiconductor substrate 410. The same applies to increasing the number of parasitic capacitances connected in series between the second finger electrode 4012 and the semiconductor substrate 410, so as to reduce the capacitance value of the parasitic capacitance between the second finger electrode 4012 and the semiconductor substrate 410, and finally achieve the purpose of reducing the parasitic capacitance between the whole capacitance C and the semiconductor substrate 410, thereby being beneficial to improving the Q value of the capacitance C.

For example, fig. 11A is a graph showing the capacitance value of the capacitor C according to the signal frequency, and it can be seen that the capacitance value of the capacitor varies according to the signal frequency. In the embodiment of the present application, the capacitor shown in fig. 9A is used, and the curve of the capacitor C for grounding the N-well 411 shown in fig. 8B is overlapped. In this case, the capacitance values of the two capacitances C are the same. For example, at node m1, the capacitance values of both capacitors C may be 5GHz.

On this basis, as shown in fig. 11B, curve (1) is a curve of the change of Q value of the capacitor C with the signal frequency shown in fig. 9A according to the embodiment of the present application. Curve (2) is a variation curve of the capacitance C with the signal frequency, which is shown in fig. 8B and connects the N-well 411 to ground. It can be seen that curve (1) is located above curve (2). For example, at node m2 where the signal frequency is 5GHz, the Q value corresponding to curve (1) is raised by about 10% relative to the Q value corresponding to curve (2). Therefore, the capacitor C shown in fig. 9A has a higher Q value in the embodiment of the present application.

In addition, as can be seen from the above description, the capacitor C provided in the present application can achieve the purpose of improving the Q value of the capacitor C only by improving the structure of the capacitor substrate 41 in the capacitor C, so that the difficulty of the manufacturing process is not increased, and the mass production of the product is easy.

As can be seen from the above, in the rf circuit 20, the impedance matching network 30 having the capacitance C can be electrically connected to the PA212 or the LNA 211. Wherein, a field effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is disposed in the PA212 or the LNA 211. In this case, at least a part of the field effect transistor may be formed of the same material as at least a part of the capacitor substrate 41 in the capacitor C. Thus, the field effect transistor can be manufactured by a semiconductor manufacturing process, and at least a part of the structure of the capacitor substrate 41 can be manufactured at the same time, so that the purposes of simplifying the process and improving the production efficiency are achieved.

As illustrated in fig. 12, PA212 may include a MOS, an isolated dc capacitance Cb, a ground capacitance Cg, and a resistor R connected to an operating voltage Vdc. The gate (gate, g) of the MOS is electrically connected to the power source Vin, the first pole a (source region or drain region) of the MOS is for receiving the input electrical signal, and the second pole b (drain region or source region) of the MOS is for electrically connecting to the impedance matching network 30 via the isolated dc capacitance Cb.

The PA212 can amplify an input electric signal by using an amplification state of the MOS, and transmit the amplified electric signal to the impedance matching network 30 through the isolation dc capacitor Cb. The following will exemplify a manner in which a part of the MOS and a part of the capacitor substrate 41 in the capacitor C are formed of the same material.

Specifically, as shown in fig. 13A, the MOS may include a P-type transistor substrate 52, an N-type source(s) region 53, and an N-type drain (d) region 54 disposed over a semiconductor substrate 410. Thus, the capacitor C and the MOS can be fabricated in different areas on the same semiconductor substrate to integrate the MOS into an integrated circuit.

In addition, a P-type transistor substrate 52 is disposed over the semiconductor substrate 410 and is of the same material as the P-type well 412 in the capacitor substrate 41 of the capacitor C. In this way, the P-type well 412 can be formed in the semiconductor substrate 410 by the P-type doping process at the position corresponding to the capacitor C, and the P-type transistor substrate 52 can be formed by the P-type doping process at the position corresponding to the MOS, thereby simplifying the manufacturing process.

Further, as shown in fig. 13A, both the N-type source region 53 and the N-type drain region 54 of the MOS are disposed over the P-type transistor substrate 52. And, the N-type source region 53 and the N-type drain region 54 are disposed at a spacing. In this case, after the P-type transistor substrate 52 is fabricated, the N-type source region 53 and the N-type drain region 54 may be formed on the P-type transistor substrate 52 using the N-type doping process. Next, a gate g, a source s, and a drain d forming a MOS may be employed with a metal. In this case, the MOS is an N-type transistor.

In order to simplify the manufacturing process, the via 55 in the MOS for electrically connecting the source s and the drain d to the N-type source region 53 and the N-type drain region 54, respectively, may be formed by the same patterning process as the first via 432 for connecting the interconnect structure 43 in the capacitor C.

The above description has been made taking an example in which a MOS is an N-type transistor, and at least a part of a field effect transistor may be formed of the same material as at least a part of the capacitor substrate 41 in the capacitor C. In other embodiments of the present application, the MOS may be a P-type transistor.

As illustrated in fig. 13B, the field effect transistor includes an N-type transistor substrate 56, a P-type source region 57, and a P-type drain region 58 disposed over a semiconductor substrate 410. The N-type transistor substrate 56 is disposed over the semiconductor substrate 410 and is of the same material as the N-well 411 in the capacitor substrate 41 of the capacitor C. In this way, the N-type well 411 can be formed in the semiconductor substrate 410, for example, a Si substrate, by using the N-type doping process at the position corresponding to the capacitor C, and the N-type transistor substrate 56 can be formed by using the N-type doping process at the position corresponding to the MOS, thereby achieving the purpose of simplifying the manufacturing process.

Further, as shown in fig. 13B, both the P-type source region 57 and the P-type drain region 58 of the MOS are disposed over the N-type transistor substrate 56. Thus, the P-type source region 57 and the P-type drain region 58 can be formed on the N-type transistor substrate 56 of the MOS, while the P-type well 412 is formed on the N-type well 411 of the capacitor C by the P-type doping process described above. Wherein the P-type source region 57 and the P-type drain region 58 are spaced apart.

Similarly, next, a gate g, a source s, and a drain d forming a MOS may be used with a metal. In this case, the MOS is a P-type transistor.

The above description is given taking an example in which at least a part of the field effect transistor in the PA212 may be made of the same material as at least a part of the capacitor substrate 41 in the capacitor C. The method for manufacturing the field effect transistor in the LNA211 of the rf circuit 20 and at least a portion of the same layer and material as the capacitor substrate 41 of the capacitor C is the same as described above, and will not be repeated here.

The above description is given taking the capacitance in the impedance matching network 30 as the capacitance C as an example. The capacitor C provided in the embodiment of the present application may be applied not only to the impedance matching network 30 but also to other circuit structures in the radio frequency circuit 20, such as a digital-to-analog converter, an analog-to-digital converter, and the like. Or may be applied to other circuits having a capacitor.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

An integrated circuit comprising an impedance matching network, said impedance matching network comprising a capacitor and an inductance electrically connected to said capacitor; the capacitor includes:

an electrode structure; the electrode structure comprises a plurality of first finger electrodes electrically connected and a plurality of second finger electrodes electrically connected; the first finger electrodes and the second finger electrodes are arranged in a staggered manner;

a capacitor substrate including an N-type well; the N-type well is arranged on the semiconductor substrate; the first finger electrode and the second finger electrode are arranged on the N-type well; the N-type well is in potential floating.
The integrated circuit of claim 1, wherein the capacitive substrate further comprises:

the P-type well is arranged between the electrode structure and the N-type well; the P-type well is in potential floating.
An integrated circuit as claimed in claim 1 or 2, wherein the vertical projection of the electrode structure onto the semiconductor substrate is within the N-well.
The integrated circuit of claim 2, wherein a vertical projection of the electrode structure onto the semiconductor substrate is within a region of the P-well.
The integrated circuit of any of claims 1-4, wherein the capacitor further comprises:

and one end of the interconnection structure is contacted with the semiconductor substrate, and the other end of the interconnection structure is used for grounding.
The integrated circuit of claim 5, wherein the interconnect structure comprises:

the P-type semiconductor doping part is arranged on the semiconductor substrate;

the first through hole penetrates through the dielectric layer, and the first end of the first through hole is electrically connected with the P-type semiconductor doping part;

and the metal part is arranged on one side surface of the dielectric layer, which is far away from the semiconductor substrate, and is electrically connected with the second end of the first through hole, and the metal part is used for grounding.
The integrated circuit of claim 5 or 6, wherein the interconnect structure is disposed around a perimeter of the N-well and is connected end-to-end.
The integrated circuit of any of claims 5-7, wherein the metal portion is the same material as the first finger electrode or the second finger electrode.
The integrated circuit of any of claims 1-8, wherein the impedance matching network is an L-type matching network, a pi-type matching network, or a T-type matching network.
A radio frequency circuit comprising a radio frequency transceiver for electrical connection with an antenna; the radio frequency circuit further comprising an integrated circuit as claimed in any one of claims 1 to 9; the impedance matching network in the integrated circuit is electrically connected between the radio frequency transceiver and the antenna.
The radio frequency circuit of claim 10, further comprising a field effect transistor integrated in the integrated circuit.
An electronic device comprising a motherboard and a radio frequency circuit as claimed in claim 10 or 11, at least a portion of the radio frequency circuit being disposed on the motherboard.