WO2022257678A1 - 一种芯片封装结构及其封装方法 - Google Patents

一种芯片封装结构及其封装方法 Download PDF

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Publication number
WO2022257678A1
WO2022257678A1 PCT/CN2022/091689 CN2022091689W WO2022257678A1 WO 2022257678 A1 WO2022257678 A1 WO 2022257678A1 CN 2022091689 W CN2022091689 W CN 2022091689W WO 2022257678 A1 WO2022257678 A1 WO 2022257678A1
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Prior art keywords
chip
layer
electrode layer
substrate
rewiring
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PCT/CN2022/091689
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English (en)
French (fr)
Inventor
王全龙
曹立强
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华进半导体封装先导技术研发中心有限公司
上海先方半导体有限公司
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Publication of WO2022257678A1 publication Critical patent/WO2022257678A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Definitions

  • the present application relates to the technical field of chip packaging, in particular to a chip packaging structure and a packaging method thereof.
  • Power integrity is very important in today's electronic products.
  • the levels of power integrity include: chip level, chip package level, circuit board level and system level. At present, in mobile terminals and high-performance computing applications, power integrity becomes more and more important.
  • the capacitor structure is separately arranged on the circuit board, so the integration degree is poor; since the space of the chip is small, and the separately arranged capacitor structure occupies limited space, it cannot obtain a large capacitance.
  • the technical problem to be solved in the present application is to overcome the defects of low integration and small capacitance of the existing packaging structure, so as to provide a chip packaging structure and a packaging method thereof.
  • the present application provides a chip packaging structure, including: a substrate; a chip disposed on the substrate; and a capacitor structure, the capacitor structure includes a first electrode layer and a second electrode layer oppositely arranged, and a A capacitive dielectric layer between the first electrode layer and the second electrode layer; the first electrode layer, the second electrode layer and the capacitive dielectric layer are all along the chip facing away from the substrate One side surface and the sidewall of the chip extend.
  • the capacitor structure is a decoupling capacitor; the first electrode layer receives a power signal, and the second electrode layer receives a ground signal; or the second electrode layer receives a power signal, and the first electrode layer Receive ground signal.
  • the substrate includes a rewiring structure
  • the rewiring structure includes a rewiring layer
  • the first electrode layer is electrically connected to the chip through the rewiring layer
  • the second electrode layer is electrically connected to the chip through the rewiring layer
  • the redistribution layer is electrically connected to the chip.
  • the chip packaging structure further includes: an insulating layer, covering the side wall of the chip and the surface of the chip on the side facing away from the substrate, and extending to the part of the surface of the rewiring structure on the side of the chip, the The insulating layer is located between the capacitor structure and the chip; the first electrode layer is located between the insulating layer and the capacitor medium layer.
  • the first electrode layer includes a first connection part, the first connection part is located on the side of the chip and is opposite to the rewiring structure;
  • the chip packaging structure further includes: a first connection part, The first connecting piece penetrates through the insulating layer and is located at the bottom of the first connecting portion, one end of the first connecting piece is connected to the first connecting portion, and the other end of the first connecting piece is connected to the Rewiring layers.
  • the second electrode layer includes a second connection portion, the second connection portion is located on the side of the chip and is opposite to the rewiring structure;
  • the chip packaging structure further includes: a second connection part, the second connecting part runs through the capacitor medium layer and the insulating layer and is located at the bottom of the second connecting part, one end of the second connecting part is connected to the second connecting part, and the second The other end of the connector is connected to the redistribution layer.
  • the chip packaging structure further includes: solder balls disposed on a side of the rewiring structure facing away from the chip.
  • the chip is connected to the solder balls through the redistribution layer, the solder balls are connected to a power module, the power module is used to output power signals to some solder balls, and the power module is used to output ground signals to some solder balls.
  • the chip is flip-chip mounted on the substrate.
  • the present application provides a packaging method, including: preparing a substrate; mounting a chip on the substrate; and forming a capacitor structure, and the method for forming a capacitor structure includes: forming a first electrode layer; forming a second electrode layer ; Between the step of forming the first electrode layer and the step of forming the second electrode layer, a capacitor dielectric layer is formed, and the first electrode layer, the second electrode layer and the capacitor dielectric layer are all along the chip facing away from the A side surface of the substrate and a side wall of the chip extend.
  • the substrate includes a rewiring structure
  • the rewiring structure includes a rewiring layer
  • the first electrode layer is electrically connected to the chip through the rewiring layer
  • the second electrode layer is electrically connected to the chip through the rewiring layer
  • the redistribution layer is electrically connected to the chip.
  • the step of forming the capacitor structure also includes: forming an insulating layer, the insulating layer covers the side wall of the chip and the surface of the chip on the side facing away from the substrate, and extends to the side of the chip Part of the rewiring structure surface; forming a first connection member penetrating through the insulating layer in the insulating layer on the side of the chip, and connecting the first connecting member to the rewiring layer; forming a first electrode layer in the In the step, the first electrode layer includes a first connection part, the first connection part is located on the side of the chip and is opposite to the rewiring structure, the first connection part is located on the side of the first connection part surface.
  • the packaging method further includes: in the step of forming the capacitor dielectric layer, the capacitor dielectric layer extends to a part of the surface of the insulating layer on the side of the chip; the packaging method further includes: The side of the chip is formed with a second connecting piece penetrating through the capacitor dielectric layer and the insulating layer, and the second connecting piece is connected to the rewiring layer; in the step of forming the second electrode layer, the second electrode layer A second connection part is included, the second connection part is located on the side of the chip and opposite to the rewiring structure, and the second connection part is located on the surface of the second connection part.
  • the packaging method further includes: preparing solder balls on a side of the rewiring structure facing away from the chip.
  • the step of mounting the chip on the substrate is to flip-chip the chip on the substrate.
  • the present application provides a chip packaging structure and a packaging method thereof.
  • the capacitor structure is applied in the package, thereby improving the integration of the chip.
  • the first electrode layer, the second electrode layer and the capacitive dielectric layer all extend along the side surface of the chip facing away from the substrate and the side wall of the chip. Therefore, the first electrode layer and the second electrode layer can obtain a larger relative area, which can improve the capacity of the capacitor.
  • FIG. 1 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application
  • step S2 is a schematic diagram of step S2 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • step S3 is a schematic diagram of step S3 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • step S4 is a schematic diagram of step S4 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • step S5 is a schematic diagram of step S5 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • step S5 is a schematic diagram of step S5 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • step S5 is a schematic diagram of step S5 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application.
  • step S6 is a schematic diagram of step S6 in the method for preparing the structure of the chip package structure provided in the embodiment of the present application;
  • Chip packaging structure 100 substrate 101; chip 102; insulating layer 103;
  • capacitor structure 104 encapsulation layer 106; solder ball 105; redistribution layer 1011;
  • Temporary carrier 110 first electrode layer 1041; capacitor dielectric layer 1042; second electrode layer 1043;
  • orientations or positional relationships indicated by the terms “upper”, “lower”, “inner”, “outer”, etc. are based on the orientation or positional relationships shown in the drawings, and are only for It is convenient to describe the application and simplify the description, but not to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as limiting the application.
  • first and second are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. 20 connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • the embodiment of the present application provides a chip packaging structure 100 , including: a substrate 101 , a chip 102 , an insulating layer 103 and a capacitor structure 104 .
  • the substrate 101 is a rewiring structure.
  • the redistribution structure includes a redistribution layer 1011 and a dielectric layer covering the redistribution layer 1011 .
  • the substrate 101 may be other substrates 101 electrically connected to the chip 102 .
  • the chip 102 is disposed on the substrate 101 and connected to the substrate 101; the number of the chips 102 can be multiple, and the present application does not limit the number of the chips 102; In this embodiment, there are two chips 102 , specifically the first chip 1021 and the second chip 1022 .
  • the first chip 1021 is a single-layer chip structure, the front of the first chip 1021 is provided with a plurality of first pads 1023, the first pads 1023 are connected to the substrate 101, the first pads 1023 and
  • the first adhesive layer 1024 is filled between the substrates 101;
  • the second chip 1022 is a stacked chip structure, and the second chip 1022 includes several stacked second sub-chips, and the front side of the second sub-chip is provided with a second pad 1025, corresponding to Adjacent second sub-chips are electrically connected through a connecting piece, the connecting piece is provided in the second sub-chip, and two ends of the connecting piece are respectively connected to the second bonding pads 1025 of the adjacent second sub-chips.
  • a second adhesive layer 1026 is filled between adjacent second sub-chips.
  • the figure shows a 3-layer silicon-based chip stack design, and the second sub-chip at the bottom is connected to the substrate 101 through the second bonding pad 1025 .
  • the chip 102 is flip-chip mounted on the substrate 101 .
  • Both the first chip 1021 and the second chip 1022 are flip-chip mounted on the substrate 101 .
  • the insulating layer 103 covers the sidewall of the chip 102 and the surface of the chip 102 facing away from the substrate 101 , and extends to a part of the surface of the rewiring structure on the side of the chip 102 .
  • the insulating layer 103 is disposed between the capacitor structure 104 and the chip 102 .
  • the capacitive structure 104 includes: a first electrode layer 1041, a capacitive dielectric layer 1042 and a second electrode layer 1043, the first electrode layer 1041 and the second electrode layer 1043 are arranged oppositely, and the capacitive dielectric layer 1042 is located between the first electrode layer 1041 and the second electrode layer 1043. between the two electrode layers 1042 .
  • the first electrode layer 1041 , the second electrode layer 1043 and the capacitive dielectric layer 1042 all extend along the side surface of the chip 102 facing away from the substrate 101 and the sidewall of the chip 102 . Therefore, the capacitor structure 104 can obtain a larger area, which can increase the capacity of the capacitor.
  • a decoupling capacitor is a capacitor installed on the power supply side of the component in the circuit. This capacitor can provide a more stable power supply, and at the same time reduce the noise coupled from the component to the power supply terminal, and indirectly reduce the influence of other components by the noise of this component.
  • the first electrode layer 1041 is arranged on the upper surface of the insulating layer 103, and the first electrode layers 1041 on adjacent chips 102 are separated from each other; the first electrode layer 1041 is electrically connected to the chip 102 through the rewiring layer 1011 . Specifically, as shown in FIG. 5 and FIG.
  • the first electrode layer 1041 includes a first connection portion 1044, and the first connection portion 1044 is located on the side of the chip 102 and is arranged opposite to the rewiring structure;
  • the chip packaging structure further includes: a first connector 1031, the first connector 1031 penetrates through the insulating layer 103 and is located at the bottom of the first connection part 1044, one end of the first connector 1031 is connected to the The first connecting portion 1044 , the other end of the first connecting member 1031 is connected to the redistribution layer 1011 , so as to realize the electrical connection between the first electrode layer 1041 and the chip 102 .
  • the capacitor dielectric layer 1042 is disposed on the upper surface of the first electrode layer 1041 .
  • the second electrode layer 1043 is disposed on the upper surface of the capacitor dielectric layer 1042 .
  • the second electrode layer 1043 is electrically connected to the chip 102 through the redistribution layer 1011 . Specifically, as shown in FIG.
  • the second electrode layer 1043 includes a second connection portion 1045, the second connection portion 1045 is located on the side of the chip 102 and is opposite to the rewiring structure, and the adjacent chip The second electrode layer 1043 on 102 is separated from each other; the chip package structure further includes: a second connecting member 1032, the second connecting member 1032 penetrates the capacitor dielectric layer 1042 and the insulating layer 103 and is located at the second connecting portion 1045 One end of the second connection part 1032 is connected to the second connection part 1045 , and the other end of the second connection part 1032 is connected to the redistribution layer 1011 .
  • the chip package structure 100 further includes an encapsulation layer 106, the encapsulation layer 106 is disposed on the substrate 101 and the capacitor structure 104, and the encapsulation layer 106 is pressed Prepared by molding, the material of the encapsulation layer 106 includes epoxy resin molding compound.
  • the solder balls 105 are disposed on a side of the substrate 101 facing away from the chip 102 .
  • the material of the solder ball 105 is tin ball.
  • the solder balls 105 are connected to the redistribution layer 1011 .
  • the solder ball 105 is connected to a power module, the power module is used to output a power signal to some solder balls, and the power module is used to output a ground signal to some solder balls.
  • the present application provides a chip packaging structure 100, in which the capacitor structure 104 is packaged on the surface and sidewall of the chip 102, thereby increasing the area of the capacitor package and further increasing the capacitance.
  • the present application provides a chip packaging structure, and the integration degree of the chip can be improved by packaging the capacitor structure on the surface and side walls of the chip.
  • the first electrode layer, the second electrode layer and the capacitive dielectric layer all extend along the side surface of the chip facing away from the substrate and the side wall of the chip. Therefore, the first electrode layer and the second electrode layer can obtain a larger relative area, which can improve the capacity of the capacitor.
  • the present application also provides a method for preparing a chip packaging structure, including the following steps S1-S7.
  • Step S1 referring to FIG. 2 , providing a temporary carrier 110 and a chip 102 .
  • Step S2 continue to refer to FIG. 2 to prepare the substrate 101 on the temporary carrier 110; the substrate 101 includes a redistribution structure (RDL); in step S2, prepare the redistribution layer 1011 on the temporary carrier On 110, the preparation process is a wafer-level photolithography and electroplating process, and the material of the rewiring layer 1011 includes copper (Cu); a dielectric layer is prepared on the temporary carrier 110 and covers the rewiring layer 1011, and the dielectric layer
  • the materials include: polyimide (PI) material, polybenzoxazole (PBO), benzoylbutene (BCB).
  • Step S3 mount the chip 102 on the substrate 101 , and the mounting method is flip chip.
  • the chip 102 includes a first chip 1021 and a second chip 1022, the first chip 1021 is a single-layer chip structure, the front side of the first chip 1021 is provided with a plurality of first pads 1023, and the first pads 1023 are connected to the substrate 101 , a first glue layer 1024 is filled between the first pad 1023 and the substrate 101 .
  • the second chip 1022 is a stacked chip structure.
  • the second chip 1022 includes several stacked second sub-chips.
  • the front side of the second sub-chip is provided with a second pad 1025. Adjacent second sub-chips are electrically connected through conductive members.
  • the conductive member is disposed in the second chiplet, and both ends of the conductive member are respectively connected to the second bonding pads 1025 of the adjacent second chiplet.
  • the second adhesive layer 1026 is also filled between the adjacent second chiplets.
  • the figure shows a stacked design of 3 layers of silicon-based chips, and the bottommost second chiplet is connected to the substrate 101 through the second pad 1025 .
  • Step S4 referring to FIG. 4 , preparing an insulating layer 103 .
  • the insulating layer 103 is prepared by a vacuum lamination process. The vacuum lamination is to directly set a thin film material, and the insulating layer 103 covers the side wall of the chip 102 and the surface of the chip 102 facing away from the substrate 101, and extending to the surface of the part of the rewiring structure on the side of the chip 102, and etching a first through hole 112 in the insulating layer 103 on the side of the chip 102, and forming a first connecting member in the first through hole 112 1031, the first connection member 1031 is connected to the redistribution layer 1011.
  • the material of the insulating layer 103 includes: polyimide (PI) material, polybenzoxazole (PBO), benzoyl butylene (BCB).
  • Step S5 preparing the capacitor structure 104; step S5 specifically includes the following steps: S501, referring to FIG. 5, preparing the first electrode layer 1041 on the surface of the insulating layer 103, specifically including depositing the first electrode layer 1041 on the insulating layer 103 surface, and the first electrode layer 1041 is etched and disconnected between adjacent chips 102; the first electrode layer 1041 is along the side surface of the chip 102 facing away from the substrate 101 and the The side walls are extended, the first electrode layer 1041 is prepared by sputtering, electroplating, etc., the first electrode layer 1041 includes a first connection part 1044, and the first connection part 1044 is located on the side of the chip 102 and Set opposite to the rewiring structure, the first connection part 1044 is located on the surface of the first connection member 1031; the material of the first electrode layer 1041 includes metal materials such as aluminum (Al) copper (Cu); S502 , Referring to FIG.
  • the capacitor dielectric layer 1042 extends along the side surface of the chip 102 facing away from the substrate 101 and the side wall of the chip 102, the capacitor dielectric layer 1042 is prepared by a vacuum lamination process, the capacitor dielectric layer 1042 extends to the surface of part of the insulating layer 103 on the side of the chip 102; in the capacitor dielectric layer 1042 on the side of the chip 102, a And the second through hole 113 of the capacitor dielectric layer 1042, and form the second connection member 1032 in the second through hole 113, the connection of the second connector 1032 is connected to the redistribution layer 1011; the material of the capacitor dielectric layer 1042 Optional epoxy resins, PI, BCB, PBO and other organic films; S503, referring to Figure 7, prepare the second electrode layer 1043, the specific method includes depositing the second electrode layer 1043 on the surface of the capacitor dielectric layer 1042, and The second electrode layer 1043 is etched and disconnected between adjacent chips 102; the second electrode layer
  • Step S6 refer to FIG. 8 to prepare the encapsulation layer 106 on the substrate 101 and the capacitor structure 104.
  • the preparation process of the encapsulation layer 106 is a compression molding process, and the preparation material of the encapsulation layer 106 includes epoxy resin.
  • Step S7 referring to FIG. 8 , removing the temporary carrier 110 and forming solder balls 105 on the back surface of the substrate 101 .
  • the material of the solder balls 105 includes solder balls.
  • the present application provides a packaging method for a chip packaging structure.
  • the capacitor structure is applied in the package, thereby improving the integration of the chip.
  • the first electrode layer, the second electrode layer and the capacitive dielectric layer all extend along the side surface of the chip facing away from the substrate and the side wall of the chip. Therefore, the first electrode layer and the second electrode layer can obtain a larger relative area, which can improve the capacity of the capacitor.

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Abstract

本申请提供一种芯片封装结构及其制备方法，芯片封装结构包括：基板、芯片、绝缘层、电容结构、以及封装层。本申请提供一种芯片封装结构及其封装方法，通过将电容结构封装于芯片的表面以及侧壁，将电容结构应用在封装中，进而可以提高芯片的集成度。本申请将所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。因此，所述第一电极层与所述第二电极层可以获得更大的相对面积，这可以提高电容的容量。

Description

一种芯片封装结构及其封装方法
本申请要求在2021年06月07日提交中国专利局、申请号为202110633653.3、发明名称为“一种芯片封装结构及其封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装技术领域，具体涉及一种芯片封装结构及其封装方法。
背景技术
电源完整性在现今的电子产品中相当重要。电源完整性的层面包括：芯片层面、芯片封装层面、电路板层面及系统层面。目前在移动终端、高性能计算应用中，随着芯片工作电流增加，时钟频率增加，电源完整性越来越重要。
为了在封装层面解决电源完整性，提出了多种不同集成方案。目前电容结构单独设于电路板上，因此集成度较差；由于芯片的空间小，并且单独设置的电容结构占用空间有限，其并不能获得较大的电容量。
发明内容
因此，本申请要解决的技术问题在于克服现有封装结构集成度低及电容量小的缺陷，从而提供一种芯片封装结构及其封装方法。
第一方面，本申请提供一种芯片封装结构，包括：基板；芯片，设于所述基板上；以及电容结构，所述电容结构包括相对设置的第一电极层和第二电极层、以及位于所述第一电极层和所述第二电极层之间的电容介质 层；所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。
可选地，所述电容结构为去耦电容；所述第一电极层接收电源信号，所述第二电极层接收接地信号；或所述第二电极层接收电源信号，所述第一电极层接收接地信号。
可选地，所述基板包括重布线结构，所述重布线结构包括重布线层；所述第一电极层通过所述重布线层与所述芯片电连接；所述第二电极层通过所述重布线层与所述芯片电连接。
可选地，所述的芯片封装结构还包括：绝缘层，覆盖所述芯片的侧壁和芯片背向基板一侧的表面，且延伸至所述芯片侧部的部分重布线结构表面，所述绝缘层位于所述电容结构与所述芯片之间；所述第一电极层位于所述绝缘层和所述电容介质层之间。
可选地，所述第一电极层包括第一连接部，所述第一连接部位于芯片的侧部且与所述重布线结构相对设置；所述芯片封装结构还包括：第一连接件，所述第一连接件贯穿所述绝缘层且位于所述第一连接部的底部，所述第一连接件的一端连接所述第一连接部，所述第一连接件的另一端连接所述重布线层。
可选地，所述第二电极层包括第二连接部，所述第二连接部位于所述芯片的侧部且与所述重布线结构相对设置；所述芯片封装结构还包括：第二连接件，所述第二连接件贯穿所述电容介质层和所述绝缘层且位于所述第二连接部的底部，所述第二连接件的一端连接所述第二连接部，所述第二连接件的另一端连接所述重布线层。
可选地，所述的芯片封装结构还包括：焊球，设于所述重布线结构背向所述芯片的一侧。
可选地，所述芯片通过所述重布线层连接所述焊球，所述焊球连接电源模块，所述电源模块用以输出电源信号至部分焊球，所述电源模块用以 输出接地信号至部分焊球。
可选地，所述芯片倒装在所述基板上。
另一方面，本申请提供一种封装方法，包括：制备基板；将芯片贴装在所述基板上；以及形成电容结构，形成电容结构的方法包括：形成第一电极层；形成第二电极层；在形成第一电极层的步骤和形成第二电极层的步骤之间，形成电容介质层，所述第一电极层、第二电极层和电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。
可选地，所述基板包括重布线结构，所述重布线结构包括重布线层；所述第一电极层通过所述重布线层与所述芯片电连接；所述第二电极层通过所述重布线层与所述芯片电连接。
可选地，在所述形成电容结构步骤之前，还包括：形成绝缘层，所述绝缘层覆盖所述芯片的侧壁和芯片背向基板一侧的表面，且延伸至所述芯片侧部的部分重布线结构表面；在所述芯片侧部的绝缘层中形成贯穿所述绝缘层的第一连接件，所述第一连接件的连接所述重布线层；在所述形成第一电极层步骤中，所述第一电极层包括第一连接部，所述第一连接部位于芯片的侧部且与所述重布线结构相对设置，所述第一连接部位于所述第一连接件的表面。
可选地，所述的封装方法还包括：在所述形成电容介质层的步骤中，所述电容介质层延伸至所述芯片侧部的部分绝缘层表面；所述封装方法还包括：在所述芯片侧部形成贯穿电容介质层中和绝缘层的第二连接件，所述第二连接件的连接所述重布线层；在所述形成第二电极层步骤中，所述第二电极层包括第二连接部，所述第二连接部位于芯片的侧部且与所述重布线结构相对设置，所述第二连接部位于所述第二连接件的表面。
可选地，所述的封装方法还包括：制备焊球于所述重布线结构背向所述芯片的一侧。
可选地，将所述芯片贴装在所述基板上的步骤为，将所述芯片倒装在 所述基板上。
本申请技术方案，具有如下优点：
本申请提供一种芯片封装结构及其封装方法，通过将电容结构封装于芯片的表面以及侧壁，将电容结构应用在封装中，进而可以提高芯片的集成度。本申请将所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。因此，所述第一电极层与所述第二电极层可以获得更大的相对面积，这可以提高电容的容量。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中提供的芯片封装结构的结构示意图；
图2为本申请实施例中提供的芯片封装结的构制备方法中步骤S2的示意图；
图3为本申请实施例中提供的芯片封装结的构制备方法中步骤S3的示意图；
图4为本申请实施例中提供的芯片封装结的构制备方法中步骤S4的示意图；
图5为本申请实施例中提供的芯片封装结的构制备方法中步骤S5的示意图；
图6为本申请实施例中提供的芯片封装结的构制备方法中步骤S5的示意图；
图7为本申请实施例中提供的芯片封装结的构制备方法中步骤S5的示意图；
图8为本申请实施例中提供的芯片封装结的构制备方法中步骤S6的示意图；
附图说明：
芯片封装结构100；基板101；芯片102；绝缘层103；
电容结构104；封装层106；焊球105；重布线层1011；
临时载片110；第一电极层1041；电容介质层1042；第二电极层1043；
第一连接件1031；第二连接件1032；第一芯片1021；第二芯片1022。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸20连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内 部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
如图1所示，本申请实施例提供一种芯片封装结构100，包括：基板101、芯片102、绝缘层103以及电容结构104。
本实施例中，所述基板101为重布线结构。所述重布线结构包括重布线层1011以及包覆所述重布线层1011的介质层。
在其他实施例中，基板101可以且其他与芯片102电学连接的基板101。
同时参阅图3所示，所述芯片102设于所述基板101上且连接所述基板101；所述芯片102的数量可以为多个，本申请并未对芯片102的数量并未作出限制；在本实施例中芯片102数量为2个，具体为第一芯片1021与第二芯片1022。同时参照图3所示，第一芯片1021为单层芯片结构，第一芯片1021的正面设有多个第一焊盘1023，第一焊盘1023连接所述基板101，第一焊盘1023与基板101之间填充第一胶层1024；第二芯片1022为叠层芯片结构，第二芯片1022包括若干个层叠的第二子芯片，第二子芯片的正面设置有第二焊盘1025，相邻的第二子芯片通过连接件电连接，所述连接件设于所述第二子芯片中，所述连接件的两端分别连接相邻第二子芯片的第二焊盘1025。相邻第二子芯片之间还填充第二胶层1026，图中为3层硅基芯片叠层设计，最底层的第二子芯片通过第二焊盘1025连接基板101。
本实施例中，所述芯片102倒装在所述基板101上。第一芯片1021和第二芯片1022均倒装在所述基板101上。
继续参阅图1所示，所述绝缘层103覆盖所述芯片102的侧壁和芯片102背向基板101一侧的表面，且延伸至所述芯片102侧部的部分重布线结构表面。所述绝缘层103设于所述电容结构104与所述芯片102之间。
所述电容结构104包括：第一电极层1041、电容介质层1042以及第二电极层1043，第一电极层1041和第二电极层1043相对设置，电容介质层1042位于第一电极层1041和第二电极层1042之间。所述第一电极层1041、 所述第二电极层1043和所述电容介质层1042均沿着所述芯片102背向所述基板101的一侧表面和所述芯片102的侧壁延伸。因此，所述电容结构104可以获得更大的面积，这可以提高电容的容量。
当所述电容结构104作为去耦电容时，所述第一电极层1041接收电源信号，所述第二电极层1042接收接地信号；或所述第二电极层1042接收电源信号，所述第一电极层1041接收接地信号。去耦电容是电路中装设在元件的电源端的电容，此电容可以提供较稳定的电源，同时也可以降低元件耦合到电源端的噪声，间接可以减少其他元件受此元件噪声的影响。
所述第一电极层1041设于所述绝缘层103上表面，相邻芯片102上的第一电极层1041相互分立；所述第一电极层1041通过重布线层1011与所述芯片102电连接。具体地，参照图5以及图6所示，所述第一电极层1041包括第一连接部1044，所述第一连接部1044位于芯片102的侧部且与所述重布线结构相对设置；所述芯片封装结构还包括：第一连接件1031，所述第一连接件1031贯穿所述绝缘层103且位于所述第一连接部1044的底部，所述第一连接件1031的一端连接所述第一连接部1044，所述第一连接件1031的另一端连接所述重布线层1011，进而实现所述第一电极层1041与所述芯片102电连接。
所述电容介质层1042设于所述第一电极层1041上表面。所述第二电极层1043设于所述电容介质层1042上表面。所述第二电极层1043通过重布线层1011与所述芯片102电连接。具体地，图7所示，所述第二电极层1043包括第二连接部1045，所述第二连接部1045位于所述芯片102的侧部且与所述重布线结构相对设置，相邻芯片102上的第二电极层1043相互分立；所述芯片封装结构还包括：第二连接件1032，所述第二连接件1032贯穿电容介质层1042和绝缘层103且位于所述第二连接部1045的底部，所述第二连接件1032的一端连接所述第二连接部1045，所述第二连接件1032的另一端连接所述重布线层1011。
在一实施例中，参阅图8所示，所述芯片封装结构100还包括封装层106，所述封装层106设于所述基板101与所述电容结构104上，所述封装 层106通过压塑成型制备，所述封装层106的材料包括环氧树脂塑封料。
所述焊球105设于所述基板101背向所述芯片102的一侧。所述焊球105材料为锡球。所述焊球105连接所述重布线层1011。所述焊球105连接电源模块，所述电源模块用以输出电源信号至部分焊球，所述电源模块用以输出接地信号至部分焊球。
本申请提供一种芯片封装结构100，将电容结构104封装于芯片102的表面以及侧壁，从而提高了电容封装面积，进而提高的电容量。
本申请提供一种芯片封装结构，通过将电容结构封装于芯片的表面以及侧壁，进而可以提高芯片的集成度。本申请将所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。因此，所述第一电极层与所述第二电极层可以获得更大的相对面积，这可以提高电容的容量。
本申请还提供一种芯片封装结构的制备方法，包括如下步骤S1～S7。
步骤S1、参阅图2所示，提供临时载片110以及芯片102。
步骤S2、继续参阅图2所示制备基板101于所述临时载片110上；所述基板101包括重布线结构(RDL)；在步骤S2中，制备中重布线层1011于所述临时载片110上，制备工艺为晶圆级光刻以及电镀工艺，重布线层1011的材料包括铜(Cu)；制备介质层于所述临时载片110上且包覆所述重布线层1011，介质层的材料包括：聚酰亚胺(PI)材料、聚苯并恶唑(PBO)，苯甲酰丁烯(BCB)。
步骤S3、参阅图3所示，将所述芯片102贴装在所述基板101上，贴装方法为倒装。所述芯片102包括第一芯片1021与第二芯片1022，第一芯片1021为单层芯片结构，第一芯片1021的正面设有多个第一焊盘1023，第一焊盘1023连接所述基板101，第一焊盘1023与基板101之间填充第一胶层1024。第二芯片1022为叠层芯片结构，第二芯片1022包括若干个层叠的第二子芯片，第二子芯片的正面设置有第二焊盘1025，相邻的第二子芯片通过导电件电连接，所述导电件设于所述第二子芯片中，所述导电件的两端分别连接相邻第二子芯片的第二焊盘1025。相邻第二子芯片之间还 填充第二胶层1026，图中为3层硅基芯片叠层设计，最底层的第二子芯片通过第二焊盘1025连接基板101。
步骤S4、参阅图4所示，制备绝缘层103。所述绝缘层103通过真空压膜工艺制备，真空压膜是将薄膜形态的材料直接设置，所述绝缘层103覆盖所述芯片102的侧壁和芯片102背向基板101一侧的表面，且延伸至所述芯片102侧部的部分重布线结构表面，并于芯片102侧部的绝缘层103中刻蚀出第一通孔112，并于所述第一通孔112中形成第一连接件1031，所述第一连接件1031连接所述重布线层1011。所述绝缘层103的材包括：聚酰亚胺(PI)材料、聚苯并恶唑(PBO)，苯甲酰丁烯(BCB)。
步骤S5、制备电容结构104；步骤S5具体包括如下步骤：S501、参阅图5所示，制备第一电极层1041于所述绝缘层103表面，具体包括沉积第一电极层1041于所述绝缘层103表面，并于相邻芯片102之间第一电极层1041刻蚀断开；所述第一电极层1041沿着所述芯片102背向所述基板101的一侧表面和所述芯片102的侧壁延伸，所述第一电极层1041制备工艺是通过溅射、电镀等方式，所述第一电极层1041包括第一连接部1044，所述第一连接部1044位于芯片102的侧部且与所述重布线结构相对设置，所述第一连接部1044位于所述第一连接件1031的表面；所述第一电极层1041的材料包括铝(Al)铜(Cu)等金属材料；S502、参阅图6所示，制备电容介质层1042，所述电容介质层1042沿着所述芯片102背向所述基板101的一侧表面和所述芯片102的侧壁延伸，所述电容介质层1042通过真空压膜工艺制备得到，所述电容介质层1042延伸至所述芯片102侧部的部分绝缘层103表面；在所述芯片102侧部的电容介质层1042中形成贯穿所述绝缘层103以及所述电容介质层1042的第二通孔113，并于第二通孔113中形成第二连接件1032，所述第二连接件1032的连接所述重布线层1011；电容介质层1042材料可选环氧树脂类，PI，BCB，PBO等有机薄膜；S503、参阅图7所示，制备第二电极层1043，具体方法包括沉积第二电极层1043于所述电容介质层1042表面，并于相邻芯片102之间第二电极层1043刻蚀断开；所述第二电极层1043沿着所述芯片102背向所述基板101的一侧 表面和所述芯片102的侧壁延伸，第二电极层1043通过溅射、电镀等方式制备得到，所述第二电极层1043包括第二连接部1045，所述第二连接部1045位于芯片102的侧部且与所述重布线结构相对设置，所述第二连接部1045位于所述第二连接件1032的表面。所述第二电极层1043的制备材料选择铝(Al)铜(Cu)等金属材料。
步骤S6、参阅图8所示制备封装层106于所述基板101与所述电容结构104上，所述封装层106的制备工艺为压塑成型工艺，所述封装层106的制备材料包括环氧树脂。
步骤S7、参阅图8所示，拆除所述临时载片110并在所述基板101的背面值球形成焊球105，焊球105的材料包括锡球。
本申请提供一种芯片封装结构的封装方法，通过将电容结构封装于芯片的表面以及侧壁，将电容结构应用在封装中，进而可以提高芯片的集成度。本申请将所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。因此，所述第一电极层与所述第二电极层可以获得更大的相对面积，这可以提高电容的容量。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (15)

  1. 一种芯片封装结构，其特征在于，包括：
    基板；
    芯片，设于所述基板上；以及
    电容结构，所述电容结构包括相对设置的第一电极层和第二电极层、以及位于所述第一电极层和所述第二电极层之间的电容介质层；所述第一电极层、所述第二电极层和所述电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述电容结构为去耦电容；所述第一电极层接收电源信号，所述第二电极层接收接地信号；或所述第二电极层接收电源信号，所述第一电极层接收接地信号。
  3. 根据权利要求1所述的芯片封装结构，其特征在于，所述基板包括重布线结构，所述重布线结构包括重布线层；所述第一电极层通过所述重布线层与所述芯片电连接；所述第二电极层通过所述重布线层与所述芯片电连接。
  4. 根据权利要求3所述的芯片封装结构，其特征在于，还包括：
    绝缘层，覆盖所述芯片的侧壁和芯片背向基板一侧的表面，且延伸至所述芯片侧部的部分重布线结构表面，所述绝缘层位于所述电容结构与所述芯片之间；
    所述第一电极层位于所述绝缘层和所述电容介质层之间。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，
    所述第一电极层包括第一连接部，所述第一连接部位于芯片的侧部且与所述重布线结构相对设置；
    所述芯片封装结构还包括：第一连接件，所述第一连接件贯穿所述绝 缘层且位于所述第一连接部的底部，所述第一连接件的一端连接所述第一连接部，所述第一连接件的另一端连接所述重布线层。
  6. 根据权利要求4所述的芯片封装结构，其特征在于，
    所述第二电极层包括第二连接部，所述第二连接部位于所述芯片的侧部且与所述重布线结构相对设置；
    所述芯片封装结构还包括：第二连接件，所述第二连接件贯穿所述电容介质层和所述绝缘层且位于所述第二连接部的底部，所述第二连接件的一端连接所述第二连接部，所述第二连接件的另一端连接所述重布线层。
  7. 根据权利要求3所述的芯片封装结构，其特征在于，还包括：焊球，设于所述重布线结构背向所述芯片的一侧。
  8. 根据权利要求7所述的芯片封装结构，其特征在于，所述芯片通过所述重布线层连接所述焊球，所述焊球连接电源模块，所述电源模块用以输出电源信号至部分焊球，所述电源模块用以输出接地信号至部分焊球。
  9. 根据权利要求1所述的芯片封装结构，其特征在于，所述芯片倒装在所述基板上。
  10. 一种封装方法，其特征在于，包括：
    制备基板；
    将芯片贴装在所述基板上；以及
    形成电容结构，形成电容结构的方法包括：形成第一电极层；形成第二电极层；在形成第一电极层的步骤和形成第二电极层的步骤之间，形成电容介质层，所述第一电极层、第二电极层和电容介质层均沿着所述芯片背向所述基板的一侧表面和所述芯片的侧壁延伸。
  11. 根据权利要求10所述的封装方法，其特征在于，所述基板包括重布线结构，所述重布线结构包括重布线层；所述第一电极层通过所述重布线层与所述芯片电连接；所述第二电极层通过所述重布线层与所述芯片电连接。
  12. 根据权利要求11所述的封装方法，其特征在于，在所述形成电容结构步骤之前，还包括：
    形成绝缘层，所述绝缘层覆盖所述芯片的侧壁和芯片背向基板一侧的表面，且延伸至所述芯片侧部的部分重布线结构表面；在所述芯片侧部的绝缘层中形成贯穿所述绝缘层的第一连接件，所述第一连接件的连接所述重布线层；
    在所述形成第一电极层步骤中，所述第一电极层包括第一连接部，所述第一连接部位于芯片的侧部且与所述重布线结构相对设置，所述第一连接部位于所述第一连接件的表面。
  13. 根据权利要求12所述的封装方法，其特征在于，还包括：在所述形成电容介质层的步骤中，所述电容介质层延伸至所述芯片侧部的部分绝缘层表面；
    所述封装方法还包括：在所述芯片侧部形成贯穿电容介质层和绝缘层的第二连接件，所述第二连接件的连接所述重布线层；
    在所述形成第二电极层步骤中，所述第二电极层包括第二连接部，所述第二连接部位于芯片的侧部且与所述重布线结构相对设置，所述第二连接部位于所述第二连接件的表面。
  14. 根据权利要求11所述的封装方法，其特征在于，还包括：制备焊球于所述重布线结构背向所述芯片的一侧。
  15. 根据权利要求10所述的封装方法，其特征在于，将所述芯片贴装 在所述基板上的步骤为：将所述芯片倒装在所述基板上。
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