WO2022252005A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022252005A1
WO2022252005A1 PCT/CN2021/097197 CN2021097197W WO2022252005A1 WO 2022252005 A1 WO2022252005 A1 WO 2022252005A1 CN 2021097197 W CN2021097197 W CN 2021097197W WO 2022252005 A1 WO2022252005 A1 WO 2022252005A1
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WO
WIPO (PCT)
Prior art keywords
spacer
base substrate
display panel
spacers
orthographic projection
Prior art date
Application number
PCT/CN2021/097197
Other languages
English (en)
French (fr)
Inventor
魏锋
胡明
周宏军
杜丽丽
刘聪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001357.XA priority Critical patent/CN115812346B/zh
Priority to EP21943386.9A priority patent/EP4207299A4/en
Priority to US17/755,430 priority patent/US20240196655A1/en
Priority to PCT/CN2021/097197 priority patent/WO2022252005A1/zh
Publication of WO2022252005A1 publication Critical patent/WO2022252005A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • a display panel comprising:
  • Substrate substrate including display area and peripheral area;
  • the sub-pixels include a first electrode, a second electrode and a functional layer between the first electrode and the second electrode;
  • first electrode layer disposed on the base substrate, the first electrodes of the plurality of sub-pixels are located on the first electrode layer;
  • a pixel defining layer disposed on a side of the first electrode layer away from the base substrate, wherein the pixel defining layer includes a pixel defining layer main body, and the pixel defining layer main body includes a first part and a second part, and the pixel defining layer includes a first part and a second part.
  • the first part is located in the display area and includes openings corresponding to the plurality of sub-pixels, the orthographic projection of the opening on the base substrate is located within the orthographic projection of the first electrodes of the plurality of sub-pixels on the base substrate ;
  • the second part is located in the peripheral area, and the second part and the first part are of an integral structure;
  • the spacer layer includes a first spacer repeating unit and a second spacer repeating unit, the first spacer repeating unit is located in the display area, and the second spacer repeating unit located in said peripheral area;
  • the orthographic projection of the second spacer repeating unit on the base substrate is located within the orthographic projection of the second portion of the pixel defining layer on the base substrate, and is located at a position where the second portion is away from the display area.
  • the boundary is close to one side of the display area, and the orthographic projection of the second spacer repeating unit on the substrate does not intersect the orthographic projection of the first electrodes of the plurality of sub-pixels on the substrate stack.
  • the plurality of sub-pixels includes at least one row of edge sub-pixels closest to the peripheral region, and at least part of the orthographic projection of the second spacer repeat unit on the base substrate is located at The orthographic projection of the first electrode of the at least one row of edge sub-pixels on the base substrate is away from the side of the display area.
  • the spacer layer includes a plurality of first spacer repeating units and a plurality of second spacer repeating units, a plurality of first spacer repeating units and a plurality of The second spacer repeating units are arranged in an array along the first direction and the second direction.
  • the orthographic projection of the second spacer repeating unit on the base substrate does not overlap the orthographic projection of the first electrode layer on the base substrate.
  • the plurality of sub-pixels are arranged in an array along a first direction and a second direction;
  • the first spacer repeating unit includes a first spacer and a third spacer, and the first spacer repeat unit includes a first spacer and a third spacer.
  • a spacer and the third spacer are located in different columns, a column of first spacers corresponds to a column of sub-pixels, and a column of second spacers corresponds to another column of sub-pixels;
  • the repeating unit of the second spacer includes the first Two spacers and a fourth spacer; and for a plurality of first spacer repeating units and a plurality of second spacer repeating units positioned in the same row along the first direction, the first spacer repeating unit Both the first spacer and the third spacer of the repeating unit of the second spacer and the second spacer and the fourth spacer of the repeating unit of the second spacer are located in the same row.
  • the repeating unit of the first spacer further includes a fifth spacer, the third spacer and the fifth spacer are alternately arranged in a row; the second spacer The spacer repeating unit further includes a sixth spacer, the fourth spacer and the sixth spacer are alternately arranged in a row; and for a plurality of first spacer repeating units located in the same row along the second direction and a plurality of second spacer repeating units, the third spacer and the fifth spacer of each first spacer repeating unit and the fourth spacer and the fifth spacer of each second spacer repeating unit All six spacers are located in the same column.
  • the fifth spacer of each first spacer repeat unit The spacers are located in the same row as the sixth spacers of each second spacer repeating unit.
  • the first spacer of each first spacer repeat unit is located in the same column as the second spacer of each second spacer repeating unit.
  • the display panel further includes a driving voltage lead disposed on the base substrate and located in the peripheral region, the driving voltage lead is used to provide a driving voltage;
  • the base substrate includes at least one corner portion, the driving voltage lead includes a plurality of steps in the at least one corner portion; and at least some of the plurality of second spacer repeating units are on the substrate
  • the orthographic projection on the substrate overlaps the orthographic projection of the plurality of steps of the driving voltage leads on the base substrate, and the at least some second spacer repeating units are distributed in steps.
  • the plurality of steps formed by the at least some second spacer repeat units are respectively Located at multiple steps of the driving voltage leads.
  • the plurality of steps includes a first step and a second step; and both the first step and the second step extend along a first direction, and the first step extends along the first direction
  • the size is larger than the size of the second step along the first direction, and the number of second spacer repeating units overlapping with one of the first steps and located in the same row is greater than that of the second spacer repeating unit overlapping with one of the second steps and located in the same row.
  • the number of second spacer repeating units in the row; and/or, both the first step and the second step extend along the second direction, and the size of the first step along the second direction is larger than that of the second step.
  • the size of the step along the second direction, the number of repeating units of the second spacer overlapping with one of the first steps and located in the same column is larger than the second spacer overlapping with one of the second steps and located in the same column number of repeating units.
  • the plurality of second spacer repeat units include A row of second spacer repeating units in the display area and located on one side of the display area, the row of second spacer repeating units is arranged along a straight line parallel to the second direction;
  • the plurality of second spacer repeating units include a row of the second spacer repeating unit that is farthest from the display area in the second direction and located on one side of the display area. Two spacer repeating units, the row of second spacer repeating units are arranged along a straight line parallel to the first direction.
  • the display panel further includes a first data lead and a second data lead disposed on the base substrate and located in the peripheral region, the first data lead is used to provide a A sub-pixel provides data signals, and the second data wiring is used to provide data signals to a column of second sub-pixels; and at least one column of second spacers arranged adjacent to the first data wiring and the second data wiring is repeated
  • the unit includes a row of spacers, the row of spacers includes alternately arranged second spacers and fourth spacers, and more than 50% of the orthographic projection of the row of spacers on the base substrate The part is located between the straight line extending of the first data lead and the straight line extending of the second data lead in the first direction.
  • the display panel further includes a third data lead disposed on the base substrate and located in the peripheral region, the third data lead is used to provide data to a column of third sub-pixels signal; and at least one column of second spacer repeating units disposed adjacent to the third data lead includes a column of sixth spacer, the orthographic projection of the third data lead on the base substrate extending through the An orthographic projection of at least one of a row of sixth spacers on the base substrate.
  • an orthographic projection of at least one of the row of sixth spacers on the base substrate is symmetrical with respect to an orthographic projection of the third data lead on the base substrate.
  • the display panel further includes: a scanning driving circuit disposed on the base substrate and in the peripheral region, the scanning driving circuit is used to output scanning signals; and disposed on the A plurality of load compensation units on the base substrate and located in the peripheral region, the plurality of load compensation units are located between the scan drive circuit and the plurality of pixel units, wherein at least some second spacers An orthographic projection of the repeating unit on the substrate substrate falls within an orthographic projection of the plurality of load compensation cells on the substrate substrate.
  • the orthographic projection of the second spacer repeating unit on the base substrate and the orthographic projection of the boundary of the pixel defining layer main body on the base substrate are separated by a prescribed distance.
  • the predetermined distance is 20-300 microns.
  • the second spacer repeating units there is a first interval distance between the second spacers adjacent along the second direction, and There is a second spacing distance between adjacent fourth spacers, and the second spacing distance is greater than the first spacing distance.
  • the width of the second spacer in the second direction is greater than the width of the fourth spacer in the second direction; and/or, the second spacer The width in one direction is not smaller than the width in the first direction of the fourth spacer.
  • an area of an orthographic projection of the sixth spacer on the base substrate is different from an area of an orthographic projection of the first spacer on the base substrate.
  • the column of the second spacer and the column of the fourth spacer are arranged alternately along the first direction; and/or, the second spacer and the fourth spacer The spacers are alternately arranged in a straight line along the first direction; and/or, the fourth spacers and the sixth spacers are alternately arranged in a row.
  • the ratio of the area of the orthographic projection of the first spacer on the base substrate to the area of the orthographic projection of the second spacer on the base substrate is 0.8 ⁇ 1.2; and/or, the ratio of the area of the orthographic projection of the third spacer on the base substrate to the area of the orthographic projection of the fourth spacer on the base substrate is 0.8 ⁇ 1.2; and/or, the ratio of the area of the orthographic projection of the fifth spacer on the base substrate to the area of the orthographic projection of the sixth spacer on the base substrate is 0.8 ⁇ 1.2.
  • the first spacer and the second spacer adjacent along the first direction there is a third spacing distance between them, there is a fourth spacing distance between the third spacer and the fourth spacer adjacent along the first direction, and the fifth spacer and the sixth spacer adjacent along the first direction There is a fifth spacing distance between the spacers; and the ratio of the spacing distance between two adjacent second spacers along the first direction to the third spacing distance is 0.8-1.2; and/or, along the first direction
  • the ratio of the separation distance between two adjacent fourth spacers in one direction to the fourth separation distance is 0.8-1.2; and/or, the distance between two adjacent sixth spacers along the first direction
  • a ratio of the interval distance between them to the fifth interval distance is 0.8 ⁇ 1.2.
  • At least one second spacer repeating unit is provided on opposite sides of a row of first spacer repeating units along the first direction; and/or, in a row of first spacer repeating units Along opposite sides of the second direction, at least two second spacer repeating units are arranged respectively.
  • the orthographic projection of a part of the boundary of the pixel defining layer body on the base substrate is located on the base substrate of the scan driving circuit. Between the orthographic projection of the load compensation unit on the base substrate, the orthographic projection of another part of the boundary of the pixel defining layer body on the base substrate falls into the scan driving circuit In orthographic projection on the substrate substrate.
  • the display panel further includes:
  • a packaging structure disposed on a side of the support portion away from the base substrate and located in the peripheral region
  • the orthographic projection of the support portion on the base substrate is located on a side away from the display area of the orthographic projection of the boundary of the main body of the pixel defining layer on the base substrate.
  • the support portion includes a support body portion, a plurality of openings or grooves and a plurality of conductive portions, the plurality of openings or grooves are located in the support body portion, the plurality of The conductive part is located on a side of the supporting main part close to the display area.
  • the display panel further includes a first voltage lead and an auxiliary conductive part, the first voltage lead is used to provide a first voltage, and the auxiliary conductive part is located on the same layer as the first electrode; And a part of the auxiliary conductive portion is in direct contact with the first voltage lead.
  • the pixel defining layer further includes a first covering portion and a second covering portion;
  • the display panel further includes a planarization layer, and the planarization layer is located on the first electrode layer close to the substrate
  • the auxiliary conductive part includes a plurality of openings, the plurality of openings respectively expose a part of the planarization layer; and the first covering part covers the plurality of openings, the The second covering part covers the edge of the auxiliary conductive part away from the display area.
  • a display device which includes the above-mentioned display panel.
  • FIG. 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure
  • FIG. 2 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, which schematically shows a pixel unit and a load compensation unit included in the display panel;
  • FIG. 3 is a cross-sectional view of a display device taken along line AA' in FIG. 1 according to some exemplary embodiments of the present disclosure
  • Fig. 4 is a partial enlarged view of part I in Fig. 1;
  • Fig. 5 is a partially enlarged view of part VII in Fig. 4;
  • FIG. 6 is a schematic diagram of the distribution of spacers according to some exemplary embodiments of the present disclosure.
  • Fig. 7 is a partially enlarged view of part VIII in Fig. 4;
  • FIG. 8 to 23 are plan views illustrating some film layers of an exemplary embodiment of part I in FIG. 1, wherein FIG. 8 schematically shows a semiconductor layer, and FIG. 9 schematically shows a first conductive layer, Figure 10 schematically shows the combination of the semiconductor layer and the first conductive layer, Figure 11 schematically shows the second conductive layer, and Figure 12 schematically shows the combination of the semiconductor layer, the first conductive layer and the second conductive layer , Figure 13A schematically shows an interlayer insulating layer, Figure 13B schematically shows a combination of a semiconductor layer, a first conductive layer, a second conductive layer and an interlayer insulating layer, and Figure 14 schematically shows a third conductive layer layer, Figure 15 schematically shows the combination of the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer and the third conductive layer, Figure 16 schematically shows the planarization layer, and Figure 17 schematically shows Showing the combination of semiconductor layer, first conductive layer, second conductive layer, interlayer insulating layer, third
  • FIG. 18 schematically shows the first electrode layer
  • Fig. 19 schematically shows A combination of a semiconductor layer, a first conductive layer, a second conductive layer, an interlayer insulating layer, a third conductive layer, a planarization layer, and a first electrode layer.
  • FIG. 20 schematically shows a pixel defining layer
  • FIG. 21 schematically shows Figure 22 schematically shows the combination of the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer, the third conductive layer, the planarization layer, the first electrode layer and the pixel defining layer.
  • layer Figure 23 schematically shows the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer, the third conductive layer, the planarization layer, the first electrode layer, the pixel defining layer and the spacer layer combination;
  • FIG. 24 is a cross-sectional view of the display panel taken along line BB' in FIG. 23 according to some exemplary embodiments of the present disclosure
  • FIG. 25A is a partially enlarged view of a display panel at part II in FIG. 1 according to some disclosed exemplary embodiments;
  • Figure 25B is a partially enlarged view of Figure 25A;
  • FIG. 26 is a partially enlarged view of a display panel at part III in FIG. 1 according to some disclosed exemplary embodiments;
  • FIG. 27 is a partially enlarged view of a display panel at part IV in FIG. 1 according to some disclosed exemplary embodiments;
  • FIG. 28 is a partially enlarged view of a display panel at part V in FIG. 1 according to some disclosed exemplary embodiments;
  • Figure 29 is a partially enlarged view of Figure 28;
  • FIG. 30 is a partially enlarged view of a display panel at part VI in FIG. 1 according to some disclosed exemplary embodiments;
  • FIG. 31 is an equivalent circuit diagram of a pixel driving circuit of a display panel according to some exemplary embodiments of the present disclosure.
  • FIG. 33 is an equivalent circuit diagram of one scan driving circuit of a display panel according to some exemplary embodiments of the present disclosure.
  • connection may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense.
  • the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first means for describing various components, components, elements, regions, layers and/or sections
  • these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another.
  • a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.
  • spatially relative terms such as “upper,” “lower,” “left,” “right,” etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression “the same layer” refers to the formation of a film layer for forming a specific pattern using the same film-forming process, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or parts located on the "same layer” are made of the same material and formed by the same patterning process. Usually, multiple elements, components, structures and/or parts located on the "same layer” Or parts have approximately the same thickness.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • the display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels arranged in the display area, the sub-pixels include a first electrode, a second electrode and a A functional layer between the second electrodes; a first electrode layer disposed on the base substrate, the first electrodes of the plurality of sub-pixels are located on the first electrode layer; disposed on the first electrode
  • spacers are provided in the display area, but also spacers are provided in the peripheral area.
  • all The above-mentioned mask plate is supported more in the peripheral area, which prevents the mask plate from being depressed in the peripheral area due to force, thereby avoiding the displacement of the vapor deposition position of the organic material. Therefore, the occurrence of color mixing can be avoided.
  • the spacers are closer to the peripheral packaging area, thereby avoiding the generation of Newton's rings.
  • FIG. 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure.
  • Fig. 2 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, which schematically shows a pixel unit and a load compensation unit included in the display panel.
  • the display device 1000 may include a display panel.
  • the display panel may include a base substrate 10, and the base substrate 10 may include a display area AA and a peripheral area NA located at least one side of the display area.
  • the peripheral area NA surrounds the display area AA, however, embodiments of the present disclosure are not limited thereto. In other embodiments, the peripheral area NA may be located at the edge of the display area AA. At least one side, but not surrounding said display area AA.
  • the display panel may include a plurality of pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit for displaying an image.
  • the pixel unit P may include a light emitting device emitting white light and/or colored light.
  • a plurality of pixel units P may be arranged in an array along rows extending in a first direction (eg, a row direction) X and columns extending in a second direction (eg, a column direction) Y.
  • a first direction eg, a row direction
  • a second direction eg, a column direction
  • Y a second direction
  • embodiments of the present disclosure do not specifically limit the arrangement form of the pixel units P, and the pixel units P may be arranged in various forms.
  • the pixel units P may be arranged such that a direction inclined with respect to the first direction X and the second direction Y becomes a column direction, and such that a direction crossing the column direction becomes a row direction.
  • One pixel unit P may include a plurality of sub-pixels.
  • one pixel unit P may include 3 sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3.
  • one pixel unit P may include 4 sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel.
  • the first sub-pixel SP1 may be a red sub-pixel
  • the second sub-pixel SP2 may be a green sub-pixel
  • the third sub-pixel SP3 may be a blue sub-pixel
  • the fourth sub-pixel may be a white sub-pixel.
  • Each sub-pixel may include a light emitting element and a pixel driving circuit for driving the light emitting element.
  • the first sub-pixel SP1 may include a first light-emitting element and a first pixel driving circuit for driving the first light-emitting element, and the first light-emitting element may emit red light
  • the second sub-pixel SP2 may include a second light-emitting element and a second pixel driving circuit for driving the second light emitting element, the second light emitting element can emit green light
  • the third sub-pixel SP3 can include a third light emitting element and a third pixel driving circuit for driving the third light emitting element, The third light emitting element may emit blue light.
  • a light-emitting element of a sub-pixel may include an anode, a light-emitting material layer, and a cathode that are stacked.
  • the light emitting region of the sub-pixel may be a region corresponding to a portion of the light emitting material layer sandwiched in front of and in contact with the anode and the cathode.
  • a pixel defining layer is formed on the anode, the pixel defining layer has an opening to expose at least part of the anode, the luminescent material layer is at least partially formed in the opening of the pixel defining layer, and a cathode is formed on it, and the light emitting area of the sub-pixel can be defined by the pixel.
  • the area defined by the layer opening may include, for example, one or more layers of a hole injection layer, a hole transport layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. It also includes other functional film layers, where the layers may include organic materials or inorganic materials such as quantum dots.
  • the display panel may include a load compensation unit 100, a test circuit 200, a scan driving circuit 300, a multiplexer 400, and the like located in the peripheral area NA.
  • the display area AA may include a first border AA1 , a second border AA2 , a third border AA3 , and a fourth border AA4 connected in sequence (for example, an upper border, a lower border, a left border, and a right border).
  • the orthographic projection of the display area AA on the base substrate 10 may be in the shape of a rounded rectangle.
  • the four rounded corners of the rounded rectangle may be referred to as a first rounded corner portion 10A, a second rounded corner portion 10B, a third rounded corner portion 10C and a fourth rounded corner portion 10D.
  • the first rounded corner 10A can be located at the upper left corner in FIG. 1
  • the second rounded corner 10B can be located at the upper right corner in FIG. 1
  • the third rounded corner 10C can be located at the lower left corner in FIG. 1
  • the fourth rounded portion 10D may be located at the lower right corner in FIG. 1 .
  • the test circuit 200 may be located on a side adjacent to the first border AA1 in the peripheral area NA, and the test circuit 200 is disposed opposite to the first border AA1 , the first rounded corner portion 10A, and the second rounded corner portion 10B.
  • the test circuit 200 may include a plurality of test pins (described below), and the plurality of test pins may be used to provide test signals, for example, the test signals may include a plurality of The data signal of the pixel unit P.
  • the multiplexer 400 may be located on a side adjacent to the second boundary AA2 in the peripheral area NA, and the multiplexer 400 is disposed opposite to the second boundary AA2, the third rounded corner portion 10C, and the fourth rounded corner portion 10D.
  • the multiplexer 400 can time-divisionally multiplex the signal lines in the routing area.
  • the display panel includes an integrated circuit IC disposed in the peripheral area NA and a wiring area 500 between the integrated circuit IC and the multiplexer 400 .
  • Various signals output by the integrated circuit IC are transmitted to the multiplexer 400 through the signal lines in the wiring area 500 .
  • each signal is output to each pixel unit P in the display area AA.
  • the scan driving circuit 300 may be located at a side adjacent to the third boundary AA3 in the peripheral area NA and at a side adjacent to the fourth boundary AA4 in the peripheral area NA. It should be noted that although it is shown in FIG. 1 that the driving circuits are located on the left and right sides of the display area AA, embodiments of the present disclosure are not limited thereto, and the driving circuits may be located at any suitable position in the peripheral area NA.
  • the scanning driving circuit 300 may include at least one of a gate scanning driving circuit and a light emission control scanning driving circuit.
  • the gate scanning driving circuit and the light emitting control scanning driving circuit may adopt GOA technology, that is, the scanning driving circuit 300 may include at least one of Gate GOA and EM GOA.
  • the gate drive circuit and the light emission control scan drive circuit are directly arranged on the array substrate instead of an external drive chip.
  • Each GOA unit is used as a first-level shift register, and each level of shift register is electrically connected to a gate line or light-emitting control line, and the turn-on voltage is sequentially output through each level of shift register to realize progressive scanning of pixels.
  • each stage of the shift register can also be connected to multiple gate lines or multiple light emitting control lines. In this way, the development trend of high resolution and narrow frame of the display panel can be adapted.
  • the display panel may include a plurality of load compensation units 100 . As shown in FIGS. 1 and 2 , some of the plurality of load compensation units 100 are located adjacent to the first fillet 10A in the peripheral area NA, and others of the plurality of load compensation units 100 are located adjacent to the first fillet portion 10A in the peripheral area NA. The position of the second fillet 10B. A plurality of load compensation units 100 are located between the test circuit 200 and the display area AA.
  • each sub-pixel SP1, SP2 or SP3 may include a light emitting element and a pixel driving circuit for driving the light emitting element.
  • the light-emitting device may include a first electrode, a second electrode, and a layer of light-emitting material between the first electrode and the second electrode
  • the pixel driving circuit may include elements such as transistors and capacitors, and the pixel driving circuit may receive signals provided on the display panel. The signal of the line generates the current for driving the light-emitting device, and by connecting with one of the first electrode or the second electrode, the purpose of driving the light-emitting device to emit light is realized.
  • the pixel driving circuit is disposed on the base substrate, and the light emitting device is located on a side away from the pixel driving circuit from the base substrate.
  • the pixel driving circuit may include common circuit structures such as 7T1C, 7T2C, 8T2C or 4T1C in the art.
  • the light emitting element may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • FIG. 3 is a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure, taken along line AA' in FIG. 1 .
  • the display device may further include a cover plate 20 , a packaging structure 30 and a spacer PS.
  • the cover plate 20 is disposed opposite to the base substrate 10 .
  • Both the package structure 30 and the spacer PS are disposed between the base substrate 10 and the cover plate 20 .
  • at least some spacers PS are disposed in the display area AA to support the cover plate 20 and form a space to be packaged between the base substrate 10 and the cover plate 20 .
  • the encapsulation structure 30 is disposed in the peripheral area NA.
  • the encapsulation structure 30 may be disposed around the display area AA to prevent water vapor, oxygen, etc. from intruding into the light emitting elements in the display area AA.
  • the encapsulation structure 30 may include Frit (glass frit).
  • FIG. 4 is a partially enlarged view of part I in FIG. 1.
  • the arrangement of some spacers PS and a plurality of sub-pixels SP1, SP2, and SP3 is schematically shown, while other structures are omitted, and other structures will be It will be described in detail below with reference to the accompanying drawings.
  • the display panel further includes a pixel defining layer located on the side of the first electrode away from the pixel driving circuit, the pixel defining layer includes a plurality of openings, and each sub-pixel corresponds to at least one pixel defining layer opening (for example, one), and the sub-pixel
  • the actual light-emitting area or display area of the sub-pixel is roughly equivalent to the opening of the pixel defining layer corresponding to the sub-pixel.
  • the area of the pixel defining layer opening or the actual light-emitting area corresponding to each sub-pixel is smaller than the area of the first electrode, and the projection on the base substrate is completely within the projection of the first electrode on the base substrate.
  • FIG. 4 only the approximate positions and shapes of the openings of the pixel defining layer of the sub-pixels are shown in FIG. 4 to represent the distribution of each sub-pixel.
  • the arrangement of sub-pixels in each pixel repeating unit can refer to the conventional pixel arrangement, such as RGB, GGRB, RGBG, RGB, etc., the embodiments of the present disclosure No limit.
  • the boundary of the display area AA is schematically shown, which may be a part of the boundary AA3 in FIG. 1 , for example.
  • a part of the spacers PS is located inside the display area AA, and another part of the spacers PS is located outside the display area AA.
  • the display panel may include a first spacer repeat unit PSX1 located within the display area AA and a second spacer repeat unit PSX2 located outside the display area AA.
  • the first spacer repeating unit PSX1 includes at least one spacer
  • the second spacer repeating unit PSX2 includes at least one spacer.
  • spacers are added around the periphery of the display area AA, so that the spacers are closer to the packaging structure 30 , so that the packaging structure 30 has more supporting force. Therefore, the non-uniform height of the packaging structure 30 due to external forces is avoided, thereby reducing the occurrence rate of Newton rings, which is beneficial to improving the display effect of the display device. Moreover, by adding spacers around the periphery of the display area AA, the edge of the display area AA can get more supporting force.
  • FIG. 5 is a partially enlarged view of part VII in FIG. 4
  • FIG. 6 is a schematic distribution diagram of spacers according to some exemplary embodiments of the present disclosure. For the convenience of illustration and description, only the positions and shapes of the pixel defining layer opening and the anode of the sub-pixel are shown in FIG. 5 .
  • the plurality of sub-pixels may include a first sub-pixel SP1 and a second sub-pixel SP2 adjacent along the second direction Y.
  • the first sub-pixel SP1 includes a first anode YG1 and a first sub-pixel opening KK1
  • the second sub-pixel SP2 includes a second anode YG2 and a second sub-pixel opening KK2.
  • the display panel may include a plurality of pixel repeating units PX.
  • Each pixel repeating unit PX may include at least one first sub-pixel SP1 and at least one second sub-pixel SP2.
  • each pixel repeating unit PX includes a first sub-pixel SP1 and a second sub-pixel SP2 adjacent along the second direction Y.
  • the first sub-pixel SP1 is a red sub-pixel
  • the second sub-pixel SP2 is a green sub-pixel
  • the red sub-pixel and the green sub-pixel are adjacent along the second direction Y.
  • the pixel repeating unit PX may further include at least one third sub-pixel SP3.
  • the pixel repeating unit may include one third sub-pixel SP3.
  • the third subpixel SP3 includes a third anode YG3 and a third subpixel opening KK3.
  • the connecting lines between the anodes of the adjacent first sub-pixel SP1 , second sub-pixel SP2 and third sub-pixel SP3 form a triangle.
  • the first sub-pixel SP1 is a red sub-pixel
  • the second sub-pixel SP2 is a green sub-pixel
  • the third sub-pixel SP3 is a blue sub-pixel.
  • the red sub-pixel, the green sub-pixel and the blue sub-pixel The connecting lines between the anodes in the pixels form a triangle.
  • the orthographic projection of the sub-pixel opening on the base substrate 10 is located within the orthographic projection of the anode on the base substrate 10 .
  • the orthographic projection of the sub-pixel opening on the base substrate 10 is a rectangle.
  • the orthographic projections of the subpixel openings in the first subpixel SP1 and the second subpixel SP2 on the base substrate 10 are both rectangular.
  • the first sub-pixel SP1 is a red sub-pixel
  • the second sub-pixel SP2 is a green sub-pixel
  • the third sub-pixel SP3 is a blue sub-pixel
  • the orthographic projections of the base substrate 10 are all rectangular.
  • the area of the sub-pixel opening in the third sub-pixel SP3 is larger than the area of the sub-pixel opening in the second sub-pixel SP2, and the area of the sub-pixel opening in the second sub-pixel SP2 is larger than that of the second sub-pixel SP2.
  • the first sub-pixel SP1 is a red sub-pixel
  • the second sub-pixel SP2 is a green sub-pixel
  • the third sub-pixel SP3 is a blue sub-pixel
  • the area of the sub-pixel opening KK3 in the blue sub-pixel is larger than that in the green sub-pixel.
  • the area of the sub-pixel opening KK2 in the green sub-pixel is larger than the area of the sub-pixel opening KK1 in the red sub-pixel.
  • the area of the sub-pixel opening in each sub-pixel can be inversely proportional to the luminous lifetime of the sub-pixel, for example, the luminous lifetime of the red sub-pixel is greater than the luminous lifetime of the green sub-pixel is greater than the luminous lifetime of the blue sub-pixel, then
  • the area of the sub-pixel opening in the blue sub-pixel can be set larger than the area of the sub-pixel opening in the green sub-pixel, and the area of the sub-pixel opening in the green sub-pixel is larger than the area of the sub-pixel opening in the red sub-pixel.
  • a plurality of first spacer repeating units PSX1 may be arranged on the substrate in an array along the first direction X and the second direction Y. on the substrate 10.
  • a first spacer repeating unit PSX1 may include at least one first spacer PS11, at least one third spacer PS12, and at least one fifth spacer PS13, for example, a first spacer repeating unit PSX1 may include a first spacer PS11 , a third spacer PS12 and a fifth spacer PS13 .
  • the first spacer PS11 and the third spacer PS12 are located in different columns.
  • a column of first spacers PS11 corresponds to a column of sub-pixels
  • a column of third spacers PS12 corresponds to another column of sub-pixels.
  • the number of sub-pixels in the column where the first spacer PS11 is located is different from the number of sub-pixels in the column where the third spacer PS12 is located.
  • a column of first spacers PS11 corresponds to anodes in one column of sub-pixels
  • a column of third spacers PS12 corresponds to anodes in another column of sub-pixels.
  • the number of anodes in the column where the first spacer PS11 is located is different from the number of anodes in the column where the third spacer PS12 is located.
  • the anode of at least one sub-pixel in the sub-pixel corresponding to the first spacer PS11 extends along the second direction Y, and the first spacer PS11 and the third spacer PS12 extend along the The first direction X extends.
  • the first spacers PS11 and the corresponding sub-pixels are arranged alternately and repeatedly along the second direction Y and are in one-to-one correspondence.
  • the orthographic projection of the first spacer PS11 in the second direction Y does not overlap with the orthographic projection of the anode in each sub-pixel in the second direction Y.
  • the area of the first spacer PS11 for example, the area of the orthographic projection of the first spacer PS11 on the base substrate 10
  • the area of the opening of the corresponding sub-pixel for example, the area of the sub-pixel has a first ratio between the area of the orthographic projection of the base substrate 10.
  • the area of the third spacer PS12 for example, the area of the orthographic projection of the third spacer PS12 on the base substrate 10
  • the first ratio is a value obtained by dividing the area of the first spacer PS11 by the area of the opening of the corresponding sub-pixel.
  • the second ratio is a value obtained by dividing the area of the third spacer PS12 by the sum of the areas of openings of all sub-pixels between two adjacent third spacers PS12 in the second direction Y.
  • the first ratio is a value obtained by dividing the area of the first spacer PS11 by the area of the opening KK3 in the third sub-pixel SP3.
  • the second ratio is a value obtained by dividing the area of the third spacer PS12 by the sum of the areas of the openings of the first sub-pixel SP1 and the second sub-pixel SP2 .
  • the area ratio of the adjacent first spacers PS11 along the second direction Y is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projection of the adjacent first spacers PS11 along the second direction Y on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of the adjacent first spacers PS11 along the second direction Y is 0.9 ⁇ 1.1.
  • an area ratio of the first spacers PS11 adjacent in the second direction Y may be 0.8.
  • the area ratio of the first spacers PS11 adjacent in the second direction Y may also be 0.9.
  • the area ratio of the first spacers PS11 adjacent in the second direction Y may also be 1.0.
  • the area ratio of the first spacers PS11 adjacent in the second direction Y may also be 1.1.
  • the area ratio of the first spacers PS11 adjacent in the second direction Y may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • FIG. 5 and FIG. 6 there is a distance HG1 between the first spacers PS11 adjacent along the second direction Y, and there is a distance HG1 between the third spacers PS12 adjacent along the second direction Y.
  • the distance HG3 may be substantially equal to the distance HG2.
  • the separation distance HG3 is greater than the separation distance HG1.
  • the interval distance HG1 may be a minimum distance between boundaries of adjacent first spacers PS11 along the second direction Y.
  • the gap distance HG2 may be a minimum distance between borders of adjacent third spacers PS12 in the second direction Y.
  • the gap distance HG3 may be a minimum distance between boundaries of adjacent fifth spacers PS13 in the second direction Y.
  • first spacer repeating unit PSX1 there is a separation distance HG4 between the third spacer PS12 and the fifth spacer PS13 adjacent along the second direction Y.
  • separation distance HG4 there is a separation distance between the third spacer PS12 and the fifth spacer PS13 adjacent in the second direction Y.
  • the ratio of the separation distance HG4 to the separation distance HG5 is 0.8 ⁇ 1.2, for example, the separation distance HG4 may be substantially equal to the separation distance HG5.
  • the spacing distances HG4 , HG5 may be the minimum distance between boundaries of the third spacer PS12 and the fifth spacer PS13 adjacent along the second direction Y.
  • the ratio of the separation distance HG2 to the separation distance HG4 or HG5 may be 0.3 ⁇ 0.5.
  • the ratio of the separation distance HG2 to the separation distance HG4 or HG5 may be 0.4 ⁇ 0.48.
  • the ratio of the separation distance HG2 to the separation distance HG4 or HG5 may be 0.4.
  • the ratio of the separation distance HG2 to the separation distance HG4 or HG5 may be 0.45.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the width of the first spacer PS11 in the second direction Y is greater than the width of the third spacer PS12 in the second direction Y; and the first spacer PS11 is The width in the first direction X is not less than the width in the first direction X of the third spacer PS12. In this way, the area of the orthographic projection of the first spacer PS11 on the base substrate 10 can be made larger than the area of the orthographic projection of the third spacer PS12 on the base substrate 10 .
  • the sub-pixels corresponding to the third spacer PS12 may include a first sub-pixel SP1 and a second sub-pixel SP2 .
  • an anode YG1 of a first sub-pixel SP1 and an anode YG2 of a second sub-pixel SP2 are disposed between adjacent third spacers PS12 along the second direction Y.
  • the adjacent third spacers PS12 along the second direction Y may be separated by the anode YG1 of one first sub-pixel SP1 and the anode YG2 of one second sub-pixel SP2.
  • the sub-pixel corresponding to the first spacer PS11 includes the third sub-pixel SP3 .
  • an anode YG3 of a third sub-pixel SP3 is disposed between adjacent first spacers PS11 along the second direction Y.
  • the adjacent first spacers PS11 along the second direction Y are separated by the anode YG3 of one third sub-pixel SP3.
  • the column where the first spacer PS11 is located and the column where the third spacer PS12 is located are alternately arranged along the first direction X; and the first spacer PS11 and the third spacer The objects PS12 are alternately arranged in a straight line along the first direction X.
  • the first spacers PS11 and the third spacers PS12 can be alternately arranged in the first direction X and the second direction Y, so that the arrangement can be as uniform as possible.
  • a plurality of fifth spacers PS13 may be spaced apart from the first spacers PS11 and the third spacers PS12 .
  • the area of the fifth spacer PS13 is different from that of the first spacer PS11.
  • the orthographic projection of the fifth spacer PS13 in the second direction Y does not overlap the orthographic projections of the first spacer PS11 and the third spacer PS12 in the second direction Y.
  • the third spacers PS12 and the fifth spacers PS13 are alternately arranged in a row, and the adjacent third spacers PS12 and fifth spacers PS13 are arranged There is a sub-pixel in the body part.
  • a fifth spacer PS13 in the second direction Y, has two adjacent third spacers PS12, and one of the two third spacers PS12 is located on the fifth spacer PS13. above, and another below the fifth spacer PS13.
  • the main part of the anode YG1 of the first sub-pixel SP1 is disposed between the fifth spacer PS13 and the third spacer PS12 above it, and the fifth spacer PS13 and the third spacer PS12 below it are arranged.
  • a main part of the anode YG2 of the second sub-pixel SP2 is disposed between the three spacers PS12.
  • the third ratio may be 0.8 ⁇ 1.2.
  • the third ratio may also be set to be 0.9 ⁇ 1.1.
  • the third ratio can be made 0.8. It is also possible to make the third ratio 0.9. It is also possible to make the third ratio 1.0. It is also possible to make the third ratio 1.1. It is also possible to make the third ratio 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the orthographic projection of the fifth spacer PS13 on the base substrate 10 and the orthographic projection of the via hole VH1 in the first sub-pixel SP1 on the base substrate 10 have at least an intersection. overlapping area.
  • the orthographic projection of the fifth spacer PS13 on the base substrate 10 may cover the orthographic projection of the via hole VH1 in the first sub-pixel SP1 on the base substrate 10 .
  • the fourth ratio may be a value obtained by dividing the width of the fifth spacer PS13 in the second direction Y by the width of the opening of the first sub-pixel SP1 in the second direction Y.
  • the fourth ratio may be 0.4 ⁇ 0.8.
  • the fourth ratio may also be set to be 0.5 ⁇ 0.7.
  • the fourth ratio can be made 0.4. It is also possible to make the fourth ratio 0.5. It is also possible to make the fourth ratio 0.6. It is also possible to make the fourth ratio 0.7. It is also possible to make the fourth ratio 0.8.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the fifth ratio may be a value obtained by dividing the width of the third spacer PS12 in the second direction Y by the width of the opening in the second sub-pixel SP2 in the second direction Y.
  • the fifth ratio may be 0.4 ⁇ 0.8.
  • the fifth ratio can be 0.5 ⁇ 0.7.
  • the fifth ratio may be 0.4. It is also possible to make the fifth ratio 0.5. It is also possible to make the fifth ratio 0.6. It is also possible to make the fifth ratio 0.7. It is also possible to make the fifth ratio 0.8.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the ratio between the second distance HW2 and the third distance HW3 can be set to be 0.8 ⁇ 1.2.
  • the ratio between the second distance HW2 and the third distance HW3 can also be set to be 0.9 ⁇ 1.1.
  • the ratio between the second pitch HW2 and the third pitch HW3 may be 0.8. It is also possible to make the ratio between the second pitch HW2 and the third pitch HW3 be 0.9. It is also possible to make the ratio between the second pitch HW2 and the third pitch HW3 1.0. It is also possible to make the ratio between the second pitch HW2 and the third pitch HW3 1.1. It is also possible to make the ratio between the second pitch HW2 and the third pitch HW3 be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the ratio between the fourth distance HW4 and the fifth distance HW5 may be 0.8 ⁇ 1.2.
  • the ratio between the fourth pitch HW4 and the fifth pitch HW5 can also be set to be 0.9 ⁇ 1.1.
  • the ratio between the fourth pitch HW4 and the fifth pitch HW5 may be 0.8. It is also possible to make the ratio between the fourth pitch HW4 and the fifth pitch HW5 0.9. It is also possible to make the ratio between the fourth pitch HW4 and the fifth pitch HW5 1.0. It is also possible to make the ratio between the fourth pitch HW4 and the fifth pitch HW5 1.1. It is also possible to make the ratio between the fourth pitch HW4 and the fifth pitch HW5 be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the fifth spacer PS13, the via hole VH1 in the first subpixel SP1, the via hole VH2 in the second subpixel SP2, and the third subpixel SP3 The via holes VH3 in are arranged on the same straight line.
  • the shape of the above-mentioned via holes and each through hole can be rectangle, rounded rectangle, circle, ellipse, square, hexagon, octagon, etc., which can be designed according to the requirements of practical applications. It is not limited here.
  • a plurality of first spacer repeating units PSX1 are arranged in an array along the first direction X and the second direction Y within the display area AA.
  • the third spacers PS12 and the fifth spacers PS13 are alternately arranged in a row, the first spacers PS11 and the third spacers PS12 are located in different rows, and a plurality of first spacers PS11 are repeatedly arranged in a row, And the columns where the third spacers PS12 and the fifth spacers PS13 are located are alternately arranged along the first direction X with the columns where the first spacers PS11 are located.
  • a plurality of second spacer repeating units PSX2 are arranged outside the display area AA, that is, in the peripheral area NA.
  • the outermost row of pixel repeating units for example, a row of pixel repeating units near the third border AA3 or a row of pixel repeating units near the fourth border AA4
  • at least one column of second spacer repeating units PSX2 is provided.
  • At least one second spacer repeating unit PSX2 is provided on the side away from the third boundary AA3, and at least one second spacer repeating unit PSX2 is provided on the side away from the fourth boundary AA4.
  • At least one second spacer repeat unit PSX2 is provided on one side. That is, on opposite sides of a row of the first spacer repeating unit PSX1 along the first direction X, at least one second spacer repeating unit PSX2 is disposed respectively.
  • 1, 2, 3 or more second spacer repeating units PSX2 are disposed on opposite sides of a row of the first spacer repeating unit PSX1, respectively.
  • At least one second spacer repeating unit PSX2 is provided on the side away from the first boundary AA1, and at least one second spacer repeating unit PSX2 is provided on the side away from the second boundary AA2.
  • one, two, three or more second spacer repeating units PSX2 are disposed on opposite sides of a row of first spacer repeating units PSX1 along the second direction Y, respectively.
  • FIG. 7 is a partially enlarged view of part VIII in FIG. 4 .
  • a second spacer repeat unit PSX2 may include at least one second spacer PS21, at least one fourth spacer PS22 and at least one sixth spacer PS23, for example, a first
  • the two-spacer repeating unit PSX2 may include a second spacer PS21 , a fourth spacer PS22 and a sixth spacer PS23 .
  • the fourth spacer PS22 and the sixth spacer PS23 are alternately arranged in a row, the second spacer PS21 and the fourth spacer PS22 are located in different columns, and a plurality of second spacers
  • the PS21 is repeatedly arranged in a row, and the row of the fourth spacer PS22 and the sixth spacer PS23 and the row of the second spacer PS21 are alternately arranged along the first direction X.
  • the second spacers PS21 and the fourth spacers PS22 are alternately arranged along the first direction X.
  • the second spacer PS21 , the fourth spacer PS22 and the sixth spacer PS23 extend along the first direction X, respectively.
  • At least one second spacer repeating unit PSX2 is disposed on opposite sides of a row of first spacer repeating unit PSX1 along the first direction X, respectively. That is, at least two second spacer repeating units PSX2 may be located in the same row as a row of first spacer repeating units PSX1.
  • the second spacer PS21, the fourth spacer PS22 and the first spacer PS11 and The third spacer PS12 is located on the same line, that is, aligned with each other along the first direction X; the sixth spacer PS23 and the third spacer PS13 are located on the same line, that is, aligned with each other along the first direction X.
  • At least one second spacer repeat unit PSX2 is disposed on opposite sides of a column of first spacer repeat unit PSX1 along the second direction Y, respectively. That is, at least two second spacer repeating units PSX2 and one column of first spacer repeating units PSX1 may be located in the same column.
  • the fourth spacer PS22, the sixth spacer PS23 and the third spacer PS12 and The fifth spacer PS13 is located on the same line, that is, aligned with each other along the second direction Y; the second spacer PS21 and the first spacer PS11 are located on the same line, that is, aligned with each other along the second direction Y.
  • the width of the second spacer PS21 in the second direction Y is greater than the width of the fourth spacer PS22 in the second direction Y; and the second spacer The width of PS21 in the first direction X is not smaller than the width of the fourth spacer PS22 in the first direction X.
  • the area of the orthographic projection of the second spacer PS21 on the base substrate 10 may be larger than the area of the orthographic projection of the fourth spacer PS22 on the base substrate 10 .
  • a plurality of sixth spacers PS23 may be spaced apart from the second spacers PS21 and the fourth spacers PS22 .
  • the area of the sixth spacer PS23 is different from that of the second spacer PS21 .
  • the orthographic projection of the sixth spacer PS23 in the second direction Y does not overlap the orthographic projections of the second spacer PS21 and the fourth spacer PS22 in the second direction Y.
  • a sixth spacer PS23 has two adjacent fourth spacers PS22, and one of the two fourth spacers PS22 is located on the sixth spacer PS23 above, and another one below the sixth spacer PS23.
  • the third ratio there is a third ratio between the area of the sixth spacer PS23 and the area of the fourth spacer PS22 , and the third ratio may be 0.8 ⁇ 1.2.
  • the third ratio may also be set to be 0.9 ⁇ 1.1.
  • the third ratio can be made 0.8. It is also possible to make the third ratio 0.9. It is also possible to make the third ratio 1.0. It is also possible to make the third ratio 1.1. It is also possible to make the third ratio 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the width of the sixth spacer PS23 in the second direction Y is substantially equal to the width of the fourth spacer PS22 in the second direction Y; and the width of the sixth spacer PS23 in the first direction X is substantially equal to the width of the fourth spacer PS23.
  • the width of the spacer PS22 in the first direction X is substantially equal to the width of the orthographic projection of the sixth spacer PS23 on the base substrate 10 .
  • the area ratio of any two second spacers PS21 is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projections of any two second spacers PS21 on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of any two second spacers PS21 is 0.9 ⁇ 1.1.
  • the area ratio of any two second spacers PS21 may be 0.8.
  • the area ratio of any two second spacers PS21 may also be 0.9.
  • the area ratio of any two second spacers PS21 may also be 1.0.
  • the area ratio of any two second spacers PS21 may also be 1.1.
  • the area ratio of any two second spacers PS21 may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the area ratio of any two fourth spacers PS22 is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projections of any two fourth spacers PS22 on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of any two fourth spacers PS22 is 0.9 ⁇ 1.1.
  • the area ratio of any two fourth spacers PS22 may be 0.8.
  • the area ratio of any two fourth spacers PS22 may also be 0.9.
  • the area ratio of any two fourth spacers PS22 may also be 1.0.
  • the area ratio of any two fourth spacers PS22 may also be 1.1.
  • the area ratio of any two fourth spacers PS22 may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the area ratio of any two sixth spacers PS23 is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projection of any two sixth spacers PS23 on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of any two sixth spacers PS23 is 0.9 ⁇ 1.1.
  • an area ratio of any two sixth spacers PS23 may be 0.8.
  • the area ratio of any two sixth spacers PS23 may also be 0.9.
  • the area ratio of any two sixth spacers PS23 may also be 1.0.
  • the area ratio of any two sixth spacers PS23 may also be 1.1.
  • the area ratio of any two sixth spacers PS23 may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the area ratio of the second spacers PS21 in the same row or in the same column to the first spacers PS11 is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projection of the second spacer PS21 on the same row or the first spacer PS11 on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of the second spacer PS21 located in the same row or the same column to the first spacer PS11 is 0.9 ⁇ 1.1.
  • the area ratio of the second spacer PS21 and the first spacer PS11 located in the same row or column may be 0.8.
  • the area ratio of the second spacer PS21 and the first spacer PS11 located in the same row or column may also be 0.9.
  • the area ratio of the second spacer PS21 and the first spacer PS11 located in the same row or column may also be 1.0.
  • the area ratio of the second spacer PS21 and the first spacer PS11 located in the same row or column may also be 1.1.
  • the area ratio of the second spacer PS21 and the first spacer PS11 located in the same row or column may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projections of the fourth spacer PS22 on the same row or the third spacer PS12 on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column is 0.9 ⁇ 1.1.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column may be 0.8.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column may also be 0.9.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column may also be 1.0.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column may also be 1.1.
  • the area ratio of the fourth spacer PS22 and the third spacer PS12 located in the same row or column may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column is 0.8 ⁇ 1.2.
  • the area ratio of the orthographic projections of the sixth spacer PS23 and the fifth spacer PS13 in the same row or column on the base substrate 10 may be 0.8 ⁇ 1.2.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column is 0.9 ⁇ 1.1.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column may be 0.8.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column may also be 0.9.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column may also be 1.0.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column may also be 1.1.
  • the area ratio of the sixth spacer PS23 and the fifth spacer PS13 located in the same row or column may also be 1.2.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • FIG. 6 and FIG. 7 there is a gap distance HG21 between the second spacers PS21 adjacent along the second direction Y, and there is a gap distance HG21 between the fourth spacers PS22 adjacent along the second direction Y.
  • There is a separation distance HG22 which is greater than the separation distance HG21.
  • the adjacent sixth spacers PS23 along the second direction Y have a distance HG23 between them.
  • the ratio of the distance HG23 to the distance HG22 is 0.8 ⁇ 1.2.
  • the distance HG23 may be substantially equal to the distance HG22.
  • the separation distance HG23 is greater than the separation distance HG21.
  • the ratio between the separation distance HG1 and the separation distance HG21 is 0.8 ⁇ 1.2, for example, the separation distance HG1 may be substantially equal to the separation distance HG21.
  • the ratio between the separation distance HG2 and the separation distance HG22 is 0.8 ⁇ 1.2, for example, the separation distance HG2 may be substantially equal to the separation distance HG22.
  • the ratio between the separation distance HG3 and the separation distance HG23 is 0.8 ⁇ 1.2, for example, the separation distance HG3 may be substantially equal to the separation distance HG23.
  • the gap distance HG21 may be a minimum distance between boundaries of adjacent second spacers PS21 along the second direction Y.
  • the gap distance HG22 may be a minimum distance between boundaries of adjacent fourth spacers PS22 in the second direction Y.
  • the gap distance HG23 may be a minimum distance between boundaries of adjacent sixth spacers PS23 in the second direction Y.
  • the separation distance HG24 between the fourth spacer PS22 and the sixth spacer PS23 adjacent along the second direction Y.
  • the ratio between the separation distance HG24 and the separation distance HG25 is 0.8 ⁇ 1.2, for example, the separation distance HG24 may be substantially equal to the separation distance HG25.
  • the spacing distances HG24 , HG25 may be the minimum distance between boundaries of the fourth spacer PS22 and the sixth spacer PS23 adjacent along the second direction Y.
  • the ratio of the separation distance HG22 to the separation distance HG24 or HG25 may be 0.3 ⁇ 0.5.
  • the ratio of the separation distance HG22 to the separation distance HG24 or HG25 may be 0.4 ⁇ 0.48.
  • the ratio of the separation distance HG22 to the separation distance HG24 or HG25 may be 0.4.
  • the ratio of the separation distance HG22 to the separation distance HG24 or HG25 may be 0.45.
  • the design may be determined according to the requirements of practical applications, and no limitation is made here.
  • first spacer repeating unit PSX1 there is an interval between the first spacer PS11 and the third spacer PS12 that are adjacent along the first direction X Distance WG1.
  • WG2 In two first spacer repeating units PSX1 adjacent along the first direction X, there is a separation distance WG2 between the first spacer PS11 and the third spacer PS12 adjacent along the first direction X.
  • the ratio between the separation distance WG1 and the separation distance WG2 is 0.8 ⁇ 1.2, for example, the separation distance WG1 may be substantially equal to the separation distance WG2.
  • the separation distance WG12 between the second spacer PS21 and the fourth spacer PS22 adjacent along the first direction X.
  • the ratio between the separation distance WG12 and the separation distance WG22 is 0.8 ⁇ 1.2, for example, the separation distance WG12 may be substantially equal to the separation distance WG22.
  • the ratio between the separation distance WG1 and the separation distance WG12 is 0.8 ⁇ 1.2, for example, the separation distance WG1 may be substantially equal to the separation distance WG12.
  • the ratio between the separation distance WG2 and the separation distance WG22 is 0.8 ⁇ 1.2, for example, the separation distance WG2 may be substantially equal to the separation distance WG22.
  • the separation distances WG1 , WG2 may be the minimum distance between boundaries of the first spacer PS11 and the third spacer PS12 adjacent along the first direction X.
  • the separation distance WG12 , WG22 may be a minimum distance between boundaries of the second spacer PS21 and the fourth spacer PS22 adjacent along the first direction X.
  • FIG. 8 to 23 are plan views illustrating some film layers of an exemplary embodiment of part I in FIG. 1, wherein FIG. 8 schematically shows a semiconductor layer, and FIG. 9 schematically shows a first conductive layer, Figure 10 schematically shows the combination of the semiconductor layer and the first conductive layer, Figure 11 schematically shows the second conductive layer, and Figure 12 schematically shows the combination of the semiconductor layer, the first conductive layer and the second conductive layer , Figure 13A schematically shows an interlayer insulating layer, Figure 13B schematically shows a combination of a semiconductor layer, a first conductive layer, a second conductive layer and an interlayer insulating layer, and Figure 14 schematically shows a third conductive layer layer, Figure 15 schematically shows the combination of the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer and the third conductive layer, Figure 16 schematically shows the planarization layer, and Figure 17 schematically shows Showing the combination of semiconductor layer, first conductive layer, second conductive layer, interlayer insulating layer, third
  • FIG. 18 schematically shows the first electrode layer
  • Fig. 19 schematically shows A combination of a semiconductor layer, a first conductive layer, a second conductive layer, an interlayer insulating layer, a third conductive layer, a planarization layer, and a first electrode layer.
  • FIG. 20 schematically shows a pixel defining layer
  • FIG. 21 schematically shows Figure 22 schematically shows the combination of the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer, the third conductive layer, the planarization layer, the first electrode layer and the pixel defining layer.
  • layer, Figure 23 schematically shows the semiconductor layer, the first conductive layer, the second conductive layer, the interlayer insulating layer, the third conductive layer, the planarization layer, the first electrode layer, the pixel defining layer and the spacer layer combination.
  • the display panel may include a pixel driving circuit disposed in the display area AA and a scan driving circuit 300 disposed in the non-display area NA.
  • both the pixel driving circuit and the scanning driving circuit 300 may include a plurality of thin film transistors and at least one capacitor.
  • FIG. 31 is an equivalent circuit diagram of one pixel driving circuit of a display panel according to some exemplary embodiments of the present disclosure.
  • the pixel driving circuit may include: a plurality of signal lines 61, 62, 63, 64, 65, 66 and 67, a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, and storage capacitor Cst.
  • the pixel driving circuit is used to drive organic light emitting diodes (ie OLEDs).
  • the plurality of thin film transistors include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , an initialization thin film transistor T4 , a first light emission control thin film transistor T5 , a second light emission control thin film transistor T6 and a bypass thin film transistor T7 .
  • the multiple signal lines include: a scanning signal line 61 for transmitting the scanning signal Sn, a reset control signal line 62 for transmitting the reset control signal Sn-1 to the initialization thin film transistor T4, and a reset control signal line 62 for transmitting the light emission control signal En to the first A light emission control thin film transistor T5 and a light emission control line 63 of the second light emission control thin film transistor T6, a data line 64 for transmitting the data signal Dm, a driving voltage line 65 for transmitting the driving voltage VDD, and a driving voltage line 65 for transmitting the initialization voltage Vint
  • the initialization voltage line 66, and the power line 67 for transmitting the first voltage VSS.
  • the first voltage may represent the VSS voltage.
  • the gate G1 of the driving thin film transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst (hereinafter referred to as the first capacitor electrode), and the source S1 of the driving thin film transistor T1 is electrically connected to the driving voltage line 65 via the first light emission control thin film transistor T5 , the drain D1 of the driving thin film transistor T1 is electrically connected to the anode of the OLED via the second light emitting control thin film transistor T6.
  • the driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 to supply the driving current Id to the OLED.
  • the gate G2 of the switching thin film transistor T2 is electrically connected to the scanning signal line 61, the source S2 of the switching thin film transistor T2 is electrically connected to the data line 64, and the drain D2 of the switching thin film transistor T2 is electrically connected to the
  • the driving voltage line 65 is also electrically connected to the source S1 of the driving thin film transistor T1.
  • the switching thin film transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm transmitted to the data line 64 to the source S1 of the driving thin film transistor T1.
  • the gate G3 of the compensation thin film transistor T3 is electrically connected to the scanning signal line 61
  • the source S3 of the compensation thin film transistor T3 is electrically connected to the anode of the OLED through the second light emission control thin film transistor T6, and is electrically connected to the drain of the driving thin film transistor T1 D1.
  • the drain D3 of the compensation thin film transistor T3 is electrically connected with one end of the storage capacitor Cst (ie, the first capacitor electrode) Cst1 , the drain D4 of the initialization thin film transistor T4 and the gate G1 of the driving thin film transistor T1 .
  • the compensation thin film transistor T3 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to connect the gate G1 and the drain D1 of the driving thin film transistor T1 to each other, thereby performing diode connection of the driving thin film transistor T1.
  • the gate G4 of the initialization TFT T4 is electrically connected to the reset control signal line 62
  • the source S4 of the initialization TFT T4 is electrically connected to the initialization voltage line 66
  • the drain D4 of the initialization thin film transistor T4 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D3 of the compensation thin film transistor T3 and the gate G1 of the driving thin film transistor T1 .
  • the initialization thin film transistor T4 is turned on according to the reset control signal Sn-1 transmitted through the reset control signal line 62, so as to transmit the initialization voltage Vint to the gate G1 of the driving thin film transistor T1, thereby performing an initialization operation to drive the gate of the thin film transistor T1.
  • the voltage of pole G1 is initialized.
  • the gate G5 of the first light emission control thin film transistor T5 is electrically connected to the light emission control line 63
  • the source S5 of the first light emission control thin film transistor T5 is electrically connected to the driving voltage line 65
  • the drain D5 of the first light emission control thin film transistor T5 is electrically connected to the source S1 of the driving thin film transistor T1 and the drain D2 of the switching thin film transistor T2 .
  • the gate G6 of the second light emission control thin film transistor T6 is electrically connected to the light emission control line 63
  • the source S6 of the second light emission control thin film transistor T6 is electrically connected to the drain D1 of the driving thin film transistor T1 and is electrically connected to the drain electrode of the compensation thin film transistor T3.
  • the drain D6 of the second light emitting control thin film transistor T6 is electrically connected to the anode of the OLED.
  • the first light emission control thin film transistor T5 and the second light emission control thin film transistor T6 are concurrently (for example, simultaneously) turned on according to the light emission control signal En transmitted through the light emission control line 63, so as to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow. into the OLED.
  • the bypass TFT T7 includes: the gate G7, connected to the reset control signal line 62; the source S7, connected to the drain D6 of the second light emission control T6 and the anode of the OLED; and the drain D7, connected to The voltage line 66 is initialized.
  • the bypass TFT T7 transmits the reset control signal Sn ⁇ 1 from the reset control signal line 62 to the gate G7.
  • the other end (hereinafter referred to as a second capacitance electrode) Cst2 of the storage capacitor Cst is electrically connected to the driving voltage line 65, and the cathode of the OLED is electrically connected to the power line 67 to receive the first voltage VSS.
  • the OLED receives the driving current Id from the driving thin film transistor T1 to emit light, thereby displaying images.
  • the GOA circuit may include a light emission control scan driving circuit, for example, the light emission control scan drive circuit may be an EM GOA circuit for sending a light emission control signal En.
  • FIG. 18 it schematically shows a circuit diagram of a light emission control scanning driving circuit according to some exemplary embodiments of the present disclosure.
  • the light emission control scanning driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB and a signal output line E0.
  • the light emission control scanning driving circuit further includes a plurality of shift register units.
  • FIG. 32 is an equivalent circuit diagram of one scan driving circuit of a display panel according to some exemplary embodiments of the present disclosure.
  • the scan driving circuit 300 may include a GATE GOA circuit for sending the scan signal Sn and/or the reset control signal Sn-1.
  • the GATE GOA circuit can be in one-to-one correspondence with the pixel row, that is, a GATE GOA circuit corresponds to a row of pixels, at this time, a signal output by a GATE GOA circuit can be used as a scanning signal of a row of pixels corresponding to the row of GATE GOA circuits, and also It can be used as a reset control signal for the next row of pixels.
  • the scanning signal of a certain row of pixels comes from the signal output by the GATE GOA circuit corresponding to the row of pixels
  • the reset control signal of the row of pixels comes from the signal output by the GATE GOA circuit corresponding to the previous row of pixels.
  • two-row driving or four-row driving can be adopted, that is, the output signal of one EM GOA circuit can be used to drive two or four rows of pixels.
  • the gate scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a third clock signal line GCK, a fourth clock signal line GCB and a signal output line GO.
  • the gate scanning driving circuit further includes a plurality of shift register units.
  • At least one shift register unit among the plurality of shift register units may include a first capacitor C1, a second capacitor C2, a first transistor Q1, a second transistor Q2, a third transistor Q3, a Four transistors Q4, fifth transistor Q5, sixth transistor Q6, seventh transistor Q7 and eighth transistor Q8.
  • the gate QG1 of the first transistor Q1 is coupled to the clock signal line GCK, the first electrode QS1 is coupled to the input signal terminal GI, and the second electrode QD1 is coupled to the gate QG2 of the second transistor.
  • the first electrode QS2 of the second transistor Q2 is coupled to the clock signal line GCK, and the second electrode QD2 is coupled to the sixth node N6.
  • the gate QG3 of the third transistor Q3 is coupled to the clock signal terminal GCK, the first electrode QS3 is coupled to the voltage signal line VGL, and the second electrode QD3 is coupled to the sixth node N6.
  • the gate QG4 of the fourth transistor Q4 is coupled to the sixth node N6, the first electrode QS4 is coupled to the voltage signal line VGH, and the second electrode QD4 is coupled to the signal output line GO.
  • the gate of the fifth transistor Q5 is coupled to the eighth node N8, the first electrode QS5 is coupled to the clock signal terminal QCB, and the second electrode QD5 is coupled to the signal output line GO.
  • the gate QG6 of the sixth transistor Q6 is coupled to the sixth node N6, the first electrode QS6 is coupled to the voltage signal line VGH, and the second electrode QD6 is coupled to the seventh node N7.
  • the gate QG7 of the seventh transistor Q7 is coupled to the clock signal terminal GCB, the first electrode QS7 is coupled to the seventh node N7, and the second electrode QD7 is coupled to the fifth node N5.
  • the gate QG8 of the eighth transistor Q8 is coupled to the voltage signal line VGL, the first electrode QS8 is coupled to the fifth node N5, and the second electrode QD8 is coupled to the eighth node N8.
  • One end of the first capacitor C1 is coupled to the eighth node N8, and the other end is coupled to the second electrode QD5 of the fifth transistor Q5.
  • One end of the second capacitor C2 is coupled to the sixth node N6, and the other end is coupled to the first electrode QS4 of the fourth transistor Q4.
  • FIG. 33 is an equivalent circuit diagram of one scan driving circuit of a display panel according to some exemplary embodiments of the present disclosure.
  • the scan driving circuit 300 may include an EM GOA circuit for sending the light emission control signal En.
  • the light emission control scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB and a signal output line E0.
  • the light emission control scanning driving circuit further includes a plurality of shift register units.
  • At least one shift register unit among the plurality of shift register units may include a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor M10, an output reset transistor M9, a first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8.
  • the gate MG10 of the output transistor M10 is coupled to the first plate C2a of the output capacitor C2, the first electrode MS10 of the output transistor M10 is coupled to the second voltage signal line VGL, and the output transistor M10 The second electrode MD10 is coupled to the signal output line E0.
  • the gate MG9 of the output reset transistor M9 is coupled to the first plate C3a of the output reset capacitor C3, and the first electrode MS9 of the output reset transistor M9 is connected to the second plate C3b of the output reset capacitor C3.
  • the second electrode MD9 of the output reset transistor M9 is coupled to the signal output line E0.
  • the second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH; the second plate C2b of the output capacitor C2 is coupled to the second clock signal line CB.
  • the first electrode MS1 of the first transistor M1 is coupled to the second clock signal line CB, the second electrode MD1 of the first transistor M1 and the first electrode MS2 of the second transistor M2 are respectively connected to the The second plate C1b of the first capacitor C1 is coupled, and the gate MG1 of the first transistor M1 is coupled to the first plate C1a of the first capacitor C1.
  • the gate MG2 of the second transistor M2 and the gate MG7 of the seventh transistor M7 are respectively coupled to the first clock signal line CB, and the second electrode MD2 of the second transistor M2 is connected to the third transistor M3
  • the second electrode MD3 of the second transistor M2 is coupled; the first electrode MS2 of the second transistor M2 is coupled to the second plate C1b of the first capacitor.
  • the gate MG3 of the third transistor M3 is coupled to the gate MG10 of the output transistor M10 , and the first electrode MS3 of the third transistor M3 is coupled to the first voltage signal line VGH.
  • Both the gate MG4 of the fourth transistor M4 and the gate MG5 of the fifth transistor M5 are coupled to the first clock signal line CK, the first electrode MS4 of the fourth transistor M4 is connected to the output transistor M10 The first electrode MS10 is coupled to the second voltage signal line VGL, and the second electrode MD4 of the fourth transistor M4 is coupled to the second electrode MD6 of the sixth transistor M6.
  • the gate MG5 of the fifth transistor M5 is coupled to the first clock signal line CK, the second electrode MD5 of the fifth transistor M5 is coupled to the gate MG6 of the sixth transistor M6; the fifth transistor The first electrode MS5 of M5 is coupled to the input signal terminal E1.
  • Both the first electrode MS1 of the sixth transistor M6 and the gate MG4 of the fourth transistor M4 are coupled to the first clock signal line CK, and the second electrode MD6 of the sixth transistor M6 is connected to the gate MG4 of the fourth transistor M4.
  • the second electrode MD4 is coupled; the gate MG6 of the sixth transistor M6 is coupled to the second electrode MD1 of the fifth transistor.
  • Both the gate MG7 of the seventh transistor M7 and the second plate C2b of the output capacitor C2 are coupled to the second clock signal line CB, and the first electrode MS7 of the seventh transistor M7 is connected to the second electrode of the eighth transistor M8.
  • the second electrode MD8 is coupled to the second electrode MD7 of the seventh transistor M7 and the gate MG6 of the sixth transistor M6 is coupled.
  • the gate MG8 of the eighth transistor M8 is coupled to the gate MG1 of the first transistor M1 , and the first electrode MS8 of the eighth transistor M8 is coupled to the first voltage signal line VGH.
  • the one labeled N1 is the first node
  • the one labeled N2 is the second node
  • the one labeled N3 is the third node
  • the one labeled N4 is the fourth node.
  • the first voltage signal line VGH can provide the high voltage VGH
  • the second voltage signal line VGL can provide the low voltage VGL, but not limited thereto.
  • the first electrode of the transistor may be a source, and the second electrode of the transistor may be a drain; or, the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source.
  • each transistor has a single gate structure, however, embodiments of the present disclosure are not limited thereto, and at least some of the various transistors may have a double gate structure.
  • the respective transistors are P-channel field effect transistors, however, embodiments of the present disclosure are not limited thereto, and at least some of the respective transistors may be N-channel field effect transistors.
  • the semiconductor layer 20 is schematically shown.
  • the active layers of the above-mentioned respective transistors may be formed along the semiconductor layer 20 as shown in FIG. 8 .
  • the semiconductor layer 20 may have a bent or bent shape, and may include active layers corresponding to respective transistors.
  • the semiconductor layer 20 may be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness may be in the range of 400-800 angstroms, for example, 500 angstroms.
  • the active layer may include, for example, polysilicon, and include, for example, a channel region, a source region, and a drain region.
  • the channel region may not be doped or the doping type is different from that of the source region and the drain region, and thus has semiconductor characteristics.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities, and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • the first conductive layer 21 is schematically shown.
  • the gates of the aforementioned transistors, one electrode of the capacitor and at least some signal lines may be located in the first conductive layer 21 .
  • the first conductive layer 21 may be formed of a conductive material forming a gate of a transistor, for example, the conductive material may be Mo, and its film thickness may be in the range of 2000 ⁇ 4000 angstroms, such as 3000 angstroms.
  • the scan signal lines 61 , the reset signal lines 62 and the light emission control lines 63 are all located in the first conductive layer 21 .
  • the gates G1 - G7 of the above transistors are all located in the first conductive layer 21 .
  • the overlapping portions of the reset signal line 62 and the semiconductor layer 20 respectively form the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, and the overlapping portions of the scanning signal line 61 and the semiconductor layer 20 form the second transistor T2 respectively.
  • the gate G2 of the fourth transistor T4 and the gate G4 of the fourth transistor T4, and the overlapping portion of the light emission control line 63 and the semiconductor layer 20 form the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5 respectively.
  • one load compensation unit 100 may include multiple compensation capacitors, for example, three compensation capacitors.
  • the plurality of compensation capacitors may include a first compensation capacitor, a second compensation capacitor and a third compensation capacitor.
  • the first compensation capacitor can be used to compensate a column of first sub-pixels SP1
  • the second compensation capacitor can be used to compensate a column of second sub-pixels SP2
  • the third compensation capacitor can be used to compensate a column of second sub-pixels SP2. It can be used to compensate a row of third sub-pixels SP3.
  • each compensation capacitor may include a first compensation capacitor electrode 101 and a second compensation capacitor electrode 102 , and the first compensation capacitor electrode 101 is located in the first conductive layer 21 .
  • the first compensation capacitor electrodes 101 of a plurality of compensation capacitors are spaced apart from each other, that is, a gap is provided between any adjacent two first compensation capacitor electrodes 101 .
  • each first compensation capacitor electrode 101 may extend along the second direction Y, and multiple first compensation capacitor electrodes 101 in one load compensation unit 1 may be arranged at intervals along the first direction X.
  • gates of transistors, an electrode of a capacitor and at least some signal lines included in the scan driving circuit 300 may be located in the first conductive layer 21 .
  • the display panel may include a supporting part 301 for supporting the encapsulation structure 30 .
  • the supporting portion 301 is located in the first conductive layer 21 .
  • the support portion 301 is located on a side of the area where the scan driving circuit 300 is located away from the display area AA.
  • the orthographic projection of the support portion 301 on the base substrate does not overlap with the orthographic projection of the semiconductor layer 20 on the base substrate.
  • the supporting part 301 may include a supporting body part 302 , a plurality of openings or grooves 303 and a plurality of conductive parts 304 .
  • the support portion 301 is spaced apart from the scan driving circuit 300 .
  • the encapsulation structure 30 of Frit can be formed in the support part 301 , so that the support part 301 can be used to support the encapsulation structure 30 .
  • a plurality of openings or grooves 303 can be formed in the supporting body portion 302, so that when forming the packaging structure 30 such as Frit, at least a part of the packaging structure 30 can be embedded in the plurality of openings or grooves 303, so as to The bonding force between the packaging structure 30 and the supporting part 301 is enhanced.
  • the orthographic projection of each opening or groove 303 on the base substrate is in the shape of a rectangle or a square. It should be noted that the embodiments of the present disclosure are not limited thereto, and the orthographic projection of each opening or groove 303 on the base substrate may have other shapes.
  • a plurality of conductive parts 304 are located on a side of the supporting body part 302 close to the scan driving circuit 300 , and the plurality of conductive parts 304 are used to electrically connect with signal lines for transmitting electrical signals, so as to access the electrical signals. In this way, it is possible to avoid the support portion being in a suspended (ie floating) state.
  • the second conductive layer 22 is schematically shown.
  • another electrode of the capacitor and at least some signal lines may be located in the second conductive layer 22 .
  • the second conductive layer 22 may be formed of a conductive material forming a gate of a transistor, for example, the conductive material may be Mo, and its film thickness may be in the range of 2000 ⁇ 4000 angstroms, such as 3000 angstroms.
  • the initialization voltage line 66 and the other electrode of the storage capacitor may be located in the second conductive layer 22 .
  • the second compensation capacitor electrode 102 of the load compensation unit may be located in the second conductive layer 22 .
  • the first compensation capacitor electrode 101 and the second compensation capacitor electrode 102 are disposed opposite to each other, the orthographic projections of the two on the base substrate at least partially overlap each other, and a dielectric layer is disposed between them.
  • the first compensation capacitor electrode 101 may be electrically connected to a data signal
  • the second compensation capacitor electrode 102 may be electrically connected to a driving voltage, that is, the two are connected to different voltage signals. In this way, the overlapping portion of the first compensation capacitor electrode 101 and the second compensation capacitor electrode 102 can form the compensation capacitor.
  • the second compensation capacitor electrodes 102 of the plurality of compensation capacitors are connected to each other.
  • a plurality of second compensation capacitor electrodes 102 of a load compensation unit is formed as an integral structure extending continuously.
  • the orthographic projections of the first compensation capacitor electrodes 101 of the plurality of compensation capacitors on the substrate fall into a plurality of second compensation capacitor electrodes 102 connected to each other on the substrate. Inside the orthographic projection on the base substrate. In this way, it is beneficial to increase the overlapping area between the first compensation capacitor electrode and the second compensation capacitor electrode, thereby helping to increase the capacitance value of the compensation capacitor.
  • the second compensation capacitor electrodes 102 of multiple adjacent load compensation units may be connected to each other.
  • the plurality of second compensation capacitor electrodes 102 of the plurality of load compensation units may be formed as a continuous extending integral structure.
  • the other electrode of the capacitor included in the scan driving circuit 300 and at least some signal lines may be located in the second conductive layer 22 .
  • the orthographic projection of the support portion 301 on the base substrate does not overlap with the orthographic projection of the second conductive layer 22 on the base substrate.
  • FIG. 13A schematically shows an interlayer insulating layer
  • FIG. 13B schematically shows a combination of a semiconductor layer 20 , a first conductive layer 21 , a second conductive layer 22 and an interlayer insulating layer 23 .
  • the interlayer insulating layer 23 covers most of the display area AA and the peripheral area NA.
  • the insulating interlayer 23 may cover most of the display area AA
  • the insulating interlayer 23 may cover most of the peripheral area NA.
  • the expression “majority” may mean a portion of 50% or more.
  • the display panel may include a plurality of via hole portions VH4, a plurality of via hole portions VH5, a plurality of via hole portions VH6, and a plurality of via hole portions VH7.
  • a plurality of via holes VH4 may be located in the display area AA, for example, a plurality of via holes VH4 may be respectively located in a plurality of sub-pixels to respectively expose a part of the pixel driving circuit of each sub-pixel.
  • a plurality of via holes VH5 may be located in the region where the scan driving circuit 300 is located, for example, the plurality of via holes VH5 may respectively expose a part of each scan driving circuit 300 .
  • the plurality of vias VH6 may be respectively located in the area where the supporting portion 301 is located, for example, the plurality of vias VH6 may respectively expose at least a part of the plurality of conductive portions 304 . In this way, when the conductive layer is subsequently formed, the corresponding conductive layer can pass through the plurality of via holes VH4, the plurality of via hole portions VH5, and the plurality of via hole portions VH6 and the exposed parts of the pixel driving circuit, the scanning driving circuit, and the conductive parts. electrical connection.
  • a plurality of via holes VH7 may be respectively located in the area where the support portion 301 is located, for example, a plurality of via holes VH7 may be respectively located in a plurality of openings or grooves 303 .
  • a packaging structure 30 such as Frit
  • at least a part of the packaging structure 30 can be respectively embedded in a plurality of openings or grooves 303 through a plurality of via holes VH7, so as to strengthen the packaging structure 30 and the support portion.
  • the binding force between 301 is provided.
  • the third conductive layer 24 is schematically shown.
  • the third conductive layer 24 can be formed of a conductive material forming the source and drain of the thin film transistor, for example, the conductive material can include Ti, Al, etc., and the third conductive layer 24 can have a stack formed of Ti/Al/Ti. layer structure, the thickness of the film layer can be in the range of 6000-9000 angstroms.
  • the thickness of each layer of Ti/Al/Ti may be about 500 angstroms, 6000 angstroms, and 500 angstroms, respectively.
  • the source and drain of each transistor included in the pixel driving circuit may be located in the third conductive layer 24, and some signal lines (such as the data signal line 64 and the driving voltage line 65) may be located in the third conductive layer 24 .
  • the source and drain of each transistor included in the scan driving circuit 300 may be located in the third conductive layer 24 , and some signal lines may be located in the third conductive layer 24 .
  • the display panel may further include a driving voltage lead 650 for providing a driving voltage VDD.
  • the driving voltage lead 650 may be located between the scan driving circuit 300 and the display area AA.
  • the driving voltage lead 650 may be electrically connected to a second compensation capacitor electrode 120 through a plurality of via holes. That is to say, one end of the second compensation capacitor electrode 120 is electrically connected to the driving voltage lead 650 , and the other end is electrically connected to the driving voltage line 65 . In this way, the driving voltage VDD supplied from the driving voltage lead 650 can be transmitted to the driving voltage line 65 .
  • the display panel may further include a first voltage lead 670 for providing a driving voltage VSS.
  • the first voltage lead 670 may be located on a side of the scan driving circuit 300 away from the display area AA.
  • the first voltage lead 670 may be electrically connected to the conductive part 304 in the first conductive layer 21 through a plurality of via holes VH6 . That is, the first voltage lead 670 may be electrically connected with the support part 301 . Through such an electrical connection manner, the supporting part 301 can be connected to the first voltage VSS, so as to prevent the supporting part 301 from being in a suspended state.
  • the planarization layer PLN is schematically shown.
  • the planarization layer PLN covers most of the area of the display area AA.
  • the planarization layer PLN may include a plurality of via holes.
  • the anodes of each sub-pixel formed subsequently may pass through these via holes and communicate with the subpixels located in the lower layer.
  • the pixel driving circuit is electrically connected.
  • the planarization layer PLN exposes most of the area of the peripheral area NA.
  • the planarization layer PLN covers the area where the scan driving circuit 300 is located.
  • the area where the scan driving circuit 300 is located includes a boundary line 300S away from the display area AA, and the planarization layer PLN does not cover the area extending from the boundary line 300S in a direction away from the display area AA.
  • the planarization layer PLN does not cover the first voltage lead 670 nor the support part 301 .
  • the planarization layer PLN includes a boundary PLNS away from the display area AA
  • the first voltage lead 670 includes a boundary 670S close to the display area AA
  • the orthographic projection of the boundary PLNS on the base substrate 10 is the same as that of the boundary 670S on the base substrate 10
  • the orthographic projections on are basically coincident.
  • the first electrode layer 25 is schematically shown.
  • the anodes YG1 - YG3 of the above-mentioned sub-pixels may be located in the first electrode layer 25 .
  • the display panel includes an auxiliary conductive part 251 located in the first electrode layer 25 .
  • the auxiliary conductive part 251 may at least partially contact the first voltage lead 670 .
  • the planarization layer PLN does not cover the first voltage lead 670.
  • the orthographic projections on 10 overlap at least partially.
  • a portion of the auxiliary conductive portion 251 may directly contact a portion of the first voltage lead 670 to form an electrical connection therebetween. That is to say, in the embodiment of the present disclosure, the first voltage lead 670 located in the third conductive layer 23 and the auxiliary conductive part 251 located in the first electrode layer 25 are connected in parallel, and they are both used to transmit the first voltage VSS . In this way, the resistance of the signal line transmitting the first voltage VSS can be reduced.
  • the orthographic projection of the auxiliary conductive portion 251 on the base substrate 10 and the orthographic projection of the scan driving circuit 300 on the base substrate 10 at least partially overlap, for example, the orthographic projection of the auxiliary conductive portion 251 on the base substrate 10
  • the orthographic projection of the scan driving circuit 300 on the base substrate 10 may be substantially completely covered. That is, the auxiliary conductive portion 251 is set wider, so as to further reduce the resistance of the signal line transmitting the first voltage VSS.
  • the auxiliary conductive part 251 may further include a plurality of openings 252 .
  • the planarization layer PLN is usually made of an organic resin material, and some organic substances that are easily volatilized by heat exist in the planarization layer PLN, such as organic solvents or small molecular materials. These organic substances are easy to volatilize when heated in the subsequent manufacturing process of the display panel, resulting in outgassing in the planarization layer.
  • the pixel defining layer PDL may include a pixel defining layer body PDL0, a first covering part PDL1, and a second covering part PDL2.
  • Most of the pixel defining layer body PDL0 is located in the display area AA.
  • the pixel defining layer PDL includes a plurality of openings, such as the openings KK1 - KK3 of the above-mentioned respective sub-pixels.
  • the pixel defining layer PDL includes a first covering part PDL1 and a second covering part PDL2.
  • the auxiliary conductive part 251 includes an edge 251S away from the display area AA.
  • the orthographic projection of the second cover part PDL2 on the base substrate 10 covers the orthographic projection of the edge 251S on the base substrate 10 .
  • the display panel may include a plurality of first covering parts PDL1, and the orthographic projections of the plurality of first covering parts PDL1 on the base substrate respectively cover the orthographic projections of the plurality of openings 252 on the base substrate.
  • the pixel defining layer body PDL0 may have a boundary PDLS away from the display area AA.
  • the boundary PDLS is located on the side of the load compensation unit 100 away from the display area AA.
  • the orthographic projection of a part of the boundary PDLS on the base substrate 10 may be located between the orthographic projection of the scan driving circuit 300 on the base substrate 10 and the orthographic projection of the load compensation unit 100 on the base substrate 10
  • the orthographic projection of another part of the boundary PDLS on the base substrate 10 may fall within the orthographic projection of the scan driving circuit 300 on the base substrate 10 .
  • the plurality of sub-pixels located in the display area AA may include an outermost column of sub-pixels, that is, a column of sub-pixels closest to the peripheral area NA.
  • the distance between the boundary PDLS and the outermost column of sub-pixels (the leftmost column of sub-pixels in FIG. 21 ) along the first direction X can be a specified value. , or in other words, the distance is within the specified range.
  • the spacer layer PSL may include the first spacer repeat unit PSX1 located inside the display area AA and the second spacer repeat unit PSX2 located outside the display area AA.
  • one first spacer repeating unit PSX1 may include at least one first spacer PS11 , at least one third spacer PS12 and at least one fifth spacer PS13 .
  • one second spacer repeating unit PSX2 may include at least one second spacer PS21 , at least one fourth spacer PS22 and at least one sixth spacer PS23 .
  • FIG. 24 is a cross-sectional view of the display panel taken along line BB' in FIG. 23 according to some exemplary embodiments of the present disclosure.
  • the display panel may include a base substrate 10; a semiconductor layer 20 disposed on the base substrate 10; a first conductive layer 21 disposed on the side of the semiconductor layer 20 away from the base substrate 10; The second conductive layer 22 disposed on the side of the first conductive layer 21 away from the base substrate 10; the interlayer insulating layer 23 disposed on the side of the second conductive layer 22 away from the base substrate 10; disposed on the interlayer insulating layer 23 away from The third conductive layer 24 on the side of the base substrate 10; the planarization layer PLN disposed on the side of the third conductive layer 24 away from the base substrate 10; the first electrode disposed on the side of the planarization layer PLN away from the base substrate 10 layer 25 ; the pixel defining layer PDL disposed on the side of the first electrode layer 25 away from the base substrate 10 ; and the spacer layer P
  • the display panel according to the embodiments of the present disclosure is not limited to the above-mentioned film layers, and one or more insulating layers may also be provided between each conductive layer.
  • a first insulating layer IL1 may be provided between the semiconductor layer 20 and the first conductive layer 21
  • a second insulating layer IL2 may be provided between the first conductive layer 21 and the second conductive layer 22 .
  • FIG. 8 to FIG. 23 show partial enlarged views of the display panel at part I in FIG. 1 according to an embodiment of the present disclosure.
  • part I is the part of the display panel at the first rounded corner 10A (that is, the upper left corner)
  • part II is the part of the display panel at the second rounded corner.
  • 10B that is, the upper right corner
  • part III is the part of the display panel at the fourth rounded corner 10D (that is, the lower right corner)
  • part IV is the portion of the display panel that is at the second rounded corner 10B (that is, the upper right corner).
  • part V is the part of the display panel near the first boundary AA1 (ie, the upper edge)
  • part VI is the part of the display panel near the second boundary AA2 (ie, the lower edge).
  • FIG. 25A is a partial enlarged view of a display panel at part II in FIG. 1 according to some disclosed exemplary embodiments.
  • Fig. 25B is a partially enlarged view of Fig. 25A.
  • FIG. 26 is a partially enlarged view of a display panel at part III in FIG. 1 according to some disclosed exemplary embodiments.
  • FIG. 27 is a partial enlarged view of a display panel at part IV in FIG. 1 according to some disclosed exemplary embodiments.
  • FIG. 28 is a partially enlarged view of a display panel at part V in FIG. 1 according to some disclosed exemplary embodiments.
  • FIG. 29 is a partially enlarged view of FIG. 28 .
  • FIG. 30 is a partially enlarged view of a display panel at part VI in FIG. 1 according to some disclosed exemplary embodiments.
  • the pixel defining layer PDL covers the spacer layer PSL, for example, the pixel defining layer body PDL0 covers the spacer PSL.
  • the orthographic projection of the pixel defining layer PDL on the base substrate 10 covers the orthographic projection of the spacer layer PSL on the base substrate 10, for example, the orthographic projection of the pixel defining layer body PDL0 on the base substrate 10 covers Orthographic projection of the spacer layer PSL on the base substrate 10 .
  • the pixel defining layer PDL (specifically, the pixel defining layer main body PDL0) includes a first part PDL01 and a second part PDL02, and the second part PDL02 and the first part PDL01 are integrally structured .
  • the first part PDL01 is located in the display area AA and includes openings corresponding to the plurality of sub-pixels, and the orthographic projection of the openings on the base substrate is located on the first electrode of the plurality of sub-pixels on the base substrate in the orthographic projection of .
  • the second portion PDL02 is located in the peripheral area NA.
  • the orthographic projection of the first spacer repeating unit PSX1 on the base substrate is located in the first part PDL01 of the pixel defining layer within the orthographic projection of the base substrate, and the second spacer repeating unit PSX2
  • the second part PDL02 of the pixel defining layer is located in the orthographic projection of the base substrate, and the second part PDL02 is located away from the boundary PDLS of the display area AA and is close to a part of the display area AA. side.
  • the orthographic projection of the second spacer repeating unit PSX2 on the base substrate does not overlap with the orthographic projection of the first electrodes of the plurality of sub-pixels on the base substrate.
  • the plurality of sub-pixels includes at least one row of edge sub-pixels closest to the peripheral area NA, for example, the leftmost column of sub-pixels shown in FIG. 23 .
  • At least part of the orthographic projection of the second spacer repeating unit PSX2 on the base substrate is located far from the orthographic projection of the first electrode of the at least one row of edge subpixels on the base substrate.
  • the spacer layer includes a plurality of first spacer repeating units PSX1 and a plurality of second spacer repeating units PSX2, a plurality of first spacer repeating units PSX1 and a plurality of The second spacer repeating units PSX2 are arranged in an array along the first direction X and the second direction Y.
  • the orthographic projection of the second spacer repeating unit PSX2 on the base substrate does not overlap with the orthographic projection of the first electrode layer 25 on the base substrate.
  • the base substrate 10 includes at least one corner portion
  • the driving voltage lead 650 includes a plurality of steps 650P located in the at least one corner portion. Orthographic projections of at least some of the second spacer repeating units PSX2 on the base substrate and the plurality of steps 650P of the driving voltage lead 650 on the base substrate Overlapping the orthographic projection on , the at least some second spacer repeating units PSX2 are distributed in steps.
  • the distribution of the at least some of the second spacer repeat units PSX2 is based on the driving
  • the extension of the voltage lead 650 at the plurality of steps 650P is regular. That is, the plurality of steps formed by the at least some second spacer repeating units PSX2 are respectively located at the plurality of steps 650P of the driving voltage lead 650 .
  • the plurality of steps 650P includes a first step 6501 and a second step 6502 .
  • the first step 6501 and the second step 6502 both extend along the first direction X, the size of the first step 6501 along the first direction X is larger than the size of the second step 6502 along the first direction X, and
  • the number of second spacer repeating units PSX2 overlapping with the first step 6501 and located in the same row is greater than the number of second spacer repeating units PSX2 overlapping with the second step 6502 and located in the same row; and /or, referring to FIG. 25A and FIG.
  • both the first step 6501 and the second step 6502 extend along the second direction Y, and the dimension of the first step 6501 along the second direction Y is larger than that of the second step
  • the size of 6502 along the second direction Y, the number of second spacer repeating units PSX2 overlapping with the first step 6501 and located in the same column is greater than the second spacer repeating unit PSX2 overlapping with the second step 6502 and located in the same column. Number of spacer repeating units PSX2.
  • the plurality of second spacer repeat units PSX2 include A row of second spacer repeating units in the area AA and located on one side of the display area AA, the row of second spacer repeating units PSX2 are arranged along a straight line parallel to the second direction Y; and/or, refer to FIG. 28 Referring to FIG.
  • the plurality of second spacer repeat units PSX2 include
  • the display area AA is a row of second spacer repeating units PSX2 located on one side of the display area AA, and the row of second spacer repeating units PSX2 is arranged along a straight line parallel to the first direction X.
  • the display panel further includes a first data lead 641 and a second data lead 642 disposed on the base substrate 10 and located in the peripheral area NA, the first data lead 641 is used to provide data signals to a column of first sub-pixels, and the second data lead 642 is used to provide data signals to a column of second sub-pixels.
  • At least one row of second spacer repeating unit PSX2 disposed adjacent to the first data lead 641 and the second data lead 642 includes a row of spacers, and the row of spacers includes alternately arranged second spacers PS21 and the fourth spacer PS22, most of the orthographic projection of the row of spacers on the base substrate (for example, more than 50%) is located on the first data lead in the first direction X 641 and the extension line of the second data lead 642 .
  • the display panel further includes a third data lead 643 disposed on the base substrate 10 and located in the peripheral area NA, and the third data lead 643 is used to provide a The three sub-pixels provide data signals.
  • at least one row of second spacer repeating unit PSX2 adjacent to the third data lead 643 includes a row of sixth spacer PS23, and the orthographic projection of the third data lead 643 on the base substrate extends through Orthographic projection of at least one of the row of sixth spacers PS23 on the base substrate.
  • the orthographic projection of at least one of the row of sixth spacers PS23 on the base substrate is symmetrical with respect to the orthographic projection of the third data lead 643 on the base substrate.
  • the orthographic projection of at least some of the second spacer repeat units PSX2 on the base substrate falls within the orthographic projection of the plurality of load compensation cells 100 on the substrate substrate.
  • the orthographic projection of the second spacer repeating unit PSX2 on the base substrate and the orthographic projection of the boundary PDLS of the main body of the pixel defining layer on the base substrate are separated by a prescribed distance.
  • the specified distance is 20-300 microns.
  • the first spacer PS11 adjacent along the first direction X there is a distance WG3 between the second spacer PS21, and there is a distance WG4 between the third spacer PS12 adjacent to the first direction X and the fourth spacer PS22.
  • the ratio of the spacing distance WG12 between two adjacent second spacers PS21 along the first direction X to the spacing distance WG3 is 0.8-1.2, or in other words, two adjacent second spacers PS21 along the first direction X
  • the separation distance WG12 between the second spacers PS12 is substantially equal to the separation distance WG3.
  • the ratio of the spacing distance between two adjacent fourth spacers PS22 along the first direction X to the spacing distance WG4 is 0.8-1.2, or in other words, the two adjacent fourth spacers PS22 along the first direction X
  • the spacing distance between the pads PS22 is substantially equal to the spacing distance WG4.
  • the ratio of the spacing distance between two adjacent sixth spacers PS23 along the first direction X to the spacing distance WG5 is 0.8-1.2, or in other words, the two sixth spacers adjacent along the first direction X
  • the spacing distance between the pads PS23 is substantially equal to the spacing distance WG5.
  • At least one second spacer repeating unit PSX2 is disposed on opposite sides of a row of the first spacer repeating unit PSX1 along the first direction X, respectively.
  • At least two second spacer repeating units PSX2 are respectively disposed on opposite sides of a row of first spacer repeating units PSX1 along the second direction Y.
  • the orthographic projection of a part of the boundary PDLS of the main body of the pixel defining layer on the base substrate 10 is located at the corner of the base substrate 10 where the scan driving circuit 300 is located on the base substrate.
  • the orthographic projection of another part of the boundary PDLS of the pixel defining layer main body on the base substrate 10 falls into the The scan driving circuit 300 is in the orthographic projection of the base substrate.
  • a display device may include the above-mentioned display panel.
  • the display device may be a smartphone, mobile phone, video phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP) , digital audio players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic bracelets or smart watches), etc.

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Abstract

一种显示面板和显示装置（1000）。显示面板包括：衬底基板（10），包括显示区域（AA）和周边区域（NA）；设置于衬底基板（10）上的第一电极层（25）；设置在第一电极层（25）远离衬底基板（10）一侧的像素界定层（PDL），其中，像素界定层（PDL）包括第一部分（PDL01）和第二部分（PDL02），第一部分（PDL01）位于显示区域（AA）且包括对应多个子像素的开口；第二部分（PDL02）位于周边区域（NA），且第二部分（PDL02）和第一部分（PDL01）为一体结构；设置在像素界定层（PDL）远离衬底基板（10）一侧的隔垫物层（PSL）。隔垫物层（PSL）包括第一隔垫物重复单元（PSX1）和第二隔垫物重复单元（PSX2），第一隔垫物重复单元（PSX1）位于显示区域（AA）中，第二隔垫物重复单元（PSX2）位于周边区域（NA）中。第二隔垫物重复单元（PSX2）在衬底基板（10）的正投影位于第二部分（PDL02）在衬底基板（10）的正投影内，且位于第二部分（PDL02）远离显示区域（AA）的边界（PDLS）靠近显示区域（AA）的一侧。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。目前，中小尺寸的有机发光二极管显示面板包括用于维持显示面板与盖板之间的间隔的隔垫物。
在本部分中公开的以上信息仅用于对本公开的发明构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示面板，包括：
衬底基板，包括显示区域和周边区域；
设置于所述显示区域中的多个子像素，所述子像素包括第一电极，第二电极和位于所述第一电极和所述第二电极之间的功能层；
设置于所述衬底基板上的第一电极层，所述多个子像素的所述第一电极位于所述第一电极层；
设置在所述第一电极层远离所述衬底基板一侧的像素界定层，其中，所述像素界定层包括像素界定层主体，所述像素界定层主体包括第一部分和第二部分，所述第一部分位于显示区域且包括对应所述多个子像素的开口，所述开口在所述衬底基板的正投影位于所述多个子像素的所述第一电极在所述衬底基板的正投影内；所述第二部分位于周边区域，且所述第二部分和所述第一部分为一体结构；
设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，
其中，所述隔垫物层包括第一隔垫物重复单元和第二隔垫物重复单元，所述第一隔垫物重复单元位于所述显示区域中，所述第二隔垫物重复单元位于所述周边区域中；
所述第二隔垫物重复单元在衬底基板的正投影位于所述像素界定层的所述第二部分在衬底基板的正投影内，且位于所述第二部分远离所述显示区域的边界靠近所述显示区域的一侧，且所述第二隔垫物重复单元在衬底基板上的正投影与所述多个子像素的所述第一电极在衬底基板上的正投影不交叠。
根据一些示例性实施例，所述多个子像素包括最靠近所述周边区域的至少一排边缘子像素，所述第二隔垫物重复单元在所述衬底基板上的正投影的至少部分位于所述至少一排边缘子像素的第一电极在所述衬底基板上的正投影远离所述显示区域的一侧。
根据一些示例性实施例，所述隔垫物层包括多个所述第一隔垫物重复单元和多个所述第二隔垫物重复单元，多个第一隔垫物重复单元和多个第二隔垫物重复单元沿第一方向和第二方向成阵列地布置。
根据一些示例性实施例，所述第二隔垫物重复单元在衬底基板上的正投影与所述第一电极层在衬底基板上的正投影不交叠。
根据一些示例性实施例，所述多个子像素沿第一方向和第二方向成阵列地布置；所述第一隔垫物重复单元包括第一隔垫物和第三隔垫物，所述第一隔垫物和所述第三隔垫物位于不同列，一列第一隔垫物对应一列子像素，一列第二隔垫物对应另一列子像素；所述第二隔垫物重复单元包括第二隔垫物和第四隔垫物；以及对于沿第一方向位于同一行的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，第一隔垫物重复单元的第一隔垫物和第三隔垫物与第二隔垫物重复单元的第二隔垫物和第四隔垫物均位于同一行。
根据一些示例性实施例，所述第一隔垫物重复单元还包括第五隔垫物，所述第三隔垫物和所述第五隔垫物交替排列于一列中；所述第二隔垫物重复单元还包括第六隔垫物，所述第四隔垫物和第六隔垫物交替排列于一列中；以及对于沿第二方向位于同一列的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第三隔垫物和第五隔垫物与各个第二隔垫物重复单元的第四隔垫物和第六隔垫物均位于同一列。
根据一些示例性实施例，对于沿第一方向位于同一行的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第五隔垫物与各个第二隔垫物重复单元的第六隔垫物均位于同一行。
根据一些示例性实施例，对于沿第二方向位于同一列的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第一隔垫物与各个第二隔垫物重复单元的第二隔垫物均位于同一列。
根据一些示例性实施例，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的驱动电压引线，所述驱动电压引线用于提供驱动电压；所述衬底基板包括至少一个拐角部，所述驱动电压引线包括位于所述至少一个拐角部中的多个台阶；以及多个第二隔垫物重复单元中的至少一些第二隔垫物重复单元在所述衬底基板上的正投影与所述驱动电压引线的多个台阶在所述衬底基板上的正投影交叠，所述至少一些第二隔垫物重复单元成台阶地分布。
根据一些示例性实施例，对于与所述驱动电压引线的多个台阶交叠的至少一些第二隔垫物重复单元而言，所述至少一些第二隔垫物重复单元形成的多个台阶分别位于所述驱动电压引线的多个台阶处。
根据一些示例性实施例，所述多个台阶包括第一台阶和第二台阶；以及所述第一台阶和所述第二台阶均沿第一方向延伸，所述第一台阶沿第一方向的尺寸大于所述第二台阶沿第一方向的尺寸，与一个所述第一台阶交叠且位于同一行的第二隔垫物重复单元的数量大于与一个所述第二台阶交叠且位于同一行的第二隔垫物重复单元的数量；和/或，所述第一台阶和所述第二台阶均沿第二方向延伸，所述第一台阶沿第二方向的尺寸大于所述第二台阶沿第二方向的尺寸，与一个所述第一台阶交叠且位于同一列的第二隔垫物重复单元的数量大于与一个所述第二台阶交叠且位于同一列的第二隔垫物重复单元的数量。
根据一些示例性实施例，对于位于衬底基板的非拐角处的多个第二隔垫物重复单元而言，所述多个第二隔垫物重复单元包括在第一方向上最远离所述显示区域且位于所述显示区域一侧的一列第二隔垫物重复单元，所述一列第二隔垫物重复单元沿平行于第二方向的直线排列；和/或，对于位于衬底基板的非拐角处的多个第二隔垫物重复单元而言，所述多个第二隔垫物重复单元包括在第二方向上最远离所述显示区域且位于所述显示区域一侧的一行第二隔垫物重复单元，所述一行第二隔垫物重复单元沿平行于第一方向的直线排列。
根据一些示例性实施例，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的第一数据引线和第二数据引线，所述第一数据引线用于给一列第一子像 素提供数据信号，所述第二数据引线用于给一列第二子像素提供数据信号；以及邻近所述第一数据引线和所述第二数据引线设置的至少一列第二隔垫物重复单元包括一列隔垫物，所述一列隔垫物包括交替排列的第二隔垫物和第四隔垫物，所述一列隔垫物在所述衬底基板上的正投影的50％以上的部分在第一方向上位于所述第一数据引线的延伸直线和所述第二数据引线的延伸直线之间。
根据一些示例性实施例，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的第三数据引线，所述第三数据引线用于给一列第三子像素提供数据信号；以及邻近所述第三数据引线设置的至少一列第二隔垫物重复单元包括一列第六隔垫物，所述第三数据引线在所述衬底基板上的正投影延伸穿过所述一列第六隔垫物中的至少一个在所述衬底基板上的正投影。
根据一些示例性实施例，所述一列第六隔垫物中的至少一个在所述衬底基板上的正投影相对于所述第三数据引线在所述衬底基板上的正投影对称。
根据一些示例性实施例，所述显示面板还包括：设置于所述衬底基板上且位于所述周边区域中的扫描驱动电路，所述扫描驱动电路用于输出扫描信号；和设置于所述衬底基板上且位于所述周边区域中的多个负载补偿单元，所述多个负载补偿单元位于所述扫描驱动电路与所述多个像素单元之间，其中，至少一些第二隔垫物重复单元在所述衬底基板上的正投影落入所述多个负载补偿单元在所述衬底基板上的正投影内。
根据一些示例性实施例，所述第二隔垫物重复单元在所述衬底基板上的正投影与所述像素界定层主体的边界在所述衬底基板上的正投影间隔规定的距离。
根据一些示例性实施例，所述规定的距离为20～300微米。
根据一些示例性实施例，在沿第二方向相邻的至少两个第二隔垫物重复单元中，沿第二方向相邻的第二隔垫物之间具有第一间隔距离，沿第二方向相邻的第四隔垫物之间具有第二间隔距离，所述第二间隔距离大于所述第一间隔距离。
根据一些示例性实施例，所述第二隔垫物在第二方向上的宽度大于所述第四隔垫物在第二方向上的宽度；和/或，所述第二隔垫物在第一方向上的宽度不小于所述第四隔垫物在第一方向上的宽度。
根据一些示例性实施例，所述第六隔垫物在所述衬底基板上的正投影的面积与所述第一隔垫物在所述衬底基板上的正投影的面积不同。
根据一些示例性实施例，所述第二隔垫物所在列和所述第四隔垫物所在列沿第一 方向交替排列；和/或，所述第二隔垫物和所述第四隔垫物沿所第一方向交替排列于一条直线上；和/或，所述第四隔垫物和所述第六隔垫物交替排列于一列中。
根据一些示例性实施例，所述第一隔垫物在所述衬底基板上的正投影的面积与所述第二隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2；和/或，所述第三隔垫物在所述衬底基板上的正投影的面积与所述第四隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2；和/或，所述第五隔垫物在所述衬底基板上的正投影的面积与所述第六隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2。
根据一些示例性实施例，在沿第一方向相邻的第一隔垫物重复单元和第二隔垫物重复单元中，沿第一方向相邻的第一隔垫物与第二隔垫物之间具有第三间隔距离，沿第一方向相邻的第三隔垫物与第四隔垫物之间具有第四间隔距离，沿第一方向相邻的第五隔垫物与第六隔垫物之间具有第五间隔距离；以及沿第一方向相邻的两个第二隔垫物之间的间隔距离与所述第三间隔距离之比为0.8～1.2；和/或，沿第一方向相邻的两个第四隔垫物之间的间隔距离与所述第四间隔距离之比为0.8～1.2；和/或，沿第一方向相邻的两个第六隔垫物之间的间隔距离与所述第五间隔距离之比为0.8～1.2。
根据一些示例性实施例，在一行第一隔垫物重复单元沿第一方向的相对侧，分别设置有至少一个第二隔垫物重复单元；和/或，在一列第一隔垫物重复单元沿第二方向的相对侧，分别设置有至少两个第二隔垫物重复单元。
根据一些示例性实施例，在所述衬底基板的拐角处，所述像素界定层主体的边界的一部分在所述衬底基板上的正投影位于所述扫描驱动电路在所述衬底基板上的正投影与所述负载补偿单元在所述衬底基板上的正投影之间，所述像素界定层主体的边界的另一部分在所述衬底基板上的正投影落入所述扫描驱动电路在所述衬底基板上的正投影内。
根据一些示例性实施例，所述显示面板还包括：
设置于所述衬底基板上且位于所述周边区域中的支撑部；和
设置于所述支撑部远离所述衬底基板一侧且位于所述周边区域中的封装结构，
其中，所述支撑部在所述衬底基板上的正投影位于所述像素界定层主体的边界在所述衬底基板上的正投影远离所述显示区域的一侧。
根据一些示例性实施例，所述支撑部包括支撑主体部、多个开孔或凹槽和多个导电部，所述多个开孔或凹槽位于所述支撑主体部中，所述多个导电部位于所述支撑主 体部靠近所述显示区域的一侧。
根据一些示例性实施例，所述显示面板还包括第一电压引线和辅助导电部，所述第一电压引线用于提供第一电压，所述辅助导电部与所述第一电极位于同一层；以及所述辅助导电部的一部分与所述第一电压引线直接接触。
根据一些示例性实施例，所述像素界定层还包括第一覆盖部和第二覆盖部；所述显示面板还包括平坦化层，所述平坦化层位于所述第一电极层靠近所述衬底基板的一侧，所述辅助导电部包括多个开孔，所述多个开孔分别暴露所述平坦化层的一部分；以及所述第一覆盖部覆盖所述多个开孔，所述第二覆盖部覆盖所述辅助导电部远离所述显示区域的边缘。
在另一方面，提供一种显示装置，其中，包括，如上所述的显示面板。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1是根据本公开的一些示例性实施例的显示装置的平面示意图；
图2是根据本公开的一些示例性实施例的显示面板的平面示意图，其中示意性示出了显示面板包括的像素单元和负载补偿单元；
图3是根据本公开的一些示例性实施例的显示装置沿图1中的线AA’截取的截面图图；
图4是图1中的部分I的局部放大图；
图5是图4中的部分VII的局部放大图；
图6是根据本公开的一些示例性实施例的隔垫物的分布示意图；
图7是图4中的部分VIII的局部放大图；
图8至图23是示出图1中的部分I的示例性实施方式的一些膜层的平面图，其中，图8示意性示出了半导体层，图9示意性示出了第一导电层，图10示意性示出了半导体层和第一导电层的组合，图11示意性示出了第二导电层，图12示意性示出了半导体层、第一导电层和第二导电层的组合，图13A示意性示出了层间绝缘层，图13B示意性示出了半导体层、第一导电层、第二导电层和层间绝缘层的组合，图14示意性示出了第三导电层，图15示意性示出了半导体层、第一导电层、第二导电层、层间绝缘 层和第三导电层的组合，图16示意性示出了平坦化层，图17示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层和平坦化层的组合，图18示意性示出了第一电极层，图19示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层和第一电极层的组合，图20示意性示出了像素界定层，图21示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层、第一电极层和像素界定层的组合，图22示意性示出了隔垫物层，图23示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层、第一电极层、像素界定层和隔垫物层的组合；
图24是根据本公开的一些示例性实施例的显示面板沿图23中的线BB’截取的截面图；
图25A为根据公开的一些示例性实施例的显示面板在图1中的部分II处的局部放大图；
图25B为图25A的局部放大图；
图26为根据公开的一些示例性实施例的显示面板在图1中的部分III处的局部放大图；
图27为根据公开的一些示例性实施例的显示面板在图1中的部分IV处的局部放大图；
图28为根据公开的一些示例性实施例的显示面板在图1中的部分V处的局部放大图；
图29为图28的局部放大图；
图30为根据公开的一些示例性实施例的显示面板在图1中的部分VI处的局部放大图；
图31是根据本公开的一些示例性实施例的显示面板的一个像素驱动电路的等效电路图；
图32是根据本公开的一些示例性实施例的显示面板的一个扫描驱动电路的等效电路图；以及
图33是根据本公开的一些示例性实施例的显示面板的一个扫描驱动电路的等效电路图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构 或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
在下面的描述中，出于解释的目的，阐述了许多具体细节以提供对各种示例性实施例的全面的理解。然而，明显的是，在不具有这些具体细节或者具有一个或多个等同布置的情况下，可以实施各种示例性实施例。在其它情况下，以框图形式示出了公知的结构和装置，以避免使各种示例性实施例不必要地模糊。此外，各种示例性实施例可以是不同的，但不必是排他的。例如，在不脱离发明构思的情况下，可以在另一示例性实施例中使用或实施示例性实施例的具体形状、配置和特性。
在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。当可以不同地实施示例性实施例时，可以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者以与描述的顺序相反的顺序执行两个连续描述的工艺。此外，同样的附图标记表示同样的元件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XY、YZ和XZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与 另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
在本文中，术语“基本上”、“大约”、“近似”、“大致”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本公开的实施例提供一种显示面板和显示装置。所述显示面板包括：衬底基板，包括显示区域和周边区域；设置于所述显示区域中的多个子像素，所述子像素包括第一电极，第二电极和位于所述第一电极和所述第二电极之间的功能层；设置于所述衬底基板上的第一电极层，所述多个子像素的所述第一电极位于所述第一电极层；设置在所述第一电极层远离所述衬底基板一侧的像素界定层，其中，所述像素界定层包括像素界定层主体，所述像素界定层主体包括第一部分和第二部分，所述第一部分位于显示区域且包括对应所述多个子像素的开口，所述开口在所述衬底基板的正投影位于所述多个子像素的所述第一电极在所述衬底基板的正投影内；所述第二部分位于周边区域，且所述第二部分和所述第一部分为一体结构；设置在所述像素界定层远离所述 衬底基板一侧的隔垫物层，其中，所述隔垫物层包括第一隔垫物重复单元和第二隔垫物重复单元，所述第一隔垫物重复单元位于所述显示区域中，所述第二隔垫物重复单元位于所述周边区域中；所述第二隔垫物重复单元在衬底基板的正投影位于所述像素界定层的所述第二部分在衬底基板的正投影内，且位于所述第二部分远离所述显示区域的边界靠近所述显示区域的一侧，且所述第二隔垫物重复单元在衬底基板上的正投影与所述多个子像素的所述第一电极在衬底基板上的正投影不交叠。在本公开的实施例中，不仅在显示区域中设置隔垫物，还在周边区域设置隔垫物，这样，在利用例如FMM的掩模板进行有机材料等的蒸镀工艺过程中，可使所述掩模板在周边区域得到更多的支撑，避免了掩模板在周边区域因受力而产生凹陷，从而避免了有机材料的蒸镀位置发生偏移。因此，可以避免混色的发生。另外，通过在周边区域设置隔垫物，使得隔垫物更靠近周边封装区域，从而避免了牛顿环的产生。
图1是根据本公开的一些示例性实施例的显示装置的平面示意图。图2是根据本公开的一些示例性实施例的显示装置的平面示意图，其中示意性示出了显示面板包括的像素单元和负载补偿单元。
结合参照图1和图2，所述显示装置1000可以包括显示面板。所述显示面板可以包括衬底基板10，所述衬底基板10可以包括显示区域AA和位于所述显示区域至少一侧的周边区域NA。需要说明的是，在图1所示的实施例中，周边区域NA包围显示区域AA，但是，本公开的实施例不局限于此，在其他实施例中，周边区域NA可以位于显示区域AA的至少一侧，但不包围所述显示区域AA。
所述显示面板可以包括位于显示区域AA中的多个像素单元P。需要说明的是，像素单元P是用于显示图像的最小单元。例如，像素单元P可以包括发射白色光和/或彩色光的发光器件。
像素单元P可以设置成多个，以沿着在第一方向(例如行方向)X上延伸的行和在第二方向(例如列方向)Y上延伸的列呈阵列形式布置。然而，本公开的实施例不具体限制像素单元P的布置形式，并且可以以各种形式布置像素单元P。例如，像素单元P可以布置为使得相对于第一方向X和第二方向Y倾斜的方向成为列方向，并且使得与列方向交叉的方向成为行方向。
一个像素单元P可以包括多个子像素。例如，一个像素单元P可以包括3个子像素，即第一子像素SP1、第二子像素SP2和第三子像素SP3。再例如，一个像素单元P可以包括4个子像素，即第一子像素、第二子像素、第三子像素和第四子像素。例如， 第一子像素SP1可以为红色子像素，第二子像素SP2可以为绿色子像素，第三子像素SP3可以为蓝色子像素，第四子像素可以为白色子像素。
每一个子像素可以包括发光元件和用于驱动发光元件的像素驱动电路。例如，第一子像素SP1可以包括第一发光元件和用于驱动第一发光元件的第一像素驱动电路，所述第一发光元件可以发射红色光；第二子像素SP2可以包括第二发光元件和用于驱动第二发光元件的第二像素驱动电路，第二发光元件可以发射绿色光；第三子像素SP3可以包括第三发光元件和用于驱动第三发光元件的第三像素驱动电路，第三发光元件可以发射蓝色光。
例如，在OLED显示面板中，子像素的发光元件可以包括叠层设置的阳极、发光材料层和阴极。例如，子像素的发光区域可以是被夹在阳极和阴极之前且与阳极和阴极接触的发光材料层的部分所对应的区域。例如，在阳极上形成有像素界定层，像素界定层具有开口暴露出至少部分阳极，发光材料层至少部分形成于像素界定层开口内，之上再形成阴极，子像素的发光区域可以是像素界定层开口限定的区域。其中，所述发光材料层例如可以包括空穴注入层，空穴传输层，发光层，空穴阻挡层，电子传输层，电子注入层等中的一层或多层，也可以除以上层外还包括其他功能膜层，其中的层可以包括有机材料，也可以包括无机材料例如量子点等。
参照图1，所述显示面板可以包括位于周边区域NA中的负载补偿单元100、测试电路200、扫描驱动电路300、多路选择器400等部件。
显示区域AA可以包括依次连接的第一边界AA1、第二边界AA2、第三边界AA3和第四边界AA4(例如上侧边界、下侧边界、左侧边界和右侧边界)。
在本公开的一些实施例中，显示区域AA在衬底基板10上的正投影可以呈圆角矩形的形状。为了描述方便，可以将圆角矩形的四个圆角分别成为第一圆角部10A、第二圆角部10B、第三圆角部10C和第四圆角部10D。例如，第一圆角部10A可以位于图1中的左上角处，第二圆角部10B可以位于图1中的右上角处，第三圆角部10C可以位于图1中的左下角处，第四圆角部10D可以位于图1中的右下角处。
测试电路200可以位于周边区域NA中邻近第一边界AA1的一侧，测试电路200与第一边界AA1、第一圆角部10A和第二圆角部10B相对设置。
例如，测试电路200可以包括多个测试引脚(将在下文中描述)，所述多个测试引脚可以用于提供测试信号，例如，所述测试信号可以包括用于显示区域AA中的多个像素单元P的数据信号。
多路选择器400可以位于周边区域NA中邻近第二边界AA2的一侧，多路选择器400与第二边界AA2、第三圆角部10C和第四圆角部10D相对设置。
例如，多路选择器400可以对布线区中的信号线进行分时复用。如图1所示，所述显示面板包括设置于周边区域NA中的集成电路IC以及位于集成电路IC与多路选择器400之间的布线区500。集成电路IC输出的各路信号通过布线区500中的信号线传输至多路选择器400。然后，在多路选择器400的信号控制端的控制下，各路信号被输出给显示区域AA中的各个像素单元P。通过设置多路选择器400，可以减小布置于布线区的信号线的数量，从而降低布线区中的布线压力。
扫描驱动电路300可以位于周边区域NA中邻近第三边界AA3的一侧和位于周边区域NA中邻近第四边界AA4的一侧。需要说明的是，虽然图1中示出驱动电路位于显示区域AA的左侧和右侧，但是，本公开的实施例不局限于此，驱动电路可以位于周边区域NA任何合适的位置。
例如，所述扫描驱动电路300可以包括栅极扫描驱动电路和发光控制扫描驱动电路中的至少一个。例如，栅极扫描驱动电路和发光控制扫描驱动电路可以采用GOA技术，即所述扫描驱动电路300可以包括Gate GOA和EM GOA中的至少一个。在GOA技术中，将栅极驱动电路和发光控制扫描驱动电路直接设置于阵列基板上，以代替外接驱动芯片。每个GOA单元作为一级移位寄存器，每级移位寄存器与一条栅线或发光控制线电连接，通过各级移位寄存器依序轮流输出开启电压，实现像素的逐行扫描。在一些实施例中，每级移位寄存器也可以与多条栅线或多条发光控制线连接。这样，可以适应显示面板高分辨率、窄边框的发展趋势。
所述显示面板可以包括多个负载补偿单元100。如图1和图2所示，多个负载补偿单元100中的一些位于周边区域NA中邻近第一圆角部10A的位置处，多个负载补偿单元100中的另一些位于周边区域NA中邻近第二圆角部10B的位置处。多个负载补偿单元100均位于测试电路200与显示区域AA之间。
在本公开的实施例中，每一个子像素SP1、SP2或SP3可以包括发光元件和用于驱动发光元件的像素驱动电路。例如，发光器件可以包括第一电极、第二电极和位于第一电极与第二电极之间的发光材料层，像素驱动电路可以包括晶体管、电容等元件，像素驱动电路接收显示面板上设置的信号线的信号，产生驱动发光器件的电流，并通过与第一电极或第二电极之一连接，实现驱动发光器件发光的目的。例如，像素驱动电路设置于衬底基板上，发光器件位于像素驱动电路远离衬底基板一侧。例如，所述 像素驱动电路可以包括本领域中常见的7T1C、7T2C、8T2C或4T1C等电路结构。例如，所述发光元件可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
图3是根据本公开的一些示例性实施例的显示装置沿图1中的线AA’截取的截面图图。结合参照图1至图3，所述显示装置还可以包括盖板20、封装结构30和隔垫物PS。盖板20与衬底基板10相对设置。封装结构30和隔垫物PS均设置在衬底基板10与盖板20之间。例如，至少一些隔垫物PS设置在显示区域AA中，以支撑盖板20以及在衬底基板10与盖板20之间形成待封装的空间。封装结构30设置在周边区域NA中，例如，封装结构30可以围绕显示区域AA一圈设置，以防止水汽、氧气等侵入位于显示区域AA中的发光元件内。例如，封装结构30可以包括Frit(玻璃粉)。
图4是图1中的部分I的局部放大图，在图4中，示意性示出了一些隔垫物PS和多个子像素SP1、SP2、SP3的布置，而省略了其他结构，其他结构将结合附图在下文中进行详细描述。
在一些实施例中，显示面板还包括位于第一电极远离像素驱动电路一侧的像素界定层，像素界定层包括多个开口，各个子像素对应至少一个像素界定层开口(例如一个)，子像素的实际发光区域或显示区域与该子像素对应的像素界定层开口大致相当。在一些实施例中，各个子像素对应的像素界定层开口或者实际发光区域面积小于第一电极的面积，且在衬底基板上的投影完全落入第一电极在衬底基板投影之内。为了方便图示和描述，图4中仅示出了子像素的像素界定层开口的大概位置和形状，以表示各个子像素的分布。
例如，在本公开的一些实施例中，每一个像素重复单元中的子像素的排布方式可以参考常规的像素排布方式，例如RGB、GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
参照图4，示意性示出了显示区域AA的边界，例如，该边界可以是图1中的边界AA3的一部分。以显示区域AA的边界为分界线，一部分隔垫物PS位于显示区域AA内，另一部分隔垫物PS位于显示区域AA外。例如，在本公开的实施例中，所述显示面板可以包括位于显示区域AA内的第一隔垫物重复单元PSX1和位于显示区域AA外的第二隔垫物重复单元PSX2。例如，第一隔垫物重复单元PSX1包括至少一个隔垫物，第二隔垫物重复单元PSX2包括至少一个隔垫物。
在本公开的实施例中，在显示区域AA外围增加了隔垫物，使隔垫物距离封装结构30更近，这样，封装结构30得到了更多的支撑力。所以，避免了封装结构30因受 到外力因素而发生高度不均一的情况，从而减小了牛顿环的发生率，有利于提高显示装置的显示效果。并且，通过在显示区域AA外围增加隔垫物，使显示区域AA的边缘得到更多的支撑力。这样，在使用FMM掩膜板的蒸镀过程中，使位于隔垫物上方的FMM掩膜板的受力均匀，降低了FMM掩膜板发生变形而导致蒸镀精度降低的风险，从而可以避免色偏的发生。
图5是图4中的部分VII的局部放大图，图6是根据本公开的一些示例性实施例的隔垫物的分布示意图。为了方便图示和描述，图5中仅示出了子像素的像素界定层开口和阳极的位置和形状。
结合参照图4至图6，示例性地，多个子像素可以包括沿第二方向Y相邻的第一子像素SP1和第二子像素SP2。其中，第一子像素SP1包括第一阳极YG1和第一子像素开口KK1，第二子像素SP2包括第二阳极YG2和第二子像素开口KK2。
进一步地，显示面板可以包括多个像素重复单元PX。每个像素重复单元PX可以包括至少一个第一子像素SP1和至少一个第二子像素SP2。例如，每个像素重复单元PX包括沿第二方向Y相邻的第一子像素SP1和第二子像素SP2。例如，第一子像素SP1为红色子像素，第二子像素SP2为绿色子像素，则红色子像素和绿色子像素沿第二方向Y相邻。
示例性地，如图5所示，像素重复单元PX还可以包括至少一个第三子像素SP3。例如，像素重复单元可以包括一个第三子像素SP3。第三子像素SP3包括第三阳极YG3和第三子像素开口KK3。其中，相邻的第一子像素SP1、第二子像素SP2以及第三子像素SP3的阳极之间的连线构成三角形。例如，第一子像素SP1为红色子像素，第二子像素SP2为绿色子像素，第三子像素SP3为蓝色子像素，同一像素重复单元中，红色子像素、绿色子像素以及蓝色子像素中的阳极之间的连线构成三角形。
示例性地，如图5所示，在同一子像素中，子像素开口在衬底基板10上的正投影位于阳极在衬底基板10上的正投影内。
示例性地，如图5所示，第一子像素SP1和第二子像素SP2中的至少一个子像素中，子像素开口在衬底基板10的正投影为矩形。例如，第一子像素SP1和第二子像素SP2中的子像素开口在衬底基板10的正投影均为矩形。例如，第一子像素SP1为红色子像素，第二子像素SP2为绿色子像素，第三子像素SP3为蓝色子像素，红色子像素中的开口KK1和绿色子像素中的开口KK2在衬底基板10的正投影均为矩形。
示例性地，如图5所示，第三子像素SP3中的子像素开口的面积大于第二子像素 SP2中的子像素开口的面积，第二子像素SP2中的子像素开口的面积大于第一子像素SP1中的子像素开口的面积。例如，第一子像素SP1为红色子像素，第二子像素SP2为绿色子像素，第三子像素SP3为蓝色子像素，蓝色子像素中的子像素开口KK3的面积大于绿色子像素中的子像素开口KK2的面积，绿色子像素中的子像素开口KK2的面积大于红色子像素中的子像素开口KK1的面积。在实际应用中，各子像素中的子像素开口的面积可以与子像素的发光寿命成反比，例如，红色子像素的发光寿命大于绿色子像素的发光寿命大于蓝色子像素的发光寿命，则可以设置蓝色子像素中的子像素开口的面积大于绿色子像素中的子像素开口的面积，绿色子像素中的子像素开口的面积大于红色子像素中的子像素开口的面积。
示例性地，如图4、图5和图6所示，在显示区域AA内，多个第一隔垫物重复单元PSX1可以沿第一方向X和第二方向Y成阵列地布置于衬底基板10上。
例如，一个第一隔垫物重复单元PSX1可以包括至少一个第一隔垫物PS11、至少一个第三隔垫物PS12和至少一个第五隔垫物PS13，例如，一个第一隔垫物重复单元PSX1可以包括一个第一隔垫物PS11、一个第三隔垫物PS12和一个第五隔垫物PS13。
参照图5和图6，第一隔垫物PS11和第三隔垫物PS12位于不同列。一列第一隔垫物PS11对应一列子像素，一列第三隔垫物PS12对应另一列子像素。第一隔垫物PS11所在列中子像素的数量和第三隔垫物PS12所在列中子像素的数量不同。示例性地，一列第一隔垫物PS11对应一列子像素中的阳极，一列第三隔垫物PS12对应另一列子像素中的阳极。并且，第一隔垫物PS11所在列中阳极的数量和第三隔垫物PS12所在列中阳极的数量不同。
示例性地，如图5所示，第一隔垫物PS11对应的子像素中的至少一个子像素的阳极沿第二方向Y延伸，第一隔垫物PS11和第三隔垫物PS12分别沿第一方向X延伸。示例性地，针对第一隔垫物PS11与对应的子像素，第一隔垫物PS11和子像素沿第二方向Y交替重复排列且一一对应。
示例性地，如图5所示，第一隔垫物PS11在第二方向Y上的正投影与各子像素中的阳极在第二方向Y上的正投影无交叠。
示例性地，如图5所示，第一隔垫物PS11的面积(例如第一隔垫物PS11在衬底基板10的正投影的面积)与对应的子像素的开口的面积(例如子像素的开口在衬底基板10的正投影的面积)之间具有第一比值。第三隔垫物PS12的面积(例如第三隔垫物PS12在衬底基板10的正投影的面积)与在第二方向Y上相邻的两个第三隔垫物 PS12之间的所有子像素的开口的面积之和(例如在第二方向Y上相邻的两个第三隔垫物PS12之间的所有子像素的开口在衬底基板10的正投影的面积之和)之间具有第二比值。可以使第一比值与第二比值不同。示例性地，可以使第一比值大于第二比值。其中，第一比值为第一隔垫物PS11的面积除以对应的子像素的开口的面积后的值。第二比值为第三隔垫物PS12的面积除以在第二方向Y上相邻的两个第三隔垫物PS12之间的所有子像素的开口的面积之和后的值。
示例性地，如图5所示，第一隔垫物PS11的面积与第三子像素SP3中的开口KK3的面积之间具有第一比值。即第一比值为第一隔垫物PS11的面积除以第三子像素SP3中的开口KK3的面积后的值。
示例性地，如图5所示，第三隔垫物PS12的面积与第一子像素SP1和第二子像素SP2的开口的面积之和之间具有第二比值。即第二比值为第三隔垫物PS12的面积除以第一子像素SP1和第二子像素SP2的开口的面积之和后的值。
示例性地，如图5所示，沿第二方向Y相邻的第一隔垫物PS11的面积比为0.8～1.2。例如，沿第二方向Y相邻的第一隔垫物PS11在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，沿第二方向Y相邻的第一隔垫物PS11的面积比为0.9～1.1。例如，沿第二方向Y相邻的第一隔垫物PS11的面积比可以为0.8。沿第二方向Y相邻的第一隔垫物PS11的面积比也可以为0.9。沿第二方向Y相邻的第一隔垫物PS11的面积比也可以为1.0。沿第二方向Y相邻的第一隔垫物PS11的面积比也可以为1.1。沿第二方向Y相邻的第一隔垫物PS11的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5和图6所示，沿第二方向Y相邻的第一隔垫物PS11之间具有间隔距离HG1，沿第二方向Y相邻的第三隔垫物PS12之间具有间隔距离HG2，间隔距离HG2大于间隔距离HG1。沿第二方向Y相邻的第五隔垫物PS13之间具有间隔距离HG3，间隔距离HG3与间隔距离HG2之间的比值为0.8～1.2，例如，间隔距离HG3可以基本等于间隔距离HG2。例如，间隔距离HG3大于间隔距离HG1。
示例性地，间隔距离HG1可以为沿第二方向Y相邻的第一隔垫物PS11的边界之间的最小距离。间隔距离HG2可以为沿第二方向Y相邻的第三隔垫物PS12的边界之间的最小距离。间隔距离HG3可以为沿第二方向Y相邻的第五隔垫物PS13的边界之间的最小距离。
在同一第一隔垫物重复单元PSX1内，沿第二方向Y相邻的第三隔垫物PS12和 第五隔垫物PS13之间具有间隔距离HG4。在沿第二方向Y相邻的两个第一隔垫物重复单元PSX1内，沿第二方向Y相邻的第三隔垫物PS12和第五隔垫物PS13之间具有间隔距离HG5。间隔距离HG4与间隔距离HG5之间的比值为0.8～1.2，例如，间隔距离HG4可以基本等于间隔距离HG5。
示例性地，间隔距离HG4、HG5可以为沿第二方向Y相邻的第三隔垫物PS12和第五隔垫物PS13的边界之间的最小距离。
示例性地，如图6所示，间隔距离HG2与间隔距离HG4或HG5之比可以为0.3～0.5。示例性地，间隔距离HG2与间隔距离HG4或HG5之比可以为0.4～0.48。例如，间隔距离HG2与间隔距离HG4或HG5之比可以为0.4。间隔距离HG2与间隔距离HG4或HG5之比可以为0.45。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5和图6所示，第一隔垫物PS11在第二方向Y的宽度大于第三隔垫物PS12在第二方向Y上的宽度；并且第一隔垫物PS11在第一方向X的宽度不小于第三隔垫物PS12在第一方向X上的宽度。这样，可以使第一隔垫物PS11在衬底基板10的正投影的面积大于第三隔垫物PS12在衬底基板10的正投影的面积。
示例性地，如图5和图6所示，第三隔垫物PS12对应的子像素可以包括第一子像素SP1和第二子像素SP2。其中，沿第二方向Y相邻的第三隔垫物PS12之间设置有一个第一子像素SP1的阳极YG1和一个第二子像素SP2的阳极YG2。这样，可以使沿第二方向Y相邻的第三隔垫物PS12被一个第一子像素SP1的阳极YG1和一个第二子像素SP2的阳极YG2间隔开。
示例性地，如图5和图6所示，第一隔垫物PS11对应的子像素包括第三子像素SP3。其中，沿第二方向Y相邻的第一隔垫物PS11之间设置有一个第三子像素SP3的阳极YG3。这样可以使沿第二方向Y相邻的第一隔垫物PS11被一个第三子像素SP3的阳极YG3间隔开。
示例性地，如图5和图6所示，第一隔垫物PS11所在列和第三隔垫物PS12所在列沿第一方向X交替排列；并且第一隔垫物PS11和第三隔垫物PS12沿第一方向X交替排列于一条直线上。这样，可以使第一隔垫物PS11和第三隔垫物PS12在第一方向X上和第二方向Y上交替排列，从而可以尽可能均匀的排列。
示例性地，如图5和图6所示，多个第五隔垫物PS13可以与第一隔垫物PS11和第三隔垫物PS12间隔设置。第五隔垫物PS13的面积与第一隔垫物PS11的面积不同。 第五隔垫物PS13在第二方向Y上的正投影与第一隔垫物PS11和第三隔垫物PS12在第二方向Y上的正投影不交叠。
示例性地，如图5和图6所示，第三隔垫物PS12和第五隔垫物PS13交替排列于一列中，且相邻的第三隔垫物PS12和第五隔垫物PS13设置有一个子像素的主体部。示例性地，在第二方向Y上，一个第五隔垫物PS13具有相邻的两个第三隔垫物PS12，这两个第三隔垫物PS12中的一个位于第五隔垫物PS13上方，另一个位于第五隔垫物PS13下方。并且，该第五隔垫物PS13与位于其上方的第三隔垫物PS12之间设置有一个第一子像素SP1的阳极YG1的主体部，该第五隔垫物PS13与位于其下方的第三隔垫物PS12之间设置有一个第二子像素SP2的阳极YG2的主体部。
示例性地，如图5和图6所示，第五隔垫物PS13的面积与第三隔垫物PS12的面积之间具有第三比值，第三比值可以为0.8～1.2。示例性地，也可以使第三比值为0.9～1.1。例如，可以使第三比值为0.8。也可以使第三比值为0.9。也可以使第三比值为1.0。也可以使第三比值为1.1。也可以使第三比值为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5和图6所示，第五隔垫物PS13在衬底基板10的正投影与第一子像素SP1中的过孔部VH1在衬底基板10的正投影至少具有交叠区域。示例性地，第五隔垫物PS13在衬底基板10的正投影可以覆盖第一子像素SP1中的过孔部VH1在衬底基板10的正投影。
示例性地，如图5和图6所示，第五隔垫物PS13在第二方向Y上的宽度与第一子像素SP1的开口在第二方向Y上的宽度之间具有第四比值。即第四比值可以为第五隔垫物PS13在第二方向Y上的宽度除以第一子像素SP1的开口在第二方向Y上的宽度后的值。示例性地，第四比值可以为0.4～0.8。示例性地，也可以使第四比值为0.5～0.7。例如，可以使第四比值为0.4。也可以使第四比值为0.5。也可以使第四比值为0.6。也可以使第四比值为0.7。也可以使第四比值为0.8。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5和图6所示，第三隔垫物PS12在第二方向Y上的宽度与第二子像素SP2中的开口在第二方向Y上的宽度之间具有第五比值。即第五比值可以为第三隔垫物PS12在第二方向Y上的宽度除以第二子像素SP2中的开口在第二方向Y上的宽度后的值。示例性地，第五比值可以为0.4～0.8。例如，可以使第五比值可以为0.5～0.7。示例性地，可以使第五比值可以为0.4。也可以使第五比值可以为0.5。也可 以使第五比值可以为0.6。也可以使第五比值可以为0.7。也可以使第五比值可以为0.8。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5和图6所示，在第二方向Y上，第一隔垫物PS11和相邻的第三子像素SP3的开口KK3之间具有第一间距HW1。在第二方向Y上，第三隔垫物PS12和最近邻的第二子像素SP2的开口KK2之间具有第二间距HW2，且第三隔垫物PS12和最近邻的第一子像素SP1的开口KK1之间具有第三间距HW3。在第二方向Y上，第五隔垫物PS13和最近邻的第二子像素SP2的开口KK2之间具有第四间距HW4，且第五隔垫物PS13和最近邻的第一子像素SP1的开口KK1之间具有第五间距HW5。第二间距HW2、第三间距HW3、第四间距HW4以及第五间距HW5均小于第一间距HW1。
示例性地，可以使第二间距HW2与第三间距HW3之间的比值为0.8～1.2。示例性地，也可以使第二间距HW2与第三间距HW3之间的比值为0.9～1.1。例如，可以使第二间距HW2与第三间距HW3之间的比值为0.8。也可以使第二间距HW2与第三间距HW3之间的比值为0.9。也可以使第二间距HW2与第三间距HW3之间的比值为1.0。也可以使第二间距HW2与第三间距HW3之间的比值为1.1。也可以使第二间距HW2与第三间距HW3之间的比值为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，可以使第四间距HW4与第五间距HW5之间的比值为0.8～1.2。示例性地，也可以使第四间距HW4与第五间距HW5之间的比值为0.9～1.1。例如，可以使第四间距HW4与第五间距HW5之间的比值为0.8。也可以使第四间距HW4与第五间距HW5之间的比值为0.9。也可以使第四间距HW4与第五间距HW5之间的比值为1.0。也可以使第四间距HW4与第五间距HW5之间的比值为1.1。也可以使第四间距HW4与第五间距HW5之间的比值为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图5所示，在行方向上，第五隔垫物PS13、第一子像素SP1中的过孔部VH1、第二子像素SP2中的过孔部VH2以及第三子像素SP3中的过孔部VH3排列于同一直线上。
需要说明的是，上述各过孔和各通孔的形状可以为矩形、圆角矩形、圆形、椭圆形、正方形、六边形、八边形等，其可以根据实际应用的需求进行设计，在此不作限定。
结合参照图4至图6，多个第一隔垫物重复单元PSX1沿第一方向X和第二方向Y成阵列地布置于显示区域AA内。第三隔垫物PS12和第五隔垫物PS13交替排列于一列中，第一隔垫物PS11和第三隔垫物PS12位于不同列，多个第一隔垫物PS11重复排列于一列中，并且第三隔垫物PS12和第五隔垫物PS13所在的列与第一隔垫物PS11所在的列沿第一方向X交替排列。
多个第二隔垫物重复单元PSX2布置于显示区域AA外，即位于周边区域NA。例如，在最外侧的一列像素重复单元(例如，靠近第三边界AA3的一列像素重复单元或靠近第四边界AA4的一列像素重复单元)的外侧(即，朝向显示面板的外侧边缘的一侧)，设置有至少一列第二隔垫物重复单元PSX2。在最外侧的一行像素重复单元(例如，靠近第一边界AA1的一行像素重复单元或靠近第二边界AA2的一行像素重复单元)的外侧(即，朝向显示面板的外侧边缘的一侧)，设置有至少一行第二隔垫物重复单元PSX2。
示例性地，参照图4，对于一行第一隔垫物重复单元PSX1，在远离第三边界AA3的一侧上设置有至少一个第二隔垫物重复单元PSX2，并且在远离第四边界AA4的一侧上设置有至少一个第二隔垫物重复单元PSX2。即，在一行第一隔垫物重复单元PSX1沿第一方向X的相对两侧上，分别设置至少一个第二隔垫物重复单元PSX2。例如，在一行第一隔垫物重复单元PSX1的相对两侧上，分别设置1个、2个、3个或更多个第二隔垫物重复单元PSX2。
对于一列第一隔垫物重复单元PSX1，在远离第一边界AA1的一侧上设置有至少一个第二隔垫物重复单元PSX2，并且在远离第二边界AA2的一侧上设置有至少一个第二隔垫物重复单元PSX2。即，在一列第一隔垫物重复单元PSX1沿第二方向Y的相对两侧上，分别设置至少一个第二隔垫物重复单元PSX2。例如，在一列第一隔垫物重复单元PSX1沿第二方向Y的相对两侧上，分别设置1个、2个、3个或更多个第二隔垫物重复单元PSX2。
图7是图4中的部分VIII的局部放大图。结合参照图4至图7，一个第二隔垫物重复单元PSX2可以包括至少一个第二隔垫物PS21、至少一个第四隔垫物PS22和至少一个第六隔垫物PS23，例如，一个第二隔垫物重复单元PSX2可以包括一个第二隔垫物PS21、一个第四隔垫物PS22和一个第六隔垫物PS23。
参照图4和图7，第四隔垫物PS22和第六隔垫物PS23交替排列于一列中，第二隔垫物PS21和第四隔垫物PS22位于不同列，多个第二隔垫物PS21重复排列于一列 中，并且第四隔垫物PS22和第六隔垫物PS23所在的列与第二隔垫物PS21所在的列沿第一方向X交替排列。第二隔垫物PS21和第四隔垫物PS22沿第一方向X交替排列。
例如，第二隔垫物PS21、第四隔垫物PS22和第六隔垫物PS23分别沿第一方向X延伸。
示例性地，如图4所示，在一行第一隔垫物重复单元PSX1沿第一方向X的相对两侧上，分别设置至少一个第二隔垫物重复单元PSX2。即，至少两个第二隔垫物重复单元PSX2与一行第一隔垫物重复单元PSX1可以位于同一行。在位于同一行的多个第一隔垫物重复单元PSX1和至少两个第二隔垫物重复单元PSX2中，第二隔垫物PS21、第四隔垫物PS22与第一隔垫物PS11和第三隔垫物PS12位于同一直线，即，沿第一方向X彼此对齐；第六隔垫物PS23与第三隔垫物PS13位于同一直线，即，沿第一方向X彼此对齐。
继续参照图4，在一列第一隔垫物重复单元PSX1沿第二方向Y的相对两侧上，分别设置至少一个第二隔垫物重复单元PSX2。即，至少两个第二隔垫物重复单元PSX2与一列第一隔垫物重复单元PSX1可以位于同一列。在位于同一列的多个第一隔垫物重复单元PSX1和至少两个第二隔垫物重复单元PSX2中，第四隔垫物PS22、第六隔垫物PS23与第三隔垫物PS12和第五隔垫物PS13位于同一直线，即，沿第二方向Y彼此对齐；第二隔垫物PS21与第一隔垫物PS11位于同一直线，即，沿第二方向Y彼此对齐。
示例性地，结合参照图4、图6和图7，第二隔垫物PS21在第二方向Y的宽度大于第四隔垫物PS22在第二方向Y上的宽度；并且第二隔垫物PS21在第一方向X的宽度不小于第四隔垫物PS22在第一方向X上的宽度。这样，可以使第二隔垫物PS21在衬底基板10的正投影的面积大于第四隔垫物PS22在衬底基板10的正投影的面积。
示例性地，多个第六隔垫物PS23可以与第二隔垫物PS21和第四隔垫物PS22间隔设置。第六隔垫物PS23的面积与第二隔垫物PS21的面积不同。第六隔垫物PS23在第二方向Y上的正投影与第二隔垫物PS21和第四隔垫物PS22在第二方向Y上的正投影不交叠。
示例性地，在第二方向Y上，一个第六隔垫物PS23具有相邻的两个第四隔垫物PS22，这两个第四隔垫物PS22中的一个位于第六隔垫物PS23上方，另一个位于第六隔垫物PS23下方。
示例性地，第六隔垫物PS23的面积与第四隔垫物PS22的面积之间具有第三比值，第三比值可以为0.8～1.2。示例性地，也可以使第三比值为0.9～1.1。例如，可以使第三比值为0.8。也可以使第三比值为0.9。也可以使第三比值为1.0。也可以使第三比值为1.1。也可以使第三比值为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
例如，第六隔垫物PS23在第二方向Y的宽度基本等于第四隔垫物PS22在第二方向Y上的宽度；并且第六隔垫物PS23在第一方向X的宽度基本等于第四隔垫物PS22在第一方向X上的宽度。这样，可以使第六隔垫物PS23在衬底基板10的正投影的面积基本等于第四隔垫物PS22在衬底基板10的正投影的面积。
继续参照图7，任意两个第二隔垫物PS21的面积比为0.8～1.2。例如，任意两个第二隔垫物PS21在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，任意两个第二隔垫物PS21的面积比为0.9～1.1。例如，任意两个第二隔垫物PS21的面积比可以为0.8。任意两个第二隔垫物PS21的面积比也可以为0.9。任意两个第二隔垫物PS21的面积比也可以为1.0。任意两个第二隔垫物PS21的面积比也可以为1.1。任意两个第二隔垫物PS21的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
任意两个第四隔垫物PS22的面积比为0.8～1.2。例如，任意两个第四隔垫物PS22在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，任意两个第四隔垫物PS22的面积比为0.9～1.1。例如，任意两个第四隔垫物PS22的面积比可以为0.8。任意两个第四隔垫物PS22的面积比也可以为0.9。任意两个第四隔垫物PS22的面积比也可以为1.0。任意两个第四隔垫物PS22的面积比也可以为1.1。任意两个第四隔垫物PS22的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
任意两个第六隔垫物PS23的面积比为0.8～1.2。例如，任意两个第六隔垫物PS23在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，任意两个第六隔垫物PS23的面积比为0.9～1.1。例如，任意两个第六隔垫物PS23的面积比可以为0.8。任意两个第六隔垫物PS23的面积比也可以为0.9。任意两个第六隔垫物PS23的面积比也可以为1.0。任意两个第六隔垫物PS23的面积比也可以为1.1。任意两个第六隔垫物PS23的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比为0.8～1.2。例如，位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比为0.9～1.1。例如，位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比可以为0.8。位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比也可以为0.9。位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比也可以为1.0。位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比也可以为1.1。位于同一行或位于同一列的第二隔垫物PS21与第一隔垫物PS11的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比为0.8～1.2。例如，位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比为0.9～1.1。例如，位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比可以为0.8。位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比也可以为0.9。位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比也可以为1.0。位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比也可以为1.1。位于同一行或位于同一列的第四隔垫物PS22与第三隔垫物PS12的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比为0.8～1.2。例如，位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13在衬底基板10的正投影的面积比可以为0.8～1.2。示例性地，位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比为0.9～1.1。例如，位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比可以为0.8。位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比也可以为0.9。位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比也可以为1.0。位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比也可以为1.1。位于同一行或位于同一列的第六隔垫物PS23与第五隔垫物PS13的面积比也可以为1.2。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图6和图7所示，沿第二方向Y相邻的第二隔垫物PS21之间具有间隔距离HG21，沿第二方向Y相邻的第四隔垫物PS22之间具有间隔距离HG22，间隔距离HG22大于间隔距离HG21。沿第二方向Y相邻的第六隔垫物PS23之间具有间隔距离HG23，间隔距离HG23与间隔距离HG22之间的比值为0.8～1.2，例如，间隔距离HG23可以基本等于间隔距离HG22。例如，间隔距离HG23大于间隔距离HG21。
例如，间隔距离HG1与间隔距离HG21之间的比值为0.8～1.2，例如，间隔距离HG1可以基本等于间隔距离HG21。间隔距离HG2与间隔距离HG22之间的比值为0.8～1.2，例如，间隔距离HG2可以基本等于间隔距离HG22。间隔距离HG3与间隔距离HG23之间的比值为0.8～1.2，例如，间隔距离HG3可以基本等于间隔距离HG23。
同样地，间隔距离HG21可以为沿第二方向Y相邻的第二隔垫物PS21的边界之间的最小距离。间隔距离HG22可以为沿第二方向Y相邻的第四隔垫物PS22的边界之间的最小距离。间隔距离HG23可以为沿第二方向Y相邻的第六隔垫物PS23的边界之间的最小距离。
在同一第二隔垫物重复单元PSX2内，沿第二方向Y相邻的第四隔垫物PS22和第六隔垫物PS23之间具有间隔距离HG24。在沿第二方向Y相邻的两个第二隔垫物重复单元PSX2内，沿第二方向Y相邻的第四隔垫物PS22和第六隔垫物PS23之间具有间隔距离HG25。间隔距离HG24与间隔距离HG25之间的比值为0.8～1.2，例如，间隔距离HG24可以基本等于间隔距离HG25。
示例性地，间隔距离HG24、HG25可以为沿第二方向Y相邻的第四隔垫物PS22和第六隔垫物PS23的边界之间的最小距离。
示例性地，如图7所示，间隔距离HG22与间隔距离HG24或HG25之比可以为0.3～0.5。示例性地，间隔距离HG22与间隔距离HG24或HG25之比可以为0.4～0.48。例如，间隔距离HG22与间隔距离HG24或HG25之比可以为0.4。间隔距离HG22与间隔距离HG24或HG25之比可以为0.45。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，如图6和图7所示，在同一第一隔垫物重复单元PSX1内，沿第一方向X相邻的第一隔垫物PS11和第三隔垫物PS12之间具有间隔距离WG1。在沿第一方向X相邻的两个第一隔垫物重复单元PSX1内，沿第一方向X相邻的第一隔垫物PS11和第三隔垫物PS12之间具有间隔距离WG2。间隔距离WG1与间隔距离WG2之间的比值为0.8～1.2，例如，间隔距离WG1可以基本等于间隔距离WG2。
在同一第二隔垫物重复单元PSX2内，沿第一方向X相邻的第二隔垫物PS21和第四隔垫物PS22之间具有间隔距离WG12。在沿第一方向X相邻的两个第二隔垫物重复单元PSX2内，沿第一方向X相邻的第二隔垫物PS21和第四隔垫物PS22之间具有间隔距离WG22。间隔距离WG12与间隔距离WG22之间的比值为0.8～1.2，例如，间隔距离WG12可以基本等于间隔距离WG22。
例如，间隔距离WG1与间隔距离WG12之间的比值为0.8～1.2，例如，间隔距离WG1可以基本等于间隔距离WG12。
例如，间隔距离WG2与间隔距离WG22之间的比值为0.8～1.2，例如，间隔距离WG2可以基本等于间隔距离WG22。
同样地，间隔距离WG1、WG2可以为沿第一方向X相邻的第一隔垫物PS11和第三隔垫物PS12的边界之间的最小距离。间隔距离WG12、WG22可以为沿第一方向X相邻的第二隔垫物PS21和第四隔垫物PS22的边界之间的最小距离。
图8至图23是示出图1中的部分I的示例性实施方式的一些膜层的平面图，其中，图8示意性示出了半导体层，图9示意性示出了第一导电层，图10示意性示出了半导体层和第一导电层的组合，图11示意性示出了第二导电层，图12示意性示出了半导体层、第一导电层和第二导电层的组合，图13A示意性示出了层间绝缘层，图13B示意性示出了半导体层、第一导电层、第二导电层和层间绝缘层的组合，图14示意性示出了第三导电层，图15示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层和第三导电层的组合，图16示意性示出了平坦化层，图17示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层和平坦化层的组合，图18示意性示出了第一电极层，图19示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层和第一电极层的组合，图20示意性示出了像素界定层，图21示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层、第一电极层和像素界定层的组合，图22示意性示出了隔垫物层，图23示意性示出了半导体层、第一导电层、第二导电层、层间绝缘层、第三导电层、平坦化层、第一电极层、像素界定层和隔垫物层的组合。
结合参照图1至图8，如上所述，所述显示面板可以包括设置在显示区域AA中的像素驱动电路以及设置在非显示区域NA中的扫描驱动电路300。示例性地，所述像素驱动电路和所述扫描驱动电路300均可以包括多个薄膜晶体管和至少一个电容。
例如，图31是根据本公开的一些示例性实施例的显示面板的一个像素驱动电路的 等效电路图。如图31所示，所述像素驱动电路可以包括：多根信号线61、62、63、64、65、66和67，多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7，以及存储电容器Cst。所述像素驱动电路用于驱动有机发光二极管(即OLED)。
多个薄膜晶体管包括驱动薄膜晶体管T1、开关薄膜晶体管T2、补偿薄膜晶体管T3、初始化薄膜晶体管T4、第一发光控制薄膜晶体管T5、第二发光控制薄膜晶体管T6以及旁路薄膜晶体管T7。
多根信号线包括：用于传输扫描信号Sn的扫描信号线61，用于将复位控制信号Sn-1传输至初始化薄膜晶体管T4的复位控制信号线62，用于将发光控制信号En传输至第一发光控制薄膜晶体管T5和第二发光控制薄膜晶体管T6的发光控制线63，用于传输数据信号Dm的数据线64，用于传输驱动电压VDD的驱动电压线65，用于传输初始化电压Vint的初始化电压线66，以及用于传输第一电压VSS的电源线67。
在本文中，除非另有说明，第一电压可以表示VSS电压。
驱动薄膜晶体管T1的栅极G1电连接至存储电容器Cst的一端Cst1(下文称为第一电容电极)，驱动薄膜晶体管T1的源极S1经由第一发光控制薄膜晶体管T5电连接至驱动电压线65，驱动薄膜晶体管T1的漏极D1经由第二发光控制薄膜晶体管T6电连接至OLED的阳极。驱动薄膜晶体管T1根据开关薄膜晶体管T2的开关操作接收数据信号Dm，以向OLED供应驱动电流Id。
开关薄膜晶体管T2的栅极G2电连接至扫描信号线61，开关薄膜晶体管T2的源极S2电连接至数据线64，开关薄膜晶体管T2的漏极D2经由第一发光控制薄膜晶体管T5电连接至驱动电压线65，同时电连接至驱动薄膜晶体管T1的源极S1。开关薄膜晶体管T2根据通过扫描信号线61传输的扫描信号Sn导通，以执行开关操作来将被传输至数据线64的数据信号Dm传输至驱动薄膜晶体管T1的源极S1。
补偿薄膜晶体管T3的栅极G3电连接至扫描信号线61，补偿薄膜晶体管T3的源极S3经由第二发光控制薄膜晶体管T6电连接至OLED的阳极，同时电连接至驱动薄膜晶体管T1的漏极D1。并且补偿薄膜晶体管T3的漏极D3与存储电容器Cst的一端(即第一电容电极)Cst1、初始化薄膜晶体管T4的漏极D4以及驱动薄膜晶体管T1的栅极G1电连接在一起。补偿薄膜晶体管T3根据通过扫描信号线61传输的扫描信号Sn导通，以将驱动薄膜晶体管T1的栅极G1和漏极D1彼此连接，从而执行驱动薄膜晶体管T1的二极管连接。
初始化薄膜晶体管T4的栅极G4电连接至复位控制信号线62，初始化薄膜晶体管 T4的源极S4电连接至初始化电压线66。并且初始化薄膜晶体管T4的漏极D4与存储电容器Cst的一端Cst1、补偿薄膜晶体管T3的漏极D3以及驱动薄膜晶体管T1的栅极G1电连接。初始化薄膜晶体管T4根据通过复位控制信号线62传输的复位控制信号Sn-1导通，以将初始化电压Vint传输至驱动薄膜晶体管T1的栅极G1，从而执行初始化操作来将驱动薄膜晶体管T1的栅极G1的电压初始化。
第一发光控制薄膜晶体管T5的栅极G5电连接至发光控制线63，第一发光控制薄膜晶体管T5的源极S5电连接至驱动电压线65。并且第一发光控制薄膜晶体管T5的漏极D5与驱动薄膜晶体管T1的源极S1和开关薄膜晶体管T2的漏极D2电连接。
第二发光控制薄膜晶体管T6的栅极G6电连接至发光控制线63，第二发光控制薄膜晶体管T6的源极S6电连接至驱动薄膜晶体管T1的漏极D1且电连接至补偿薄膜晶体管T3的源极S3。并且第二发光控制薄膜晶体管T6的漏极D6电连接至OLED的阳极。第一发光控制薄膜晶体管T5和第二发光控制薄膜晶体管T6根据通过发光控制线63传输的发光控制信号En并发(例如同时)导通，以将驱动电压VDD传输至OLED，从而允许驱动电流Id流进OLED中。
旁路薄膜品体管T7包括：栅极G7，连接至复位控制信号线62；源极S7，连接至第二发光控制薄膜晶体管T6的漏极D6和OLED的阳极；以及漏极D7，连接至初始化电压线66。旁路薄膜晶体管T7将复位控制信号Sn-1从复位控制信号线62传送至栅极G7。
存储电容器Cst的另一端(下文称为第二电容电极)Cst2电连接至驱动电压线65，并且OLED的阴极电连接至电源线67，以接收第一电压VSS。相应地，OLED从驱动薄膜晶体管T1接收驱动电流Id来发光，从而显示图像。
在本公开的示例性实施例中，所述GOA电路可以包括发光控制扫描驱动电路，例如，所述发光控制扫描驱动电路可以是用于发送发光控制信号En的EM GOA电路。如图18所示，其示意性示出了根据本公开的一些示例性实施例的发光控制扫描驱动电路的电路图。所述发光控制扫描驱动电路包括第一电压信号线VGH、第二电压信号线VGL、第一时钟信号线CK、第二时钟信号线CB和信号输出线E0。所述发光控制扫描驱动电路还包括多个移位寄存器单元。
例如，图32是根据本公开的一些示例性实施例的显示面板的一个扫描驱动电路的等效电路图。例如，所述扫描驱动电路300可以包括用于发送扫描信号Sn和/或复位控制信号Sn-1的GATE GOA电路。例如，GATE GOA电路可以与像素行一一对应， 即，一个GATE GOA电路对应一行像素，此时，一个GATE GOA电路输出的信号可以作为与该行GATE GOA电路对应的一行像素的扫描信号，也可以作为下一行像素的复位控制信号。换句话说，某一行像素的扫描信号来自与该行像素对应的GATE GOA电路输出的信号，该行像素的复位控制信号来自上一行像素对应的GATE GOA电路输出的信号。需要说明的是，对于EM GOA电路，可以采用两行驱动或四行驱动的方式，即，一个EM GOA电路的输出信号可以用于驱动两行或四行像素。
如图32所示，所述栅极扫描驱动电路包括第一电压信号线VGH、第二电压信号线VGL、第三时钟信号线GCK、第四时钟信号线GCB和信号输出线GO。所述栅极扫描驱动电路还包括多个移位寄存器单元。
如图32所示，所述多个移位寄存器单元中的至少一个移位寄存器单元可以包括第一电容C1、第二电容C2、第一晶体管Q1、第二晶体管Q2、第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第六晶体管Q6、第七晶体管Q7和第八晶体管Q8。
第一晶体管Q1的栅极QG1与时钟信号线GCK耦接，第一电极QS1与输入信号端GI耦接，第二电极QD1与第二晶体管的栅极QG2耦接。
第二晶体管Q2的第一电极QS2与时钟信号线GCK耦接，第二电极QD2与第六节点N6耦接。
第三晶体管Q3的栅极QG3与时钟信号端GCK耦接，第一电极QS3与电压信号线VGL耦接，第二电极QD3与第六节点N6耦接。
第四晶体管Q4的栅极QG4与第六节点N6耦接，第一电极QS4与电压信号线VGH耦接，第二电极QD4与信号输出线GO耦接。
第五晶体管Q5的栅极与第八节点N8耦接，第一电极QS5与时钟信号端QCB耦接，第二电极QD5与信号输出线GO耦接。
第六晶体管Q6的栅极QG6与第六节点N6耦接，第一电极QS6与电压信号线VGH耦接，第二电极QD6与第七节点N7耦接。
第七晶体管Q7的栅极QG7与时钟信号端GCB耦接，第一电极QS7与第七节点N7耦接，第二电极QD7与第五节点N5耦接。
第八晶体管Q8的栅极QG8与电压信号线VGL耦接，第一电极QS8与第五节点N5耦接，第二电极QD8与第八节点N8耦接。
第一电容C1的一端与第八节点N8耦接，另一端与第五晶体管Q5的第二电极QD5耦接。第二电容C2的一端与第六节点N6耦接，另一端与第四晶体管Q4的第一电极 QS4耦接。
例如，图33是根据本公开的一些示例性实施例的显示面板的一个扫描驱动电路的等效电路图。例如，所述扫描驱动电路300可以包括用于发送发光控制信号En的EM GOA电路。如图33所示，所述发光控制扫描驱动电路包括第一电压信号线VGH、第二电压信号线VGL、第一时钟信号线CK、第二时钟信号线CB和信号输出线E0。所述发光控制扫描驱动电路还包括多个移位寄存器单元。
如图33所示，所述多个移位寄存器单元中的至少一个移位寄存器单元可以包括第一电容C1、输出电容C2、输出复位电容C3、输出晶体管M10、输出复位晶体管M9、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8。
所述输出晶体管M10的栅极MG10与所述输出电容C2的第一极板C2a耦接，所述输出晶体管M10的第一电极MS10与第二电压信号线VGL耦接，所述输出晶体管M10的第二电极MD10与所述信号输出线E0耦接。
所述输出复位晶体管M9的栅极MG9与所述输出复位电容C3的第一极板C3a耦接，所述输出复位晶体管M9的第一电极MS9与所述输出复位电容C3的第二极板C3b耦接，所述输出复位晶体管M9的第二电极MD9与所述信号输出线E0耦接。
所述输出复位电容C3的第二极板C3b与所述第一电压信号线VGH耦接；所述输出电容C2的第二极板C2b与第二时钟信号线CB耦接。
所述第一晶体管M1的第一电极MS1与所述第二时钟信号线CB耦接，所述第一晶体管M1的第二电极MD1和所述第二晶体管M2的第一电极MS2分别与所述第一电容C1的第二极板C1b耦接，所述第一晶体管M1的栅极MG1与所述第一电容C1的第一极板C1a耦接。
所述第二晶体管M2的栅极MG2和第七晶体管M7的栅极MG7分别与所述第一时钟信号线CB耦接，所述第二晶体管M2的第二电极MD2与所述第三晶体管M3的第二电极MD3耦接；所述第二晶体管M2的第一电极MS2所述第一电容的第二极板C1b耦接。
所述第三晶体管M3的栅极MG3与所述输出晶体管M10的栅极MG10耦接，所述第三晶体管M3的第一电极MS3与所述第一电压信号线VGH耦接。
所述第四晶体管M4的栅极MG4与所述第五晶体管M5的栅极MG5都与第一时钟信号线CK耦接，所述第四晶体管M4的第一电极MS4与所述输出晶体管M10的第 一电极MS10都与第二电压信号线VGL耦接，所述第四晶体管M4的第二电极MD4与所述第六晶体管M6的第二电极MD6耦接。
所述第五晶体管M5的栅极MG5与所述第一时钟信号线CK耦接，第五晶体管M5的第二电极MD5与所述第六晶体管M6的栅极MG6耦接；所述第五晶体管M5的第一电极MS5与输入信号端E1耦接。
所述第六晶体管M6的第一电极MS1与第四晶体管M4的栅极MG4都与第一时钟信号线CK耦接，所述第六晶体管M6的第二电极MD6与所述第四晶体管M4的第二电极MD4耦接；所述第六晶体管M6的栅极MG6与第五晶体管的第二电极MD1耦接。
所述第七晶体管M7的栅极MG7与输出电容C2的第二极板C2b都与第二时钟信号线CB耦接，所述第七晶体管M7的第一电极MS7与所述第八晶体管M8的第二电极MD8耦接，所述第七晶体管M7的第二电极MD7与所述第六晶体管M6的栅极MG6耦接。
所述第八晶体管M8的栅极MG8与所述第一晶体管M1的栅极MG1耦接，所述第八品体管M8的第一电极MS8与第一电压信号线VGH耦接。
在图33中，标号为N1的为第一节点，标号为N2的为第二节点，标号为N3的为第三节点，标号为N4的为第四节点。
在图33所示的实施例中，第一电压信号线VGH可以提供高电压VGH，第二电压信号线VGL可以提供低电压VGL，但不以此为限。
在本公开的实施例中，晶体管的第一电极可以为源极，晶体管的第二电极可以为漏极；或者，晶体管的第一电极可以为漏极，晶体管的第二电极可以为源极。
需要说明的是，在图31至图33中，各个晶体管具有单栅极结构，但是，本公开的实施例不局限于此，所述各个晶体管中的至少一些可以具有双栅极结构。在图31至图33中，各个晶体管是P沟道场效应晶体管，但是，本公开的实施例不局限于此，各个晶体管中的至少一些可以是N沟道场效应晶体管。
在上面的描述中，以7T1C像素驱动电路等电路结构为例，对位于显示区域AA中的每一个子像素的所述像素驱动电路的结构和位于非显示区域中的扫描驱动电路的结构进行详细描述，但是，本公开的实施例并不局限于上述的电路结构，在不冲突的情况下，其它已知的电路结构都可以应用于本公开的实施例中。
返回参照图8，示意性示出了半导体层20。例如，上述各个晶体管的有源层可沿 着如图8中的半导体层20形成。半导体层20可具有弯曲或弯折形状，并且可包括对应于各个晶体管的有源层。例如，半导体层20可以由诸如低温多晶硅的半导体材料形成，其膜层厚度可以在400～800埃的范围内，例如500埃。所述有源层可以包括例如多晶硅，并且例如包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
参照图9，示意性示出了第一导电层21。例如，上述各个晶体管的栅极、电容的一个电极以及至少一些信号线可以位于第一导电层21中。例如，第一导电层21可以由形成晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～4000埃的范围内，例如3000埃。
示例性地，参照图9和图10，在显示区域AA中，扫描信号线61、复位信号线62和发光控制线63均位于第一导电层21中。上述各个晶体管的栅极G1～G7也均位于第一导电层21中。例如，复位信号线62与半导体层20重叠的部分分别形成第一晶体管T1的栅极G1和第七晶体管T7的栅极G7，扫描信号线61与半导体层20重叠的部分分别形成第二晶体管T2的栅极G2和第四晶体管T4的栅极G4，发光控制线63与半导体层20重叠的部分分别形成第六晶体管T6的栅极G6和第五晶体管T5的栅极G5。
示例性地，参照图9至图12，在周边区域NA中，一个负载补偿单元100可以包括多个补偿电容，例如3个补偿电容。所述多个补偿电容可以包括第一补偿电容、第二补偿电容和第三补偿电容。在一组对应的负载补偿单元100和一列像素单元P中，第一补偿电容可以用于补偿一列第一子像素SP1，第二补偿电容可以用于补偿一列第二子像素SP2，第三补偿电容可以用于补偿一列第三子像素SP3。例如，每一个补偿电容可以包括第一补偿电容电极101和第二补偿电容电极102，第一补偿电容电极101位于第一导电层21中。如图9所示，在一个负载补偿单元中，多个补偿电容的第一补偿电容电极101彼此之间间隔设置，即，在任意相邻的两个第一补偿电容电极101之间设置有间隙。例如，在图示的实施例中，每一个第一补偿电容电极101可以沿第二方向Y延伸，一个负载补偿单元1内的多个第一补偿电容电极101可以沿第一方向X间隔设置。
示例性地，参照图9和图10，在周边区域NA中，所述扫描驱动电路300包括的 晶体管的栅极、电容的一个电极以及至少一些信号线可以位于第一导电层21中。
示例性地，参照图9和图10，在周边区域NA中，所述显示面板可以包括用于承载封装结构30的支撑部301。该支撑部301位于第一导电层21中。支撑部301位于扫描驱动电路300所在的区域远离显示区域AA的一侧。支撑部301在衬底基板上的正投影与半导体层20在所述衬底基板上的正投影不重叠。
例如，支撑部301可以包括支撑主体部302、多个开孔或凹槽303和多个导电部304。在第一导电层21中，支撑部301与扫描驱动电路300间隔设置。例如Frit的封装结构30可以形成在该支撑部301中，这样，支撑部301可以用来支撑所述封装结构30。例如，多个开孔或凹槽303可以形成在支撑主体部302中，这样，在形成例如Frit的封装结构30时，封装结构30的至少一部分可以嵌入多个开孔或凹槽303中，以增强所述封装结构30与所述支撑部301之间的结合力。例如，在图示的实施例中，每一个开孔或凹槽303在衬底基板上的正投影呈矩形或正方形形状。需要说明的是，本公开的实施例不局限于此，每一个开孔或凹槽303在衬底基板上的正投影可以具有其他形状。
多个导电部304位于支撑主体部302靠近所述扫描驱动电路300的一侧，多个导电部304用于与传输电信号的信号线电连接，以接入所述电信号。以此方式，可以避免所述支撑部处于悬置(即floating)状态。
参照图11，示意性示出了第二导电层22。例如，电容的另一个电极以及至少一些信号线可以位于第二导电层22中。例如，第二导电层22可以由形成晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～4000埃的范围内，例如3000埃。
示例性地，参照图11和图12，在显示区域AA中，初始化电压线66和存储电容器的另一电极可以位于第二导电层22中。
示例性地，参照图11和图12，在周边区域NA中，所述负载补偿单元的第二补偿电容电极102可以位于第二导电层22中。例如，第一补偿电容电极101和第二补偿电容电极102相对设置，二者在衬底基板上的正投影彼此至少部分重叠，并且它们之间设置有介电层。例如，第一补偿电容电极101可以电连接至数据信号，第二补偿电容电极102可以电连接至驱动电压，即二者连接至不同的电压信号。这样，第一补偿电容电极101和第二补偿电容电极102彼此重叠的部分可以形成所述补偿电容。
在本公开的一些示例性实施例中，在一个负载补偿单元中，所述多个补偿电容的 第二补偿电容电极102彼此连接。换句话说，一个负载补偿单元的多个第二补偿电容电极102形成为连续延伸的整体结构。
例如，在一个负载补偿单元100中，所述多个补偿电容的第一补偿电容电极101在所述衬底基板上的正投影落入彼此连接的多个第二补偿电容电极102在所述衬底基板上的正投影内。通过这样的方式，有利于增大第一补偿电容电极与第二补偿电容电极之间的交叠面积，从而有利于增大补偿电容的电容值。
需要说明的是，在本公开的实施例中，多个相邻的负载补偿单元的第二补偿电容电极102可以彼此连接。换句话说，多个负载补偿单元的多个第二补偿电容电极102可以形成为连续延伸的整体结构。
示例性地，参照图11和图12，在周边区域NA中，所述扫描驱动电路300包括的电容的另一个电极以及至少一些信号线可以位于第二导电层22中。
示例性地，参照图11和图12，在周边区域NA中，所述支撑部301在衬底基板上的正投影与第二导电层22在所述衬底基板上的正投影不重叠。
图13A示意性示出了层间绝缘层，图13B示意性示出了半导体层20、第一导电层21、第二导电层22和层间绝缘层23的组合。如图13A和图13B所示，层间绝缘层23覆盖显示区域AA和周边区域NA的大部分。例如，层间绝缘层23可以覆盖显示区域AA中的大部分区域，并且层间绝缘层23可以覆盖周边区域NA中的大部分区域。
例如，在本文中，表述“大部分”可以表示50％以上的部分。
例如，所述显示面板可以包括多个过孔部VH4、多个过孔部VH5、多个过孔部VH6和多个过孔部VH7。多个过孔部VH4可以位于显示区域AA中，例如，多个过孔部VH4可以分别位于多个子像素中，以分别暴露各个子像素的像素驱动电路的一部分。多个过孔部VH5可以位于扫描驱动电路300所在的区域，例如，多个过孔部VH5可以分别暴露各个扫描驱动电路300的一部分。多个过孔部VH6可以分别位于支撑部301所在的区域，例如，多个过孔部VH6可以分别暴露多个导电部304的至少一部分。这样，在后续形成导电层时，相应的导电层可以分别通过多个过孔部VH4、多个过孔部VH5和多个过孔部VH6与像素驱动电路、扫描驱动电路和导电部暴露的部分电连接。
多个过孔部VH7可以分别位于支撑部301所在的区域，例如，多个过孔部VH7可以分别位于多个开孔或凹槽303中。这样，在形成例如Frit的封装结构30时，封装结构30的至少一部分可以通过多个过孔部VH7分别嵌入多个开孔或凹槽303中，以 增强所述封装结构30与所述支撑部301之间的结合力。
参照图14和图15，示意性示出了第三导电层24。例如，第三导电层24可以由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第三导电层24可以具有由Ti/Al/Ti形成的叠层结构，其膜层厚度可以在6000～9000埃的范围内。例如，在第三导电层24具有由Ti/Al/Ti形成的叠层结构的情况下，Ti/Al/Ti每一层的厚度可以分别为约500埃、6000埃和500埃。
示例性地，在显示区域AA中，所述像素驱动电路包括的各个晶体管的源极和漏极可以位于第三导电层24中，一些信号线(例如数据信号线64以及驱动电压线65)可以位于第三导电层24中。
示例性地，在周边区域NA中，所述扫描驱动电路300包括的各个晶体管的源极和漏极可以位于第三导电层24中，一些信号线可以位于第三导电层24中。
例如，所述显示面板还可以包括驱动电压引线650，用于提供驱动电压VDD。例如，驱动电压引线650可以位于扫描驱动电路300与显示区域AA之间。驱动电压引线650可以通过多个过孔与一个第二补偿电容电极120电连接。也就是说，第二补偿电容电极120的一端电连接至驱动电压引线650，另一端电连接至驱动电压线65。以此方式，可以将驱动电压引线650提供的驱动电压VDD传输给驱动电压线65。
例如，所述显示面板还可以包括第一电压引线670，用于提供驱动电压VSS。例如，第一电压引线670可以位于扫描驱动电路300远离显示区域AA的一侧。
参照图15，第一电压引线670可以通过多个过孔VH6与位于第一导电层21中的导电部304电连接。即，第一电压引线670可以与支撑部301电连接。通过这样的电连接方式，支撑部301可以接入第一电压VSS，以避免支撑部301处于悬置状态。
参照图16和图17，示意性示出了平坦化层PLN。在显示区域AA中，平坦化层PLN覆盖显示区域AA的大部分区域，例如，平坦化层PLN可以包括多个过孔，例如，后续形成的各个子像素的阳极可以通过这些过孔与位于下层的像素驱动电路电连接。在周边区域NA中，平坦化层PLN暴露周边区域NA的大部分区域。例如，平坦化层PLN覆盖所述扫描驱动电路300所在的区域。所述扫描驱动电路300所在的区域包括远离显示区域AA的边界线300S，平坦化层PLN不覆盖从边界线300S朝着远离显示区域AA的方向延伸的区域。例如，平坦化层PLN不覆盖第一电压引线670，也不覆盖支撑部301。换句话说，平坦化层PLN包括远离显示区域AA的边界PLNS，第一电压引线670包括靠近显示区域AA的边界670S，边界PLNS在衬底基板10上的正 投影与边界670S在衬底基板10上的正投影基本重合。
参照图18和图19，示意性示出了第一电极层25。在显示区域AA中，上述各个子像素的阳极YG1～YG3可以位于该第一电极层25中。在周边区域NA中，所述显示面板包括位于第一电极层25中的辅助导电部251。例如，辅助导电部251可以与第一电压引线670至少部分接触。如上所述，平坦化层PLN未覆盖第一电压引线670，在形成第一电极层25时，可以使辅助导电部251在衬底基板10上的正投影与第一电压引线670在衬底基板10上的正投影至少部分重叠。这样，辅助导电部251的一部分可以与第一电压引线670的一部分直接接触，从而在二者之间形成电连接。也就是说，在本公开的实施例中，位于第三导电层23中的第一电压引线670和位于第一电极层25中的辅助导电部251并联连接，它们都用来传输第一电压VSS。采用这样的方式，可以减小传输第一电压VSS的信号线上的电阻。
参照图19，辅助导电部251在衬底基板10上的正投影与扫描驱动电路300在衬底基板10上的正投影至少部分重叠，例如，辅助导电部251在衬底基板10上的正投影可以基本完全覆盖扫描驱动电路300在衬底基板10上的正投影。即，辅助导电部251设置得较宽，从而有利于进一步减小传输第一电压VSS的信号线上的电阻。
示例性地，辅助导电部251还可以包括多个开孔252。平坦化层PLN通常采用有机树脂材料制作形成，平坦化层PLN中存在有部分遇热易挥发的有机物质，例如有机溶剂或小分子材料等。这些有机物质容易在显示面板后续的制作工艺中遇热挥发，导致平坦化层出现放气现象。通过在第一电极层25中设置多个开孔252，有利于平坦化层PLN中的有机物质在显示面板后续的制作工艺中遇热挥发出去，从而可以避免在第一电极层25面向平坦化层PLN的表面出现气泡集聚。这样，有利于确保显示面板的工艺良率，进而确保显示面板的显示效果良好。
参照图20和图21，示意性示出了像素界定层PDL。例如，像素界定层PDL可以包括像素界定层主体PDL0、第一覆盖部PDL1和第二覆盖部PDL2。像素界定层主体PDL0的大部分都位于显示区域AA中，例如，在显示区域AA中，像素界定层PDL包括多个开口，例如上述各个子像素的开口KK1～KK3。在周边区域NA中，像素界定层PDL包括第一覆盖部PDL1和第二覆盖部PDL2。例如，参照图18和图19，辅助导电部251包括远离显示区域AA的边缘251S。参照图21，第二覆盖部PDL2在衬底基板10上的正投影覆盖边缘251S在衬底基板10上的正投影。例如，所述显示面板可以包括多个第一覆盖部PDL1，多个第一覆盖部PDL1在衬底基板上的正投影分别覆盖 多个开孔252在衬底基板上的正投影。通过设置第一覆盖部PDL1和第二覆盖部PDL2，可以将第一电极层25的边缘都覆盖住，从而可以保护第一电极层25。
在本公开的实施例中，像素界定层主体PDL0可以具有远离显示区域AA的边界PDLS。在图21所示的区域中，所述边界PDLS位于负载补偿单元100远离显示区域AA的一侧。例如，所述边界PDLS的一部分在衬底基板10上的正投影可以位于所述扫描驱动电路300在衬底基板10上的正投影与负载补偿单元100在衬底基板10上的正投影之间，所述边界PDLS的另一部分在衬底基板10上的正投影可以落入所述扫描驱动电路300在衬底基板10上的正投影内。
例如，位于显示区域AA中的多个子像素可以包括最靠外侧的一列子像素，即，最靠近周边区域NA的一列子像素。所述边界PDLS与最靠外侧的一列子像素间隔一定的距离。例如，在图21所示的区域中，所述边界PDLS与最靠外侧的一列子像素(图21中位于最左侧的一列子像素)沿第一方向X之间的距离可以为规定的值，或者说，该距离在规定的范围内。
需要说明的是，在下面的描述中，将进一步描述所述边界PDLS在显示面板的其他区域中的相对位置。
参照图22和图23，示意性示出了隔垫物层PSL。如上所述，所述隔垫物层PSL可以包括位于显示区域AA内的第一隔垫物重复单元PSX1和位于显示区域AA外的第二隔垫物重复单元PSX2。例如，一个第一隔垫物重复单元PSX1可以包括至少一个第一隔垫物PS11、至少一个第三隔垫物PS12和至少一个第五隔垫物PS13。例如，一个第二隔垫物重复单元PSX2可以包括至少一个第二隔垫物PS21、至少一个第四隔垫物PS22和至少一个第六隔垫物PS23。
图24是根据本公开的一些示例性实施例的显示面板沿图23中的线BB’截取的截面图。结合参照图8至图24，所述显示面板可以包括衬底基板10；设置于衬底基板10上的半导体层20；设置于半导体层20远离衬底基板10一侧的第一导电层21；设置于第一导电层21远离衬底基板10一侧的第二导电层22；设置于第二导电层22远离衬底基板10一侧的层间绝缘层23；设置于层间绝缘层23远离衬底基板10一侧的第三导电层24；设置于第三导电层24远离衬底基板10一侧的平坦化层PLN；设置于平坦化层PLN远离衬底基板10一侧的第一电极层25；设置于第一电极层25远离衬底基板10一侧的像素界定层PDL；和设置于像素界定层PDL远离衬底基板10一侧的隔垫物层PSL。
需要说明的是，根据本公开的实施例的显示面板不局限于上述膜层，在各个导电层之间，还可以设置一层或多层绝缘层。例如，在半导体层20与第一导电层21之间可以设置第一绝缘层IL1，在第一导电层21与第二导电层22之间可以设置第二绝缘层IL2。
如上所述，图8至图23示出的是根据本公开实施例的显示面板在图1中的部分I处的局部放大图。例如，在本公开的实施例中，参照图1，部分I为所述显示面板在第一圆角部10A(即左上角)处的部分，部分II为所述显示面板在第二圆角部10B(即右上角)处的部分，部分III为所述显示面板在第四圆角部10D(即右下角)处的部分，部分IV为所述显示面板在第二圆角部10B(即右上角)处的部分，部分V为所述显示面板在第一边界AA1附近(即上侧边缘)的部分，部分VI为所述显示面板在第二边界AA2附近(即下侧边缘)的部分。
图25A为根据公开的一些示例性实施例的显示面板在图1中的部分II处的局部放大图。图25B为图25A的局部放大图。图26为根据公开的一些示例性实施例的显示面板在图1中的部分III处的局部放大图。图27为根据公开的一些示例性实施例的显示面板在图1中的部分IV处的局部放大图。图28为根据公开的一些示例性实施例的显示面板在图1中的部分V处的局部放大图。图29为图28的局部放大图。图30为根据公开的一些示例性实施例的显示面板在图1中的部分VI处的局部放大图。
参照图23、图25A至图30，像素界定层PDL覆盖隔垫物层PSL，例如，像素界定层主体PDL0覆盖隔垫物PSL。换句话说，像素界定层PDL在衬底基板10上的正投影覆盖隔垫物层PSL在衬底基板10上的正投影，例如，像素界定层主体PDL0在衬底基板10上的正投影覆盖隔垫物层PSL在衬底基板10上的正投影。
参照图20和图21，所述像素界定层PDL(具体地，所述像素界定层主体PDL0)包括第一部分PDL01和第二部分PDL02，所述第二部分PDL02和所述第一部分PDL01为一体结构。所述第一部分PDL01位于显示区域AA且包括对应所述多个子像素的开口，所述开口在所述衬底基板的正投影位于所述多个子像素的所述第一电极在所述衬底基板的正投影内。所述第二部分PDL02位于周边区域NA。
结合参照图20至图23，第一隔垫物重复单元PSX1在衬底基板的正投影位于像素界定层的第一部分PDL01在所述衬底基板的正投影内，第二隔垫物重复单元PSX2在衬底基板的正投影位于像素界定层的第二部分PDL02在衬底基板的正投影内，且位于所述第二部分PDL02远离所述显示区域AA的边界PDLS靠近所述显示区域AA的一 侧。例如，所述第二隔垫物重复单元PSX2在衬底基板上的正投影与所述多个子像素的所述第一电极在衬底基板上的正投影不交叠。
参照图23，所述多个子像素包括最靠近所述周边区域NA的至少一排边缘子像素，例如，图23中所示的最左侧的一列子像素。所述第二隔垫物重复单元PSX2在所述衬底基板上的正投影的至少部分位于所述至少一排边缘子像素的第一电极在所述衬底基板上的正投影远离所述显示区域AA的一侧。
参照图22，所述隔垫物层包括多个所述第一隔垫物重复单元PSX1和多个所述第二隔垫物重复单元PSX2，多个第一隔垫物重复单元PSX1和多个第二隔垫物重复单元PSX2沿第一方向X和第二方向Y成阵列地布置。
结合参照图18、图19和图23，所述第二隔垫物重复单元PSX2在衬底基板上的正投影与第一电极层25在衬底基板上的正投影不交叠。
结合参照图1、图25A至图27，所述衬底基板10包括至少一个拐角部，所述驱动电压引线650包括位于所述至少一个拐角部中的多个台阶650P。多个第二隔垫物重复单元PSX2中的至少一些第二隔垫物重复单元PSX2在所述衬底基板上的正投影与所述驱动电压引线650的多个台阶650P在所述衬底基板上的正投影交叠，所述至少一些第二隔垫物重复单元PSX2成台阶地分布。
例如，对于与所述驱动电压引线650的多个台阶650P交叠的至少一些第二隔垫物重复单元PSX2而言，所述至少一些第二隔垫物重复单元PSX2的分布是基于所述驱动电压引线650在所述多个台阶650P处的延伸规律的。即，所述至少一些第二隔垫物重复单元PSX2形成的多个台阶分别位于所述驱动电压引线650的多个台阶650P处。
例如，参照图25A、图25B和图26，所述多个台阶650P包括第一台阶6501和第二台阶6502。所述第一台阶6501和所述第二台阶6502均沿第一方向X延伸，所述第一台阶6501沿第一方向X的尺寸大于所述第二台阶6502沿第一方向X的尺寸，与所述第一台阶6501交叠且位于同一行的第二隔垫物重复单元PSX2的数量大于与所述第二台阶6502交叠且位于同一行的第二隔垫物重复单元PSX2的数量；和/或，参照图25A和图27，所述第一台阶6501和所述第二台阶6502均沿第二方向Y延伸，所述第一台阶6501沿第二方向Y的尺寸大于所述第二台阶6502沿第二方向Y的尺寸，与所述第一台阶6501交叠且位于同一列的第二隔垫物重复单元PSX2的数量大于与所述第二台阶6502交叠且位于同一列的第二隔垫物重复单元PSX2的数量。
例如，对于位于衬底基板10的非拐角处的多个第二隔垫物重复单元PSX2而言， 所述多个第二隔垫物重复单元PSX2包括在第一方向X上最远离所述显示区域AA且位于所述显示区域AA一侧的一列第二隔垫物重复单元，所述一列第二隔垫物重复单元PSX2沿平行于第二方向Y的直线排列；和/或，参照图28至图30，对于位于衬底基板10的非拐角处的多个第二隔垫物重复单元PSX2而言，所述多个第二隔垫物重复单元PSX2包括在第二方向Y上最远离所述显示区域AA且位于所述显示区域AA一侧的一行第二隔垫物重复单元PSX2，所述一行第二隔垫物重复单元PSX2沿平行于第一方向X的直线排列。
结合参照图28和图29，所述显示面板还包括设置于所述衬底基板10上且位于所述周边区域NA中的第一数据引线641和第二数据引线642，所述第一数据引线641用于给一列第一子像素提供数据信号，所述第二数据引线642用于给一列第二子像素提供数据信号。例如，邻近所述第一数据引线641和所述第二数据引线642设置的至少一列第二隔垫物重复单元PSX2包括一列隔垫物，所述一列隔垫物包括交替排列的第二隔垫物PS21和第四隔垫物PS22，所述一列隔垫物在所述衬底基板上的正投影的大部分(例如50％以上的部分)在第一方向X上位于所述第一数据引线641的延伸直线和所述第二数据引线642的延伸直线之间。
结合参照图28和图29，所述显示面板还包括设置于所述衬底基板10上且位于所述周边区域NA中的第三数据引线643，所述第三数据引线643用于给一列第三子像素提供数据信号。例如，邻近所述第三数据引线643设置的至少一列第二隔垫物重复单元PSX2包括一列第六隔垫物PS23，所述第三数据引线643在所述衬底基板上的正投影延伸穿过所述一列第六隔垫物PS23中的至少一个在所述衬底基板上的正投影。
例如，所述一列第六隔垫物PS23中的至少一个在所述衬底基板上的正投影相对于所述第三数据引线643在所述衬底基板上的正投影对称。
参照图23和图25A，至少一些第二隔垫物重复单元PSX2在所述衬底基板上的正投影落入所述多个负载补偿单元100在所述衬底基板上的正投影内。
例如，所述第二隔垫物重复单元PSX2在所述衬底基板上的正投影与所述像素界定层主体的边界PDLS在所述衬底基板上的正投影间隔规定的距离。例如，所述规定的距离为20～300微米。
结合参照图22和图23，在沿第一方向X相邻的第一隔垫物重复单元PSX1和第二隔垫物重复单元PSX2中，沿第一方向X相邻的第一隔垫物PS11与第二隔垫物PS21之间具有间隔距离WG3，沿第一方向X相邻的第三隔垫物PS12与第四隔垫物PS22 之间具有间隔距离WG4，沿第一方向X相邻的第五隔垫物PS13与第六隔垫物PS23之间具有间隔距离WG5。例如，沿第一方向X相邻的两个第二隔垫物PS21之间的间隔距离WG12与所述间隔距离WG3之比为0.8～1.2，或者说，沿第一方向X相邻的两个第二隔垫物PS12之间的间隔距离WG12与所述间隔距离WG3基本相等。沿第一方向X相邻的两个第四隔垫物PS22之间的间隔距离与所述间隔距离WG4之比为0.8～1.2，或者说，沿第一方向X相邻的两个第四隔垫物PS22之间的间隔距离与所述间隔距离WG4基本相等。沿第一方向X相邻的两个第六隔垫物PS23之间的间隔距离与所述间隔距离WG5之比为0.8～1.2，或者说，沿第一方向X相邻的两个第六隔垫物PS23之间的间隔距离与所述间隔距离WG5基本相等。
例如，在一行第一隔垫物重复单元PSX1沿第一方向X的相对侧，分别设置有至少一个第二隔垫物重复单元PSX2。
例如，在一列第一隔垫物重复单元PSX1沿第二方向Y的相对侧，分别设置有至少两个第二隔垫物重复单元PSX2。
参照图23，在所述衬底基板10的拐角处，所述像素界定层主体的边界PDLS的一部分在所述衬底基板10上的正投影位于所述扫描驱动电路300在所述衬底基板上的正投影与所述负载补偿单元100在所述衬底基板上的正投影之间，所述像素界定层主体的边界PDLS的另一部分在所述衬底基板10上的正投影落入所述扫描驱动电路300在所述衬底基板上的正投影内。
在本公开的另一些实施例中，还提供一种显示装置。所述显示装置可以包括上述显示面板。例如，所述显示装置可以是智能电话、移动电话、视频电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环或智能手表)等。
虽然根据本公开的总体发明构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不远离本公开的总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (31)

  1. 一种显示面板，包括：
    衬底基板，包括显示区域和周边区域；
    设置于所述显示区域中的多个子像素，所述子像素包括第一电极，第二电极和位于所述第一电极和所述第二电极之间的功能层；
    设置于所述衬底基板上的第一电极层，所述多个子像素的所述第一电极位于所述第一电极层；
    设置在所述第一电极层远离所述衬底基板一侧的像素界定层，其中，所述像素界定层包括像素界定层主体，所述像素界定层主体包括第一部分和第二部分，所述第一部分位于显示区域且包括对应所述多个子像素的开口，所述开口在所述衬底基板的正投影位于所述多个子像素的所述第一电极在所述衬底基板的正投影内；所述第二部分位于周边区域，且所述第二部分和所述第一部分为一体结构；
    设置在所述像素界定层远离所述衬底基板一侧的隔垫物层，
    其中，所述隔垫物层包括第一隔垫物重复单元和第二隔垫物重复单元，所述第一隔垫物重复单元位于所述显示区域中，所述第二隔垫物重复单元位于所述周边区域中；
    所述第二隔垫物重复单元在衬底基板的正投影位于所述像素界定层的所述第二部分在衬底基板的正投影内，且位于所述第二部分远离所述显示区域的边界靠近所述显示区域的一侧，且所述第二隔垫物重复单元在衬底基板上的正投影与所述多个子像素的所述第一电极在衬底基板上的正投影不交叠。
  2. 如权利要求1所述的显示面板，其中，所述多个子像素包括最靠近所述周边区域的至少一排边缘子像素，所述第二隔垫物重复单元在所述衬底基板上的正投影的至少部分位于所述至少一排边缘子像素的第一电极在所述衬底基板上的正投影远离所述显示区域的一侧。
  3. 如权利要求1或2所述的显示面板，其中，所述隔垫物层包括多个所述第一隔垫物重复单元和多个所述第二隔垫物重复单元，多个第一隔垫物重复单元和多个第二隔垫物重复单元沿第一方向和第二方向成阵列地布置。
  4. 如权利要求1或2所述的显示面板，其中，所述第二隔垫物重复单元在衬底基板上的正投影与所述第一电极层在衬底基板上的正投影不交叠。
  5. 如权利要求1或2所述的显示面板，其中，所述多个子像素沿第一方向和第二方向成阵列地布置；
    所述第一隔垫物重复单元包括第一隔垫物和第三隔垫物，所述第一隔垫物和所述第三隔垫物位于不同列，一列第一隔垫物对应一列子像素，一列第二隔垫物对应另一列子像素；
    所述第二隔垫物重复单元包括第二隔垫物和第四隔垫物；以及
    对于沿第一方向位于同一行的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，第一隔垫物重复单元的第一隔垫物和第三隔垫物与第二隔垫物重复单元的第二隔垫物和第四隔垫物均位于同一行。
  6. 如权利要求5所述的显示面板，其中，所述第一隔垫物重复单元还包括第五隔垫物，所述第三隔垫物和所述第五隔垫物交替排列于一列中；
    所述第二隔垫物重复单元还包括第六隔垫物，所述第四隔垫物和第六隔垫物交替排列于一列中；以及
    对于沿第二方向位于同一列的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第三隔垫物和第五隔垫物与各个第二隔垫物重复单元的第四隔垫物和第六隔垫物均位于同一列。
  7. 如权利要求4所述的显示面板，其中，对于沿第一方向位于同一行的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第五隔垫物与各个第二隔垫物重复单元的第六隔垫物均位于同一行。
  8. 如权利要求6所述的显示面板，其中，对于沿第二方向位于同一列的多个第一隔垫物重复单元和多个第二隔垫物重复单元而言，各个第一隔垫物重复单元的第一隔垫物与各个第二隔垫物重复单元的第二隔垫物均位于同一列。
  9. 如权利要求1-8中任一项所述的显示面板，其中，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的驱动电压引线，所述驱动电压引线用于提供驱动电压；
    所述衬底基板包括至少一个拐角部，所述驱动电压引线包括位于所述至少一个拐角部中的多个台阶；以及
    多个第二隔垫物重复单元中的至少一些第二隔垫物重复单元在所述衬底基板上的正投影与所述驱动电压引线的多个台阶在所述衬底基板上的正投影交叠，所述至少一些第二隔垫物重复单元成台阶地分布。
  10. 如权利要求9所述的显示面板，其中，对于与所述驱动电压引线的多个台阶交叠的至少一些第二隔垫物重复单元而言，所述至少一些第二隔垫物重复单元形成的多个台阶分别位于所述驱动电压引线的多个台阶处。
  11. 如权利要求10所述的显示面板，其中，所述多个台阶包括第一台阶和第二台阶；以及
    所述第一台阶和所述第二台阶均沿第一方向延伸，所述第一台阶沿第一方向的尺寸大于所述第二台阶沿第一方向的尺寸，与一个所述第一台阶交叠且位于同一行的第二隔垫物重复单元的数量大于与一个所述第二台阶交叠且位于同一行的第二隔垫物重复单元的数量；和/或，所述第一台阶和所述第二台阶均沿第二方向延伸，所述第一台阶沿第二方向的尺寸大于所述第二台阶沿第二方向的尺寸，与一个所述第一台阶交叠且位于同一列的第二隔垫物重复单元的数量大于与一个所述第二台阶交叠且位于同一列的第二隔垫物重复单元的数量。
  12. 如权利要求1-11中任一项所述的显示面板，其中，对于位于衬底基板的非拐角处的多个第二隔垫物重复单元而言，所述多个第二隔垫物重复单元包括在第一方向上最远离所述显示区域且位于所述显示区域一侧的一列第二隔垫物重复单元，所述一列第二隔垫物重复单元沿平行于第二方向的直线排列；和/或，
    对于位于衬底基板的非拐角处的多个第二隔垫物重复单元而言，所述多个第二隔垫物重复单元包括在第二方向上最远离所述显示区域且位于所述显示区域一侧的一行第二隔垫物重复单元，所述一行第二隔垫物重复单元沿平行于第一方向的直线排列。
  13. 如权利要求12所述的显示面板，其中，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的第一数据引线和第二数据引线，所述第一数据引线用于给一列第一子像素提供数据信号，所述第二数据引线用于给一列第二子像素提供数据信号；以及
    邻近所述第一数据引线和所述第二数据引线设置的至少一列第二隔垫物重复单元包括一列隔垫物，所述一列隔垫物包括交替排列的第二隔垫物和第四隔垫物，所述一列隔垫物在所述衬底基板上的正投影的50％以上的部分在第一方向上位于所述第一数据引线的延伸直线和所述第二数据引线的延伸直线之间。
  14. 如权利要求13所述的显示面板，其中，所述显示面板还包括设置于所述衬底基板上且位于所述周边区域中的第三数据引线，所述第三数据引线用于给一列第三子像素提供数据信号；以及
    邻近所述第三数据引线设置的至少一列第二隔垫物重复单元包括一列第六隔垫物，所述第三数据引线在所述衬底基板上的正投影延伸穿过所述一列第六隔垫物中的至少一个在所述衬底基板上的正投影。
  15. 如权利要求14所述的显示面板，其中，所述一列第六隔垫物中的至少一个在所述衬底基板上的正投影相对于所述第三数据引线在所述衬底基板上的正投影对称。
  16. 如权利要求1-15中任一项所述的显示面板，其中，所述显示面板还包括：
    设置于所述衬底基板上且位于所述周边区域中的扫描驱动电路，所述扫描驱动电路用于输出扫描信号；和
    设置于所述衬底基板上且位于所述周边区域中的多个负载补偿单元，所述多个负载补偿单元位于所述扫描驱动电路与所述多个像素单元之间，
    其中，至少一些第二隔垫物重复单元在所述衬底基板上的正投影落入所述多个负载补偿单元在所述衬底基板上的正投影内。
  17. 如权利要求1-16中任一项所述的显示面板，其中，所述第二隔垫物重复单元在所述衬底基板上的正投影与所述像素界定层主体的边界在所述衬底基板上的正投影间隔规定的距离。
  18. 如权利要求17所述的显示面板，其中，所述规定的距离为20～300微米。
  19. 如权利要求6所述的显示面板，其中，在沿第二方向相邻的至少两个第二隔垫物重复单元中，沿第二方向相邻的第二隔垫物之间具有第一间隔距离，沿第二方向相邻的第四隔垫物之间具有第二间隔距离，所述第二间隔距离大于所述第一间隔距离。
  20. 如权利要求6或19所述的显示面板，其中，所述第二隔垫物在第二方向上的宽度大于所述第四隔垫物在第二方向上的宽度；和/或，
    所述第二隔垫物在第一方向上的宽度不小于所述第四隔垫物在第一方向上的宽度。
  21. 如权利要求6所述的显示面板，其中，所述第六隔垫物在所述衬底基板上的正投影的面积与所述第一隔垫物在所述衬底基板上的正投影的面积不同。
  22. 如权利要求6所述的显示面板，其中，所述第二隔垫物所在列和所述第四隔垫物所在列沿第一方向交替排列；和/或，
    所述第二隔垫物和所述第四隔垫物沿所第一方向交替排列于一条直线上；和/或，
    所述第四隔垫物和所述第六隔垫物交替排列于一列中。
  23. 如权利要求6、19-22中任一项所述的显示面板，其中，所述第一隔垫物在所述衬底基板上的正投影的面积与所述第二隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2；和/或，
    所述第三隔垫物在所述衬底基板上的正投影的面积与所述第四隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2；和/或，
    所述第五隔垫物在所述衬底基板上的正投影的面积与所述第六隔垫物在所述衬底基板上的正投影的面积之比为0.8～1.2。
  24. 如权利要求6、19-23中任一项所述的显示面板，其中，在沿第一方向相邻的第一隔垫物重复单元和第二隔垫物重复单元中，沿第一方向相邻的第一隔垫物与第二隔垫物之间具有第三间隔距离，沿第一方向相邻的第三隔垫物与第四隔垫物之间具有第四间隔距离，沿第一方向相邻的第五隔垫物与第六隔垫物之间具有第五间隔距离；以及
    沿第一方向相邻的两个第二隔垫物之间的间隔距离与所述第三间隔距离之比为0.8～1.2；和/或，沿第一方向相邻的两个第四隔垫物之间的间隔距离与所述第四间隔距离之比为0.8～1.2；和/或，沿第一方向相邻的两个第六隔垫物之间的间隔距离与所述第五间隔距离之比为0.8～1.2。
  25. 如权利要求3-24中任一项所述的显示面板，其中，在一行第一隔垫物重复单元沿第一方向的相对侧，分别设置有至少一个第二隔垫物重复单元；和/或，
    在一列第一隔垫物重复单元沿第二方向的相对侧，分别设置有至少两个第二隔垫物重复单元。
  26. 如权利要求16所述的显示面板，其中，在所述衬底基板的拐角处，所述像素界定层主体的边界的一部分在所述衬底基板上的正投影位于所述扫描驱动电路在所述衬底基板上的正投影与所述负载补偿单元在所述衬底基板上的正投影之间，所述像素界定层主体的边界的另一部分在所述衬底基板上的正投影落入所述扫描驱动电路在所述衬底基板上的正投影内。
  27. 如权利要求1-26中任一项所述的显示面板，其中，所述显示面板还包括：
    设置于所述衬底基板上且位于所述周边区域中的支撑部；和
    设置于所述支撑部远离所述衬底基板一侧且位于所述周边区域中的封装结构，
    其中，所述支撑部在所述衬底基板上的正投影位于所述像素界定层主体的边界在所述衬底基板上的正投影远离所述显示区域的一侧。
  28. 如权利要求27所述的显示面板，其中，所述支撑部包括支撑主体部、多个开孔或凹槽和多个导电部，所述多个开孔或凹槽位于所述支撑主体部中，所述多个导电部位于所述支撑主体部靠近所述显示区域的一侧。
  29. 如权利要求23所述的显示面板，其中，所述显示面板还包括第一电压引线和辅助导电部，所述第一电压引线用于提供第一电压，所述辅助导电部与所述第一电极位于同一层；以及
    所述辅助导电部的一部分与所述第一电压引线直接接触。
  30. 如权利要求29所述的显示面板，其中，所述像素界定层还包括第一覆盖部和第二覆盖部；
    所述显示面板还包括平坦化层，所述平坦化层位于所述第一电极层靠近所述衬底基板的一侧，所述辅助导电部包括多个开孔，所述多个开孔分别暴露所述平坦化层的一部分；以及
    所述第一覆盖部覆盖所述多个开孔，所述第二覆盖部覆盖所述辅助导电部远离所述显示区域的边缘。
  31. 一种显示装置，其中，包括，如权利要求1-30中任一项所述的显示面板。
PCT/CN2021/097197 2021-05-31 2021-05-31 显示面板和显示装置 WO2022252005A1 (zh)

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