WO2022247775A1 - 存储器及其擦除验证方法、操作方法、存储器系统 - Google Patents

存储器及其擦除验证方法、操作方法、存储器系统 Download PDF

Info

Publication number
WO2022247775A1
WO2022247775A1 PCT/CN2022/094436 CN2022094436W WO2022247775A1 WO 2022247775 A1 WO2022247775 A1 WO 2022247775A1 CN 2022094436 W CN2022094436 W CN 2022094436W WO 2022247775 A1 WO2022247775 A1 WO 2022247775A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
verification
voltage
block
erasing
Prior art date
Application number
PCT/CN2022/094436
Other languages
English (en)
French (fr)
Inventor
井冲
曹宏
Original Assignee
长江存储科技有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to CN202280001459.6A priority Critical patent/CN115136238A/zh
Publication of WO2022247775A1 publication Critical patent/WO2022247775A1/zh
Priority to US18/092,082 priority patent/US20240013842A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a memory and its erasure verification method, operation method, and memory system.
  • semiconductor memories having memory cells stacked vertically are widely used in electronic devices, which typically include vertically stacked multiple levels (e.g., three-dimensional nonvolatile There are multiple vertically stacked memory cells in each level in three-dimensional nonvolatile memory, so that each level can be read, programmed, and erased independently operate.
  • 3D three dimensions
  • the data system When the data system operates the three-dimensional non-volatile memory, it usually judges whether the erasing operation or the programming operation succeeds or fails according to the status fed back by the three-dimensional non-volatile memory. Generally, when the data system receives the status fed back by the three-dimensional non-volatile memory about the success of the program operation, the data stored in the cache of the data system will be released.
  • the embodiments of the present disclosure propose a memory and its erasure verification method, operation method, and memory system. By performing two verification operations on the memory, it is determined whether the memory block is a bad block, so as to determine whether to perform a program operation on the memory block, so that data loss can be reduced, and NPD phenomenon will not be caused in multi-faceted programming.
  • An embodiment of the present disclosure provides a memory erasure verification method, including:
  • the first verification result is configured to reflect whether the memory block is successfully erased after the erase operation
  • the second erasure verification operation is configured to determine whether the memory block has leakage between word lines.
  • the determining whether to perform a second erasure verification operation on the storage block based on the first verification result includes:
  • the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, it is determined to perform the second erasing verification operation on the storage block;
  • the first verification result is configured to indicate that the storage block is not successfully erased after the erasing operation, it is determined not to perform the second erasing verification operation on the storage block.
  • the erasing verification method also includes:
  • the second verification result is configured to reflect whether there is leakage between word lines in the memory block.
  • the erasing verification method also includes:
  • the first mark is configured to indicate that the storage block is a bad block.
  • the erasing verification method also includes:
  • a second flag is saved; the second flag is configured to indicate that the memory block is an available block.
  • the first erasing verification operation includes: applying an erasing verification voltage to the memory block, sensing a signal to be verified corresponding to the erasing verification voltage; determining the first verification signal based on the signal to be verified A first verification result of an erase verification operation.
  • the memory includes a plurality of storage blocks; each storage block includes a plurality of storage units and a plurality of word lines respectively coupled to the plurality of storage units; the applying erasure verification to the storage block voltage, including:
  • the erase verify voltage is applied to the plurality of word lines in the memory block using the same or different voltage sources.
  • the second erasing verification operation includes: applying a leakage detection voltage to the word line to be detected in the memory block, detecting the residual voltage of the word line to be detected after a preset time; comparing the residual voltage and a reference voltage to obtain a comparison result; and determine the second verification result based on the comparison result.
  • the applying leakage detection voltage to the word line to be detected in the memory block, and detecting the residual voltage of the word line to be detected after a preset time includes:
  • the remaining voltage of the word line to be detected is detected.
  • the determining the second verification result based on the comparison result includes:
  • determining that the second verification result is configured to indicate that the word line to be detected in the memory block is identical to the reference voltage There is no leakage between adjacent word lines;
  • the comparison result is that the absolute value of the difference between the remaining voltage and the reference voltage is not less than the preset threshold, it is determined that the second verification result is configured to indicate that the pending Leakage is detected between the word line and the adjacent word line.
  • the second erasing verification operation is performed by a leakage detection circuit between word lines built in the memory.
  • the erasing verification method also includes:
  • the first verification result is configured to indicate that the memory block is successfully erased after the erase operation, it is determined to perform the second erase verification operation on a predetermined range of word lines in the memory block.
  • the first flag or the second flag is stored in a register in the memory.
  • An embodiment of the present disclosure provides an operation method, including:
  • the operation method also includes:
  • the first verification result fed back is configured to indicate that the memory block has not been successfully erased after the erasing operation, judging whether the currently performed erasing operation has reached the maximum number of times of erasing;
  • An embodiment of the present disclosure provides a memory, including: a storage array; the storage array includes a plurality of storage blocks;
  • the peripheral circuit is configured to: perform a first erase verification operation on the memory block after performing an erase operation on the memory block selected in the memory; determine a first Verification result; determine whether to perform a second erasing verification operation on the storage block based on the first verification result; the first verification result is configured to reflect whether the storage block is successfully erased after the erasing operation In addition; the second erase verification operation is configured to determine whether there is leakage between word lines in the memory block.
  • the peripheral circuit includes: a control circuit, a voltage generator, a word line driver, and a sense amplifier; the voltage generator, the word line driver, and the sense amplifier are coupled to the plurality of memory blocks connected and controlled by the control circuit;
  • the word line driver is configured to: apply an erase verification voltage to the memory block through the voltage generator under the control of the control circuit;
  • the sense amplifier is configured to: sense a signal to be verified corresponding to the erase verification voltage;
  • the control circuit is configured to: determine a first verification result of the first erasure verification operation based on the signal to be verified; determine whether to perform a second erasure verification operation on the memory block based on the first verification result .
  • control circuit is further configured as:
  • the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, it is determined to perform the second erasing verification operation on the storage block;
  • the first verification result is configured to indicate that the storage block is not successfully erased after the erasing operation, it is determined not to perform the second erasing verification operation on the storage block.
  • control circuit is further configured to: when determining to perform the second erase verification operation on the storage block, perform the second erase verification operation on the stored block; determine the second A second verification result of the erase verification operation; the second verification result is configured to reflect whether there is leakage between word lines in the memory block.
  • the peripheral circuit further includes: a first register configured to: when the first verification result is configured to indicate that the memory block has not been successfully erased after the erase operation or when the When the second verification result indicates that the storage block has leakage between word lines, the first flag is saved; the first flag is configured to indicate that the storage block is a bad block.
  • the peripheral circuit further includes: a second register configured to: save a second flag when the second verification result shows that there is no leakage between word lines in the storage block; the second flag configured to characterize the memory block as an available block.
  • the peripheral circuit further includes: a leakage detection circuit between word lines, and the leakage detection circuit between word lines is coupled to the memory block;
  • the word line driver is further configured to: under the control of the control circuit, apply a leakage detection voltage to the word line to be detected in the memory block through the voltage generator; The word line is grounded; when the leakage detection voltage of the word line to be detected reaches a predetermined value, stop applying the leakage detection voltage to the word line to be detected;
  • the leakage detection circuit between word lines is configured to: detect the residual voltage of the word line to be detected after a preset time; compare the residual voltage with a reference voltage to obtain a comparison result; transmit the comparison result to the control circuit result;
  • the control circuit is further configured to: receive the comparison result and feed back the second verification result to the control circuit based on the comparison result.
  • control circuit is further configured as:
  • determining that the second verification result is configured to indicate that the word line to be detected in the memory block is identical to the reference voltage There is no leakage between adjacent word lines;
  • the comparison result is that the absolute value of the difference between the remaining voltage and the reference voltage is not less than the preset threshold, it is determined that the second verification result is configured to indicate that the pending Leakage is detected between the word line and the adjacent word line.
  • the peripheral circuit further includes: a first register configured to: when the first verification result is configured to indicate that the memory block has not been successfully erased after the erase operation or when the When the second verification result indicates that the storage block has leakage between word lines, the first flag is saved; the first flag is configured to indicate that the storage block is a bad block.
  • the peripheral circuit further includes: a second register configured to: save a second flag when the second verification result shows that there is no leakage between word lines in the storage block; the second flag configured to characterize the memory block as an available block.
  • the peripheral circuit further includes: a leakage detection circuit between word lines, and the leakage detection circuit between word lines is coupled to the memory block;
  • the word line driver is further configured to: under the control of the control circuit, apply a leakage detection voltage to the word line to be detected in the memory block through the voltage generator; The word line is grounded; when the leakage detection voltage of the word line to be detected reaches a predetermined value, stop applying the leakage detection voltage to the word line to be detected;
  • the leakage detection circuit between word lines is configured to: detect the residual voltage of the word line to be detected after a preset time; compare the residual voltage with a reference voltage to obtain a comparison result; transmit the comparison result to the control circuit result;
  • the control circuit is further configured to: receive the comparison result and feed back the second verification result to the control circuit based on the comparison result.
  • control circuit is further configured as:
  • determining that the second verification result is configured to indicate that the word line to be detected in the memory block is identical to the reference voltage There is no leakage between adjacent word lines;
  • the comparison result is that the absolute value of the difference between the remaining voltage and the reference voltage is not less than the preset threshold, it is determined that the second verification result is configured to indicate that the pending Leakage is detected between the word line and the adjacent word line.
  • the leakage detection circuit between word lines includes: a comparison module; wherein,
  • the comparison module is configured to: detect the residual voltage of the word line to be detected after a preset time; compare the residual voltage with the reference voltage to obtain a comparison result; transmit the comparison result to the control circuit .
  • the leakage detection circuit between word lines further includes: an isolation module, wherein the isolation module is configured to: isolate the comparison module and the voltage generator.
  • the comparison module includes: a reference voltage source and a comparator, wherein,
  • the reference voltage source is configured to: provide the reference voltage, and input the reference voltage to the comparator;
  • the comparator is configured to: detect the residual voltage of the word line to be detected after a preset time, and receive the reference voltage; compare the residual voltage with the reference voltage to obtain a comparison result; The comparison result is transmitted.
  • the isolation module includes: an isolation capacitor configured to: isolate the comparison module and the voltage generator.
  • the peripheral circuit is further configured to: when the first verification result indicates that the memory block has not been successfully erased after the erasing operation, determine that the A predetermined range of word lines performs the second erase verification operation.
  • the memory includes a three-dimensional NAND memory.
  • An embodiment of the present disclosure also provides a memory system, including:
  • a memory controller coupled to the memory.
  • the peripheral circuit is configured to receive a first instruction; in response to the first instruction, perform an erase operation on a selected storage block in the memory, and perform a first erase operation on the storage block Verification operation; feeding back the first verification result of the first erasing verification operation; determining whether to perform a second erasing verification operation on the storage block based on the first verification result; the second erasing verification operation is configured In order to determine whether there is leakage between word lines in the storage block; the first verification result is configured to indicate that the storage block has not been successfully erased after the erasing operation or there is leakage between word lines in the storage block In the case, save the first mark; when the first verification result is configured to indicate that the memory block is successfully erased after the erase operation and there is no leakage between word lines in the memory block, save the first mark two marks;
  • the memory controller is configured to, according to the first flag, issue a second instruction; according to the second flag, issue a third instruction;
  • the peripheral circuit is configured to receive the second instruction; in response to the second instruction, no longer program the memory block; receive the third instruction; in response to the third instruction, The memory block performs a program operation.
  • Embodiments of the present disclosure provide a memory and its erasure verification method, operation method, and memory system.
  • the erasing verification method includes: after performing the erasing operation on the selected storage block in the memory, performing a first erasing verification operation on the storage block; determining the first erasing verification operation A first verification result; the first verification result is configured to reflect whether the storage block is successfully erased after the erasing operation; based on the first verification result, it is determined whether to perform a second erasure on the storage block In addition to the verification operation; the second erasing verification operation is configured to determine whether there is leakage between word lines in the memory block.
  • the erasure verification method determines whether the selected storage block that has performed the erasing operation passes by determining the first verification result of the first erasure verification operation, and then determines whether to The storage block performs the second erasing verification operation to detect whether there is leakage between word lines in the storage block (it has been found through research that leakage between word lines is the main factor leading to data discarding), and through the erasing verification operation of the present disclosure, it can Effectively detect whether the memory block is a bad block, so as to effectively avoid data loss caused by abnormalities in subsequent programming operations.
  • programming exceptions can be limited to the abnormal storage plane itself , to reduce the impact of programming abnormalities on other normal storage planes, that is, to reduce the adverse effects caused by adjacent plane interference, that is, to reduce the probability of NPD phenomenon.
  • FIG. 1 is a block diagram of an exemplary system with memory provided according to an embodiment of the present disclosure
  • FIG. 2A is a schematic diagram of an exemplary memory card with memory according to an embodiment of the disclosure.
  • FIG. 2B is a schematic diagram of an exemplary solid-state drive (SSD) with memory provided in accordance with an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of an exemplary memory including peripheral circuits provided according to an embodiment of the present disclosure
  • Fig. 4a is an exemplary circuit diagram of a memory cell string provided according to an embodiment of the present disclosure
  • FIG. 4b is a schematic structural diagram of an exemplary memory cell string provided according to an embodiment of the present disclosure.
  • FIG. 5 is an exemplary structural diagram of a single storage block in a 3D memory according to an embodiment of the present disclosure
  • FIG. 6 is a block diagram of an exemplary memory including a memory array and peripheral circuits provided according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a memory including two storage planes provided according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an NPD phenomenon that occurs when a memory performs a programming operation in the related art
  • FIG. 9 is a schematic diagram of an implementation flow of a memory erasure verification method provided according to an embodiment of the present disclosure.
  • FIG. 10(A) and FIG. 10(B) are schematic diagrams of connections between word lines, between word lines and bit lines, leakage detection circuits, memory arrays, and peripheral circuits according to embodiments of the present disclosure
  • FIG. 11 is a schematic diagram of an implementation flow of a memory erasure verification method provided according to an embodiment of the present disclosure.
  • Fig. 12 is a schematic flowchart of an operation method of a memory system according to an embodiment of the present disclosure.
  • spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “on” and so on may be used herein to describe an element shown in the drawings. Or the relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of up and down.
  • descriptions of a first feature "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed on top of the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.
  • the term "three-dimensional (3D) memory device” refers to strings of memory cell transistors (herein referred to as “memory cell strings”, such as NAND strings) having vertical orientation on a laterally oriented substrate such that A semiconductor device in which strings of memory cells extend in a vertical direction with respect to a substrate.
  • memory cell strings such as NAND strings
  • vertical/vertically means nominally perpendicular to a lateral surface of the substrate.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned. Materials added on top of the substrate may be patterned or may remain unpatterned.
  • the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like.
  • the substrate can be made of a non-conductive material such as glass, plastic or a sapphire wafer.
  • a layer refers to a portion of material comprising a region having a thickness.
  • a layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure.
  • a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes there. Layers may extend horizontally, vertically and/or along the tapered surface.
  • a substrate may be a layer, may include one or more layers, and/or may have one or more layers thereon, above, and/or below. Layers may include multiple layers.
  • interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
  • FIG. 1 shows a block diagram of an example system 100 embodying a memory device in accordance with aspects of the present disclosure.
  • System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device or any other suitable electronic device having memory therein.
  • the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit ( CPU) or a system on chip (SoC), where the system on chip may be, for example, an application processor (AP).
  • CPU central processing unit
  • SoC system on chip
  • Host 108 may be configured to send data to or receive data from memory 104 .
  • the memory 104 may be any storage device disclosed in the present disclosure.
  • the memory 104 is, for example, a NAND flash storage device (such as a three-dimensional (3D) NAND flash storage device).
  • memory controller 106 is coupled to memory 104 and host 108 . And configured to control the memory 104 . Memory controller 106 may manage data stored in memory 104 and communicate with host 108 . In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives , or other media for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile phones, etc.
  • SD Secure Digital
  • CF Compact Flash
  • USB Universal Serial Bus
  • the memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as devices such as smartphones, tablets, laptops, Data storage for mobile devices in high duty cycle environments such as laptops and enterprise storage arrays.
  • the memory controller 106 may be configured to control operations of the memory 104, such as read, erase and program operations.
  • Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like.
  • memory controller 106 is also configured to process error correction code (ECC) on data read from or written to memory 104 .
  • ECC error correction code
  • Memory controller 106 may also perform any other suitable functions, such as formatting memory 104 .
  • Memory controller 106 may communicate with external devices (eg, host 108 ) according to a particular communication protocol.
  • the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.
  • PCI Peripheral Component Interconnect
  • PCI-E PCI Express
  • ATA Advanced Technology Attachment
  • SCSI Small Computer Small Interface
  • ESDI Enhanced Small Disk Interface
  • IDE Integrated Drive Electronics
  • Memory controller 106 and one or more memories 104 may be integrated into various types of storage devices, eg, included in the same package (eg, Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.
  • memory controller 106 and a single memory 104 may be integrated into memory card 202 .
  • the memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc.
  • the memory card 202 may also include a memory card connector 204 that couples the memory card 202 with a host (eg, host 108 in FIG. 1 ).
  • memory controller 106 and multiple memories 104 may be integrated into SSD 206.
  • SSD 206 may also include SSD connector 208 that couples SSD 206 to a host (e.g., host 108 in FIG. 1 ).
  • the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.
  • FIG. 3 shows a schematic circuit diagram of an exemplary memory 104 including peripheral circuits in accordance with aspects of the present disclosure.
  • the memory 104 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301 .
  • the memory array 301 may be a NAND flash memory array in which the memory transistors 306 are provided in an array of NAND memory cell strings 308 each extending vertically over a substrate (not shown).
  • each NAND memory cell string 308 includes a plurality of memory transistors 306 coupled in series and stacked vertically.
  • Each storage transistor 306 may hold a continuous analog value, eg, voltage or charge, depending on the number of electrons trapped within the area of the storage transistor 306 .
  • Each memory transistor 306 may be a floating gate type memory transistor including a floating gate transistor, or a charge trap type memory transistor including a charge trap transistor.
  • Each of the above-discussed storage transistors 306 may be a single-level memory cell or a multi-level memory cell, wherein a single-level memory cell may be a single-level cell capable of storing 1 bit (bit).
  • SLC the multilevel storage unit can be a multilevel cell (MLC) capable of storing 2 bits, a tertiary level cell (TLC) capable of storing 3 bits, a quadruple level cell (QLC) capable of storing 4 bits, and capable of storing 5-bit five-level unit (PLC) and so on.
  • MLC multilevel cell
  • TLC tertiary level cell
  • QLC quadruple level cell
  • PLC 5-bit five-level unit
  • each NAND memory cell string 308 may include a source select gate (SSG) 310 at its source terminal and a drain select gate (DSG) 312 at its drain terminal.
  • SSG 310 and DSG 312 may be configured to activate selected NAND memory cell strings 308 (columns of the array) during read and program operations.
  • the sources of the NAND memory cell strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (eg, a common SL).
  • SL source line
  • all NAND memory cell strings 308 in the same memory block 304 have an array common source (ACS).
  • each NAND memory cell string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown).
  • each NAND memory cell string 308 is configured to be selected by applying a select voltage (e.g., higher than the threshold voltage of the transistor with DSG 312) or a deselect voltage (e.g., 0 V) via one or more DSG lines 313.
  • a select voltage e.g., above the threshold voltage of a transistor with SSG 310
  • a deselect voltage e.g., 0V
  • NAND memory cell string 308 may be organized into a plurality of memory blocks 304 each of which may have a common source line 314 (eg, coupled to ground).
  • each memory block 304 is the basic data unit for an erase operation, ie, all memory transistors 306 on the same memory block 304 are erased simultaneously. It should be appreciated that, in some examples, erase operations may be performed at the half-block level, at the quarter-block level, or at any suitable number or fraction of blocks.
  • the storage transistors 306 of adjacent NAND memory cell strings 308 may be coupled by a word line 318 that selects which row of storage transistors 306 is affected by read and program operations.
  • each word line 318 is coupled to a page 320 of storage transistors 306, which is the basic unit of data for programming operations.
  • the size of a page 320 in bits may be related to the number of NAND memory cell strings 308 coupled by word lines 318 in a memory block 304 .
  • Each word line 318 may include a plurality of control gates (gate electrodes) at each storage transistor 306 in a corresponding page 320 and a gate line coupled to the control gates.
  • a storage block 304 can also be divided into multiple storage sub-blocks, and each storage sub-block is called a string. Then, performing an erasing operation on a storage block is to perform an erasing operation on all strings contained in the storage block.
  • FIG. 4 a and FIG. 4 b respectively show an exemplary circuit diagram and an exemplary structural schematic diagram of the memory cell string 308 .
  • the case where the memory cell string includes 4 memory transistors is shown in this embodiment. It can be understood that the present disclosure is not limited thereto, and the number of storage transistors in the storage cell string can be any number, such as 32 or 64.
  • the memory cell string 308 includes a plurality of transistors connected in series between a first terminal and a second terminal, including an upper selection transistor TSG, memory transistors M1 to M4, and a lower selection transistor BSG.
  • the upper selection transistor TSG is connected to the string selection line SSL through its included drain selection gate (DSG)
  • the lower selection transistor BSG is connected to the ground selection line GSL through its included source selection gate (SSG).
  • the gate conductors of memory transistors M1 - M4 are connected to respective ones of word lines WL1 - WL4 .
  • the drain select gate (DSG) may also be referred to as a first control gate
  • the source select gate (SSG) may also be referred to as a second control gate.
  • the memory cell string 308 structure includes channel pillars 110 .
  • the middle part of the channel column 110 includes a channel region 111 and a tunneling dielectric layer 112 , a charge storage layer 113 and a blocking dielectric layer 114 are disposed in the channel region 111 to form storage transistors M1 to M4 .
  • the channel region 111 is made of doped polysilicon, for example, and the tunnel dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114 can be respectively made of nitride, such as silicon nitride, silicon oxynitride, silicon or any combination thereof.
  • the channel region 111 is used to provide the channel region of the selection transistor and the storage transistor, and the doping type of the channel region 111 is the same as that of the selection transistor and the storage transistor.
  • the channel region 111 may be N-type doped polysilicon.
  • the core of the channel column 110 is the channel region 111 , and the tunneling dielectric layer 112 , the charge storage layer 113 and the blocking dielectric layer 114 form a laminated structure fixed around the sidewall of the core.
  • the core of the channel pillar 110 is an additional insulating layer, and the channel region 111 , the tunneling dielectric layer 112 , the charge storage layer 113 and the blocking dielectric layer 114 form a stacked structure surrounding the core.
  • the upper selection transistor TSG and the lower selection transistor BSG, and the storage transistors M1 to M4 use a common channel region 111 and a blocking dielectric layer 114.
  • the channel region 111 provides source and drain regions and channel regions of a plurality of transistors.
  • the semiconductor layer and the blocking dielectric layer of the upper selection transistor TSG and the lower selection transistor BSG and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4 may be formed in separate steps.
  • the memory block 500 includes multiple layers stacked on a substrate (not shown) and parallel to the surface of the substrate.
  • FIG. 5 shows four word lines (WL) on four layers. They are denoted as WL0 to WL3.
  • the memory block 500 is also arranged with a plurality of via holes perpendicular to the word lines. The intersection of a word line and a via hole forms a memory cell, so a via hole can also be called a memory cell string.
  • a via hole can also be called a memory cell string.
  • the memory block 500 may include 64 word lines, and 64 word lines intersect with one memory cell string. 64 memory cells along the string of memory cells are formed.
  • the number of memory cell strings included in the memory block 500 can be calculated on the order of one hundred thousand, one million, or even larger, and a word line includes several million memory cell strings formed by intersecting it with, for example, several million memory cell strings. storage unit.
  • the storage unit in the storage block 5 can be a single-level storage unit or a multi-level storage unit, wherein the single-level storage unit can be a single-level cell (SLC) capable of storing 1 bit (bit); the multi-level storage unit can be a Multi-level cell (MLC) that can store 2 bits, tertiary-level cell (TLC) that can store 3 bits, quad-level cell (QLC) that can store 4 bits, and quintuple-level cell (PLC) that can store 5 bits .
  • SLC single-level cell
  • MLC Multi-level cell
  • TLC tertiary-level cell
  • QLC quad-level cell
  • PLC quintuple-level cell
  • the memory block 500 also includes a bit line (BL), a bit line selector (BLS, also referred to as a string selection line SSL), a source line (SL), a source selection line (SLS, also These circuit lines, which may be referred to as ground selection lines (GSL), together with the word lines (WL), can address any memory cell in the memory block 500 .
  • BL bit line
  • BLS bit line selector
  • SSL string selection line
  • SSL source line
  • SLS source selection line
  • GSL ground selection lines
  • peripheral circuitry 302 may be coupled to memory array 301 through bit lines 316 , word lines 318 , source lines 314 , SSG lines 315 , and DSG lines 313 .
  • Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage signals and/or current signals via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Sensing a voltage signal and/or a current signal to and from each target storage transistor 306 facilitates operation of the memory array 301 .
  • the peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG.
  • MOS metal-oxide-semiconductor
  • Peripheral circuit 302 includes page buffer/sense amplifier 604, column decoder/bit line driver 606, row decoder/WL driver 608, voltage generator 610, control circuit 612 , register 614 , interface 616 and data bus 618 . It should be understood that in some examples, additional peripheral circuitry not shown in FIG. 6 may also be included.
  • the page buffer/sense amplifier 604 may be configured to read data from and program (write) data to the memory array 301 according to control signals from the control circuit 612 .
  • page buffer/sense amplifier 604 may store a page of program data (write data) to be programmed into one page 320 of memory array 301 .
  • the page buffer/sense amplifier 604 may perform a program verify operation to ensure that data has been correctly programmed into the storage transistor 306 coupled to the selected word line 318 .
  • page buffer/sense amplifier 604 may also sense a low power signal from bit line 316 representing a data bit stored in storage transistor 306 and amplify the small voltage swing during a read operation to a recognizable logic level.
  • Column decoder/bit line (BL) driver 606 may be configured to be controlled by control circuit 612 and to select one or more strings of NAND memory cells 308 by applying a bit line voltage generated from voltage generator 610 .
  • Row decoder/WL driver 608 may be configured to be controlled by control circuit 612 and select/deselect memory blocks 304 of memory array 301 and select/deselect word lines 318 of memory blocks 304 . Row decoder/WL driver 608 may also be configured to drive word line 318 using a word line voltage generated from voltage generator 610 . In some implementations, the row decoder/word line (WL) driver 608 can also select/deselect and drive the SSG line 315 and the DSG line 313 . As described in detail below, row decoder/WL driver 608 is configured to perform erase operations on storage transistors 306 coupled to selected word line(s) 318 .
  • the voltage generator 610 may be configured to be controlled by the control circuit 612, and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages to be supplied to the memory array 301, voltage and source line voltage.
  • word line voltages eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.
  • Control circuitry 612 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits.
  • the register 614 may be coupled to the control circuit 612 and includes a status register, a command register and an address register for storing status information, command operation code (OP code) and command address for controlling the operation of each peripheral circuit.
  • Interface 616 may be coupled to control circuit 612 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control circuit 612 and to buffer status information received from control circuit 612 and Relay it to the host.
  • Interface 616 may also be coupled to column decoder/bit line driver 606 via data bus 618 and act as a data I/O interface and data buffer to buffer and relay data to and from memory array 301 or buffer data.
  • the storage array 301 may include multiple storage planes (Planes), each storage plane includes multiple storage blocks (Blocks), and each storage block includes multiple storage pages (Pages).
  • a memory page is the smallest unit for reading and writing (that is, programming), and a memory block is the smallest unit for erasing.
  • FIG. 7 it shows a schematic structural diagram of a memory including two storage planes provided by an embodiment of the present disclosure. And may include peripheral circuits; wherein, the peripheral circuits may include: control circuit 612, voltage generator 610, row decoder/WL driver 608, column decoder/BL driver 606(a), 606(b); storage plane It includes storage planes 701 and 702 . Although a dual plane structure is used in this embodiment, it should be understood that other numbers of planes may also be employed within the scope of the present application. When the multi-plane programming mode is adopted, the storage planes 701 and 702 can be programmed at the same time.
  • control circuit 612 may be coupled to the voltage generator 610, the row decoder/WL driver 608 and the column decoder/BL drivers 606(a), 606(b).
  • Voltage generator 610 may be coupled to row decoder/WL driver 608 .
  • Row decoder/WL driver 608 may be coupled to storage plane 702 via string select line SSL2, word lines WL2(1) to WL2(N), and ground select line GSL2.
  • Column driver 132 may be coupled to storage plane 702 via bit lines BL2(1) to BL2(M).
  • Each of the memory planes 701, 702 may contain multiple memory blocks, each memory block may contain multiple memory pages, and each memory page may contain multiple memory cells.
  • the storage cells in the storage plane 701 can be addressed by the word lines WL1(1) to WL1(N) and the bit lines BL1(1) to BL1(M), and the storage cells in the storage plane 702 can be addressed by the word lines WL2(1 ) to WL2(N) and bit lines BL2(1) to BL2(M) for addressing.
  • the control circuit 612 can communicate with a host or a memory controller (Memory Controller) to receive data to be stored in the storage planes 701, 702 and to send data obtained from the storage planes 701, 702.
  • the control circuit 612 may receive commands, addresses or data from a host or a memory controller and generate column address signals Scadr1, Scadr2, row address signals Sradr, and voltage control signals Svc.
  • the voltage generator 610 may generate voltages for read, program, erase, and verify operations in response to a voltage control signal Svc from the control circuit 612 . The voltage generated by the voltage generator 610 may exceed the power supply voltage supplied to the memory 1 .
  • Row decoder/WL driver 608 may operate in response to row address signal Sradr from control circuit 612 to select a word line for read, program, erase and verify operations.
  • Column decoders/BL drivers 606(a), 606(b) may operate in response to column address signals Scadr1, Scadr2 from control circuit 612 to generate bit line signals to select for reading, programming, erasing and verifying manipulated bit lines.
  • the voltage generator 610 may use a power supply voltage (eg, 3.3V) to generate a program voltage (eg, 20V) and a program pass voltage (eg, 10V), and the row decoder/WL driver 608 may supply the selected A program pulse with the magnitude of the program voltage is applied to the word lines, a program pass voltage is applied to the unselected word lines, a supply voltage is applied to the string select lines SSL1, SSL2, and a ground voltage is applied to the ground select lines GSL1, GSL2, and the columns are decoded
  • the register/BL drivers 606(a), 606(b) may apply a ground voltage (eg, 0V) to selected bit lines and a supply voltage to unselected bit lines.
  • the voltage generator 610 may generate an appropriate verify voltage
  • the row decoder/WL driver 608 may apply the appropriate verify voltage to the selected word line, apply the supply voltage to the string select lines SSL1, SSL2, and Supply voltage is applied to ground select lines GSL1, GSL2, and column decoder/BL drivers 606(a), 606(b) may apply ground voltage to unselected bit lines and supply voltage to storage plane 701, respectively , 702 to read data from the selected memory cell on the selected bit line. If the data read is incorrect, the control circuit 612 may verify the selected memory cell as fail, and if the data read is correct, the control circuit 612 may verify the selected memory cell as pass.
  • the memory cells may be of single level cell (SLC) type, two level cell (MLC) type, triple level cell (TLC) type, quad level cell (QLC) type, five level cell (PLC) type or higher.
  • the Q possible data states may include erased state S(0) and program states S(1) through S(Q-1), where program state S(1) is the lowest program state and program state S(Q- 1) In the highest program state.
  • the TLC can be programmed to one of 8 possible data states, where program state S(1) is the lowest program state and program state S(7) is the highest program state.
  • a memory cell may be initially set to an erased state S(0), and later, a series of program-verify operations may be performed on the memory cell to program it to a corresponding target program state.
  • a series of program verify operations may start from the lowest program state S(1) and proceed to higher program states until the threshold voltages of selected memory cells reach the corresponding verify voltage levels of the corresponding target program states.
  • the verification voltages can be respectively selected as the minimum threshold voltages of the threshold voltage distribution curves of the program states S(1) to S(Q ⁇ 1).
  • Each program verify operation may include a program operation and a subsequent verify operation.
  • some of the memory cells may be selected and programmed into the program state in a row-by-row fashion from the first row to the Nth row, or from the Nth row to the first row.
  • the memory cell array of the three-dimensional NAND memory needs to withstand high pressure stress during programming and erasing cycles, and weak structures in some memory cell arrays of the three-dimensional NAND memory will develop into defects after cycling.
  • these defects may not affect the successful execution status of the erase operation and programming operation feedback, that is to say, the existence of these defects can also be the status of the successful execution of the erase operation and programming operation.
  • the written data may have been abnormal, resulting in UECC of the read operation, which in turn causes data loss.
  • each WL may correspond to multiple character string storage units, based on this, a large amount of data may be lost, which may cause failures to the memory system.
  • This type of failure is generally defined as a reliability failure of a three-dimensional NAND type memory, which may further cause a failure of the memory system in the field.
  • the internal voltage bias power supply is usually shared between different planes during programming operations in order to save circuit area and power consumption. If one memory plane is defective, the other memory planes that share the internal voltage bias supply may not reach the target level, that is, a PSF in one memory plane will also affect the x-path in other adjacent memory planes. Therefore, even if only one surface has physical defects, UCEE in read operations often occurs on multiple storage surfaces. This phenomenon can be called Neighbor Plane Disturb (NPD, Neighbor Plane Disturb). Obviously, adjacent surface interference will cause data loss. Refer to FIG. 8 for details. In FIG. 8 for details. In FIG.
  • Str0-Str5 in FIG. 8 represent storage sub-blocks in Plane0, Plane1, Plane2, and Plane3.
  • the storage system can use Redundant Arrays of Independent Disks (RAID, Redundant Arrays of Independent Disks) or host storage backup (HMB, Host Memory Buffer) to restore lost data, but these methods are harmful to the entire system Performance is negatively affected.
  • RAID Redundant Arrays of Independent Disks
  • HMB Host Memory Buffer
  • a general storage system adopts a plane-level RAID, and the plane-level RAID can only recover a failure of one storage plane. If programming fails on multiple memory planes, the memory system will not be able to recover the data. For such failures, the memory system can implement RAID at the die (Die) level, but the configuration cost of the memory system will increase.
  • an embodiment of the present disclosure provides a memory (memory device) erasure verification method, as shown in FIG. 9 , which shows a schematic diagram of the implementation flow of the memory device erasure verification method provided by the embodiment of the present disclosure.
  • the erasing verification method may include:
  • Step 901 After performing an erase operation on a selected storage block in the memory, perform a first erase verification operation on the storage block;
  • Step 902 Determine a first verification result of the first erasing verification operation; the first verification result is configured to reflect whether the storage block is successfully erased after the erasing operation;
  • Step 903 Determine whether to perform a second erasing verification operation on the memory block based on the first verification result; the second erasing verification operation is configured to determine whether there is leakage between word lines in the memory block.
  • the memory includes a plurality of memory blocks.
  • the erasure verification method is performed on selected storage blocks in the memory. It can be understood that the selected storage block may include at least one storage block, that is, the number of the selected storage block may be one or more.
  • the first erasing verification operation may be a verification operation performed after the erasing operation is performed on the selected storage block, which is configured to verify whether the erasing operation has been performed on the storage block was successfully erased.
  • the first erase verification operation includes: applying an erase verification voltage to the memory block, sensing a signal to be verified corresponding to the erase verification voltage; determining the signal to be verified based on the signal to be verified
  • the first verification result of the first erase verification operation is described above.
  • the memory includes a plurality of memory blocks; each memory block includes a plurality of memory cells and a plurality of word lines respectively coupled to the plurality of memory cells; the applying erase to the memory block In addition to verify voltages, can include:
  • the erase verify voltage is applied to the plurality of word lines in the memory block using the same or different voltage sources.
  • a storage block can be divided into multiple storage sub-blocks, (String), based on this, when the first erasure verification operation is performed on the storage block, the storage unit in String can be Carry out the first erasure verification operation together, verify each String in the described storage block in turn, wherein, when carrying out the first erasure verification operation together to the storage unit in String, need all word lines WL in a String Apply the erasing verification voltage, and then sense (Sense) through a sense amplifier to obtain a signal to be verified, and verify whether the erasing operation is successful based on the signal to be verified.
  • the signal to be verified may be a voltage signal or a current signal.
  • the voltage sources that apply the erase verification voltage to the multiple word lines included in each String in the memory block may be the same or different. It is set according to the specific structure of the memory, and is not limited here.
  • step 902 After performing the first erasure verification operation on each String in the memory, determine the first verification result of the first erasure verification operation, that is, step 902, wherein the first verification result is also It is the status that is fed back after the first erase operation is performed after the above-mentioned erase operation is completed.
  • the first verification result is configured to reflect whether the storage block is successfully erased after the erasing operation.
  • step 903 the determining whether to perform a second erasure verification operation on the storage block based on the first verification result may include:
  • the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, it is determined to perform the second erasing verification operation on the storage block;
  • the first verification result is configured to indicate that the storage block is not successfully erased after the erasing operation, it is determined not to perform the second erasing verification operation on the storage block.
  • a second erasing verification operation needs to be performed: when the first verification result is configured to indicate that the memory block is successfully erased after the erasing operation, determining to perform a second erase verification operation on the storage block; when the first verification result is configured to indicate that the storage block has not been successfully erased after the erase operation, determining not to perform the operation on the storage block Second erase verify operation.
  • the erasure verification method also includes:
  • the second verification result is configured to reflect whether there is leakage between word lines in the memory block.
  • the second erase verification operation may be a leakage detection operation between word lines in the memory block. That is, when it is determined to perform the second erasure verification operation on the storage block, perform the second erasure verification operation on the storage block, and determine the second erasure verification operation of the second erasure verification operation. Verification result; the second verification result is configured to reflect whether there is leakage between word lines in the memory block. That is, through the second erasing verification operation, it is determined whether the selected memory still has leakage between word lines after successful erasing.
  • the erasure verification method also includes:
  • the first verification result is configured to indicate that the memory block is not successfully erased after the erasing operation or when the second verification result is configured to indicate that the memory block has an inter-word line leakage condition , saving a first flag; the first flag is configured to indicate that the storage block is a bad block.
  • the erasure verification method also includes:
  • a second flag is saved; the second flag is configured to indicate that the memory block is an available block.
  • bad block described here may be a storage block that cannot be programmed in the future.
  • the available blocks may be storage blocks that can be programmed subsequently.
  • said first flag or said second flag is stored in a register in said memory.
  • the register may be a status register.
  • the second erase verification operation may be performed by a leakage detection circuit between word lines built in the memory.
  • the second erase verification operation may include: applying a leakage detection voltage to the word line to be detected in the memory block, and detecting the residual voltage of the word line to be detected after a preset time. voltage; comparing the residual voltage with a reference voltage to obtain a comparison result; determining the second verification result based on the comparison result.
  • the applying leakage detection voltage to the word line to be detected in the memory block, and detecting the residual voltage of the word line to be detected after a preset time may include:
  • the remaining voltage of the word line to be detected is detected.
  • the determining the second verification result based on the comparison result may include:
  • determining that the second verification result is configured to indicate that the word line to be detected in the memory block is identical to the reference voltage There is no leakage between adjacent word lines;
  • the comparison result is that the absolute value of the difference between the remaining voltage and the reference voltage is not less than the preset threshold, it is determined that the second verification result is configured to indicate that the pending Leakage is detected between the word line and the adjacent word line.
  • FIG. 10(A) shows the structure of a leakage detection circuit between word lines provided by the present disclosure, and the connection relationship between the circuit and the word line to be detected is used to measure the leakage between the word line to be detected and the adjacent word line.
  • FIG. 10(B) shows a structural circuit of a leakage detection circuit between word lines provided by the present disclosure and the connection relationship between the word line to be detected for measuring the leakage between the word line to be detected and the bit line Schematic diagram of the situation.
  • Sel WL is the word line to be detected; Adjacent WL and Sel WL are adjacent word lines.
  • the equivalent resistance 1003 between the word line Sel WL to be detected and the adjacent word line Adjacent WL represents the leakage path between the word line Sel WL to be detected and the adjacent word line Adjacent WL; between the word line Sel WL to be detected and the adjacent word line In the case of leakage between the lines Adjacent WL, the equivalent resistance 1003 is equivalent to a short circuit state; when there is no abnormality between the word line Sel WL to be detected and the adjacent word line Adjacent WL, the equivalent resistance 1003 is equivalent to an open circuit state .
  • the equivalent resistance 1004 between the word line Sel WL to be detected and the bit line BL represents the leakage path between the word line Sel WL to be detected and the bit line BL.
  • the equivalent resistance 1004 is equivalent to a short circuit state; when there is no abnormal state in the leakage between the word line Sel WL and the bit line BL to be detected, the equivalent resistance 1004 is equivalent to an open circuit state.
  • the leakage detection circuit between the word lines may include: an isolation module 1001 and a comparison module 1002, wherein the isolation module 1001 includes an electronic switch SW2, a high-voltage isolation capacitor C1, Clamp electrostatic protection component 1001-1; the comparison module includes a voltage source VDD, an electronic switch SW3 and a comparator 1002-1.
  • the leakage detection voltage applied to the word line to be detected is generated by the aforementioned voltage generator 610; specifically, the leakage detection circuit between the word lines responds to the leakage detection command signal, and can pass through the electronic switch SW1 and the row decoder.
  • the driving voltage is coupled to the word line to be detected.
  • an isolation module can also be coupled to the word line to be detected and a comparison module, wherein the electronic switch in the isolation module SW2 couples the isolation module to the word line to be detected.
  • the high-voltage isolation capacitor C1 in the isolation module can effectively isolate the comparison module (leakage detection circuit between word lines) and the voltage generator (word line working circuit, erasing or programming applied voltage circuit), realizing the Switching of the word line between the high-voltage working mode and the low-voltage leakage detection mode.
  • the value range of the high-voltage isolation capacitor C1 may be determined by the voltage coupling ratio and the size of the storage array.
  • a Clamp electrostatic protection component 1001-1 is also provided between the high voltage isolation capacitor C1 and the comparator.
  • the Clamp electrostatic protection component 1001-1 has a strong current discharge capability. Using the transient characteristics of its capacitance, when the electrostatic voltage is applied to the Clamp electrostatic protection component 1001-1, due to the RC time constant (1 microsecond or more ) is much longer than the electrostatic voltage loading time (about 10 nanoseconds), which will make the transient effect of the capacitor very obvious, so the voltage at the input terminal of the comparator cannot be raised immediately, which can effectively prevent the comparator from being in the safe operating area (SOA, Safe Operating Area) fails to protect the comparator.
  • SOA Safe Operating Area
  • the comparator 1002-1 in the comparison module 1002 is configured to determine the difference between the reference voltage and the voltage of the word line to be detected, and then compare the difference with a preset threshold to determine the word to be detected. Whether there is leakage between the line and the adjacent word line, that is, to determine the second verification result of the second erasing verification.
  • the voltage of the word line to be detected received by the comparator 1002-1 is the remaining voltage on the word line to be detected within a predetermined time period.
  • the reference voltage is provided by a reference voltage source Vref.
  • control circuit After the control circuit receives the leakage detection instruction signal, it controls the row decoder to apply a leakage detection voltage to the word line to be detected through the voltage generator, and grounds the word line adjacent to the word line to be detected; then, When the leakage detection voltage of the word line to be detected reaches a predetermined value, stop applying the leakage detection voltage to the word line to be detected; after the preset time, detect the remaining voltage of the word line to be detected. The residual voltage detected at this time is also the voltage to be compared with the reference voltage.
  • the preset threshold and reference voltage may be empirical values.
  • the specific process of measuring the remaining voltage of the word line to be detected is as follows: when the leakage detection voltage applied to the word line to be detected by the voltage generator 610 reaches a predetermined value, stop applying the leakage detection voltage to the word line to be detected.
  • the electronic switch SW3 is closed, and the voltage of C1 is charged to VDD through VDD, and then the electronic switch SW3 is turned off; during the floating process of the word line to be detected, the left side of C1 is changed due to the change of the voltage on the word line to be detected.
  • the potential of the parallel plate, through the coupling effect, the potential of the parallel plate on the right will also change. After a preset time, the potential of the parallel plate on the right of C1 changes from VDD to a lower potential. The lower potential is the residual voltage .
  • FIG. 10(A) and FIG. 10(B) only show the leakage detection between word lines of a word line to be detected.
  • the elements in the leakage detection circuit between word lines provided by the present application are all realized by low-voltage devices, the area of the circuit itself is relatively small, and a plurality of leakage detection circuits between word lines can be set in the memory to realize simultaneous detection of Leakage between word lines of multiple word lines to be detected is detected.
  • the erasure verification method also includes:
  • the first verification result is configured to indicate that the memory block is successfully erased after the erase operation, it is determined to perform the second erase verification operation on a predetermined range of word lines in the memory block.
  • the lines are all WL0, where WL0 is the first word line in the memory to perform programming operations. In order to save detection time, only high-risk word lines can be detected, for example, word line WL0.
  • the predetermined range can be freely set by a designer.
  • a set of registers can be added to the memory controller, for example, a register used to control whether the leakage detection circuit between word lines is turned on; another example, used to store preset words Registers for the start address and end address of the line range, and so on.
  • An embodiment of the present disclosure provides an erasure verification method.
  • the first verification result of the first erasure verification operation it is determined whether the memory block on which the erasing operation has been performed has been successfully erased, and then according to the first verification result, it is determined whether the memory block Block performs the second erasing verification operation to detect whether there is leakage between word lines in the memory block (it has been found through research that leakage between word lines is the main factor leading to data discarding).
  • the verification operation of the present disclosure it is possible to effectively detect Detect whether the storage block is a bad block, so as to effectively avoid data loss caused by abnormalities in subsequent programming operations.
  • FIG. 11 shows a schematic flowchart of a memory erasure verification method provided by an embodiment of the present disclosure.
  • the process of the erasure verification method may specifically include:
  • Step 1101 after the erasing operation performed on the selected memory block in the memory, perform a first erasure verification operation on the memory block;
  • Step 1102 Determine the first verification result of the first erasing verification operation; wherein, when the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, jump to Execute step 1103; when the first verification result is configured to indicate that the storage block has not been successfully erased after the erasing operation, jump to step 1105;
  • Step 1103 Execute a second erasure verification operation on the storage block
  • Step 1104 Determine the second verification result of the second erase verification operation; when the verification result is configured to indicate that there is no leakage between word lines in the memory block, jump to step 1106; in the verification When the result is configured to indicate that there is leakage between word lines in the memory block, jump to step 1105;
  • Step 1105 saving a first mark; the first mark is configured to indicate that the storage block is a bad block;
  • Step 1106 Save a second flag; the second flag is configured to indicate that the storage block is an available block.
  • the second erasure verification operation of the memory block is started, which not only saves verification time, but also can identify those that have failed programming due to leakage between word lines. storage block.
  • the determined first verification result is configured to indicate that the storage block has not been successfully erased after the erase operation
  • the erasing operation reaches the maximum number of erasing times, and it is determined to mark the storage block as a bad block. Because there are many storage units in the storage block, the structure of different storage units is still slightly different, and the states of the storage units are also different. Some storage units can be erased successfully at one time; The unit needs to be erased many times, so the maximum number of times of erasing can be set to accurately identify whether the memory block is a bad block.
  • the present disclosure also provides a memory operation method, specifically, the operation method may include:
  • the method of operation also includes:
  • the first verification result fed back is configured to indicate that the memory block has not been successfully erased after the erasing operation, judging whether the currently performed erasing operation has reached the maximum number of times of erasing;
  • the aforementioned erasing verification method can be an erasing verification step in the operation method. Therefore, the operation method here and the aforementioned erasing verification method are methods of the same inventive concept. The nouns that appear here have been described above. This will not be repeated here.
  • the maximum number of erasing times may be artificially set according to actual conditions.
  • the maximum erasing times may be 5 times or 6 times.
  • the erasing operation on the memory is continued until the maximum number of times of erasing is reached, and if the feedback of the first verification result still fails, the storage block is marked as a bad block.
  • FIG. 12 shows a schematic flowchart of the operation method of the memory provided by the embodiment of the present disclosure.
  • the operation method may specifically include:
  • Step 1201 Perform an erase operation on the selected memory block in the memory
  • Step 1202 After performing the erase operation on the selected memory block in the memory, perform a first erase verification operation on the memory block;
  • Step 1203 Determine the first verification result of the first erasing verification operation; wherein, when the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, jump to Execute step 1204; when the first verification result is configured to indicate that the storage block has not been successfully erased after the erasing operation, jump to step 1206;
  • Step 1204 Execute a second erasure verification operation on the storage block
  • Step 1205 Determine the second verification result of the second erase verification operation; wherein, when the verification result is configured to indicate that there is no leakage between word lines in the memory block, jump to step 1208; When the verification result is configured to indicate that there is leakage between word lines in the memory block, jump to step 1207;
  • Step 1206 If the first verification result fed back is configured to indicate that the memory block has not been successfully erased after the erase operation, determine whether the currently executed erase operation has reached the maximum number of erase times; If it is determined that the erasing operation currently performed has not reached the maximum erasing times, jump to step 1201 until the maximum erasing times is reached; if it is determined that the erasing operation currently performed has reached the maximum erasing times Divide times, jump to 1207;
  • Step 1207 Save the first mark; the first mark is configured to indicate that the storage block is a bad block;
  • Step 1208 Save a second flag; the second flag is configured to indicate that the storage block is an available block.
  • An embodiment of the present disclosure also provides a memory, including: a storage array; the storage array includes a plurality of storage blocks;
  • the peripheral circuit is configured to: perform a first erase verification operation on the memory block after the erase operation performed on the memory block selected in the memory; determine a first erase operation of the first erase verification operation. Verification result; determine whether to perform a second erasing verification operation on the storage block based on the first verification result; the first verification result is configured to reflect whether the storage block is successfully erased after the erasing operation In addition; the second erase verification operation is configured to determine whether there is leakage between word lines in the memory block.
  • the peripheral circuit includes: a control circuit, a voltage generator, a word line driver, and a sense amplifier; the voltage generator, the word line driver, and the sense amplifier are connected to the plurality of memory The blocks are coupled and controlled by the control circuit;
  • the word line driver is configured to: apply an erase verification voltage to the memory block through the voltage generator under the control of the control circuit;
  • the sense amplifier is configured to: sense a signal to be verified corresponding to the erase verification voltage;
  • the control circuit is configured to: determine a first verification result of the first erasure verification operation based on the signal to be verified; determine whether to perform a second erasure verification operation on the memory block based on the first verification result .
  • the signal to be verified is a voltage signal or a current signal, which is used for the control circuit to determine a first verification result (or erase status) of the erasing operation.
  • control circuit is further configured to:
  • the first verification result is configured to indicate that the storage block is successfully erased after the erasing operation, it is determined to perform the second erasing verification operation on the storage block;
  • the first verification result is configured to indicate that the storage block is not successfully erased after the erasing operation, it is determined not to perform the second erasing verification operation on the storage block.
  • control circuit is further configured to: when determining to perform the second erase-verify operation on the memory block, perform the second erase-verify operation on the stored block; determine the A second verification result of the second erasing verification operation; the second verification result is configured to reflect whether there is leakage between word lines in the memory block.
  • the peripheral circuit further includes: a first register configured to: when the first verification result is configured to indicate that the memory block has not been successfully erased after the erase operation or when The verification result is configured to save a first flag when the storage block has leakage between word lines; the first flag is configured to indicate that the storage block is a bad block.
  • the peripheral circuit further includes: a second register configured to save a second flag when the verification result is configured to indicate that there is no leakage between word lines in the memory block; the first Two flags are configured to characterize the storage block as an available block.
  • first register and the second register are only used to describe the registers in different situations.
  • the first register and the second register may be one in the actual application process, that is, the first and second registers described here , are not intended to limit the present disclosure.
  • the peripheral circuit further includes: a leakage detection circuit between word lines, and the leakage detection circuit between word lines is coupled to the memory block;
  • the word line driver is further configured to: under the control of the control circuit, apply a leakage detection voltage to the word line to be detected in the memory block through the voltage generator; The word line is grounded; when the leakage detection voltage of the word line to be detected reaches a predetermined value, stop applying the leakage detection voltage to the word line to be detected;
  • the leakage detection circuit between word lines is configured to: detect the residual voltage of the word line to be detected after a preset time; compare the residual voltage with a reference voltage to obtain a comparison result; transmit the comparison result to the control circuit result;
  • the control circuit is configured to: receive the comparison result and feed back the second verification result to the control circuit based on the comparison result.
  • control circuit is further configured to:
  • determining that the second verification result is configured to indicate that the word line to be detected in the memory block is identical to the reference voltage There is no leakage between adjacent word lines;
  • the comparison result is that the absolute value of the difference between the remaining voltage and the reference voltage is not less than the preset threshold, it is determined that the second verification result is configured to indicate that the pending Leakage is detected between the word line and the adjacent word line.
  • the leakage detection circuit between word lines includes: a comparison module; wherein,
  • the comparison module is configured to: detect the residual voltage of the word line to be detected after a preset time; compare the residual voltage with the reference voltage to obtain a comparison result; transmit the comparison result to the control circuit .
  • the leakage detection circuit between word lines further includes: an isolation module, wherein the isolation module is configured to: isolate the comparison module and the voltage generator.
  • the comparison module includes: a reference voltage source and a comparator, wherein,
  • the reference voltage source is configured to: provide the reference voltage, and input the reference voltage to the comparator;
  • the comparator is configured to: detect the residual voltage of the word line to be detected after a preset time, and receive the reference voltage; compare the residual voltage with the reference voltage to obtain a comparison result; The comparison result is transmitted.
  • the isolation module includes: an isolation capacitor configured to: isolate the comparison module and the voltage generator.
  • the peripheral circuit is further configured to: when the first verification result is configured to indicate that the memory block is successfully erased after the erasing operation, determine that the predetermined A range of word lines perform the second erase verify operation.
  • the memory includes three-dimensional NAND type memory.
  • An embodiment of the present disclosure also provides a memory system, including:
  • a memory controller coupled to the memory.
  • the peripheral circuit is configured to receive a first instruction; in response to the first instruction, perform an erase operation on a selected storage block in the memory, and perform a first operation on the storage block.
  • Erase verification operation determine a first verification result of the first erasure verification operation; determine whether to perform a second erasure verification operation on the storage block based on the first verification result; the second erasure verification operation It is configured to determine whether there is leakage between word lines in the memory block; the first verification result is configured to indicate that the memory block has not been successfully erased after the erase operation or that word lines exist in the memory block In the case of leakage between lines, the first mark is saved; when the first verification result is configured to indicate that the memory block is successfully erased after the erasing operation and there is no leakage between word lines in the memory block , save the second token;
  • the memory controller is configured to, according to the first flag, issue a second instruction; according to the second flag, issue a third instruction;
  • the peripheral circuit is configured to receive the second instruction; in response to the second instruction, no longer program the memory block; receive the third instruction; in response to the third instruction, The memory block performs a program operation.
  • the first instruction is transmitted from the memory control 602 to the peripheral circuit 302 through the interface 616, so that the peripheral circuit performs an erase operation on the selected memory block in the memory in response to the first instruction, and the performing a first erasure verification operation on the memory block; determining a first verification result of the first erasure verification operation; and determining whether to perform a second erasure verification operation on the memory block based on the first verification result.
  • the second instruction is transmitted by the memory controller 602 to the peripheral circuit through the interface 616, so that the peripheral circuit no longer performs programming operations on the memory block in response to the second instruction.
  • the third instruction is transmitted by the memory controller 602 to the peripheral circuit 302 through the interface 616, so that the peripheral circuit performs a programming operation on the memory block in response to the third instruction.
  • the memory system here belongs to the same inventive concept as the above-mentioned erasure verification method and memory, and the terms and operations appearing here have been described in detail above and will not be repeated here.

Landscapes

  • Read Only Memory (AREA)

Abstract

本公开实施例提供了一种存储器及其擦除验证方法、操作方法、存储器系统，其中，存储器的擦除验证方法包括：在对所述存储器中选定的存储块执行的擦除操作之后，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。

Description

存储器及其擦除验证方法、操作方法、存储器系统
相关申请的交叉引用
本公开基于申请号为202110573212.9、申请日为2021年05月25日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种存储器及其擦除验证方法、操作方法、存储器系统。
背景技术
近来，具有垂直(即，以三维(3D))堆叠的存储单元的半导体存储器被广泛使用于电子设备中，其通常包括垂直堆叠的多个层级(例如，通过双堆叠工艺形成的三维非易失性存储器中的顶部层级和底部层级)、三维非易失性存储器中的每个层级中均存在多个垂直堆叠的存储单元，从而使得每个层级可单独地执行读取、编程和擦除等操作。
数据系统在操作三维非易失性存储器时，通常根据三维非易失性存储器反馈的状态(status)来判断擦除操作或编程操作是成功还是失败。一般情况下，在数据系统接收到三维非易失性存储器反馈的关于编程操作成功的状态时，会释放掉存在数据系统缓存中的数据。但由于三维非易失性存储器本身存在一些缺陷，这些缺陷不影响擦除操作或编程操作的成功，但写入的数据还是有可能发生异常，造成后续读操作的不能纠正的错误编码(UECC，Unable Error Correcting Code或者Uncorrectable Error Correction Code)，引起数据丢失(data loss)，尤其在多面编程时，一个面的数据丢失，还会引起邻近的面的数据丢失(这种情况称之为邻近面干扰(NPD， Neighbor Plane Disturb))。因此，如何防止数据丢失是本领域技术人员亟待解决的问题。
发明内容
为解决现有存在的技术问题的一个或多个，本公开实施例提出一种存储器及其擦除验证方法、操作方法、存储器系统。通过对存储器执行两种验证操作，以确定该存储块是否为坏块，以确定是否对该存储块执行编程操作，这样可以减少数据丢失的情况，进而在多面编程中也不会造成NPD现象。
本公开实施例提供了一种存储器的擦除验证方法，包括：
在对所述存储器中选定的存储块执行的擦除操作之后，对所述存储块执行第一擦除验证操作；
确定所述第一擦除验证操作的第一验证结果；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；
基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
上述方案中，所述基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作，包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
上述方案中，所述擦除验证方法还包括：
在确定对所述存储块执行所述第二擦除验证操作时，对所述存储块执行所述第二擦除验证操作；
确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配 置为反映所述存储块是否存在字线间漏电情况。
上述方案中，所述擦除验证方法还包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
上述方案中，所述擦除验证方法还包括：
在所述第二验证结果表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
上述方案中，所述第一擦除验证操作包括：向所述存储块施加擦除验证电压，感测与所述擦除验证电压对应的待验证信号；基于所述待验证信号确定所述第一擦除验证操作的第一验证结果。
上述方案中，所述存储器包括多个存储块；每一个存储块包括多个存储单元以及与所述多个存储单元分别耦接的多个字线；所述向所述存储块施加擦除验证电压，包括：
利用相同或不同电压源，向所述存储块中的所述多个字线施加所述擦除验证电压。
上述方案中，所述第二擦除验证操作包括：向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和参考电压，获得比较结果；基于所述比较结果确定所述第二验证结果。
上述方案中，所述向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压，包括：
向所述待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；
当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
经过所述预设时间后，检测所述待检测字线的剩余电压。
上述方案中，所述基于所述比较结果确定所述第二验证结果，包括：
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
上述方案中，所述第二擦除验证操作通过内置在所述存储器中的字线间漏电检测电路进行。
上述方案中，所述擦除验证方法还包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
上述方案中，所述第一标记或所述第二标记存储在所述存储器中的寄存器中。
本公开实施例提供一种操作方法，包括：
对所述存储器中选定的存储执行擦除操作；
对所述存储器执行上述任一项所述的擦除验证方法，以确定所述存储块是否存在字线间漏电情况。
上述方案中，所述操作方法还包括：
若反馈的所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，判断当前执行的所述擦除操作是否达到最大擦除次数；
若判定当前执行的所述擦除操作未达到所述最大擦除次数，继续执行所述擦除操作和第一擦除验证操作，直到到达所述最大擦除次数为止；
若判定当前执行的所述擦除操作达到所述最大擦除次数，确定标记所 述存储块为坏块。
本公开实施例提供了一种存储器，包括：存储阵列；所述存储阵列包括多个存储块；
以及与所述存储阵列耦接的外围电路；其中，
所述外围电路被配置为：在对所述存储器中选定的存储块执行擦除操作之后，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
上述方案中，所述外围电路包括：控制电路、电压生成器、字线驱动器和感测放大器；所述电压生成器、所述字线驱动器和所述感测放大器与所述多个存储块耦接，并被所述控制电路所控制；
所述字线驱动器被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块施加擦除验证电压；
所述感测放大器被配置为：感测与所述擦除验证电压对应的待验证信号；
所述控制电路被配置为：基于所述待验证信号确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作。
上述方案中，所述控制电路还被配置为：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
上述方案中，所述控制电路还被配置为：在确定对所述存储块执行所 述第二擦除验证操作时，对所存储块执行所述第二擦除验证操作；确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。
上述方案中，所述外围电路还包括：第一寄存器，被配置为：在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
上述方案中，所述外围电路还包括：第二寄存器，被配置为：在所述第二验证结果表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
上述方案中，所述外围电路还包括：字线间漏电检测电路，所述字线间漏电检测电路与所述存储块耦接；
所述字线驱动器还被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块中待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
所述字线间漏电检测电路被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压与参考电压，获得比较结果；向所述控制电路传输所述比较结果；
所述控制电路还被配置为：接收所述比较结果并基于所述比较结果向所述控制电路反馈所述第二验证结果。
上述方案中，所述控制电路还被配置为：
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小 于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
上述方案中，所述外围电路还包括：第一寄存器，被配置为：在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
上述方案中，所述外围电路还包括：第二寄存器，被配置为：在所述第二验证结果表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
上述方案中，所述外围电路还包括：字线间漏电检测电路，所述字线间漏电检测电路与所述存储块耦接；
所述字线驱动器还被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块中待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
所述字线间漏电检测电路被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压与参考电压，获得比较结果；向所述控制电路传输所述比较结果；
所述控制电路还被配置为：接收所述比较结果并基于所述比较结果向所述控制电路反馈所述第二验证结果。
上述方案中，所述控制电路还被配置为：
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的 所述待检测字线与相邻字线之间存在漏电情况。
上述方案中，所述字线间漏电检测电路包括：比较模组；其中，
所述比较模组被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
上述方案中，所述字线间漏电检测电路还包括：隔离模组，其中，所述隔离模组被配置为：隔离所述比较模组和所述电压生成器。
上述方案中，所述比较模组包括：参考电压源和比较器，其中，
所述参考电压源被配置为：提供所述参考电压，向所述比较器输入所述参考电压；
所述比较器被配置为：检测所述待检测字线经预设时间后的剩余电压，接收所述参考电压；比较所述剩余电压与所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
上述方案中，所述隔离模组包括：隔离电容，被配置为：隔离所述比较模组和所述电压生成器。
上述方案中，所述外围电路还被配置为：在所述第一验证结果第一验证结果表明经所述擦除操作后所述存储块未被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
上述方案中，所述存储器包括三维NAND型存储器。
本公开实施例还提供了一种存储器系统，包括：
一个或多个如上述实施例中任一项所述的存储器；以及
存储器控制器，其与所述存储器耦接。
上述方案中，所述外围电路配置为，接收到第一指令；响应于所述第一指令，对所述存储器中选定的存储块执行擦除操作，对所述存储块执行第一擦除验证操作；反馈所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二 擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦或所述存储块存在字线间漏电情况时，保存第一标记；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除且所述存储块不存在字线间漏电情况时，保存第二标记；
所述存储器控制器配置为，根据所述第一标记，发出第二指令；根据所述第二标记，发出第三指令；
所述外围电路配置为，接收到所述第二指令；响应于所述第二指令，不再对所述存储块进行编程操作；接收所述第三指令；响应于所述第三指令，对所述存储块进行编程操作。
本公开实施例提供一种存储器及其擦除验证方法、操作方法、存储器系统。其中，所述擦除验证方法包括：在对所述存储器中选定的存储块执行擦除操作之后，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。本公开实施例提供的擦除验证方法，通过确定第一擦除验证操作的第一验证结果确定执行了擦除操作的选定的存储块是否通过，然后根据这个第一验证结果确定是否对该存储块执行第二擦除验证操作，以检测该存储块是否存在字线间漏电情况(经研究发现，字线间漏电是导致数据丢弃的主要因素)，通过本公开的擦除验证操作，可以有效的侦测到存储块是否为坏块，从而可以有效地避免在后续的编程操作中发生异常而造成数据丢失，如此，在多面编程中，能够将编程异常限制在本身存在异常的存储面内，减轻编程异常对其它正常存储面的影响，即减小邻面干扰带来的不利影响，也即减少了发生NPD现象的概率。
附图说明
本公开的实施方式在附图的图示中以示例性的方式而非限制性的方式示出，在附图中，相同的附图标记指示类似的元件。
图1是根据本公开实施例提供的具有存储器的示例性系统的块图；
图2A是根据本公开实施例提供的具有存储器的示例性存储卡的示意图；
图2B是根据本公开实施例提供的具有存储器的示例性固态驱动器(SSD)的示意图；
图3是根据本公开的实施例提供的包括外围电路的示例性存储器的示意图；
图4a是根据本公开实施例提供的存储单元串示例性的电路图；
图4b是根据本公开实施例提供的存储单元串示例性的结构示意图；
图5是根据本公开实施例提供的3D存储器中单块存储块的示例性结构图；
图6是根据本公开实施例提供的包括存储阵列和外围电路的示例性存储器的块图；
图7是根据本公开实施例提供的包括两个存储面的存储器的结构示意图。
图8是相关技术中存储器执行编程操作出现的NPD现象的示意图；
图9是根据本公开实施例提供的存储器的擦除验证方法的实现流程示意图。
图10(A)和图10(B)是根据本公开实施例提供的字线间、字线与位线间漏电检测电路与存储器阵列、外围电路之间的连接关系示意图；
图11是根据本公开实施例提供的一种存储器的擦除验证方法的实现流程示意图。
图12是根据本公开实施例提供的一种存储器系统的操作方法的流程示意图。
具体实施方式
为让本公开的上述目的、特征和优点能更明显易懂，以下结合附图对本公开的具体实施方式作详细说明。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是本公开还可以采用其它不同于在此描述的其它方式来实施，因此本公开不受下面公开的具体实施例的限制。
如本公开和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
在详述本公开实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。例如，如果翻转附图中的器件，则被描述为在其他元件或特征“下方”或“之下”或“下面”的元件的方向将改为在所述其他元件或特征的“上方”。因而，示例性的词语“下方”和“下面”能够包含上和下两个方向。器件也可能具有其他朝向(旋转90度或处于其他方向)，因此应相应地解释此 处使用的空间关系描述词。此外，还将理解，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本公开的上下文中，所描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对相应零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本公开保护范围的限制。
在本文中所使用的术语“三维(3D)存储器件”是指在横向取向的衬底上具有竖直取向的存储单元晶体管串(在文中被称为“存储单元串”，例如NAND串)从而存储单元串相对于衬底在竖直方向上延伸的半导体器件。如在本文中所使用的，术语“竖直/竖直地”表示标称垂直于衬底的横向表面。
在本文中所使用的属于“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。添加在衬底的顶部上的材料可以被图案化或可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、锗、砷化镓、磷化铟等。或者，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开中所使用的术语“层”是指包括具有厚度的区域的材料部分。层可以在整个下层或上层结构上延伸，或者可以具有小于下层或上层结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均匀或不均匀连续结构的区域。例如，层可以位于连续结构的顶表面和底表面之间或其处的任何一对水平平面之间。层可以水平地、垂直地和/或沿着锥形表面延伸。衬底可以是层，其中可以包括一层或多层，和/或可以在其上、其上方和/ 或其下方具有一层或多层。层可以包括多个层。例如，互连层可以包括一个或多个导体和触点层(其中形成有触点、互连线和/或通孔)以及一个或多个电介质层。
本公开中使用了流程图用来说明根据本公开的实施例的系统所执行的操作。应当理解的是，前面或下面操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤。同时，或将其他操作添加到这些过程。
图1示出了根据本公开的一些方面的具体有存储器件的示例性系统100的块图。系统100可以是移动电话、台式计算机、膝上型计算机、平板计算机、车辆计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或者其中具有储存器的任何其他合适的电子设备。如图1所示，系统100可以包括主机108和存储器系统102，其中，存储器系统102具有一个或多个存储器104和存储器控制器106；主机108可以是电子设备的处理器，如中央处理单元(CPU)或者片上系统(SoC)，其中，片上系统例如可以为应用处理器(AP)。主机108可以被配置为将数据发送到存储器104或从存储器104接收数据。
具体的，存储器104可以是本公开中公开的任何存储器件，如下文详细公开的，存储器104，比如，NAND闪存存储器件(如三维(3D)NAND闪存存储器件)。
根据一些实施方式，存储器控制器106耦接到存储器104和主机108。并且被配置为控制存储器104。存储器控制器106可以管理存储在存储器104中的数据，并与主机108通信。在一些实施例中，存储器控制器106被设计为用于在低占空比环境中操作，比如在安全数字(SD)卡、紧凑型闪存(CF)卡、通用串行总线(USB)闪存驱动器、或用于在诸如个人计算器、数字相机、移动电话等低占空比环境的电子设备中使用的其他介质。在一些实施例中，存储器控制器106被设计为用于在高占空比环境中操作， 比如SSD或嵌入式多媒体卡(eMMC)，其中SSD或eMMC用作诸如智能电话、平板计算机、膝上型计算机等高占空比环境的移动设备的数据储存器以及企业存储阵列。存储器控制器106可以被配置为控制存储器104的操作，例如读取、擦除和编程操作。存储器控制器106还可以被配置为管理关于存储在或要存储在存储器104中的数据的各种功能，包括但不限于坏块管理、垃圾收集、逻辑到物理地址转换、损耗均衡等。在一些实施方式中，存储器控制器106还被配置为处理关于从存储器104读取的或者被写入到存储器104的数据的纠错码(ECC)。存储器控制器106还可以执行任何其他合适的功能，例如，格式化存储器104。存储器控制器106可以根据特定通信协议与外部设备(例如，主机108)通信。例如，存储器控制器106可以通过各种接口协议中的至少一种与外部设备通信，接口协议例如USB协议、MMC协议、外围部件互连(PCI)协议、PCI高速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(SCSI)协议、增强型小型磁盘接口(ESDI)协议、集成驱动电子设备(IDE)协议、Firewire协议等。
存储器控制器106和一个或多个存储器104可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(UFS)封装或eMMC封装)中。也就是说，存储器系统102可以实施并且封装到不同类型的终端电子产品中。在如图2A中所示的一个示例中，存储器控制器106和单个存储器104可以集成到存储器卡202中。存储器卡202可以包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、CF卡、智能媒体(SM)卡、存储器棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。存储器卡202还可以包括将存储器卡202与主机(例如，图1中的主机108)耦接的存储器卡连接器204。在如图2B中所示的另一示例中，存储器控制器106和多个存储器104可以集成到SSD 206中。SSD 206还可以包括将SSD 206与主机(例如，图1中 的主机108)耦接的SSD连接器208。在一些实施方式中，SSD 206的存储容量和/或操作速度大于存储器卡202的存储容量和/或操作速度。
图3示出了根据本公开的一些方面的包括外围电路的示例性存储器104的示意电路图。如图3所示，存储器104可以包括存储阵列301和耦接到存储阵列301的外围电路302。存储阵列301可以是NAND闪存存储阵列，其中，存储晶体管306以NAND存储单元串308的阵列的形式提供，每个NAND存储单元串308在衬底(未示出)上方垂直地延伸。在一些实施方式中，每个NAND存储单元串308包括串联耦接并且垂直地堆叠的多个存储晶体管306。每个存储晶体管306可以保持连续模拟值，例如，电压或电荷，其取决于在存储晶体管306的区域内捕获的电子的数量。每个存储晶体管306可以是包括浮栅晶体管的浮栅类型的存储晶体管，或者是包括电荷捕获晶体管的电荷捕获类型的存储晶体管。
上面讨论的每一个存储晶体管306(也即后述的存储单元)可以是单级存储单元或者多级存储单元，其中，单级存储单元可以是能够存储1个比特(bit)的单级单元(SLC)；多级存储单元可以是能够存储2个bit的多级单元(MLC)，能够存储3个bit的三级单元(TLC)，能够存储4个bit的四级单元(QLC)，能够存储5个bit的五级单元(PLC)等等。
再返回如图3中所示，每个NAND存储单元串308可以包括在其源极端处的源极选择栅极(SSG)310和在其漏极端处的漏极选择栅极(DSG)312。SSG 310和DSG 312可以被配置为在读取和编程操作期间激活选定的NAND存储单元串308(阵列的列)。在一些实施方式中，同一存储块304中的NAND存储单元串308的源极通过同一源极线(SL)314(例如，公共SL)耦接。换句话说，根据一些实施方式，同一存储块304中的所有NAND存储单元串308具有阵列公共源极(ACS)。根据一些实施方式，每个NAND存储单元串308的DSG 312耦接到相应的位线316，可以经由输出总线(未示出)从位线316读取或写入数据。在一些实施方式中，每个NAND存储 单元串308被配置为通过经由一个或多个DSG线313将选择电压(例如，高于具有DSG 312的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的DSG 312和/或通过经由一个或多个SSG线315将选择电压(例如，高于具有SSG 310的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的SSG 310而被选择或被取消选择。
再如图3中所示，NAND存储单元串308可以被组织为多个存储块304，多个存储块304的每一个可以具有公共源极线314(例如，耦接到地)。在一些实施方式中，每个存储块304是用于擦除操作的基本数据单位，即，同一存储块304上的所有存储晶体管306同时被擦除。应当理解，在一些示例中，可以在半块级、在四分之一块级或者在具有任何合适数量的块或块的任何合适的分数的级执行擦除操作。相邻NAND存储单元串308的存储晶体管306可以通过字线318耦接，字线318选择存储晶体管306的哪一行受读取和编程操作的影响。在一些实施方式中，每个字线318耦接到存储晶体管306的页320，页320是用于编程操作的基本数据单位。以位为单位的一页320的大小可以与一个存储块304中由字线318耦接的NAND存储单元串308的数量相关。每个字线318可以包括在相应页320中的每个存储晶体管306处的多个控制栅极(栅极电极)以及耦接控制栅极的栅极线。在一些实施例中，一个存储块304还可以被分成多个存储子块，每一个存储子块被称之为一个string。那么，对一个存储块执行擦除操作，也就是对存储块中包含的所有string执行擦除操作。
图4a和图4b分别示出存储单元串308的一种示例性的电路图和一种示例性的结构示意图。在该实施例中示出的存储单元串包括4个存储晶体管的情形。可以理解的是，本公开不限于此，存储单元串中的存储晶体管数量可以为任意多个，例如32个或64个。
如图4a所示，存储单元串308的第一端连接至位线BL，第二端连接至源极线SL。存储单元串308包括第一端和第二端之间串联连接的多个晶 体管，包括上选择晶体管TSG、存储晶体管M1至M4以及下选择晶体管BSG。上选择晶体管TSG通过其包含的漏极选择栅极(DSG)连接至串选择线SSL，下选择晶体管BSG通过其包含的源极选择栅极(SSG)连接至地选择线GSL。存储晶体管M1至M4的栅极导体分别连接至字线WL1至WL4的相应字线318。在一些实施例中，所述漏极选择栅极(DSG)也可以称之为第一控制栅极；所述源极选择栅极(SSG)也可以称之为第二控制栅极。
如图4b所示，存储单元串308结构包括沟道柱110。在沟道柱110的中间部分包括沟道区111以及在沟道区111设置遂穿介质层112、电荷存储层113和阻挡介质层114，以形成存储晶体管M1至M4。在该实施例中，沟道区111例如由掺杂多晶硅组成，遂穿介质层112、电荷存储层113和阻挡介质层114可以分别由氮化物组成，例如氮化硅、氮氧化硅、硅或其任何组合。沟道区111用于提供选择晶体管和存储晶体管的沟道区，沟道区111的掺杂类型与选择晶体管和存储晶体管的类型相同。例如，对于N型的选择晶体管和存储晶体管，沟道区111可以是N型掺杂的多晶硅。
在该实施例中，沟道柱110的芯部为沟道区111，隧穿介质层112、电荷存储层113阻挡介质层114形成固绕芯部侧壁的叠层结构。在替代的实施例中，沟道柱110的芯部为附加的绝缘层，沟道区111、隧穿介质层112、电荷存储层113和阻挡介质层114形成围绕芯部的叠层结构。
在该实施例中，上选择晶体管TSG和下选择晶体管BSG、存储晶体管Ml至M4使用公共的沟道区111和阻挡介质层114。在沟道柱110中，沟道区111提供多个晶体管的源漏区和沟道区。在替代的实施例中，可以采用彼此独立的步骤，分别形成上选择晶体管TSG和下选择晶体管BSG的半导体层和阻挡介质层以及存储晶体管Ml至M4半导体层和阻挡介质层。
如图5所示，其示出本公开实施例提供的单存储块的三维存储器阵列 的结构示意图。参考图5，存储块500包含堆叠在衬底(未示出)之上且平行于衬底表面的多个层，图5示出了四个层上的四个字线(WL)，不妨将其记为WL0至WL3。存储块500还布置有多个与字线垂直的通孔。一个字线与一个通孔的交叉点形成一个存储单元，因此也可以将一个通孔称之为存储单元串。本领域技术人员应该理解的是，存储块500的字线的数量和存储单元串的数量不限于特定的值，比如，存储块500可以包括64字线，64个字线与一个存储单元串交叉形成沿着存储单元串的64个存储单元。再比如，存储块500包括存储单元串的数量可以是以十万、百万甚至更大的数量级计算，一个字线上包括其与例如几百万个存储单元串交叉而形成的几百万个存储单元。存储块5中的存储单元可以是单级存储单元或者多级存储单元，其中，单级存储单元可以是能够存储1个比特(bit)的单级单元(SLC)；多级存储单元可以是能够存储2个bit的多级单元(MLC)，能够存储3个bit的三级单元(TLC)，能够存储4个bit的四级单元(QLC)，能够存储5个bit的五级单元(PLC)。如图5所示，存储块500还包括位线(BL)、位线选择器(BLS，也可以称之为串选择线SSL)、源极线(SL)、源极选择线(SLS，也可称之为地选择线GSL)，这些电路线和字线(WL)一起可以实现对存储块500中任何存储单元的寻址。
返回参考图3，外围电路302可以通过位线316、字线318、源极线314、SSG线315和DSG线313耦接到存储阵列301。外围电路302可以包括任何合适的模拟、数字以及混合信号电路，以用于通过经由位线316、字线318、源极线314、SSG线315和DSG线313将电压信号和/或电流信号施加到每个目标存储晶体管306以及从每个目标存储晶体管306感测电压信号和/或电流信号来促进存储阵列301的操作。外围电路302可以包括使用金属-氧化物-半导体(MOS)技术形成的各种类型的外围电路。例如，图6示出了一些示例性外围电路，外围电路302包括页缓存器/感测放大器604、列解码器/位线驱动器606、行解码器/WL驱动器608、电压发生器610、控 制电路612、寄存器614、接口616和数据总线618。应当理解，在一些示例中，还可以包括图6中未示出的附加外围电路。
页缓存器/感测放大器604可以被配置为根据来自控制电路612的控制信号从存储阵列301读取数据以及向存储阵列301编程(写入)数据。在一个示例中，页缓存器/感测放大器604可以存储要被编程到存储阵列301的一个页320中的一页编程数据(写入数据)。在另一示例中，页缓存器/感测放大器604可以执行编程验证操作，以确保数据已经被正确地编程到耦接到选定字线318的存储晶体管306中。在又一示例中，页缓存器/感测放大器604还可以感测来自位线316的表示存储在存储晶体管306中的数据位的低功率信号，并且在读取操作中将小电压摆幅放大到可识别的逻辑电平。列解码器/位线(BL)驱动器606可以被配置为由控制电路612控制，并且通过施加从电压发生器610生成的位线电压来选择一个或多个NAND存储单元串308。
行解码器/WL驱动器608可以被配置为由控制电路612控制，并且选择/取消选择存储阵列301的存储块304并且选择/取消选择存储块304的字线318。行解码器/WL驱动器608还可以被配置为使用从电压发生器610生成的字线电压来驱动字线318。在一些实施方式中，行解码器/字线(WL)驱动器608还可以选择/取消选择并且驱动SSG线315和DSG线313。如下文详细描述的，行解码器/WL驱动器608被配置为对耦接到(一个或多个)选定字线318的存储晶体管306执行擦除操作。电压发生器610可以被配置为由控制电路612控制，并且生成要被供应到存储阵列301的字线电压(例如，读取电压、编程电压、通过电压、局部电压、验证电压等)、位线电压和源极线电压。
控制电路612可以耦接到上文描述的每个外围电路，并且被配置为控制每个外围电路的操作。寄存器614可以耦接到控制电路612，并且包括状态寄存器、命令寄存器和地址寄存器，以用于存储用于控制每个外围电路 的操作的状态信息、命令操作码(OP码)和命令地址。接口616可以耦接到控制电路612，并且充当控制缓冲器，以缓冲从主机(未示出)接收的控制命令并且并将其中继到控制电路612，以及缓冲从控制电路612接收的状态信息并且将其中继到主机。接口616还可以经由数据总线618耦接到列解码器/位线驱动器606，并且充当数据I/O接口和数据缓冲器，以缓冲数据并且将其中继到存储阵列301或从存储阵列301中继或缓冲数据。
实际应用中，存储阵列301可以包括多个存储面(Plane)，每一个存储面包括多个存储块(Block)，每一个存储块包括多个存储页(Page)。存储页是读取和写入(也即编程)的最小单元，而存储块是擦除的最小单位。如图7所示，其示出本公开实施例提供包括两个存储面的存储器的结构示意图。并且可以包括外围电路；其中，所述外围电路可以包括：控制电路612、电压生成器610、行解码器/WL驱动器608、列解码器/BL驱动器606(a)、606(b)；存储面包括存储面701、702。尽管在该实施例中使用了双存储面结构，但是应当理解，在本申请的范围内也可以采用其它数量的存储面。在采用多面编程模式时，可以同时对存储面701、702进行编程。
实际应用中，控制电路612可以耦接到电压生成器610、行解码器/WL驱动器608和列解码器/BL驱动器606(a)、606(b)。电压生成器610可以耦接到行解码器/WL驱动器608。行解码器/WL驱动器608可以经由串选择线SSL1、字线WL1(1)到WL1(N)以及接地选择线GSL1耦接到存储面701，N是正整数，例如，N＝128。行解码器/WL驱动器608可以经由串选择线SSL2、字线WL2(1)至WL2(N)以及接地选择线GSL2耦接到存储面702。列解码器/BL驱动器606可以经由位线BL1(1)到BL1(M)耦接到存储面701，M是正整数，例如，M＝131072。列驱动器132可以经由位线BL2(1)至BL2(M)耦接到存储面702。存储面701、702中的每一个可以包含多个存储块，每个存储块可以包含多个存储页，每个 存储页可以包含多个存储单元。存储面701中的存储单元可以通过字线WL1(1)到WL1(N)以及位线BL1(1)至BL1(M)进行寻址，存储面702中的存储单元可以通过字线WL2(1)至WL2(N)以及位线BL2(1)到BL2(M)进行寻址。
控制电路612可以与主机、或存储器控制器(Memory Controlller)进行通信以接收数据以便存储在存储面701、702中并发送从存储面701、702获取的数据。控制电路612可以从主机或存储器控制器接收命令、地址或数据并且生成列地址信号Scadr1、Scadr2、行地址信号Sradr以及电压控制信号Svc。响应于来自控制电路612的电压控制信号Svc，电压生成器610可以生成用于读取、编程、擦除和验证操作的电压。电压生成器610生成的电压可能超过提供给存储器1的电源电压。行解码器/WL驱动器608可以响应于来自控制电路612的行地址信号Sradr而操作，以便选择用于读取、编程、擦除和验证操作的字线。列解码器/BL驱动器606(a)、606(b)可以响应于来自控制电路612的列地址信号Scadr1、Scadr2而操作，以便生成位线信号以选择用于读取、编程、擦除和验证操作的位线。
在编程操作中，电压生成器610可以使用电源电压(例如，3.3V)来生成编程电压(例如，20V)和编程通过电压(例如，10V)，行解码器/WL驱动器608可以向所选择的字线施加具有编程电压的幅度的编程脉冲，向未选定的字线施加编程通过电压，向串选择线SSL1、SSL2施加电源电压，以及向接地选择线GSL1、GSL2施加接地电压，并且列解码器/BL驱动器606(a)、606(b)可以向所选择的位线施加接地电压(例如，0V)，以及向未选定的位线施加电源电压。在验证操作中，电压生成器610可以生成合适的验证电压，行解码器/WL驱动器608可以将合适的验证电压施加到所选择的字线，将电源电压施加到串选择线SSL1、SSL2，并且将电源电压施加到接地选择线GSL1、GSL2，并且列解码器/BL驱动器606(a)、606(b)可以将接地电压施加到未选择的位线，并且将电源电压分别施加 到存储面701、702的被选择的位线以便在所选择的位线上从所选择的存储单元中读取数据。如果数据读取是不正确的，则控制电路612可以将所选择的存储单元验证为失败，而如果数据读取是正确的，则控制电路612可以将所选择的存储单元验证为通过。
存储单元可以是单级单元(SLC)类型、二级单元(MLC)类型、三级单元(TLC)类型、四级单元(QLC)类型、五级单元(PLC)类型或更高级别类型。每个存储单元可以保持Q个可能的数据状态之一，其中，Q是等于或大于2的正整数，例如，对于SLC，Q＝2，对于MLC，Q＝4，对于TLC，Q＝8，对于QLC，Q＝16，并且对于PLC，Q＝32。Q个可能的数据状态可以包括擦除状态S(0)和程序状态S(1)至S(Q-1)，其中，程序状态S(1)是最低程序状态，而程序状态S(Q-1)处于最高程序状态。在一个示例中，TLC可以被编程为8种可能的数据状态之一，其中，程序状态S(1)是最低程序状态，而程序状态S(7)是最高程序状态。
存储单元可以起初设置为擦除状态S(0)，并且稍后，可以对存储单元执行一系列编程验证操作，以便将其编程为相应的目标程序状态。一系列编程验证操作可以从最低程序状态S(1)开始，然后进行到较高的程序状态，直到所选择的存储单元的阈值电压达到相应的目标程序状态的相应验证电压电平为止。在一些实施例中，可以将验证电压分别选择作为程序状态S(1)至S(Q-1)的阈值电压分布曲线的最小阈值电压。每个编程验证操作可以包括编程操作和后续的验证操作。在编程操作中，可以选择存储单元中的一些并且按照从第一行到第N行、或者从第N行到第一行的逐行方式编程到程序状态中。
在实际使用过程中，存储器系统中的三维NAND型存储器存在多种缺陷，有些缺陷可以在出厂时检测到，有些缺陷是在出厂后随着使用环境的变化而暴露出来的。实际应用中，三维NAND型存储器的某些存储单元阵列中可能存在结构性薄弱点，这些结构性薄弱点可能需要较长的时间或较 多次编程操作、擦除操作后才能发展并成为缺陷。例如，三维NAND型存储器的存储单元阵列在编程和擦除循环过程中需要经受高压应力，三维NAND型存储器的某些存储单元阵列中薄弱结构会在循环后发展为缺陷。
三维NAND型存储器出现缺陷时，这些缺陷有可能并不影响擦除操作、编程操作反馈的执行成功的status，也就是说这些缺陷的存在也能是擦除操作、编程操作返回执行成功的status，但是写入的数据有可能已经发生异常，造成读取操作的UECC，进而引起数据丢失的现象。
经研究发现，在3D NAND闪存的应用中，数据系统在写入数据的时候会由于字线漏电(WL lkg，Word Line Leakage)等缺陷的存在从而发生编程状态失败(PSF，Programming Status Failed)，尤其在进行多存储面编程时，如果一个Plane中的某个Block由于这种WL lkg的存在造成PSF，这种漏电会影响到整个多存储面编程操作中x-path上的电压(一般，将向字线上施加的电压可以称之x-path上的电压)，也就是说，影响施加在字线上的电压，则整个WL对应的存储单元中的数据均可能被破坏。由于每个WL可以对应多个字符串的存储单元，基于此，可能出现大量数据丢失的现象，从而给存储器系统带来故障。这种类型的故障一般被定义为三维NAND型存储器的可靠性故障，该故障在现场可能会进一步导致存储器系统的故障。
在三维NAND型存储器中，内部电压偏置电源通常在编程操作期间在不同面之间共享，这是为了节省电路面积和功耗。如果一个存储面有缺陷，则共享内部电压偏置电源的其它存储面可能均无法达到目标电平，也即在出现一个存储面出现PSF，也会影响其他邻近的存储面中x-path上的电压，从而对其他邻近的存储面中的写入的数据产生影响，因此即使只有一个面有物理缺陷，也经常会在多个存储面出现读取操作中的UCEE，这种现象可以称之为邻面干扰(NPD，Neighbor Plane Disturb)。显然，邻面干扰会带来数据丢失。具体参见图8所示，在图8中，当Plane0中的字线WLn中的 Str3出现PSF，邻近的Plane1、Plane2、Plane3中的字线WLn中的string3中包含的存储单元的阈值电压的分布发生异常，造成UECC，从而引起数据丢失。需要说明的是，图8中Str0-Str5代表Plane0、Plane1、Plane2、Plane3中的存储子块。
为了避免由于PSF引起数据的UECC，存储器系统可以使用独立冗余磁盘阵列(RAID，Redundant Arrays of Independent Disks)或者主机存储备份(HMB，Host Memory Buffer)来恢复丢失的数据，但这些方式对整个系统性能造成负面影响。比如，一般存储器系统采用面级别的RAID，面级别的RAID只能恢复一个存储面的故障。如果多个存储面出现编程失败，存储器系统将无法恢复数据。对于此类故障，存储器系统可以在管芯(Die)级别进行RAID，但存储器系统的配置成本将会增加。特别是为了解决上文提到的NPD现象，由于造成数据丢失的WL/Str(String，存储子块)的范围比较大，数据系统需要耗费较大的资源来备份正在写入的数据，从而对数据系统性能造成更大的负面影响。并且，并非所有的存储器控制器或固件(FW，Fireware)都能够自带系统解决方案来解决NPD问题，这就不可避免的造成了数据丢失。
为了解决上述技术问题，本公开实施例提供一种存储器(memory device)的擦除验证方法，如图9所示，其示出本公开实施例提供的存储器的擦除验证方法的实现流程示意图。具体地，所述擦除验证方法可以包括：
步骤901：在对所述存储器中选定的存储块执行擦除操作之后，对所述存储块执行第一擦除验证操作；
步骤902：确定所述第一擦除验证操作的第一验证结果；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；
步骤903：基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
这里，所述存储器包括多个存储块。所述擦除验证方法是针对所述存储器中选定的存储块进行的。可以理解的是，选定的存储块可以包括至少一个存储块，也就是说，选定的存储块的数量可以为一个或多个。
在步骤901中，所述第一擦除验证操作可以是对选定的存储块执行完擦除操作后执行的验证操作，其被配置为验证所述存储块执行完所述擦除操作是否已经被成功的擦除。
在一些实施例中，所述第一擦除验证操作包括：向所述存储块施加擦除验证电压，感测与所述擦除验证电压对应的待验证信号；基于所述待验证信号确定所述第一擦除验证操作的第一验证结果。
在一些实施例中，所述存储器包括多个存储块；每一个存储块包括多个存储单元以及与所述多个存储单元分别耦接的多个字线；所述向所述存储块施加擦除验证电压，可以包括：
利用相同或不同电压源，向所述存储块中的所述多个字线施加所述擦除验证电压。
需要说明的是，前述已经描述，一个存储块可以分为多个存储子块，(String)，基于此，在对所述存储块进行第一擦除验证操作时，可以对String中的存储单元一起进行第一擦除验证操作，依次验证所述存储块中的每一个String，其中，在对String中的存储单元一起进行第一擦除验证操作时，需要在一个String中所有的字线WL上施加所述擦除验证电压，然后，通过感测放大器进行感测(Sense)，获得待验证信号，基于所述待验证信号以验证所述擦除操作是否成功。需要说明的是，该待验证信号可以是电压信号或电流信号。
其中，向所述存储块中每一个String中包含的多个字线施加所述擦除验证电压的电压源可以相同，也可以不同。根据存储器的具体结构进行设置，在此不进行限制。
在对所述存储器中的每一个String均进行了第一擦除验证操作之后， 确定所述第一擦除验证操作的第一验证结果，也即步骤902，其中，所述第一验证结果也就是前述所说完成擦除操作后，执行第一擦除操作之后，反馈的status。在实际应用过程中，所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除。
在步骤903中，所述基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作，可以包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
这里，根据所述擦除操作是否执行成功，来确定是否需要执行第二擦除验证操作：在第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行第二擦除验证操作；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行第二擦除验证操作。
在一些实施例中，所述擦除验证方法还包括：
在确定对所述存储块执行所述第二擦除验证操作时，对所述存储块执行所述第二擦除验证操作；
确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。
这里，所述第二擦除验证操作可以是一种对所述存储块中字线间的漏电检测操作。也就是，在前述确定对所述存储块执行所述第二擦除验证操作时，对所述存储块执行所述第二擦除验证操作，并确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。也就是，通过第二擦除验证操作，来确定所述选中的存储器在擦除成功后，是否还存在字线间漏电的情况。
在一些实施例中，所述擦除验证方法还包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果被配置为表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
在一些实施例中，所述擦除验证方法还包括：
在所述第二验证结果被配置为表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
需要说明的是，这里描述的所述坏块可以是后续不能继续进行编程操作的存储块。所述可用块可以是后续能够继续进行编程的存储块。
在一些实施例中，所述第一标记或所述第二标记存储在所述存储器中的寄存器中。其中，所述寄存器可以是状态寄存器。
对于第二擦除验证操作，在一些实施例中，所述第二擦除验证操作可以通过内置在所述存储器中的字线间漏电检测电路进行。
具体地，在一些实施例中，所述第二擦除验证操作，可以包括：向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和参考电压，获得比较结果；基于所述比较结果确定所述第二验证结果。
在一些实施例中，所述向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压，可以包括：
向所述待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；
当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
经过所述预设时间后，检测所述待检测字线的剩余电压。
在一些实施例中，所述基于所述比较结果确定所述第二验证结果，可以包括：
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
需要说明的是，该字线间漏电检测电路可以是外围电路的一部分。具体电路结构参见图10(A)和图10(B)。其中，图10(A)示出本公开提供的一种字线间漏电检测电路的结构电路与待检测字线之间的连接关系用于测量待检测字线与相邻字线之间的漏电情况的示意图；图10(B)示出本公开提供的一种字线间漏电检测电路的结构电路与待检测字线之间的连接关系用于测量待检测字线与位线之间的漏电情况的示意图。
需要说明的是，在图10(A)和图10(B)中，Sel WL为待检测字线；Adjacent WL与Sel WL是相邻字线。位于待检测字线Sel WL与相邻字线Adjacent WL之间的等效电阻1003表示检测字线Sel WL与相邻字线Adjacent WL之间漏电路径；在待检测字线Sel WL与相邻字线Adjacent WL之间出现漏电的情况下，等效电阻1003相当于短路状态；在待检测字线Sel WL与相邻字线Adjacent WL之间无异常的情况下，等效电阻1003相当于开路状态。待检测字线Sel WL与位线BL之间的等效电阻1004表示待检测字线Sel WL与位线BL之间漏电路径，在待检测字线Sel WL与位线BL之间出现漏电情况下，等效电阻1004相当于短路状态；待检测字线Sel WL与位线BL之间漏电无异常状态时，等效电阻1004相当于开路状态。
如图10(A)和图10(B)所示，所述字线间漏电检测电路可以包括：隔离模组1001和比较模组1002，其中，隔离模组1001包括电子开关SW2、高压隔离电容C1、Clamp静电保护组件1001-1；所述比较模组包括电压源VDD、电子开关SW3和比较器1002-1。
需要说明的是，向待检测字线施加的漏电检测电压，由前述电压发生器610产生；具体的，字线间漏电检测电路响应于漏电检测指令信号，可以通过电子开关SW1和行解码器将驱动电压耦接到待检测字线。
这里，在所述字线间漏电检测电路响应于漏电检测指令信号时，还可以将隔离模组耦接到所述待检测字线和比较模组，其中，所述隔离模组中的电子开关SW2将隔离模组耦接到所述待检测字线。所述隔离模组中的高压隔离电容C1可有效的隔离比较模组(字线间漏电检测电路)与电压发生器(字线工作电路，擦除或编程的施加电压电路)，实现了待检测字线在高压工作模式和低压漏电检测模式之间的切换。其中，高压隔离电容C1的数值范围可以由电压耦合率和存储阵列的尺寸确定。
进一步的，在高压隔离电容C1与比较器之间还设置有Clamp静电保护组件1001-1。Clamp静电保护组件1001-1具有较强的电流泄放能力，利用其电容的瞬态特性，在静电电压加到Clamp静电保护组件1001-1上的时候，由于RC时间常数(1微秒甚至以上)比静电电压加载时间(10纳秒左右)长太多，会使电容的瞬态效应非常明显，因此比较器输入端的电压无法立刻抬高，可有效防止比较器的安全工作区(SOA，Safe Operating Area)失效，对比较器起到保护作用。
其中，比较模组1002中的比较器1002-1，被配置为确定参考电压与待检测字线的电压之间的差值，然后根据这个差值与预设阈值进行比较，从而确定待检测字线与相邻字线间是否有漏电情况，也即确定第二擦除验证的第二验证结果。比较器1002-1接收的待检测字线的电压是预设时间内待检测字线上的剩余电压。参考电压是由参考电压源Vref提供的。具体来说，控制电路在接收到漏电检测指令信号后，控制行解码器通过电压发生器给待检测字线施加漏电检测电压，将与所述待检测字线相邻的字线接地；然后，当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；经过所述预设时间后，检测所述待检测字线 的剩余电压。此时检测的剩余电压也即要与参考电压比较的那个电压。
之后，根据剩余电压与参考电压之间的差值，确定所述存储块中所述待检测字线与相邻字线之间是否存在漏电情况。其中，所述预设阈值和参考电压可以是经验值。
这里，具体测量待检测字线的剩余电压的过程如下：在通过电压发生器610给检测字线的漏电检测电压达到预定值，停止向所述待检测字线施加所述漏电检测电压。电子开关SW3闭合，通过VDD给C1充电使其电压达到VDD，然后将电子开关SW3断开；待检测字线在浮置的过程中，由于待检测字线上的电压的变化而改变了C1左边平行板的电势，通过耦合效应，其右边平行板的电势也会改变，经过预设时间后，C1右边平行板的电势从VDD改变到一个低一些的电势，该低一些的电势也就是剩余电压。
需要说明的是，图10(A)和图10(B)仅示出了一个待检测字线的字线间漏电检测。事实上，由于本申请提供的字线间漏电检测电路中的元件皆通过低压器件实现，因而电路自身的面积较小，在存储器中可设置多个该字线间漏电检测电路，以实现同时对多条待检测字线的字线间漏电情况进行检测。
在一些实施例中，所述擦除验证方法还包括：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
需要说明的是，经研究发现，在对存储器进行擦除时，由于工艺的缺陷会产生字线间漏电，而由于现有工艺的特点，根据TAS DPPM测试，绝大多数的存储器有漏电的字线均是WL0，其中，WL0是存储器中执行编程操作的第一根字线。为了节省检测时间，可以仅对高风险的字线进行检测，比如，字线WL0。所述预定范围可以根据设计人员自由设定。
为了实现仅对设定范围的字线进行检测，可以在存储器控制器中添加 一组寄存器，比如，用于控制字线间漏电检测电路是是否开启的寄存器；再比如，用于存储预设字线范围的起始地址与结束地址的寄存器等等。
本公开实施例提供擦除验证方法，通过确定第一擦除验证操作的第一验证结果确定执行了擦除操作的存储块是否被成功擦除，然后根据这个第一验证结果确定是否对该存储块执行第二擦除验证操作，以检测该存储块是否存在字线间漏电情况(经研究发现，字线间漏电是导致数据丢弃的主要因素)，通过本公开的验证操作，可以有效的侦测到存储块是否为坏块，从而可以有效地避免在后续的编程操作中发生异常而造成数据丢失，如此，在多面编程中，能够将编程异常限制在本身存在异常的存储面内，减轻编程异常对其它正常存储面的影响，即减小邻面干扰带来的不利影响，也即减少了发生NPD现象的概率。
为了理解本公开，如图11所示，其示出本公开实施例提供的一种存储器的擦除验证方法的流程示意图。
如图11所示，应用于存储器侧，所述擦除验证方法的流程具体可以包括：
步骤1101：在对所述存储器中选定的存储块执行的擦除操作之后，对所述存储块执行第一擦除验证操作；
步骤1102：确定所述第一擦除验证操作的第一验证结果；其中，在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，跳转执行步骤1103；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，跳转执行步骤1105；
步骤1103：对所述存储块执行第二擦除验证操作；
步骤1104：确定所述第二擦除验证操作的第二验证结果；在所述验证结果被配置为表明所述存储块不存在字线间漏电情况时，跳转执行步骤1106；在所述验证结果被配置为表明所述存储块存在字线间漏电情况时，跳转执行步骤1105；
步骤1105：保存第一标记；所述第一标记被配置为表征所述存储块为坏块；
步骤1106：保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
这里，也就是在存储块的第一擦除验证成功的情况下，才开启对存储块的第二擦除验证操作，这样不仅节省验证时间，而且能够识别哪些因字线间漏电导致编程失败的存储块。
需要说明的是，在确定的所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，判断当前执行的所述擦除操作是否达到最大擦除次数；若判定当前执行的所述擦除操作未达到所述最大擦除次数，继续执行所述擦除操作和第一擦除验证操作，直到到达所述最大擦除次数为止；若判定当前执行的所述擦除操作达到所述最大擦除次数，确定标记所述存储块为坏块。因为，存储块中包含很多的存储单元，不同的存储单元在结构上还是有稍微差别，以及存储单元所处的态也是有所不同的，有的存储单元一次就能擦除成功；有的存储单元需要多次，因此，可以设置最大擦除次数，以准确识别存储块是否是坏块。
本公开还提供一种存储器的操作方法，具体地，所述操作方法可以包括：
对所述存储器中选定的存储执行擦除操作；
对所述存储器执行前述任一所述的擦除验证方法，以确定所述存储块是否存在字线间漏电情况。
在一些实施例中，所述操作方法还包括：
若反馈的所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，判断当前执行的所述擦除操作是否达到最大擦除次数；
若判定当前执行的所述擦除操作未达到所述最大擦除次数，继续执行所述擦除操作和第一擦除验证操作，直到到达所述最大擦除次数为止；
若判定当前执行的所述擦除操作达到所述最大擦除次数，确定标记所述存储块为坏块。
需要说明的是，前述擦除验证方法可以是操作方法中的擦除验证步骤，因此，这里的操作方法与前述擦除验证方法是同一发明构思的方法，这里出现的名词在前述已经描述，在此不再赘述。
这里，所述最大擦除次数可以根据实际情况人为的设定。比如，所述最大擦除次数可以为5次或6次等。
也就是，在没有达到最大擦除次数时，继续对存储器执行擦除操作，直到到达所述最大擦除次数为止，若反馈的第一验证结果还是失败，则将存储块记为坏块。
为了理解本公开的实施例提供的存储器的操作方法，如图12所示，其示出本公开实施例提供的一种存储器的操作方法的流程示意图。
在图12中，在存储器侧，所述操作方法具体可以包括：
步骤1201：对所述存储器中选定的存储块执行擦除操作；
步骤1202：在对所述存储器中选定的存储块执行的擦除操作之后，对所述存储块执行第一擦除验证操作；
步骤1203：确定所述第一擦除验证操作的第一验证结果；其中，在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，跳转执行步骤1204；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，跳转执行步骤1206；
步骤1204：对所述存储块执行第二擦除验证操作；
步骤1205：确定所述第二擦除验证操作的第二验证结果；其中，在所述验证结果被配置为表明所述存储块不存在字线间漏电情况时，跳转执行步骤1208；在所述验证结果被配置为表明所述存储块存在字线间漏电情况时，跳转执行步骤1207；
步骤1206：若反馈的所述第一验证结果被配置为表明经所述擦除操作 后所述存储块未被成功擦除时，判断当前执行的所述擦除操作是否达到最大擦除次数；若判定当前执行的所述擦除操作未达到所述最大擦除次数，跳转执行步骤1201，直到到达所述最大擦除次数为止；若判定当前执行的所述擦除操作达到所述最大擦除次数，跳转1207；
步骤1207：保存第一标记；所述第一标记被配置为表征所述存储块为坏块；
步骤1208：保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
需要说明的是，这里在存储器侧的操作方法的完成流程图。这里出现的名词及步骤在前述已经详细描述在此不再赘述。
本公开实施例还提供一种存储器，包括：存储阵列；所述存储阵列包括多个存储块；
以及与所述存储阵列耦接的外围电路；其中，
所述外围电路配置为：在对所述存储器中选定的存储块执行的擦除操作之后，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
在一些实施例中，所述外围电路包括：控制电路、电压生成器、字线驱动器和感测放大器；所述电压生成器、所述字线驱动器和所述感测放大器与所述多个存储块耦接，并被所述控制电路所控制；
所述字线驱动器被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块施加擦除验证电压；
所述感测放大器被配置为：感测与所述擦除验证电压对应的待验证信号；
所述控制电路被配置为：基于所述待验证信号确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作。
这里，所述待验证信号为电压信号或电流信号，其用于使所述控制电路确定所述擦除操作的第一验证结果(或擦除status)。
在一些实施例中，所述控制电路还被配置为：
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
在一些实施例中，所述控制电路还被配置为：在确定对所述存储块执行所述第二擦除验证操作时，对所存储块执行所述第二擦除验证操作；确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。
在一些实施例中，所述外围电路还包括：第一寄存器，配置为：在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述验证结果被配置为表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
在一些实施例中，所述外围电路还包括：第二寄存器，配置为：在所述验证结果被配置为表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
需要说明的是，第一寄存器和第二寄存器仅是为了方面描述不同情况下的寄存器，第一寄存器和第二寄存器在实际应用过程可能是一个，也就是说，这里描述的第一、第二，不用于限制本公开。
在一些实施例中，所述外围电路还包括：字线间漏电检测电路，所述字线间漏电检测电路与所述存储块耦接；
所述字线驱动器还被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块中待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
所述字线间漏电检测电路被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压与参考电压，获得比较结果；向所述控制电路传输所述比较结果；
所述控制电路被配置为：接收所述比较结果并基于所述比较结果向所述控制电路反馈所述第二验证结果。
在一些实施例中，所述控制电路还被配置为：
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
在一些实施例中，所述字线间漏电检测电路包括：比较模组；其中，
所述比较模组被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
在一些实施例中，所述字线间漏电检测电路还包括：隔离模组，其中，所述隔离模组被配置为：隔离所述比较模组和所述电压生成器。
在一些实施例中，所述比较模组包括：参考电压源和比较器，其中，
所述参考电压源被配置为：提供所述参考电压，向所述比较器输入所述参考电压；
所述比较器被配置为：检测所述待检测字线经预设时间后的剩余电压， 接收所述参考电压；比较所述剩余电压与所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
在一些实施例中，所述隔离模组包括：隔离电容，被配置为：隔离所述比较模组和所述电压生成器。
需要说明的是，对于字线间漏电检测电路的描述，可参见前述图10(A)和10(B)以及文字描述。
在一些实施例中，所述外围电路还配置为：在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
在一些实施例中，所述存储器包括三维NAND型存储器。
需要说明的是，这里的存储器与前述的擦除验证方法属于同一发明构思，这里出现的名词及操作，在前述已经详细描述，在此不再赘述。
本公开实施例还提供一种存储器系统，包括：
一个或多个如前述任一所述的存储器；以及
存储器控制器，其与所述存储器耦接。
在一些实施例中，所述外围电路配置为，接收到第一指令；响应于所述第一指令，对所述存储器中选定的存储块执行擦除操作，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除或所述存储块存在字线间漏电情况时，保存第一标记；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除且所述存储块不存在字线间漏电情况时，保存第二标记；
所述存储器控制器配置为，根据所述第一标记，发出第二指令；根据所述第二标记，发出第三指令；
所述外围电路配置为，接收到所述第二指令；响应于所述第二指令，不再对所述存储块进行编程操作；接收所述第三指令；响应于所述第三指令，对所述存储块进行编程操作。
这里，所述第一指令为存储器控制602通过接口616传输给外围电路302，以使所述外围电路响应于该第一指令对所述存储器中选定的存储块执行擦除操作，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作。所述第二指令为存储器控制器602通过接口616传输给外围电路，以使所述外围电路响应于所述第二指令不再对所述存储块进行编程操作。所述第三指令为存储器控制器602通过接口616传输给外围电路302，以使所述外围电路响应于所述第三指令，对所述存储块进行编程操作。
这里的存储器系统与前述的擦除验证方法、存储器属于同一发明构思，这里出现的名词及操作，在前述已经详细描述，在此不再赘述。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本申请实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。

Claims (30)

  1. 一种存储器的擦除验证方法，包括：
    在对所述存储器中选定的存储块执行擦除操作之后，对所述存储块执行第一擦除验证操作；
    确定所述第一擦除验证操作的第一验证结果；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；
    基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
  2. 根据权利要求1所述的擦除验证方法，其中，所述基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作，包括：
    在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
    在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
  3. 根据权利要求2所述的擦除验证方法，其中，所述擦除验证方法还包括：
    在确定对所述存储块执行所述第二擦除验证操作时，对所述存储块执行所述第二擦除验证操作；
    确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。
  4. 根据权利要求3所述的擦除验证方法，其中，所述擦除验证方法还包括：
    在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果被配置为表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
  5. 根据权利要求4所述的擦除验证方法，其中，所述擦除验证方法还包括：
    在所述第二验证结果被配置为表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为后续能够进行编程操作的可用块。
  6. 根据权利要求1所述的擦除验证方法，其中，所述第一擦除验证操作包括：向所述存储块施加擦除验证电压，感测与所述擦除验证电压对应的待验证信号；基于所述待验证信号确定所述第一擦除验证操作的第一验证结果。
  7. 根据权利要求6所述的擦除验证方法，其中，所述存储器包括多个存储块；每一个存储块包括多个存储单元以及与所述多个存储单元分别耦接的多个字线；所述向所述存储块施加擦除验证电压，包括：
    利用相同或不同电压源，向所述存储块中的所述多个字线施加所述擦除验证电压。
  8. 根据权利要求3所述的擦除验证方法，其中，所述第二擦除验证操作包括：向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和参考电压，获得比较结果；基于所述比较结果确定所述第二验证结果。
  9. 根据权利要求8所述的擦除验证方法，其中，所述向所述存储块中待检测字线施加漏电检测电压，检测所述待检测字线经预设时间后的剩余电压，包括：
    向所述待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；
    当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
    经过所述预设时间后，检测所述待检测字线的剩余电压。
  10. 根据权利要求9所述的擦除验证方法，其中，所述基于所述比较结果确定所述第二验证结果，包括：
    在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检测字线与相邻字线之间不存在漏电情况；
    在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
  11. 根据权利要求1所述的擦除验证方法，其中，所述第二擦除验证操作通过内置在所述存储器中的字线间漏电检测电路进行。
  12. 根据权利要求2所述的擦除验证方法，其中，所述擦除验证方法还包括：
    在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
  13. 根据权利要求5所述的擦除验证方法，其中，所述第一标记或所述第二标记存储在所述存储器中的寄存器中。
  14. 一种存储器的操作方法，包括：
    对所述存储器中选定的存储块执行擦除操作；
    对所述存储器执行权利要求1至13任一项所述的擦除验证方法，以确定所述存储块是否存在字线间漏电情况。
  15. 根据权利要求14所述的操作方法，其中，所述操作方法还包括：
    若反馈的所述第一验证结果表明经所述擦除操作后所述存储块未被成功擦除时，判断当前执行的所述擦除操作是否达到最大擦除次数；
    若判定当前执行的所述擦除操作未达到所述最大擦除次数，继续执行所述擦除操作和第一擦除验证操作，直到到达所述最大擦除次数为止；
    若判定当前执行的所述擦除操作达到所述最大擦除次数，确定标记所述存储块为坏块。
  16. 一种存储器，包括：存储阵列；所述存储阵列包括多个存储块；
    以及与所述存储阵列耦接的外围电路；其中，
    所述外围电路被配置为：在对所述存储器中选定的存储块执行擦除操作之后，对所述存储块执行第一擦除验证操作；确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第一验证结果被配置为反映经所述擦除操作后所述存储块是否被成功擦除；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况。
  17. 根据权利要求16所述的存储器，其中，所述外围电路包括：控制电路、电压生成器、字线驱动器和感测放大器；所述电压生成器、所述字线驱动器和所述感测放大器与所述多个存储块耦接，并被所述控制电路所控制；
    所述字线驱动器被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块施加擦除验证电压；
    所述感测放大器被配置为：感测与所述擦除验证电压对应的待验证信号；
    所述控制电路被配置为：基于所述待验证信号确定所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作。
  18. 根据权利要求17所述的存储器，其中，所述控制电路还被配置为：
    在所述第一验证结果表明经所述擦除操作后所述存储块被成功擦除时，确定对所述存储块执行所述第二擦除验证操作；
    在所述第一验证结果表明经所述擦除操作后所述存储块未被成功擦除时，确定不对所述存储块执行所述第二擦除验证操作。
  19. 根据权利要求18所述的存储器，其中，所述控制电路还被配置为：在确定对所述存储块执行所述第二擦除验证操作时，对所存储块执行所述第二擦除验证操作；确定所述第二擦除验证操作的第二验证结果；所述第二验证结果被配置为反映所述存储块是否存在字线间漏电情况。
  20. 根据权利要求19所述的存储器，其中，所述外围电路还包括：第一寄存器，被配置为：在所述第一验证结果表明经所述擦除操作后所述存储块未被成功擦除时或在所述第二验证结果表明所述存储块存在字线间漏电情况时，保存第一标记；所述第一标记被配置为表征所述存储块为坏块。
  21. 根据权利要求20所述的存储器，其中，所述外围电路还包括：第二寄存器，被配置为：在所述第二验证结果表明所述存储块不存在字线间漏电情况时，保存第二标记；所述第二标记被配置为表征所述存储块为可用块。
  22. 根据权利要求19所述的存储器，其中，所述外围电路还包括：字线间漏电检测电路，所述字线间漏电检测电路与所述存储块耦接；
    所述字线驱动器还被配置为：在所述控制电路的控制下，通过所述电压生成器向所述存储块中待检测字线施加漏电检测电压；将与所述待检测字线相邻的字线接地；当所述待检测字线的漏电检测电压达到预定值时，停止向所述待检测字线施加所述漏电检测电压；
    所述字线间漏电检测电路被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压与参考电压，获得比较结果；向所述控制电路传输所述比较结果；
    所述控制电路还被配置为：接收所述比较结果并基于所述比较结果向所述控制电路反馈所述第二验证结果。
  23. 根据权利要求22所述的存储器，其中，所述控制电路还被配置为：
    在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值小于预设阈值时，确定所述第二验证结果被配置为表明所述存储块中所述待检 测字线与相邻字线之间不存在漏电情况；
    在所述比较结果为所述剩余电压与所述参考电压的差值的绝对值不小于所述预设阈值时，确定所述第二验证结果被配置为表明所述存储块中的所述待检测字线与相邻字线之间存在漏电情况。
  24. 根据权利要求22所述的存储器，其中，所述字线间漏电检测电路包括：比较模组；其中，
    所述比较模组被配置为：检测所述待检测字线经预设时间后的剩余电压；比较所述剩余电压和所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
  25. 根据权利要求24所述的存储器，其中，所述字线间漏电检测电路还包括：隔离模组，其中，所述隔离模组被配置为：隔离所述比较模组和所述电压生成器。
  26. 根据权利要求24所述的存储器，其中，所述比较模组包括：参考电压源和比较器，其中，
    所述参考电压源被配置为：提供所述参考电压，向所述比较器输入所述参考电压；
    所述比较器被配置为：检测所述待检测字线经预设时间后的剩余电压，接收所述参考电压；比较所述剩余电压与所述参考电压，获得比较结果；向所述控制电路传输所述比较结果。
  27. 根据权利要求25所述的存储器，其中，所述隔离模组包括：隔离电容，被配置为：隔离所述比较模组和所述电压生成器。
  28. 根据权利要求18所述的存储器，其中，所述外围电路还被配置为：在所述第一验证结果表明经所述擦除操作后所述存储块未被成功擦除时，确定对所述存储块中预定范围的字线执行所述第二擦除验证操作。
  29. 一种存储器系统，包括：
    一个或多个如权利要求16至28中任一项所述的存储器；以及
    存储器控制器，其与所述存储器耦接。
  30. 根据权利要求29所述的存储器系统，其中，
    所述外围电路配置为，接收到第一指令；响应于所述第一指令，对所述存储器中选定的存储块执行擦除操作，对所述存储块执行第一擦除验证操作；反馈所述第一擦除验证操作的第一验证结果；基于所述第一验证结果确定是否对所述存储块执行第二擦除验证操作；所述第二擦除验证操作被配置为确定所述存储块是否存在字线间漏电情况；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块未被成功擦或所述存储块存在字线间漏电情况时，保存第一标记；在所述第一验证结果被配置为表明经所述擦除操作后所述存储块被成功擦除且所述存储块不存在字线间漏电情况时，保存第二标记；
    所述存储器控制器配置为，根据所述第一标记，发出第二指令；根据所述第二标记，发出第三指令；
    所述外围电路配置为，接收到所述第二指令；响应于所述第二指令，不再对所述存储块进行编程操作；接收所述第三指令；响应于所述第三指令，对所述存储块进行编程操作。
PCT/CN2022/094436 2021-05-25 2022-05-23 存储器及其擦除验证方法、操作方法、存储器系统 WO2022247775A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280001459.6A CN115136238A (zh) 2021-05-25 2022-05-23 存储器及其擦除验证方法、操作方法、存储器系统
US18/092,082 US20240013842A1 (en) 2021-05-25 2022-12-30 Memory and its erase verification method, operation method, and a memory system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110573212.9 2021-05-25
CN202110573212.9A CN113223596B (zh) 2021-05-25 2021-05-25 一种三维非易失性存储器及其数据擦除验证方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/092,082 Continuation US20240013842A1 (en) 2021-05-25 2022-12-30 Memory and its erase verification method, operation method, and a memory system

Publications (1)

Publication Number Publication Date
WO2022247775A1 true WO2022247775A1 (zh) 2022-12-01

Family

ID=77099500

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/094436 WO2022247775A1 (zh) 2021-05-25 2022-05-23 存储器及其擦除验证方法、操作方法、存储器系统

Country Status (2)

Country Link
CN (1) CN113223596B (zh)
WO (1) WO2022247775A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113223596B (zh) * 2021-05-25 2022-06-17 长江存储科技有限责任公司 一种三维非易失性存储器及其数据擦除验证方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150117114A1 (en) * 2013-10-28 2015-04-30 Sandisk Technologies Inc. Word line coupling for deep program-verify, erase-verify and read
CN105513639A (zh) * 2014-10-13 2016-04-20 爱思开海力士有限公司 非易失性存储器件及其操作方法
CN107045888A (zh) * 2016-02-05 2017-08-15 华邦电子股份有限公司 数据擦除方法
CN113223596A (zh) * 2021-05-25 2021-08-06 长江存储科技有限责任公司 一种三维非易失性存储器及其数据擦除验证方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06251593A (ja) * 1993-02-24 1994-09-09 Matsushita Electron Corp フラッシュメモリの消去あるいは書き込み制御方法
US20050128807A1 (en) * 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
JP4642018B2 (ja) * 2004-04-21 2011-03-02 スパンション エルエルシー 不揮発性半導体装置および不揮発性半導体装置の消去動作不良自動救済方法
CN112614526B (zh) * 2021-01-06 2022-05-13 长江存储科技有限责任公司 用于半导体器件的擦除验证方法及半导体器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150117114A1 (en) * 2013-10-28 2015-04-30 Sandisk Technologies Inc. Word line coupling for deep program-verify, erase-verify and read
CN105513639A (zh) * 2014-10-13 2016-04-20 爱思开海力士有限公司 非易失性存储器件及其操作方法
CN107045888A (zh) * 2016-02-05 2017-08-15 华邦电子股份有限公司 数据擦除方法
CN113223596A (zh) * 2021-05-25 2021-08-06 长江存储科技有限责任公司 一种三维非易失性存储器及其数据擦除验证方法

Also Published As

Publication number Publication date
CN113223596A (zh) 2021-08-06
CN113223596B (zh) 2022-06-17

Similar Documents

Publication Publication Date Title
KR102423291B1 (ko) 프로그램 전압을 보정하는 플래시 메모리 장치, 3차원 메모리 장치, 메모리 시스템 및 그의 프로그램 방법
KR102512448B1 (ko) 메모리 시스템 및 그의 동작 방법
US10296226B2 (en) Control logic, semiconductor memory device, and operating method
TW201640649A (zh) 包含虛擬記憶體單元的半導體記憶體裝置和操作其之方法
US10497452B2 (en) Semiconductor memory device and method of operating the same
KR20160073873A (ko) 메모리 시스템 및 메모리 시스템의 동작 방법
KR20170129516A (ko) 반도체 메모리 장치 및 이의 동작 방법
KR20170021402A (ko) 메모리 시스템 및 그의 동작방법
US11894092B2 (en) Memory system including a nonvolatile memory device, and an erasing method thereof
WO2023272470A1 (en) Page buffer circuits in three-dimensional memory devices
US20220028466A1 (en) Memory device and a memory system including the same
WO2022247775A1 (zh) 存储器及其擦除验证方法、操作方法、存储器系统
KR20210069262A (ko) 메모리 장치 및 그것의 동작 방법
US11538535B2 (en) Apparatus for rapid data destruction
WO2023272471A1 (en) Page buffer circuits in three-dimensional memory devices
CN113421601B (zh) 闪存存储器的操作方法以及闪存存储器
US20240013842A1 (en) Memory and its erase verification method, operation method, and a memory system
US11966608B2 (en) Memory controller with improved data reliability and memory system including the same
US11966625B2 (en) Memory device and operating method for setting and repairing data errors
US20240126478A1 (en) Memory systems and operation methods thereof, memory controllers and memories
US20240046980A1 (en) Systems, methods and media of optimization of temporary read errors in 3d nand memory devices
US11615835B2 (en) Memory device
WO2022204930A1 (en) Asynchronous multi-plane independent scheme dynamic analog resource sharing in three-dimensional memory devices
WO2022256956A1 (en) Methods of reducing program disturb by array source coupling in 3d nand memory devices
CN115206386A (zh) 存储器的操作方法、存储器、存储器系统及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22810500

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22810500

Country of ref document: EP

Kind code of ref document: A1