WO2022247150A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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WO2022247150A1
WO2022247150A1 PCT/CN2021/128672 CN2021128672W WO2022247150A1 WO 2022247150 A1 WO2022247150 A1 WO 2022247150A1 CN 2021128672 W CN2021128672 W CN 2021128672W WO 2022247150 A1 WO2022247150 A1 WO 2022247150A1
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Prior art keywords
transistor
group
pole
gate
reset
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PCT/CN2021/128672
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English (en)
French (fr)
Inventor
王利忠
宁策
邸云萍
童彬彬
徐成福
薛大鹏
董水浪
姚念琦
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京东方科技集团股份有限公司
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Priority to EP21942714.3A priority Critical patent/EP4203040A1/en
Publication of WO2022247150A1 publication Critical patent/WO2022247150A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the number of transistors in the driving circuit is relatively large, resulting in a wider frame or a lower resolution of the display device.
  • a display substrate including: a substrate and a plurality of driving circuits arranged on the substrate, each of the driving circuits includes a first transistor group and a second transistor group, and the first transistor group Located on a side of the second transistor group away from the substrate;
  • Each of the first transistor group and the second transistor group includes at least one transistor, and the material of the active layer of each transistor in the first transistor group is an oxide semiconductor, and each of the second transistor group The material of the active layer of the transistor is polysilicon;
  • the area enclosed by the orthographic projection of each transistor in the first transistor group on the substrate is surrounded by the orthographic projection of each transistor in the second transistor group on the substrate within the area.
  • the first transistor group includes a first transistor and a second transistor
  • the second transistor group includes a third transistor
  • the third transistor is a Any transistor other than the transistor and the second transistor
  • the drive circuit further includes a storage capacitor, and the second pole of the first transistor and the second transistor are both connected to the first end of the storage capacitor.
  • the gate of the third transistor is also connected to the first end of the storage capacitor
  • the orthographic projection of the gate of the first transistor and/or the gate of the second transistor on the substrate is located within the orthographic projection of the gate of the third transistor on the substrate.
  • the first transistor and the second transistor are arranged in the same layer, and both the first transistor and the second transistor are separated from the third transistor by a first buffer layer.
  • the second transistor is located on a side of the first transistor away from the third transistor;
  • a second buffer layer is provided between the first transistor and the third transistor, and a third buffer layer is provided between the first transistor and the second transistor.
  • the first transistor is located on a side of the second transistor away from the third transistor;
  • a fourth buffer layer is provided between the second transistor and the third transistor, and a fifth buffer layer is provided between the second transistor and the first transistor.
  • a flat layer is provided between the first transistor group and the second transistor group, and the flat layer covers each transistor in the second transistor group.
  • the material of the planar layer is organosiloxane, and the thickness of the planar layer is 0.5 ⁇ m to 2 ⁇ m.
  • the driving circuit is a pixel driving circuit arranged in the display area of the display substrate and used to drive the light emitting device to emit light;
  • the first transistor is a first reset transistor
  • the second transistor is a compensation transistor
  • the third transistor is a drive transistor
  • the gate of the first reset transistor is connected to the first reset signal line, the first pole of the first reset transistor is connected to the initialization signal line, and the second pole of the first reset transistor is connected to the storage capacitor The first end of the connection;
  • the gate of the compensation transistor is connected to the first gate line, the first pole of the compensation transistor is connected to the second pole of the driving transistor, the second pole of the compensation transistor is connected to the first terminal of the storage capacitor connect;
  • the gate of the driving transistor is connected to the first end of the storage capacitor.
  • the second transistor group further includes a data write transistor, a first light emission control transistor, a second light emission control transistor, and a second reset transistor;
  • the gate of the data writing transistor is connected to the second gate line, the first pole of the data writing transistor is connected to the data line, the second pole of the data writing transistor is connected to the first pole of the driving transistor connect;
  • the gate of the first light emission control transistor is connected to the light emission control signal line, the first pole of the first light emission control transistor is connected to the first power signal line, and the second pole of the first light emission control transistor is connected to the light emission control signal line. a first pole connection of the drive transistor;
  • the gate of the second light emission control transistor is connected to the light emission control signal line, the first electrode of the second light emission control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor
  • the diode is connected to the first pole of the light emitting device
  • the gate of the second reset transistor is connected to the second gate line, the first pole of the second reset transistor is connected to the initialization signal line, and the second pole of the second reset transistor is connected to the light emitting device. first pole connection;
  • the second end of the storage capacitor is connected to the first power signal line.
  • the drive transistor, the data write transistor, the first light emission control transistor, the second light emission control transistor and the second reset transistor are all arranged in the same layer.
  • the driving circuit is a GOA circuit arranged in the non-display area of the display substrate;
  • the first transistor is a third reset transistor, the second transistor is an input transistor, and the third transistor is an output transistor;
  • the gate of the third reset transistor is connected to the second reset signal line, the first pole of the third reset transistor is connected to the second power signal line, and the second pole of the third reset transistor is connected to the The first end of the storage capacitor is connected;
  • Both the gate and the first pole of the input transistor are connected to the input signal line, and the second pole of the input transistor is connected to the first end of the storage capacitor;
  • the gate of the output transistor is also connected to the first end of the storage capacitor, the first pole of the output transistor is connected to the clock signal line, and the second pole of the output transistor is connected to the output signal line,
  • the second end of the storage capacitor is also connected to the output signal line.
  • the second transistor group further includes a fourth reset transistor
  • the gate of the fourth reset transistor is connected to the second reset signal line, the first pole of the fourth reset transistor is connected to the second power signal line, and the second pole of the fourth reset transistor is connected to the second power supply signal line.
  • the output signal line is connected.
  • the output transistor and the fourth reset transistor are arranged on the same layer.
  • a method for manufacturing a display substrate including:
  • both the first transistor group and the second transistor group include at least one transistor, and the material of the active layer of each transistor in the first transistor group is an oxide semiconductor, and in the second transistor group The material of the active layer of each transistor is polysilicon;
  • the area enclosed by the orthographic projection of each transistor in the first transistor group on the substrate overlaps with the area enclosed by the orthographic projection of each transistor in the second transistor group on the substrate area.
  • the method further includes:
  • a flat layer is formed covering each transistor in the second transistor group.
  • a display device including the above-mentioned display substrate.
  • FIG. 1 shows a schematic structural view of a display substrate according to an embodiment of the present application
  • FIG. 2 shows a schematic diagram in which the driving circuit in the embodiment of the present application is a pixel driving circuit
  • FIG. 3 shows a schematic diagram in which the driving circuit in the embodiment of the present application is a GOA circuit
  • FIG. 4 shows a schematic diagram of the gate projection relationship of the first transistor, the second transistor, and the third transistor in the embodiment of the present application
  • FIG. 5 shows a working timing diagram corresponding to the pixel driving circuit shown in FIG. 2;
  • FIG. 6 shows a working sequence diagram corresponding to the GOA circuit shown in FIG. 3;
  • FIG. 7 shows a flow chart of a method for manufacturing a display substrate according to an embodiment of the present application.
  • FIG. 1 it shows a schematic structural diagram of a display substrate according to an embodiment of the present application.
  • FIG. 2 shows a schematic diagram of a pixel driving circuit in which the driving circuit in the embodiment of the present application is used.
  • FIG. 3 shows a schematic diagram of a pixel driving circuit in the embodiment of the present application. Schematic diagram of the driving circuit for the GOA circuit.
  • the embodiment of the present application discloses a display substrate, including: a substrate 10 and a plurality of driving circuits arranged on the substrate 10, each driving circuit includes a first transistor group 20 and a second transistor group 30, and the first transistor group 20 is located at The second transistor group 30 is away from the side of the substrate 10; the first transistor group 20 and the second transistor group 30 each include at least one transistor, and the material of the active layer of each transistor in the first transistor group 20 is an oxide semiconductor, The material of the active layer of each transistor in the second transistor group 30 is polysilicon; Wherein, the area enclosed by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 is the same as that in the second transistor group 30 The areas enclosed by the orthographic projections of the respective transistors on the substrate 10 have overlapping areas.
  • the substrate 10 may be a rigid substrate, such as a glass substrate, or the substrate 10 may be a flexible substrate, such as a PI (Polyimide, polyimide) substrate.
  • PI Polyimide, polyimide
  • a plurality of driving circuits are provided on one side of the substrate 10 .
  • the drive circuit may be a pixel drive circuit located in the display area of the display substrate and used to drive the light-emitting device to emit light. Therefore, each sub-pixel area in the display area is provided with a pixel drive circuit, which is controlled by the pixel drive circuit. The light-emitting device connected to it emits light, thereby realizing the display of the picture.
  • the pixel drive circuit controls the OLED light-emitting device to emit light; the drive circuit can also be located in the display
  • the GOA (GateDriver on Array, array substrate row driver) circuit in the non-display area of the substrate is used to provide corresponding signals to the signal lines in the display area, for example, in an LCD (Liquid Crystal Display, liquid crystal display) display device , the GOA circuit is used to provide a gate signal to a row of gate lines in the display area, so as to control the opening and closing of the thin film transistors connected to the row of gate lines.
  • each transistor in each drive circuit is divided into a first transistor group 20 and a second transistor group according to the material of the active layer.
  • Two transistor groups 30 Specifically, the transistors in the driving circuit that use oxide semiconductor as the active layer material are divided into the first transistor group 20 , and the transistors in the driving circuit that use polysilicon as the active layer material are divided into the second transistor group 30 .
  • the active layer material of each transistor in the first transistor group 20 is an oxide semiconductor
  • the oxide semiconductor can be IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), wherein the atoms of indium, gallium, and zinc The molar ratio is 1:1:1.
  • the atomic molar ratio of indium, gallium, and zinc in IGZO can also be in other ratios; or, the oxide semiconductor can also be other materials, such as ITGO (Indium Tin Gallium Oxide, indium gallium tin oxide), etc.
  • the first transistor group 20 is arranged on the side of the second transistor group 30 away from the substrate 10, that is, the second transistor group 30 is first arranged on the substrate 10, and then the second transistor group 30 is arranged on the side away from the substrate 10.
  • a transistor group 20, each transistor in the first transistor group 20 and each transistor in the second transistor group 30 are not arranged on the same layer, but are stacked on the substrate 10; and the first transistor group 20 and the second transistor Groups 30 each include at least one transistor.
  • the area enclosed by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 overlaps with the area enclosed by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10,
  • the area of the orthographic projection of each driving circuit on the substrate 10 is reduced, that is, the area occupied by each driving circuit is reduced.
  • the driving circuit is a GOA circuit
  • the frame width occupied by the same number of driving circuits is reduced, and the frame width of the display device can be reduced;
  • the driving circuit is For the pixel driving circuit, when the area occupied by each driving circuit is reduced, a larger number of pixel driving circuits can be arranged under the same area, that is, the number of sub-pixels arranged under the same area is larger, therefore, the resolution of the display device can be improved Rate.
  • the first transistor group 20 using oxide semiconductor as the active layer material needs to be arranged on the side away from the substrate 10 of the second transistor group 30 using polysilicon as the active layer material, so as to Ensure the stable performance of each transistor in the drive circuit.
  • the active layer of each transistor in the second transistor group 30 it is necessary to deposit a layer of amorphous silicon film first, and then pattern the amorphous silicon film to obtain a patterned amorphous silicon layer, and then , using a laser annealing process to crystallize the amorphous silicon layer, so as to convert the amorphous silicon layer into a polysilicon layer, so as to obtain the active layer of each transistor in the second transistor group 30 . If the second transistor group 30 is arranged on the side of the first transistor group 20 away from the substrate 10, since the material of the active layer of each transistor in the first transistor group 20 is an oxide semiconductor, and the thermal conductivity of the oxide semiconductor is relatively low.
  • the performance of each transistor in the driving circuit can be guaranteed to be stable.
  • the area enclosed by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 is located within the area enclosed by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10 .
  • the orthographic projection area of each driving circuit on the substrate 10 that is, the orthographic projection area of each transistor in the second transistor group 30 on the substrate 10, can further reduce the area occupied by each driving circuit, To further increase the frame width of the display device, or further increase the resolution of the display device.
  • the first transistor group 20 includes a first transistor T1 and a second transistor T2
  • the second transistor group 30 includes a third transistor T3, and the third transistor T3 is the driving circuit except the first transistor T3.
  • the drive circuit also includes a storage capacitor Cst, and the second pole 152 of the first transistor T1 and the second pole 252 of the second transistor T2 are all connected to the first terminal of the storage capacitor Cst connect.
  • the leakage current of a transistor using an oxide semiconductor as an active layer material is smaller than that of a transistor using polysilicon as an active layer material, in the driving circuit, for the first transistor T1 and the second transistor connected to the storage capacitor Cst
  • the second transistor T2 whose active layer is selected from an oxide semiconductor, can correspondingly prevent the storage capacitor Cst from leaking to the first transistor T1 and the second transistor T2, so that the voltage stability of the storage capacitor Cst is better, even at a low refresh rate, The voltage of the storage capacitor Cst is also more stable, so that the problem of screen flickering can be prevented even at a low refresh rate, and the required power consumption is also lower.
  • the gate 33 of the third transistor T3 is also connected to the first end of the storage capacitor Cst; the orthographic projection of the gate 13 of the first transistor T1 and/or the gate 23 of the second transistor T2 on the substrate 10 is located at the first end of the storage capacitor Cst.
  • the gate 33 of the three-transistor T3 is in an orthographic projection on the substrate 10 .
  • the first end of the storage capacitor Cst is actually the first pole plate of the storage capacitor Cst, and the first pole plate is a bulk electrode whose orthographic shape on the substrate 10 is rectangular.
  • the third transistor T3 The gate 33 actually refers to the first plate of the storage capacitor Cst.
  • the gate 33 of the third transistor T3 has a larger area, if the orthographic projection of the gate 13 of the first transistor T1 on the substrate 10 is set to be located at the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10 In this way, the first transistor T1 can form a double-gate structure, thereby improving the stability of the first transistor T1; correspondingly, if the orthographic projection of the gate 23 of the second transistor T2 on the substrate 10 is set to be located at In the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10 , the second transistor T2 can form a structure similar to double gates, thereby improving the stability of the second transistor T2 .
  • the orthographic projections of the gate 13 of the first transistor T1 and the gate 23 of the second transistor T2 on the substrate 10 are located within the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10, so that Can improve the stability of the first transistor T1 and the second transistor T2
  • FIG. 4 shows the corresponding projection relationship when the driving circuit is a pixel driving circuit , at this time, the gate 13 of the first transistor T1 is connected to the first reset signal line Reset1, and the gate 13 of the first transistor T1 is actually the active gate of the first transistor T1 in the first reset signal line Reset1.
  • layer 11 where there is an overlapping region; the gate 23 of the second transistor T2 is connected to the first gate line Gate1, and the gate 23 of the second transistor T2 is actually connected to the second transistor T2 in the first gate line Gate1.
  • the active layer 21 has overlapping regions.
  • the gate projection relationship of the first transistor T1, the second transistor T2 and the third transistor T3 is similar to that in FIG.
  • the reset signal line Reset2 is connected, and the gate 23 of the second transistor T2 is connected to the input signal line Input.
  • the active layer materials of other transistors can also be replaced with oxide semiconductors, and there will be Transistors whose source layer material is an oxide semiconductor are divided into the first transistor group 20, which is not limited to only dividing the first transistor T1 and the second transistor T2 into the first transistor group 20, and dividing other transistors into the second transistor group. Group 30.
  • each transistor in the first transistor group 20 can be in one-to-one correspondence with each transistor in the second transistor group 30, that is, one transistor in the first transistor group 20 and one transistor in the second transistor group 30 are on the substrate 10, there is an overlapping area, and another transistor in the first transistor group 20 and another transistor in the second transistor group 30 also have an overlapping area on the substrate 10; or, the first A plurality of transistors in the transistor group 20 corresponds to a transistor in the second transistor group 30, so that the orthographic projection of the plurality of transistors in the first transistor group 20 on the substrate 10 corresponds to a transistor in the second transistor group 30
  • the orthographic projections on the substrate 10 have areas of overlap.
  • the orthographic projection of the first transistor T1 in the first transistor group 20 on the substrate 10 is set to overlap with the orthographic projection of the third transistor T3 in the second transistor group 30 on the substrate 10, and the first The orthographic projection of the second transistor T2 in the transistor group 20 on the substrate 10 overlaps with the orthographic projections of other transistors in the second transistor group 30 except the third transistor T3 on the substrate 10; or, the first The orthographic projections of the first transistor T1 and the second transistor T2 in the transistor group 20 on the substrate 10 overlap with the orthographic projections of the third transistor T3 in the second transistor group 30 on the substrate 10 .
  • the first transistor group 20 includes a first transistor T1 and a second transistor T2
  • the first transistor T1 and the second transistor T2 may also be arranged in the same layer or in different layers.
  • the first transistor T1 and the second transistor T2 are arranged in the same layer, and both the first transistor T1 and the second transistor T2 are separated from the third transistor T3 by the first buffer layer 41 .
  • the first transistor T1 includes a first active layer 11, a first gate insulating layer 12, a first gate 13, a first interlayer dielectric layer 14 and
  • the first source and drain electrodes, the first source and drain electrodes include a first source 151 and a first drain 152, and both the first source 151 and the first drain 152 pass through the first interlayer dielectric layer 14 and the first gate
  • the via holes in the insulating layer 12 are connected to the first active layer 11 .
  • the first active layer 11 refers to the active layer of the first transistor T1
  • the first gate 13 refers to the gate of the first transistor T1
  • one of the first source 151 and the first drain 152 One refers to the first pole of the first transistor T1
  • the other refers to the second pole of the first transistor T1.
  • the second transistor T2 includes a second active layer 21, a first gate insulating layer 12, a second gate 23, a first interlayer dielectric layer 14 and a second
  • the source-drain electrodes, the second source-drain electrodes include a second source electrode 251 and a second drain electrode 252, and both the second source electrode 251 and the second drain electrode 252 pass through the first interlayer dielectric layer 14 and the first gate insulating layer 12 is connected to the second active layer 21.
  • the second active layer 21 refers to the active layer of the second transistor T2
  • the second gate 23 refers to the gate of the second transistor T2
  • one of the second source 251 and the second drain 252 One refers to the first pole of the second transistor T2, and the other refers to the second pole of the second transistor T2.
  • first active layer 11 and the second active layer 21 are arranged in the same layer
  • first gate 13 and the second gate 23 are arranged in the same layer
  • first source-drain electrodes and the second source-drain electrodes are also arranged in the same layer.
  • the third transistor T3 includes a third active layer 31, a third gate insulating layer 32, a third gate 33, a third interlayer dielectric layer 34 and a third Three source-drain electrodes
  • the third source-drain electrode includes a third source electrode 351 and a third drain electrode 352
  • the third source electrode 351 and the third drain electrode 352 pass through the third interlayer dielectric layer 34 and the third gate insulation
  • the vias of layer 32 are connected to the third active layer 31 .
  • the third active layer 31 refers to the active layer of the third transistor T3
  • the third gate 33 refers to the gate of the third transistor T3
  • one of the third source 351 and the third drain 352 One refers to the first pole of the third transistor T3, and the other refers to the second pole of the third transistor T3.
  • both the first transistor T1 and the second transistor T2 are separated from the third transistor T3 by the first buffer layer 41, specifically, the first active layer 11 and the second active layer 21 are separated by the first buffer layer 41 and the third transistor T3.
  • the third source-drain electrodes of the third transistor T3 are spaced apart.
  • the first buffer layer 41 can be a single-layer silicon oxide film with a thickness of to
  • the first buffer layer 41 may also be a stacked silicon nitride film and a silicon oxide film, and the silicon oxide film is disposed on a side of the silicon nitride film away from the third transistor T3.
  • the material of the first active layer 11 and the second active layer 21 is an oxide semiconductor, and its thickness is to
  • the material of the first gate insulating layer 12 is silicon oxide, and its thick bottom is to
  • the material of the first grid 13 and the second grid 23 is Mo, Cu or other alloys, laminated metals, etc., and its thick bottom is to
  • the first interlayer dielectric layer 14 can be a single-layer silicon oxide film, or a laminated silicon nitride film and silicon oxide film, with a total thickness of to
  • the second transistor T2 is located on the side of the first transistor T1 away from the third transistor T3; a second buffer layer is provided between the first transistor T1 and the third transistor T3, and the first transistor T1 and the second transistor A third buffer layer is arranged between T2.
  • the third transistor T3, the first transistor T1 and the second transistor T2 are arranged in sequence, the third transistor T3 and the first transistor T1 are separated by the second buffer layer, and the first transistor T1 is separated from the second transistor T2 by the third buffer layer.
  • the material of the second buffer layer and the third buffer layer is a single-layer silicon oxide film, or stacked silicon nitride film and silicon oxide film, and its total thickness is to
  • the first transistor T1 includes a first active layer 11 , a first gate insulating layer 12 , a first gate 13 , a first interlayer dielectric layer 14 , and a first interlayer dielectric layer 14 arranged along a direction perpendicular to the substrate 10 and arranged in sequence away from the substrate 10 .
  • a source-drain electrode, the second transistor T2 includes a second active layer 21, a second gate insulating layer, a second gate 23, a second interlayer dielectric layer and the second source and drain electrodes.
  • the third source-drain electrode of the third transistor T3 is separated from the first active layer 11 of the first transistor T1 through the second buffer layer, and the first source-drain electrode of the first transistor T1 is separated from the first active layer 11 through the third buffer layer.
  • the second active layer 21 of the second transistor T2 is spaced apart.
  • the first transistor T1 is located on the side of the second transistor T2 away from the third transistor T3; a fourth buffer layer is arranged between the second transistor T2 and the third transistor T3, and the second transistor T2 and the first transistor A fifth buffer layer is arranged between T1.
  • the third transistor T3, the second transistor T2 and the first transistor T1 are arranged in sequence, the third transistor T3 and the second transistor T2 are separated by the fourth buffer layer, and the second transistor T2 is separated from the first transistor T1 by the fifth buffer layer.
  • the material of the fourth buffer layer and the fifth buffer layer is a single-layer silicon oxide film, or stacked silicon nitride film and silicon oxide film, the total thickness of which is to
  • the first transistor T1 includes a first active layer 11 , a first gate insulating layer 12 , a first gate 13 , a first interlayer dielectric layer 14 , and a first interlayer dielectric layer 14 arranged along a direction perpendicular to the substrate 10 and arranged in sequence away from the substrate 10 .
  • a source-drain electrode, the second transistor T2 includes a second active layer 21, a second gate insulating layer, a second gate 23, a second interlayer dielectric layer and the second source and drain electrodes.
  • the third source-drain electrode of the third transistor T3 is separated from the second active layer 21 of the second transistor T2 through the fourth buffer layer, and the second source-drain electrode of the second transistor T2 is separated from the second active layer 21 through the fifth buffer layer.
  • the first active layer 11 of the first transistor T1 is spaced apart.
  • a sixth buffer layer 42 is disposed between the substrate 10 and the second transistor group 30, and the material of the sixth buffer layer 42 is also a single-layer silicon oxide film, or a laminated silicon nitride film and silicon oxide film .
  • a flat layer 43 is disposed between the first transistor group 20 and the second transistor group 30 , and the flat layer 43 covers each transistor in the second transistor group 30 .
  • the material of the flat layer 43 is SOG (Siloxane organic, organosiloxane), and the thickness of the flat layer 43 is 0.5 ⁇ m to 2 ⁇ m, such as the thickness of the flat layer 43 can be 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m or 2 ⁇ m.
  • SOG Silicone organic, organosiloxane
  • a planar layer 43 covering each transistor in the second transistor group 30 is first formed, and organic siloxane is used as the material of the planar layer 43, so that the The structure in front of the first transistor group 20 is planarized, and the planarization effect is better than that of common organic materials.
  • each transistor in the first transistor group 20 will be caused by the interface
  • the unevenness leads to the increase of defect states. Therefore, in the embodiment of the present application, by using organosiloxane as the material of the planar layer 43, the structure before the fabrication of the first transistor group 20 is planarized, so that when the first transistor group 20 is subsequently fabricated on the planar layer 43, it is possible to avoid Each transistor in the first transistor group 20 has a problem of increased defect states due to uneven interfaces.
  • each transistor in the first transistor group 20 on the flat layer 43 after forming an active layer made of an oxide semiconductor, it is necessary to anneal the oxide semiconductor to reduce the defect states of the oxide semiconductor. , and its annealing temperature is as high as 350 °C. If a conventional organic material, such as resin, is used as the material of the planar layer 43 , it cannot withstand a high temperature above 350° C., which will cause problems in the planar layer 43 . In the embodiment of the present application, organosiloxane is used as the material of the planar layer 43. Since organosiloxane can form a material similar to silicon dioxide after curing, it can withstand high temperatures above 350° C.
  • the temperature when annealing the oxide semiconductor will not damage the planarization layer 43 using organosiloxane as the material, that is, the use of organosiloxane as the planarization layer 43
  • the material can ensure that the high-temperature annealing process of the active layer of each transistor in the first transistor group 20 is normally carried out, thereby ensuring the stability of the performance of each transistor in the first transistor group 20 .
  • the buffer layer can be the first buffer layer 41 , the second buffer layer or the fourth buffer layer, so as to separate the second transistor group 30 from the first transistor group 20 .
  • the drive circuit is a pixel drive circuit arranged in the display area of the display substrate and used to drive the light-emitting device to emit light
  • the first transistor group 20 is formed on the side of the second transistor group 30 away from the substrate 10
  • the material of the planarization film may be resin, and its thickness is 1 ⁇ m to 3 ⁇ m, and then exposure and development processes are used to form via holes penetrating the planarization film, and then A patterned anode is formed on the planarization film, and the anode is connected to the corresponding electrodes in the lower second transistor group 30 through the via holes penetrating the planarization film and other film layers, so as to obtain the final display substrate.
  • the drive circuit is a pixel drive circuit arranged in the display area of the display substrate and used to drive the light-emitting device to emit light; as shown in Figure 3, the first transistor T1 is a first reset transistor, and the second Transistor T2 is a compensation transistor, and the third transistor T3 is a drive transistor; the gate of the first reset transistor is connected to the first reset signal line Reset1, the first pole of the first reset transistor is connected to the initialization signal line Vinit, and the gate of the first reset transistor is connected to the initialization signal line Vinit.
  • the second pole is connected to the first end of the storage capacitor Cst; the gate of the compensation transistor is connected to the first gate line Gate1, the first pole of the compensation transistor is connected to the second pole of the driving transistor, and the second pole of the compensation transistor is connected to the storage capacitor
  • the first terminal of Cst is connected; the gate of the driving transistor is connected with the first terminal of the storage capacitor Cst.
  • the first reset transistor is used to conduct under the control of the first reset signal input from the first reset signal line Reset1, and transmit the initialization signal provided by the initialization signal line Vinit to the first end of the storage capacitor Cst and drive
  • the gate of the transistor is used to reset the storage capacitor Cst and the gate of the driving transistor;
  • the compensation transistor refers to the transistor for compensating the threshold voltage of the driving transistor, and the driving transistor refers to the transistor for driving the light emitting device to emit light.
  • the driving transistor Since the driving transistor needs to drive the light-emitting device to emit light, the driving transistor needs a higher carrier mobility.
  • the driving transistor By using polysilicon as the active layer material of the driving transistor, the driving transistor has a higher carrier mobility. Then the drive transistor is divided into the second transistor group 30, and the first reset transistor and the compensation transistor need to have a lower leakage current to prevent the leakage of the storage capacitor Cst. Therefore, an oxide semiconductor is used as an active part of the first reset transistor and the compensation transistor. Source layer material, so that the first reset transistor and the compensation transistor have lower leakage current, then the first reset transistor and the compensation transistor are divided into the first transistor group 20 .
  • the second transistor group also includes a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6 and a second reset transistor T7;
  • the gate of the data write transistor T4 is connected to the second gate line Gate2
  • the first pole of the data writing transistor T4 is connected to the data line Data
  • the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor
  • the gate of the first light emitting control transistor T5 is connected to the light emitting control signal line EM
  • the first pole of the first light emission control transistor T5 is connected to the first power signal line VDD
  • the second pole of the first light emission control transistor T5 is connected to the first pole of the drive transistor
  • the gate of the second light emission control transistor T6 is connected to the light emission control
  • the signal line EM is connected, the first pole of the second light emission control transistor T6 is connected with the second pole of the driving transistor, the second pole of the second light emission control transistor T6 is connected with the first pole of the light emitting device EL
  • the driving transistor, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6 and the second reset transistor T7 are all arranged in the same layer.
  • the active layers of the transistors in the second transistor group 30 are arranged in the same layer
  • the gates of the transistors in the second transistor group 30 are arranged in the same layer, and the source and drain electrodes of the transistors in the second transistor group 30 are also arranged in the same layer.
  • the first transistor group 20 in the pixel driving circuit only includes the first reset transistor and the compensation transistor, while the second transistor group 30 includes other transistors remaining in the driving circuit, that is, the second transistor group 30 includes driving transistors, data write The transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7.
  • the first reset transistor and the compensation transistor are all N-type transistors
  • the driving transistor, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7 are all P-type transistors
  • the first gate line Gate1 connected to the compensation transistor is not the same gate line as the second gate line Gate2 connected to the data writing transistor T4.
  • the first reset signal input by the first reset signal line Reset1 is a high-level signal, so that the first reset transistor is turned on, and the initialization signal input by the initialization signal line Vinit has an effect on the storage capacitor Cst. and the gate of the drive transistor are reset; at this time, since the first gate signal input by the first gate line Gate1 is a low-level signal, the second gate signal input by the second gate line Gate2 and the light emission control signal EM input
  • the light emission control signals are all high level signals, so that the compensation transistor, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are all turned off.
  • the first gate signal input by the first gate line Gate1 is a high-level signal
  • the second gate signal input by the second gate line Gate2 is a low-level signal, so that the compensation transistor and the data writing
  • the transistor T4 is turned on, and the data signal input by the data line Data charges the storage capacitor Cst through the data writing transistor T4, the driving transistor and the compensation transistor, and makes the gate voltage of the driving transistor Vdata+Vth, Vth refers to the driving transistor
  • the threshold voltage, Vdata refers to the voltage of the data signal.
  • the first reset transistor T1 and the first light emission control transistor T5 and the second light emission control transistor T6 are turned off; correspondingly, the second reset transistor T7 is also turned on, and the second reset transistor T7 resets the first pole of the light emitting device EL through the initialization signal input by the initialization signal line Vinit.
  • the light-emitting control signal input by the light-emitting control signal line EM is a low-level signal, so that the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and then the first light-emitting control transistor T5, the driving transistor and the second light-emitting control transistor T5 are turned on.
  • the second light emission control transistor T6 provides a driving current to the first pole of the light emitting device EL to drive the light emitting device EL to emit light, and the magnitude of the driving current is related to the voltage Vdd of the high level voltage signal provided by the first power signal line VDD and the data signal related to the voltage Vdata.
  • the second gate signal input by the second gate line Gate2 is high level signal, so that the first reset transistor, the compensation transistor, the data writing transistor T4 and the second reset transistor T7 are all turned off.
  • the driving circuit is a GOA circuit arranged in the non-display area of the display substrate; as shown in FIG. 3 , the first transistor T1 is a third reset transistor, and the second transistor T2 is an input transistor.
  • the third transistor T3 is an output transistor; the gate of the third reset transistor is connected to the second reset signal line Reset2, the first pole of the third reset transistor is connected to the second power signal line VGL, and the second pole of the third reset transistor is connected to the second power signal line VGL.
  • the first end of the storage capacitor Cst is connected; the gate and the first pole of the input transistor are connected to the input signal line Input, and the second pole of the input transistor is connected to the first end of the storage capacitor Cst; the gate of the output transistor is also connected to the storage
  • the first terminal of the capacitor Cst is connected, the first terminal of the output transistor is connected to the clock signal line CLK, the second terminal of the output transistor is connected to the output signal line Output, and the second terminal of the storage capacitor Cst is also connected to the output signal line Output.
  • the third reset transistor is used to reset the storage capacitor Cst
  • the input transistor is used to charge the storage capacitor Cst
  • the output transistor is used to output a corresponding signal to the output signal line Output under the action of the storage capacitor Cst
  • the output signal line Output is actually connected to the signal lines provided in the display area, and is used to provide corresponding signals to the signal lines in the display area.
  • the output signal line Output is connected to a row of gate lines, and is used to provide gate signals to the gate lines to control turning on and off of thin film transistors connected to the row of gate lines.
  • the second transistor group also includes a fourth reset transistor T8; the gate of the fourth reset transistor T8 is connected to the second reset signal line Reset2, the first pole of the fourth reset transistor T8 is connected to the second power signal line VGL, and the gate of the fourth reset transistor T8 is connected to the second power signal line VGL.
  • the second pole of the quad reset transistor T8 is connected to the output signal line Output.
  • the fourth reset transistor T8 is used to reset the output signal line Output.
  • the output transistor and the fourth reset transistor T8 are arranged on the same layer. That is to say, the active layers of the output transistor and the fourth reset transistor T8 are set on the same layer, the gates of the output transistor and the fourth reset transistor T8 are set on the same layer, and the source and drain electrodes of the output transistor and the fourth reset transistor T8 are also set on the same layer. set up.
  • the first transistor group 20 in the GOA circuit only includes the third reset transistor and the input transistor, while the second transistor group 30 includes the output transistor and the fourth reset transistor T8.
  • the third reset transistor, the input transistor, the output transistor and the fourth reset transistor T8 are all N-type transistors.
  • the input signal line Input inputs a high-level signal, so that the input transistor is turned on, so as to charge the storage capacitor Cst.
  • the output transistor is also turned on, but because the clock signal input by the clock signal line CLK is low level, what the output transistor outputs to the output signal line Output is a low level signal; and, because the second reset signal line Reset2 inputs The second reset signal is a low-level signal, so that the third reset transistor and the fourth reset transistor T8 are turned off.
  • the gate voltage of the output transistor is further pulled up, the output transistor is turned on, and the clock signal input by the clock signal line CLK is a high-level signal, then the output transistor sends to the output The signal line Output outputs a high-level signal; at this time, both the input signal line Input and the second reset signal line Reset2 input a low-level signal, so that the third reset transistor, the input transistor and the fourth reset transistor T8 are all turned off.
  • the second reset signal input by the second reset signal line Reset2 is a high-level signal, so that the third reset transistor and the fourth reset transistor T8 are turned on, and the third reset transistor pulls down the first end of the storage capacitor Cst
  • the fourth reset transistor T8 pulls down the voltage of the output signal line Output to reset the storage capacitor Cst and the output signal line Output respectively.
  • the GOA circuit is not limited to only including the above-mentioned third reset transistor, input transistor, output transistor and fourth reset transistor T8, it may also include transistors that control the potential of the pull-up node and/or the pull-down node, etc., According to actual needs, the transistors using oxide semiconductor as the active layer material are divided into the first transistor group 20, and the transistors using polysilicon as the active layer material are divided into the second transistor group 30, and the first transistor group 20 It is arranged on the side of the second transistor group 30 away from the substrate 10 .
  • the first transistor group using oxide semiconductor as the active layer material is arranged on the side away from the substrate of the second transistor group using polysilicon as the active layer material, and the first transistor group
  • the area enclosed by the orthographic projection of each transistor on the substrate overlaps with the area enclosed by the orthographic projection of each transistor in the second transistor group on the substrate, ensuring that the first transistor group and
  • the area occupied by the driving circuit can be reduced, so as to reduce the border width of the display device or improve the resolution of the display device.
  • FIG. 7 shows a flow chart of a method for manufacturing a display substrate according to an embodiment of the present application, which may specifically include the following steps:
  • Step 701 providing a substrate.
  • a substrate 10 is fabricated, and the substrate 10 may be a glass substrate or a PI substrate or the like.
  • Step 702 respectively forming a second transistor group corresponding to each driving circuit on the substrate.
  • each transistor in the second transistor group 30 corresponding to each driving circuit is respectively formed on the substrate 10 .
  • the second transistor group 30 includes at least one transistor, and the material of the active layer of each transistor in the second transistor group 30 is polysilicon.
  • Step 703 forming a first transistor group on a side of each second transistor group away from the substrate.
  • each transistor in the first transistor group 20 is formed on the side of each second transistor group 30 away from the substrate 10 .
  • the first transistor group 20 includes at least one transistor, and the material of the active layer of each transistor in the first transistor group 20 is an oxide semiconductor; and each transistor in the first transistor group 20 is on the substrate 10.
  • the area enclosed by the projection overlaps with the area enclosed by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10 , so as to improve the resolution of the display device or reduce the frame width.
  • the method further includes: forming a flat layer covering each transistor in the second transistor group.
  • a planar layer 43 covering each transistor in the second transistor group 30 is formed, and the material of the planar layer 43 is organic silicon oxane.
  • the organosiloxane is coated on the surface of the second transistor group 30 away from the substrate 10 by using a coating process, and then the organosiloxane is cured to obtain a planar layer 43 .
  • the first transistor group using oxide semiconductor as the active layer material is arranged on the side away from the substrate of the second transistor group using polysilicon as the active layer material, and the first transistor group
  • the area enclosed by the orthographic projection of each transistor on the substrate overlaps with the area enclosed by the orthographic projection of each transistor in the second transistor group on the substrate, ensuring that the first transistor group and
  • the area occupied by the driving circuit can be reduced, so as to reduce the border width of the display device or improve the resolution of the display device.
  • An embodiment of the present application also provides a display device, including the above-mentioned display substrate.
  • the display substrate can be used in LCD display devices, OLED display devices, Mini LED display devices, quantum dot LED display devices and other products to reduce the frame width of the display device or improve the resolution of the display device.
  • the above-mentioned display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

显示基板及其制作方法、显示装置，涉及显示技术领域。本申请通过将采用氧化物半导体作为有源层材料的第一晶体管组，设置在采用多晶硅作为有源层材料的第二晶体管组远离基底的一侧，且第一晶体管组中的各个晶体管在基底上的正投影所围成的区域，与第二晶体管组中的各个晶体管在基底上的正投影所围成的区域存在重合区域，在保证位于不同层的第一晶体管组和第二晶体管组的制作过程中，其包括的各个晶体管的性能稳定的同时，可减小驱动电路所占用的面积，以减小显示装置的边框宽度或者提高显示装置的分辨率。

Description

显示基板及其制作方法、显示装置
本申请要求在2021年05月24日提交中国专利局、申请号为202110564793.X、申请名称为“显示基板及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，人们对显示装置的边框宽度、分辨率等有了更高的要求，显示装置也逐渐向窄边框、高分辨率等方向发展。
但是，目前的显示装置中，驱动电路中的晶体管的个数较多，导致显示装置的边框较宽或者分辨率较低。
概述
本申请一些实施例提供了如下技术方案：
第一方面，提供了一种显示基板，包括：基底以及设置在所述基底上的多个驱动电路，每个所述驱动电路包括第一晶体管组和第二晶体管组，所述第一晶体管组位于所述第二晶体管组远离所述基底的一侧；
所述第一晶体管组和所述第二晶体管组均包括至少一个晶体管，所述第一晶体管组中的各个晶体管的有源层的材料均为氧化物半导体，所述第二晶体管组中的各个晶体管的有源层的材料均为多晶硅；
其中，所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，与所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域存在重合区域。
可选的，所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，位于所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域内。
可选的，所述第一晶体管组包括一个第一晶体管和一个第二晶体管， 所述第二晶体管组包括一个第三晶体管，且所述第三晶体管为所述驱动电路中除所述第一晶体管和所述第二晶体管外的任意一个晶体管；
所述驱动电路还包括存储电容，所述第一晶体管的第二极和所述第二晶体管的第二极均与所述存储电容的第一端连接。
可选的，所述第三晶体管的栅极也与所述存储电容的第一端连接；
其中，所述第一晶体管的栅极和/或所述第二晶体管的栅极在所述基底上的正投影，位于所述第三晶体管的栅极在所述基底上的正投影内。
可选的，所述第一晶体管和所述第二晶体管同层设置，且所述第一晶体管和所述第二晶体管均通过第一缓冲层与所述第三晶体管间隔。
可选的，所述第二晶体管位于所述第一晶体管远离所述第三晶体管的一侧；
其中，所述第一晶体管与所述第三晶体管之间设置有第二缓冲层，所述第一晶体管与所述第二晶体管之间设置有第三缓冲层。
可选的，所述第一晶体管位于所述第二晶体管远离所述第三晶体管的一侧；
其中，所述第二晶体管与所述第三晶体管之间设置有第四缓冲层，所述第二晶体管与所述第一晶体管之间设置有第五缓冲层。
可选的，所述第一晶体管组与所述第二晶体管组之间设置有平坦层，所述平坦层覆盖所述第二晶体管组中的各个晶体管。
可选的，所述平坦层的材料为有机硅氧烷，所述平坦层的厚度为0.5μm至2μm。
可选的，所述驱动电路为设置在所述显示基板的显示区内且用于驱动发光器件发光的像素驱动电路；
所述第一晶体管为第一复位晶体管，所述第二晶体管为补偿晶体管，所述第三晶体管为驱动晶体管；
其中，所述第一复位晶体管的栅极与第一复位信号线连接，所述第一复位晶体管的第一极与初始化信号线连接，所述第一复位晶体管的第二极与所述存储电容的第一端连接；
所述补偿晶体管的栅极与第一栅线连接，所述补偿晶体管的第一极与 所述驱动晶体管的第二极连接，所述补偿晶体管的第二极与所述存储电容的第一端连接；
所述驱动晶体管的栅极与所述存储电容的第一端连接。
可选的，所述第二晶体管组还包括数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管和第二复位晶体管；
所述数据写入晶体管的栅极与第二栅线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极连接；
所述第一发光控制晶体管的栅极与发光控制信号线连接，所述第一发光控制晶体管的第一极与第一电源信号线连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；
所述第二发光控制晶体管的栅极与所述发光控制信号线连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光器件的第一极连接；
所述第二复位晶体管的栅极与所述第二栅线连接，所述第二复位晶体管的第一极与所述初始化信号线连接，所述第二复位晶体管的第二极与发光器件的第一极连接；
所述存储电容的第二端与所述第一电源信号线连接。
可选的，所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管和所述第二复位晶体管均同层设置。
可选的，所述驱动电路为设置在所述显示基板的非显示区内的GOA电路；
所述第一晶体管为第三复位晶体管，所述第二晶体管为输入晶体管，所述第三晶体管为输出晶体管；
其中，所述第三复位晶体管的栅极与第二复位信号线连接，所述第三复位晶体管的第一极与第二电源信号线连接，所述第三复位晶体管的第二极与所述存储电容的第一端连接；
所述输入晶体管的栅极和第一极均与输入信号线连接，所述输入晶体管的第二极与所述存储电容的第一端连接；
所述输出晶体管的栅极也与所述存储电容的第一端连接，所述输出晶体管的第一极与时钟信号线连接，所述输出晶体管的第二极与输出信号线连接，
所述存储电容的第二端还与所述输出信号线连接。
可选的，所述第二晶体管组还包括第四复位晶体管；
所述第四复位晶体管的栅极与所述第二复位信号线连接，所述第四复位晶体管的第一极与所述第二电源信号线连接，所述第四复位晶体管的第二极与所述输出信号线连接。
可选的，所述输出晶体管和所述第四复位晶体管同层设置。
第二方面，提供了一种显示基板的制作方法，包括：
提供一基底；
在所述基底上分别形成每个驱动电路对应的第二晶体管组；
在每个所述第二晶体管组远离所述基底的一侧形成第一晶体管组；
其中，所述第一晶体管组和所述第二晶体管组均包括至少一个晶体管，所述第一晶体管组中的各个晶体管的有源层的材料均为氧化物半导体，所述第二晶体管组中的各个晶体管的有源层的材料均为多晶硅；
所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，与所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域存在重合区域。
可选的，在所述基底上分别形成每个驱动电路对应的第二晶体管组的步骤之后，还包括：
形成覆盖所述第二晶体管组中的各个晶体管的平坦层。
第三方面，提供了一种显示装置，包括上述的显示基板。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本申请实施例的一种显示基板的结构示意图；
图2示出了本申请实施例中的驱动电路为像素驱动电路的示意图；
图3示出了本申请实施例中的驱动电路为GOA电路的示意图；
图4示出了本申请实施例的第一晶体管、第二晶体管和第三晶体管的栅极投影关系示意图；
图5示出了图2所示的像素驱动电路对应的工作时序图；
图6示出了图3所示的GOA电路对应的工作时序图；
图7示出了本申请实施例的一种显示基板的制作方法的流程图。
具体实施例
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
参照图1，示出了本申请实施例的一种显示基板的结构示意图，图2示出了本申请实施例中的驱动电路为像素驱动电路的示意图，图3示出了本申请实施例中的驱动电路为GOA电路的示意图。
本申请实施例公开了一种显示基板，包括：基底10以及设置在基底10上的多个驱动电路，每个驱动电路包括第一晶体管组20和第二晶体管组30，第一晶体管组20位于第二晶体管组30远离基底10的一侧；第一晶体管组20和第二晶体管组30均包括至少一个晶体管，第一晶体管组20中的各个晶体管的有源层的材料均为氧化物半导体，第二晶体管组30中的各个晶体管的有源层的材料均为多晶硅；其中，第一晶体管组20中的各个晶体管在基底10上的正投影所围成的区域，与第二晶体管组30中的各个晶体管在基底10上的正投影所围成的区域存在重合区域。
在实际产品中，基底10可以为刚性基底，如玻璃基底等，基底10也可以为柔性基底，如PI(Polyimide，聚酰亚胺)基底等。
在基底10的一侧设置有多个驱动电路。其中，该驱动电路可以是位于 显示基板的显示区内且用于驱动发光器件发光的像素驱动电路，因此，显示区内的每个子像素区域内均设置有一个像素驱动电路，通过像素驱动电路控制与其连接的发光器件发光，从而实现画面的显示，例如，在OLED(OrganicLight-Emitting Diode，有机发光二极管)显示装置中，该像素驱动电路控制OLED发光器件进行发光；该驱动电路也可以是位于显示基板的非显示区内的GOA(GateDriver on Array，阵列基板行驱动)电路，其用于向显示区内的信号线提供相应的信号，例如，在LCD(Liquid Crystal Display，液晶显示器)显示装置中，GOA电路用于向显示区内设置的一行栅线提供栅极信号，以控制与该行栅线连接的薄膜晶体管的开启和关闭。
无论驱动电路是设置在显示区的像素驱动电路，还是设置在非显示区的GOA电路，将每个驱动电路中的各个晶体管都按照有源层的材料不同，划分为第一晶体管组20和第二晶体管组30。具体的，将驱动电路中采用氧化物半导体作为有源层材料的晶体管划分至第一晶体管组20，将驱动电路中采用多晶硅作为有源层材料的晶体管划分至第二晶体管组30。
其中，第一晶体管组20中的各个晶体管的有源层材料为氧化物半导体，该氧化物半导体可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，其中的铟、镓、锌的原子摩尔比为1:1:1，当然，IGZO中的铟、镓、锌的原子摩尔比还可以为其他比例关系；或者，该氧化物半导体还可以是其他材料，如ITGO(Indium Tin Gallium Oxide，铟镓锡氧化物)等。
并且，将第一晶体管组20设置在第二晶体管组30远离基底10的一侧，即在基底10上先设置第二晶体管组30，再在第二晶体管组30远离基底10的一侧设置第一晶体管组20，第一晶体管组20中的各个晶体管与第二晶体管组30中的各个晶体管不是同层设置，其是叠层设置在基底10上的；而第一晶体管组20和第二晶体管组30均包括至少一个晶体管。
此外，第一晶体管组20中的各个晶体管在基底10上的正投影所围成的区域，与第二晶体管组30中的各个晶体管在基底10上的正投影所围成的区域存在重合区域，使得每个驱动电路在基底10上的正投影面积减小，即减小每个驱动电路所占用的面积。若该驱动电路为GOA电路，当每个驱动电路所占用的面积减小时，则相同数量下的驱动电路所占用的边框宽度减小， 即可减小显示装置的边框宽度；若该驱动电路为像素驱动电路，当每个驱动电路所占用的面积减小时，相同面积下可设置更多数量的像素驱动电路，即相同面积下设置的子像素的数量更多，因此，可提高显示装置的分辨率。
需要说明的是，本申请实施例需要将采用氧化物半导体作为有源层材料的第一晶体管组20，设置在采用多晶硅作为有源层材料的第二晶体管组30远离基底10的一侧，以保证驱动电路中的各个晶体管的性能稳定。
在制作第二晶体管组30中的各个晶体管的有源层时，需要先沉积一层非晶硅薄膜，再对该非晶硅薄膜进行图案化处理，以得到图案化的非晶硅层，接着，采用激光退火工艺对非晶硅层进行晶化处理，从而将非晶硅层转换为多晶硅层，以得到第二晶体管组30中的各个晶体管的有源层。若将第二晶体管组30设置在第一晶体管组20远离基底10的一侧，由于第一晶体管组20中的各个晶体管的有源层的材料为氧化物半导体，而氧化物半导体的导热性能较好，因此，在采用激光退火工艺对第二晶体管组30中的非晶硅层进行晶化处理时，热量会朝向第一晶体管组20中的有源层方向进行传导，导致第二晶体管组30中的非晶硅层的结晶度不佳，进而导致第二晶体管组30中的各个晶体管的性能不稳定；并且，在第二晶体管组30的激光退火工艺中，激光也会对第一晶体管组20中的各个晶体管的性能产生较大的影响，从而导致第一晶体管组20中的各个晶体管也不稳定。
因此，本申请实施例通过将第一晶体管组20设置在第二晶体管组30远离基底10的一侧，可保证驱动电路中的各个晶体管的性能稳定。
可选的，第一晶体管组20中的各个晶体管在基底10上的正投影所围成的区域，位于第二晶体管组30中的各个晶体管在基底10上的正投影所围成的区域内。
此时，每个驱动电路在基底10上的正投影面积，也就是第二晶体管组30中的各个晶体管在基底10上的正投影面积，从而可进一步减小每个驱动电路所占用的面积，以进一步显示装置的边框宽度，或者进一步提高显示装置的分辨率。
如图1至图3所示，第一晶体管组20包括一个第一晶体管T1和一个第二晶体管T2，第二晶体管组30包括一个第三晶体管T3，且第三晶体管T3 为驱动电路中除第一晶体管T1和第二晶体管T2外的任意一个晶体管；驱动电路还包括存储电容Cst，第一晶体管T1的第二极152和第二晶体管T2的第二极252均与存储电容Cst的第一端连接。
由于采用氧化物半导体作为有源层材料的晶体管的漏电流，小于采用多晶硅作为有源层材料的晶体管的漏电流，因此，在驱动电路中，针对与存储电容Cst连接的第一晶体管T1和第二晶体管T2，其有源层选取氧化物半导体，可相应防止存储电容Cst向第一晶体管T1和第二晶体管T2进行漏电，使得存储电容Cst的电压稳定性更好，即使在低刷新频率下，存储电容Cst的电压也更稳定，从而在低刷新频率下也可以防止画面闪烁的问题，且所需的功耗也较低。
此外，第三晶体管T3的栅极33也与存储电容Cst的第一端连接；第一晶体管T1的栅极13和/或第二晶体管T2的栅极23在基底10上的正投影，位于第三晶体管T3的栅极33在基底10上的正投影内。
在实际产品中，存储电容Cst的第一端实际上是存储电容Cst的第一极板，第一极板是一个块状电极，其在基底10上的正投影形状为矩形，第三晶体管T3的栅极33实际上指的是存储电容Cst的第一极板。
由于第三晶体管T3的栅极33的面积较大，若将第一晶体管T1的栅极13在基底10上的正投影，设置成位于第三晶体管T3的栅极33在基底10上的正投影内，可使得第一晶体管T1形成类似双栅的结构，从而可提升第一晶体管T1的稳定性；相应的，若将第二晶体管T2的栅极23在基底10上的正投影，设置成位于第三晶体管T3的栅极33在基底10上的正投影内，可使得第二晶体管T2形成类似双栅的结构，从而可提升第二晶体管T2的稳定性。
如图4所示，第一晶体管T1的栅极13和第二晶体管T2的栅极23在基底10上的正投影，位于第三晶体管T3的栅极33在基底10上的正投影内，从而可提高第一晶体管T1和第二晶体管T2的稳定性
需要说明的是，11指的是第一晶体管T1的有源层，21指的是第二晶体管T2的有源层；并且，图4示出的是驱动电路为像素驱动电路时对应的投影关系，此时，第一晶体管T1的栅极13是与第一复位信号线Reset1连接 的，则第一晶体管T1的栅极13实际上是第一复位信号线Reset1中与第一晶体管T1的有源层11存在交叠区域的部位；第二晶体管T2的栅极23是与第一栅线Gate1连接的，则第二晶体管T2的栅极23实际上是第一栅线Gate1中与第二晶体管T2的有源层21存在交叠区域的部位。
当然，当驱动电路为GOA电路时，第一晶体管T1、第二晶体管T2和第三晶体管T3的栅极投影关系与图4类似，只是此时的第一晶体管T1的栅极13是与第二复位信号线Reset2连接的，第二晶体管T2的栅极23是与输入信号线Input连接的。
值得注意的是，在驱动电路中，除了将第一晶体管T1和第二晶体管T2划分在第一晶体管组20内，还可将其他晶体管的有源层材料也换成氧化物半导体，并将有源层材料为氧化物半导体的晶体管划分至第一晶体管组20内，其不局限于仅将第一晶体管T1和第二晶体管T2划分在第一晶体管组20，而将其他晶体管划分在第二晶体管组30。
此外，为了保证第一晶体管组20中的各个晶体管在基底10上的正投影所围成的区域，与第二晶体管组30中的各个晶体管在基底10上的正投影所围成的区域存在重合区域，可将第一晶体管组20中的各个晶体管与第二晶体管组30中的各个晶体管进行一一对应，即第一晶体管组20中的一个晶体管与第二晶体管组30中的一个晶体管在基底10上的正投影存在重合区域，而第一晶体管组20中的另一个晶体管与第二晶体管组30中的另一个晶体管在基底10上的正投影也存在重合区域；或者，也可以将第一晶体管组20中的多个晶体管与第二晶体管组30中的一个晶体管进行对应，使得第一晶体管组20中的多个晶体管在基底10上的正投影，与第二晶体管组30中的一个晶体管在基底10上的正投影存在重合区域。
例如，将第一晶体管组20中的第一晶体管T1在基底10上的正投影，设置成与第二晶体管组30中的第三晶体管T3在基底10上的正投影存在重合区域，而第一晶体管组20中的第二晶体管T2在基底10上的正投影，是与第二晶体管组30中的除第三晶体管T3外的其他晶体管在基底10上的正投影存在重合区域；或者，第一晶体管组20中的第一晶体管T1和第二晶体管T2在基底10上的正投影，与第二晶体管组30中的第三晶体管T3在基底 10上的正投影均存在重合区域。
而在实际产品中，当第一晶体管组20包括一个第一晶体管T1和一个第二晶体管T2时，第一晶体管T1和第二晶体管T2也可以是同层设置，也可以是异层设置。
一些实施例中，如图1所示，第一晶体管T1和第二晶体管T2同层设置，且第一晶体管T1和第二晶体管T2均通过第一缓冲层41与第三晶体管T3间隔。
此时，第一晶体管T1包括沿垂直于基底10方向上且依次远离基底10设置的第一有源层11、第一栅绝缘层12、第一栅极13、第一层间介质层14和第一源漏电极，第一源漏电极包括第一源极151和第一漏极152，且第一源极151和第一漏极152均通过贯穿第一层间介质层14和第一栅绝缘层12的过孔与第一有源层11连接。其中，第一有源层11指的是第一晶体管T1的有源层，第一栅极13指的是第一晶体管T1的栅极，第一源极151和第一漏极152中的一者指的是第一晶体管T1的第一极，另一者指的是第一晶体管T1的第二极。
而第二晶体管T2包括沿垂直于基底10方向上且依次远离基底10设置的第二有源层21、第一栅绝缘层12、第二栅极23、第一层间介质层14和第二源漏电极，第二源漏电极包括第二源极251和第二漏极252，且第二源极251和第二漏极252均通过贯穿第一层间介质层14和第一栅绝缘层12的过孔与第二有源层21连接。其中，第二有源层21指的是第二晶体管T2的有源层，第二栅极23指的是第二晶体管T2的栅极，第二源极251和第二漏极252中的一者指的是第二晶体管T2的第一极，另一者指的是第二晶体管T2的第二极。
并且，第一有源层11和第二有源层21同层设置，第一栅极13和第二栅极23同层设置，第一源漏电极和第二源漏电极也同层设置。
另外，第三晶体管T3包括沿垂直于基底10方向上且依次远离基底10设置的第三有源层31、第三栅绝缘层32、第三栅极33、第三层间介质层34和第三源漏电极，第三源漏电极包括第三源极351和第三漏极352，且第三源极351和第三漏极352均通过贯穿第三层间介质层34和第三栅绝缘层32 的过孔与第三有源层31连接。其中，第三有源层31指的是第三晶体管T3的有源层，第三栅极33指的是第三晶体管T3的栅极，第三源极351和第三漏极352中的一者指的是第三晶体管T3的第一极，另一者指的是第三晶体管T3的第二极。
此时，第一晶体管T1和第二晶体管T2均通过第一缓冲层41与第三晶体管T3间隔，具体的，第一有源层11和第二有源层21是通过第一缓冲层41与第三晶体管T3的第三源漏电极间隔的。
第一缓冲层41可以为单层的氧化硅薄膜，其厚度为
Figure PCTCN2021128672-appb-000001
至
Figure PCTCN2021128672-appb-000002
第一缓冲层41也可以为叠层的氮化硅薄膜和氧化硅薄膜，且氧化硅薄膜设置在氮化硅薄膜远离第三晶体管T3的一侧。
第一有源层11和第二有源层21的材料为氧化物半导体，其厚度为
Figure PCTCN2021128672-appb-000003
至
Figure PCTCN2021128672-appb-000004
第一栅绝缘层12的材料为氧化硅，其厚底为
Figure PCTCN2021128672-appb-000005
至
Figure PCTCN2021128672-appb-000006
第一栅极13和第二栅极23的材料为Mo、Cu或其他合金、叠层金属等，其厚底为
Figure PCTCN2021128672-appb-000007
至
Figure PCTCN2021128672-appb-000008
第一层间介质层14可以为单层的氧化硅薄膜，或者叠层的氮化硅薄膜和氧化硅薄膜，其总厚度为
Figure PCTCN2021128672-appb-000009
至
Figure PCTCN2021128672-appb-000010
另一些实施例中，第二晶体管T2位于第一晶体管T1远离第三晶体管T3的一侧；第一晶体管T1与第三晶体管T3之间设置有第二缓冲层，第一晶体管T1与第二晶体管T2之间设置有第三缓冲层。
此时，沿着远离基底10的方向上，依次设置的是第三晶体管T3、第一晶体管T1和第二晶体管T2，第三晶体管T3与第一晶体管T1通过第二缓冲层间隔，第一晶体管T1与第二晶体管T2通过第三缓冲层间隔。其中，第二缓冲层和第三缓冲层的材料为单层的氧化硅薄膜，或者，叠层的氮化硅薄膜和氧化硅薄膜，其总厚度为
Figure PCTCN2021128672-appb-000011
至
Figure PCTCN2021128672-appb-000012
并且，第一晶体管T1包括沿垂直于基底10方向上且依次远离基底10设置的第一有源层11、第一栅绝缘层12、第一栅极13、第一层间介质层14和第一源漏电极，第二晶体管T2包括沿垂直于基底10方向上且依次远离基底10设置的第二有源层21、第二栅绝缘层、第二栅极23、第二层间介质层和第二源漏电极。因此，第三晶体管T3的第三源漏电极是通过第二缓冲层与第一晶体管T1的第一有源层11间隔的，第一晶体管T1的第一源漏电极 是通过第三缓冲层与第二晶体管T2的第二有源层21间隔的。
再一些实施例中，第一晶体管T1位于第二晶体管T2远离第三晶体管T3的一侧；第二晶体管T2与第三晶体管T3之间设置有第四缓冲层，第二晶体管T2与第一晶体管T1之间设置有第五缓冲层。
此时，沿着远离基底10的方向上，依次设置的是第三晶体管T3、第二晶体管T2和第一晶体管T1，第三晶体管T3与第二晶体管T2通过第四缓冲层间隔，第二晶体管T2与第一晶体管T1通过第五缓冲层间隔。其中，第四缓冲层和第五缓冲层的材料为单层的氧化硅薄膜，或者，叠层的氮化硅薄膜和氧化硅薄膜，其总厚度为
Figure PCTCN2021128672-appb-000013
至
Figure PCTCN2021128672-appb-000014
并且，第一晶体管T1包括沿垂直于基底10方向上且依次远离基底10设置的第一有源层11、第一栅绝缘层12、第一栅极13、第一层间介质层14和第一源漏电极，第二晶体管T2包括沿垂直于基底10方向上且依次远离基底10设置的第二有源层21、第二栅绝缘层、第二栅极23、第二层间介质层和第二源漏电极。因此，第三晶体管T3的第三源漏电极是通过第四缓冲层与第二晶体管T2的第二有源层21间隔的，第二晶体管T2的第二源漏电极是通过第五缓冲层与第一晶体管T1的第一有源层11间隔的。
另外，在基底10与第二晶体管组30之间设置有第六缓冲层42，第六缓冲层42的材料也为单层的氧化硅薄膜，或者，叠层的氮化硅薄膜和氧化硅薄膜。
如图1所示，第一晶体管组20与第二晶体管组30之间设置有平坦层43，平坦层43覆盖第二晶体管组30中的各个晶体管。
其中，平坦层43的材料为SOG(Siloxane organic，有机硅氧烷)，平坦层43的厚度为0.5μm至2μm，如平坦层43的厚度可以为0.5μm、1μm、1.5μm或2μm等。
在基底10上制作得到第二晶体管组30中的各个晶体管之后，先形成覆盖第二晶体管组30中的各个晶体管的平坦层43，通过采用有机硅氧烷作为平坦层43的材料，使得在制作第一晶体管组20前的结构呈平坦化，且平坦化效果较一般的有机材料的平坦化效果更好。
由于在制作第二晶体管组30中的各个晶体管时，受到第二晶体管组30 中的各个晶体管的有源层材料的结晶影响，以及第二晶体管组30中的各个晶体管的源漏电极的图案化影响，会导致制作得到的第二晶体管组30的表面不平坦，若直接在不平坦的第二晶体管组30上制作第一晶体管组20时，会导致第一晶体管组20中的各个晶体管由于界面不平整而导致缺陷态的增加。因此，本申请实施例通过采用有机硅氧烷作为平坦层43的材料，使得制作第一晶体管组20前的结构呈平坦化，则后续在平坦层43上制作第一晶体管组20时，可避免第一晶体管组20中的各个晶体管由于界面不平整而导致缺陷态增加的问题。
另外，在平坦层43上制作第一晶体管组20中的各个晶体管时，在形成材料为氧化物半导体的有源层之后，需要对氧化物半导体进行退火处理，以减小氧化物半导体的缺陷态，其退火温度高达350℃。若采用常规的有机材料，如树脂等作为平坦层43的材料，其无法耐受350℃以上的高温，会导致平坦层43出现问题。而本申请实施例采用有机硅氧烷作为平坦层43的材料，由于有机硅氧烷在固化之后可形成类似二氧化硅的材料，可以耐受350℃以上的高温，因此，在制作第一晶体管组20中的各个晶体管的有源层时，对氧化物半导体进行退火处理时的温度不会损坏采用有机硅氧烷作为材料的平坦层43，也就是说，采用有机硅氧烷作为平坦层43的材料，可保证第一晶体管组20中的各个晶体管的有源层的高温退火工艺正常进行，从而保证第一晶体管组20中的各个晶体管的性能的稳定。
需要说明的是，在基底10上制作得到第二晶体管组30中的各个晶体管之后，先形成覆盖第二晶体管组30中的各个晶体管的平坦层43，然后，还需要在平坦层43远离基底10的一侧形成缓冲层，该缓冲层可以为第一缓冲层41、第二缓冲层或第四缓冲层，以间隔第二晶体管组30和第一晶体管组20。
此外，若该驱动电路为设置在显示基板的显示区内且用于驱动发光器件发光的像素驱动电路，在第二晶体管组30远离基底10的一侧形成第一晶体管组20之后，还需要在第一晶体管组20远离基底10的表面涂覆平坦化薄膜，该平坦化薄膜的材料可以为树脂，其厚度为1μm至3μm，然后采用曝光、显影工艺，形成贯穿平坦化薄膜的过孔，接着，在平坦化薄膜上形成 图案化的阳极，且阳极通过贯穿平坦化薄膜以及其他膜层的过孔，与下层的第二晶体管组30中相应的电极连接，以得到最终的显示基板。
一种可选的实施方式中，驱动电路为设置在显示基板的显示区内且用于驱动发光器件发光的像素驱动电路；如图3所示，第一晶体管T1为第一复位晶体管，第二晶体管T2为补偿晶体管，第三晶体管T3为驱动晶体管；第一复位晶体管的栅极与第一复位信号线Reset1连接，第一复位晶体管的第一极与初始化信号线Vinit连接，第一复位晶体管的第二极与存储电容Cst的第一端连接；补偿晶体管的栅极与第一栅线Gate1连接，补偿晶体管的第一极与驱动晶体管的第二极连接，补偿晶体管的第二极与存储电容Cst的第一端连接；驱动晶体管的栅极与存储电容Cst的第一端连接。
在实际产品中，第一复位晶体管用于在第一复位信号线Reset1输入的第一复位信号的控制下导通，将初始化信号线Vinit提供的初始化信号传输至存储电容Cst的第一端和驱动晶体管的栅极，以对存储电容Cst和驱动晶体管的栅极进行复位；补偿晶体管指的是对驱动晶体管的阈值电压进行补偿的晶体管，驱动晶体管指的是驱动发光器件进行发光的晶体管。
由于驱动晶体管需要驱动发光器件进行发光，因此，驱动晶体管需要较高的载流子迁移率，通过采用多晶硅作为驱动晶体管的有源层材料，以使得驱动晶体管具有较高的载流子迁移率，则驱动晶体管被划分至第二晶体管组30，而第一复位晶体管和补偿晶体管需要具有较低的漏电流以防止存储电容Cst漏电，因此，采用氧化物半导体作为第一复位晶体管和补偿晶体管的有源层材料，以使得第一复位晶体管和补偿晶体管具有较低的漏电流，则第一复位晶体管和补偿晶体管被划分至第一晶体管组20。
此外，第二晶体管组还包括数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7；数据写入晶体管T4的栅极与第二栅线Gate2连接，数据写入晶体管T4的第一极与数据线Data连接，数据写入晶体管T4的第二极与驱动晶体管的第一极连接；第一发光控制晶体管T5的栅极与发光控制信号线EM连接，第一发光控制晶体管T5的第一极与第一电源信号线VDD连接，第一发光控制晶体管T5的第二极与驱动晶体管的第一极连接；第二发光控制晶体管T6的栅极与发光控制信号 线EM连接，第二发光控制晶体管T6的第一极与驱动晶体管的第二极连接，第二发光控制晶体管T6的第二极与发光器件EL的第一极连接；第二复位晶体管T7的栅极与第二栅线Gate2连接，第二复位晶体管T7的第一极与初始化信号线Vinit连接，第二复位晶体管T7的第二极与发光器件EL的第一极连接；存储电容Cst的第二端与第一电源信号线VDD连接；而发光器件EL的第二极与第三电源信号线VSS连接。
可选的，驱动晶体管、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均同层设置。
也就是说，针对驱动晶体管、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7，第二晶体管组30中的各个晶体管的有源层同层设置，第二晶体管组30中的各个晶体管的栅极同层设置，第二晶体管组30中的各个晶体管的源漏电极也同层设置。
此时，像素驱动电路中的第一晶体管组20仅包括第一复位晶体管和补偿晶体管，而第二晶体管组30包括驱动电路剩余的其他晶体管，即第二晶体管组30包括驱动晶体管、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7。
其中，第一复位晶体管和补偿晶体管均为N型晶体管，而驱动晶体管、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均为P型晶体管；并且，补偿晶体管所连接的第一栅线Gate1，与数据写入晶体管T4所连接的第二栅线Gate2不是同一条栅线。
如图5所示，在复位阶段t11，第一复位信号线Reset1输入的第一复位信号为高电平信号，使得第一复位晶体管导通，则初始化信号线Vinit输入的初始化信号对存储电容Cst和驱动晶体管的栅极进行复位；此时，由于第一栅线Gate1输入的第一栅极信号为低电平信号，第二栅线Gate2输入的第二栅极信号和发光控制信号EM输入的发光控制信号均为高电平信号，使得补偿晶体管、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均关闭。
在数据写入阶段t12，第一栅线Gate1输入的第一栅极信号为高电平信号，第二栅线Gate2输入的第二栅极信号为低电平信号，使得补偿晶体管和 数据写入晶体管T4导通，数据线Data输入的数据信号通过数据写入晶体管T4、驱动晶体管和补偿晶体管对存储电容Cst进行充电，并使得驱动晶体管的栅极电压为Vdata+Vth，Vth指的是驱动晶体管的阈值电压，Vdata指的是数据信号的电压。此时，由于第一复位信号线Reset1输入的第一复位信号为低电平，且发光控制信号EM输入的发光控制信号为高电平信号，使得第一复位晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6均关闭；相应的，第二复位晶体管T7也导通，第二复位晶体管T7通过初始化信号线Vinit输入的初始化信号对发光器件EL的第一极进行复位。
在发光阶段t13，发光控制信号线EM输入的发光控制信号为低电平信号，使得第一发光控制晶体管T5和第二发光控制晶体管T6打开，则通过第一发光控制晶体管T5、驱动晶体管和第二发光控制晶体管T6向发光器件EL的第一极提供驱动电流，以驱动发光器件EL发光，并且，驱动电流的大小与第一电源信号线VDD提供的高电平电压信号的电压Vdd和数据信号的电压Vdata相关。此时，由于第一复位信号线Reset1输入的第一复位信号和第一栅线Gate1输入的第一栅极信号均为低电平信号，第二栅线Gate2输入的第二栅极信号为高电平信号，使得第一复位晶体管、补偿晶体管、数据写入晶体管T4和第二复位晶体管T7均关闭。
另一种可选的实施方式中，驱动电路为设置在显示基板的非显示区内的GOA电路；如图3所示，第一晶体管T1为第三复位晶体管，第二晶体管T2为输入晶体管，第三晶体管T3为输出晶体管；第三复位晶体管的栅极与第二复位信号线Reset2连接，第三复位晶体管的第一极与第二电源信号线VGL连接，第三复位晶体管的第二极与存储电容Cst的第一端连接；输入晶体管的栅极和第一极均与输入信号线Input连接，输入晶体管的第二极与存储电容Cst的第一端连接；输出晶体管的栅极也与存储电容Cst的第一端连接，输出晶体管的第一极与时钟信号线CLK连接，输出晶体管的第二极与输出信号线Output连接，存储电容Cst的第二端还与输出信号线Output连接。
在实际产品中，第三复位晶体管用于对存储电容Cst进行复位，输入晶体管用于对存储电容Cst进行充电，输出晶体管用于在存储电容Cst的作用 下，向输出信号线Output输出相应的信号，该输出信号线Output实际上与显示区内设置的信号线连接，用于向显示区内的信号线提供相应的信号。例如，在LCD显示装置中，该输出信号线Output与一行栅线连接，用于向栅线提供栅极信号，以控制与该行栅线连接的薄膜晶体管的开启和关闭。
此外，第二晶体管组还包括第四复位晶体管T8；第四复位晶体管T8的栅极与第二复位信号线Reset2连接，第四复位晶体管T8的第一极与第二电源信号线VGL连接，第四复位晶体管T8的第二极与输出信号线Output连接。该第四复位晶体管T8用于对输出信号线Output进行复位。
可选的，输出晶体管和第四复位晶体管T8同层设置。也就是说，输出晶体管和第四复位晶体管T8的有源层同层设置，输出晶体管和第四复位晶体管T8的栅极同层设置，输出晶体管和第四复位晶体管T8的源漏电极也同层设置。
此时，GOA电路中的第一晶体管组20仅包括第三复位晶体管和输入晶体管，而第二晶体管组30包括输出晶体管和第四复位晶体管T8。
其中，第三复位晶体管、输入晶体管、输出晶体管和第四复位晶体管T8均为N型晶体管。
如图6所示，第一阶段t21，输入信号线Input输入高电平信号，使得输入晶体管导通，以对存储电容Cst进行充电。此时，输出晶体管也导通，但是由于时钟信号线CLK输入的时钟信号为低电平，则输出晶体管向输出信号线Output输出的是低电平信号；并且，由于第二复位信号线Reset2输入的第二复位信号为低电平信号，使得第三复位晶体管和第四复位晶体管T8关闭。
第二阶段t22，由于存储电容Cst的自举作用，输出晶体管的栅极电压被进一步拉高，输出晶体管导通，并且时钟信号线CLK输入的时钟信号为高电平信号，则输出晶体管向输出信号线Output输出的是高电平信号；此时，输入信号线Input和第二复位信号线Reset2均输入低电平信号，使得第三复位晶体管、输入晶体管和第四复位晶体管T8均关闭。
第三阶段t23，第二复位信号线Reset2输入的第二复位信号为高电平信号，使得第三复位晶体管和第四复位晶体管T8导通，则第三复位晶体管拉 低存储电容Cst第一端的电压，第四复位晶体管T8拉低输出信号线Output的电压，以分别对存储电容Cst和输出信号线Output进行复位。
需要说明的是，GOA电路不局限于仅包括上述的第三复位晶体管、输入晶体管、输出晶体管和第四复位晶体管T8，其还可以包括控制上拉节点和/或下拉节点的电位的晶体管等，按照实际需要，将采用氧化物半导体作为有源层材料的晶体管划分为第一晶体管组20，而将采用多晶硅作为有源层材料的晶体管划分为第二晶体管组30，并将第一晶体管组20设置在第二晶体管组30远离基底10的一侧。
在本申请实施例中，通过将采用氧化物半导体作为有源层材料的第一晶体管组，设置在采用多晶硅作为有源层材料的第二晶体管组远离基底的一侧，且第一晶体管组中的各个晶体管在基底上的正投影所围成的区域，与第二晶体管组中的各个晶体管在基底上的正投影所围成的区域存在重合区域，在保证位于不同层的第一晶体管组和第二晶体管组的制作过程中，其包括的各个晶体管的性能稳定的同时，可减小驱动电路所占用的面积，以减小显示装置的边框宽度或者提高显示装置的分辨率。
参照图7，示出了本申请实施例的一种显示基板的制作方法的流程图，具体可以包括如下步骤：
步骤701，提供一基底。
在本申请实施例中，首先，制作基底10，该基底10可以为玻璃基底或PI基底等。
步骤702，在所述基底上分别形成每个驱动电路对应的第二晶体管组。
在本申请实施例中，在基底10上分别形成每个驱动电路对应的第二晶体管组30中的各个晶体管。
其中，第二晶体管组30均包括至少一个晶体管，且第二晶体管组30中的各个晶体管的有源层的材料均为多晶硅。
步骤703，在每个所述第二晶体管组远离所述基底的一侧形成第一晶体管组。
在本申请实施例中，在制作得到每个驱动电路对应的第二晶体管组30之后，在每个第二晶体管组30远离基底10的一侧形成第一晶体管组20中 的各个晶体管。
其中，第一晶体管组20包括至少一个晶体管，第一晶体管组20中的各个晶体管的有源层的材料均为氧化物半导体；并且，第一晶体管组20中的各个晶体管在基底10上的正投影所围成的区域，与第二晶体管组30中的各个晶体管在基底10上的正投影所围成的区域存在重合区域，以提高显示装置的分辨率或降低边框宽度。
可选的，在步骤702之后，还包括：形成覆盖所述第二晶体管组中的各个晶体管的平坦层。
在本申请实施例中，在制作得到每个驱动电路对应的第二晶体管组30之后，首先，形成覆盖第二晶体管组30中的各个晶体管的平坦层43，该平坦层43的材料为有机硅氧烷。具体的，采用涂覆工艺将有机硅氧烷涂覆在第二晶体管组30远离基底10一侧的表面上，然后对有机硅氧烷进行固化处理，以得到平坦层43。
在本申请实施例中，通过将采用氧化物半导体作为有源层材料的第一晶体管组，设置在采用多晶硅作为有源层材料的第二晶体管组远离基底的一侧，且第一晶体管组中的各个晶体管在基底上的正投影所围成的区域，与第二晶体管组中的各个晶体管在基底上的正投影所围成的区域存在重合区域，在保证位于不同层的第一晶体管组和第二晶体管组的制作过程中，其包括的各个晶体管的性能稳定的同时，可减小驱动电路所占用的面积，以减小显示装置的边框宽度或者提高显示装置的分辨率。
本申请实施例还提供了一种显示装置，包括上述的显示基板。
在实际产品中，该显示基板可应用在LCD显示装置、OLED显示装置、Mini LED显示装置、量子点LED显示装置等产品中，以减小显示装置的边框宽度或者提高显示装置的分辨率。
在具体实施时，本申请实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
此外，关于显示装置中的显示基板的具体结构，可参照上述显示基板的描述，且效果与上述显示基板达到的效果类似，为避免重复，在此不再赘述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (18)

  1. 一种显示基板，包括：
    基底；以及
    多个驱动电路，设置在所述基底上，每个所述驱动电路包括：
    第一晶体管组；
    第二晶体管组，所述第一晶体管组位于所述第二晶体管组远离所述基底的一侧；
    所述第一晶体管组和所述第二晶体管组均包括至少一个晶体管，所述第一晶体管组中的各个晶体管的有源层的材料均为氧化物半导体，所述第二晶体管组中的各个晶体管的有源层的材料均为多晶硅；
    其中，所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，与所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域存在重合区域。
  2. 根据权利要求1所述的显示基板，其中，所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，位于所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域内。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一晶体管组包括一个第一晶体管和一个第二晶体管，所述第二晶体管组包括一个第三晶体管，且所述第三晶体管为所述驱动电路中除所述第一晶体管和所述第二晶体管外的任意一个晶体管；
    所述驱动电路还包括存储电容，所述第一晶体管的第二极和所述第二晶体管的第二极均与所述存储电容的第一端连接。
  4. 根据权利要求3所述的显示基板，其中，所述第三晶体管的栅极也与所述存储电容的第一端连接；
    其中，所述第一晶体管的栅极和/或所述第二晶体管的栅极在所述基底上的正投影，位于所述第三晶体管的栅极在所述基底上的正投影内。
  5. 根据权利要求3所述的显示基板，其中，所述第一晶体管和所述第二晶体管同层设置，且所述第一晶体管和所述第二晶体管均通过第一缓冲层与所述第三晶体管间隔。
  6. 根据权利要求3所述的显示基板，其中，所述第二晶体管位于所述第一晶体管远离所述第三晶体管的一侧；
    其中，所述第一晶体管与所述第三晶体管之间设置有第二缓冲层，所述第一晶体管与所述第二晶体管之间设置有第三缓冲层。
  7. 根据权利要求3所述的显示基板，其中，所述第一晶体管位于所述第二晶体管远离所述第三晶体管的一侧；
    其中，所述第二晶体管与所述第三晶体管之间设置有第四缓冲层，所述第二晶体管与所述第一晶体管之间设置有第五缓冲层。
  8. 根据权利要求1所述的显示基板，其中，所述第一晶体管组与所述第二晶体管组之间设置有平坦层，所述平坦层覆盖所述第二晶体管组中的各个晶体管。
  9. 根据权利要求8所述的显示基板，其中，所述平坦层的材料为有机硅氧烷，所述平坦层的厚度为0.5μm至2μm。
  10. 根据权利要求3所述的显示基板，其中，所述驱动电路为设置在所述显示基板的显示区内且用于驱动发光器件发光的像素驱动电路；
    所述第一晶体管为第一复位晶体管，所述第二晶体管为补偿晶体管，所述第三晶体管为驱动晶体管；
    其中，所述第一复位晶体管的栅极与第一复位信号线连接，所述第一复位晶体管的第一极与初始化信号线连接，所述第一复位晶体管的第二极与所述存储电容的第一端连接；
    所述补偿晶体管的栅极与第一栅线连接，所述补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述补偿晶体管的第二极与所述存储电容的第一端连接；
    所述驱动晶体管的栅极与所述存储电容的第一端连接。
  11. 根据权利要求10所述的显示基板，其中，所述第二晶体管组还包括数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管和第二复位晶体管；
    所述数据写入晶体管的栅极与第二栅线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一 极连接；
    所述第一发光控制晶体管的栅极与发光控制信号线连接，所述第一发光控制晶体管的第一极与第一电源信号线连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第二发光控制晶体管的栅极与所述发光控制信号线连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光器件的第一极连接；
    所述第二复位晶体管的栅极与所述第二栅线连接，所述第二复位晶体管的第一极与所述初始化信号线连接，所述第二复位晶体管的第二极与发光器件的第一极连接；
    所述存储电容的第二端与所述第一电源信号线连接。
  12. 根据权利要求11所述的显示基板，其中，所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管和所述第二复位晶体管均同层设置。
  13. 根据权利要求3所述的显示基板，其中，所述驱动电路为设置在所述显示基板的非显示区内的GOA电路；
    所述第一晶体管为第三复位晶体管，所述第二晶体管为输入晶体管，所述第三晶体管为输出晶体管；
    其中，所述第三复位晶体管的栅极与第二复位信号线连接，所述第三复位晶体管的第一极与第二电源信号线连接，所述第三复位晶体管的第二极与所述存储电容的第一端连接；
    所述输入晶体管的栅极和第一极均与输入信号线连接，所述输入晶体管的第二极与所述存储电容的第一端连接；
    所述输出晶体管的栅极也与所述存储电容的第一端连接，所述输出晶体管的第一极与时钟信号线连接，所述输出晶体管的第二极与输出信号线连接，
    所述存储电容的第二端还与所述输出信号线连接。
  14. 根据权利要求13所述的显示基板，其中，所述第二晶体管组还包括第四复位晶体管；
    所述第四复位晶体管的栅极与所述第二复位信号线连接，所述第四复位晶体管的第一极与所述第二电源信号线连接，所述第四复位晶体管的第二极与所述输出信号线连接。
  15. 根据权利要求14所述的显示基板，其中，所述输出晶体管和所述第四复位晶体管同层设置。
  16. 一种显示基板的制作方法，包括：
    提供一基底；
    在所述基底上分别形成每个驱动电路对应的第二晶体管组；
    在每个所述第二晶体管组远离所述基底的一侧形成第一晶体管组；
    其中，所述第一晶体管组和所述第二晶体管组均包括至少一个晶体管，所述第一晶体管组中的各个晶体管的有源层的材料均为氧化物半导体，所述第二晶体管组中的各个晶体管的有源层的材料均为多晶硅；
    所述第一晶体管组中的各个晶体管在所述基底上的正投影所围成的区域，与所述第二晶体管组中的各个晶体管在所述基底上的正投影所围成的区域存在重合区域。
  17. 根据权利要求16所述的方法，其中，在所述基底上分别形成每个驱动电路对应的第二晶体管组的步骤之后，还包括：
    形成覆盖所述第二晶体管组中的各个晶体管的平坦层。
  18. 一种显示装置，包括如权利要求1至15中任一项所述的显示基板。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012869A (ja) * 1998-06-24 2000-01-14 Sanyo Electric Co Ltd 薄膜トランジスタ及びそれを用いた表示装置
CN108598087A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置
CN108845702A (zh) * 2018-06-28 2018-11-20 武汉华星光电技术有限公司 触控显示面板及其测试方法、触控显示装置
CN110581142A (zh) * 2019-08-23 2019-12-17 武汉华星光电技术有限公司 阵列基板及其制造方法、显示面板
CN112510069A (zh) * 2020-11-27 2021-03-16 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN215342598U (zh) * 2021-05-24 2021-12-28 京东方科技集团股份有限公司 显示基板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3276664B1 (en) * 2016-07-29 2020-11-11 LG Display Co., Ltd. Thin film transistor device, method for manufacturing the same, and display device including the same
CN109935580A (zh) * 2017-12-19 2019-06-25 京东方科技集团股份有限公司 基板及其制作方法、电子装置
CN111489647B (zh) * 2020-04-26 2022-09-16 京东方科技集团股份有限公司 显示模组及其制造方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012869A (ja) * 1998-06-24 2000-01-14 Sanyo Electric Co Ltd 薄膜トランジスタ及びそれを用いた表示装置
CN108598087A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置
CN108845702A (zh) * 2018-06-28 2018-11-20 武汉华星光电技术有限公司 触控显示面板及其测试方法、触控显示装置
CN110581142A (zh) * 2019-08-23 2019-12-17 武汉华星光电技术有限公司 阵列基板及其制造方法、显示面板
CN112510069A (zh) * 2020-11-27 2021-03-16 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN215342598U (zh) * 2021-05-24 2021-12-28 京东方科技集团股份有限公司 显示基板及显示装置

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