WO2022247148A1 - 薄膜晶体管及其制备方法、阵列基板 - Google Patents

薄膜晶体管及其制备方法、阵列基板 Download PDF

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WO2022247148A1
WO2022247148A1 PCT/CN2021/128401 CN2021128401W WO2022247148A1 WO 2022247148 A1 WO2022247148 A1 WO 2022247148A1 CN 2021128401 W CN2021128401 W CN 2021128401W WO 2022247148 A1 WO2022247148 A1 WO 2022247148A1
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active layer
layer
gate
insulating layer
thin film
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PCT/CN2021/128401
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French (fr)
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黄杰
宁策
李正亮
胡合合
姚念琦
赵坤
周天民
雷利平
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京东方科技集团股份有限公司
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Definitions

  • Embodiments of the present disclosure relate to a thin film transistor, an array substrate, and a manufacturing method of the thin film transistor.
  • the thin film transistor can be divided into the top gate structure and the bottom gate structure, and the thin film transistor can be divided into the top contact structure according to the position of the source drain electrode layer relative to the active layer
  • the bottom contact structure that is, the thin film transistor includes four structures: bottom gate top contact, bottom gate bottom contact, top gate top contact and top gate bottom contact.
  • Thin film transistors include silicon-based thin film transistors, metal oxide thin film transistors, and organic thin film transistors. Silicon-based thin film transistors are widely used in display panels because of their good performance and large-area fabrication. With the development of display technology, the inherent disadvantages of silicon-based thin film transistors, such as low mobility and poor stability of amorphous silicon thin film transistors, poor uniformity and high cost of polysilicon thin film transistors, make it difficult for silicon-based thin film transistors to meet the needs of development. Although organic thin film transistors can effectively reduce costs, their performance is far from meeting the needs of display technology.
  • metal oxide thin film transistors Compared with silicon-based thin film transistors, metal oxide thin film transistors have obvious technical advantages, such as higher mobility, steeper subthreshold swing, smaller off-state leakage current, and better device performance consistency.
  • the process of the metal oxide semiconductor is simple, the process temperature is low, and the stability is good, and the metal oxide thin film transistor formed has a high transmittance for visible light, and the characteristics of the metal oxide thin film transistor device do not degrade significantly in a bent state.
  • At least one embodiment of the present disclosure provides a thin film transistor, which includes: a base substrate; a first active layer, a first insulating layer, and a second active layer sequentially stacked on the base substrate; wherein , the first active layer is in contact with the second active layer through a first via structure located in the first insulating layer, and the first active layer is not in contact with the second active layer The portions are spaced apart by the first insulating layer.
  • the thin film transistor provided in at least one embodiment of the present disclosure further includes a source-drain electrode layer, wherein the source-drain electrode layer is electrically connected to the first active layer and the second active layer.
  • the source-drain electrode layer is electrically connected to the second active layer through a second via structure, and the first via structure is in the substrate
  • the orthographic projection on the substrate and the orthographic projection of the second via structure on the base substrate at least partially overlap, and at least part of the source-drain electrode layer extends into the first via structure.
  • the thin film transistor provided in at least one embodiment of the present disclosure further includes a first gate and a second gate, wherein the first gate is on a side of the first active layer close to the base substrate. side, and a first gate insulating layer is provided between the first gate and the first active layer; the second gate is on the second active layer away from the base substrate One side, and a second gate insulating layer is disposed between the second gate and the second active layer.
  • an interlayer insulating layer is arranged on the side of the second gate away from the base substrate, and the source-drain electrode layer is arranged on the layer On the side of the interlayer insulating layer away from the base substrate, the second via structure sequentially passes through the interlayer insulating layer, the second gate insulating layer and part of the first insulating layer.
  • the thin film transistor provided in at least one embodiment of the present disclosure further includes a third active layer, wherein the third active layer is disposed on a side of the second gate away from the base substrate, so The interlayer insulating layer is disposed between the third active layer and the second gate, and the third active layer is electrically connected to the source-drain electrode layer.
  • the thin film transistor provided in at least one embodiment of the present disclosure further includes a gate, wherein the gate is between the first active layer and the second active layer.
  • a gate insulating layer is provided on a side of the gate far away from the first insulating layer, and the first via structure penetrates through the first insulating layer and the gate insulating layer.
  • a second insulating layer is provided between the second active layer and the source-drain electrode layer, and the second via hole structure penetrates the first Two insulating layers.
  • the source-drain electrode layer and the second gate are arranged on the same layer, and the side of the second gate close to the base substrate
  • An interlayer insulating layer is provided, and the second via structure sequentially penetrates through the interlayer insulating layer, the second gate insulating layer and part of the first insulating layer.
  • the first active layer includes a first sub-active layer and a second sub-active layer stacked, and/or the second active layer It includes a third sub-active layer and a fourth sub-active layer which are stacked.
  • At least one embodiment of the present disclosure further provides an array substrate including the thin film transistor described in any one of the above.
  • At least one embodiment of the present disclosure also provides a manufacturing method of a thin film transistor, the manufacturing method comprising: providing a base substrate; forming a first active layer on the base substrate; Applying a first insulating layer film to one side of the base substrate; patterning the first insulating layer film to form a first insulating layer with a first via hole structure; A second active layer is formed on one side of the base substrate, wherein the second active layer is in contact with the first active layer through the first via structure, and the first active layer is in contact with the first active layer. The uncontacted portion of the second active layer is separated by the first insulating layer.
  • the preparation method provided in at least one embodiment of the present disclosure further includes forming a source-drain electrode layer, wherein the source-drain electrode layer is electrically connected to the first active layer and the second active layer.
  • the source-drain electrode layer is electrically connected to the second active layer through a second via structure, and the first via structure is in the substrate
  • the orthographic projection on the substrate and the orthographic projection of the second via structure on the base substrate at least partially overlap, and at least part of the source-drain electrode layer extends into the first via structure.
  • the preparation method provided in at least one embodiment of the present disclosure further includes: forming a first gate on a side of the first active layer close to the base substrate; A first gate insulating layer is formed between the first active layers; a second gate is formed on a side of the second active layer away from the substrate; a second gate is formed between the second gate and the second A second gate insulating layer is formed between the active layers.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 8 is a block diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • 10A-10E are process diagrams of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • 12A-12K are process diagrams of a manufacturing method of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor.
  • a buffer layer 02, a bottom gate 03, a bottom gate insulating layer 04, an active layer 05, a top Gate insulating layer 06, top gate 07, insulating layer 08 and source 09a/drain 09b that is, the structure shown in Figure 1 is a double gate single active layer, and the structure shown in Figure 1 uses a bottom gate 03 and the top gate 07 act on an active layer 05 at the same time, so that the on-state current of the thin film transistor can be increased.
  • the structure shown in FIG. 1 also has the following defects: since only the bottom gate insulating layer 04, the top gate insulating layer 06 and the active layer 05 exist between the top gate 07 and the bottom gate 03 for isolation, on the one hand, when the top When the distance between the gate 07 and the bottom gate 03 is relatively close, it is easy to cause crosstalk between the electric field of the top gate 07 and the electric field of the bottom gate 03, thereby causing the stability of carriers in the active layer 05 to change. poor, the characteristic control of the thin film transistor becomes difficult. For example, the voltage of the structure of the thin film transistor shown in FIG.
  • the thin film transistor shown in FIG. 1 is susceptible to positive and negative shifts due to changes in the voltage of the top gate 07, thereby deteriorating the characteristics of the thin film transistor; on the other hand, the thin film transistor shown in FIG. 1 cannot Realize the double increase of the on-state current.
  • the structure shown in Figure 1 can only increase the on-state current by about 50%, and the thin-film transistor shown in Figure 1 can only increase the on-state current. When it is in the panel, it cannot meet the requirements of the display panel for on-state current and resolution.
  • the inventors of the present disclosure noticed that it is possible to design a thin film transistor having a plurality of active layers such that charges accumulate on both surfaces of each active layer, thereby multiplying the number of charges accumulated on the surfaces of the active layers Increased, and then doubled the on-state current of the thin film transistor.
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor provided by an embodiment of the present disclosure.
  • the active layer 104, the first insulating layer 105 and the second active layer 106 the first active layer 104 is in contact with the second active layer 106 through the first via structure 116 in the first insulating layer 105, the first A portion of the active layer 104 not in contact with the second active layer 106 is separated by the first insulating layer 105 .
  • the first active layer 104 is in contact with the second active layer 106 through the first via structure 116 to realize the electrical connection between the first active layer 104 and the second active layer 106; the first active layer 104 is separated from the second active layer 106 by the first insulating layer 105, which can make the surface of the first active layer 104 close to the base substrate 101 and the surface of the first active layer 104 close to the second active layer 104
  • the surfaces of the layers are all accumulated with charges, and the surface of the second active layer 106 close to the base substrate 101 and the surface of the second active layer 106 away from the base substrate 101 are all accumulated with charges, so that the active layer ( The amount of charges accumulated on the surface including the first active layer 104 and the second active layer 106) is multiplied, so that the on-state current can be doubled.
  • the first active layer 104 is in contact with the second active layer 106 through the first via structure 116 in the first insulating layer 105 to realize electrical connection.
  • the number of the first via structure 116 can be one or more.
  • there are two first via hole structures 116 the two first via hole structures 116 are spaced apart from each other, and the two first via hole structures 116 are close to the substrate.
  • the sum of the widths of one side of the substrate 101 is smaller than the maximum horizontal width of the first active layer 104 and smaller than the maximum horizontal width of the second active layer 106 .
  • each first via structure 116 close to the substrate 101 and the sidewall defining the first via structure 116 are covered with the second active layer 106, and each first via structure 116 Neither is filled by the second active layer 106 .
  • the orthographic projection of each first via hole structure 116 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101, and smaller than the orthographic projection of the second active layer 104 on the base substrate 101.
  • Orthographic projection of 106 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101, and smaller than the orthographic projection of the second active layer 104 on the base substrate 101.
  • the sum of the orthographic projections of the plurality of first via hole structures 116 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101 and smaller than the orthographic projection of the second active layer 106 on the base substrate 101
  • the embodiments of the present disclosure are not limited thereto, and the orthographic projection of each first via hole structure 116 on the base substrate 101 may also be greater than or equal to that of the first active layer 104 on the base substrate 101 orthographic projection of .
  • the materials of the first active layer 104 and the second active layer 106 can be the same or different.
  • the materials of the first active layer 104 and the second active layer 106 may both be silicon-based materials, or both be metal oxide semiconductor materials, or both be organic semiconductor materials.
  • the material of the first active layer 104 is one of silicon-based materials, metal oxide semiconductor materials and organic semiconductor materials, and the material of the second active layer 106 is two other materials different from the materials of the first active layer 104. one of the materials.
  • the metal oxide semiconductor materials include zinc oxide (ZnO), indium oxide (In 2 O 3 ), oxide Indium Zinc (IZO), Aluminum Doped Zinc Oxide (AZO), Boron Doped Zinc Oxide (BZO), Magnesium Doped Zinc Oxide (MZO), Zinc Tin Oxide (ZTO), Indium Gallium Zinc Oxide (IGZO), Indium Oxide n-type semiconductor materials such as tin zinc (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO) and tin oxide (SnO 2 ), as well as tin oxide (SnO) and Copper (Cu 2 O) and other p-type semiconductor materials.
  • the first active layer 104 and the second active layer 106 of metal oxide semiconductor materials may be formed by magnetron sputtering, reactive sputtering, ano
  • the material of the first active layer 104 and the second active layer 106 may also be silicon, germanium, silicon-germanium mixed material, and the like.
  • the first active layer 104 and the second active layer 106 of the above-mentioned semiconductor material may be formed by magnetron sputtering or spin coating.
  • the material of the first active layer 104 and the second active layer 106 can also be an organic semiconductor material
  • the organic semiconductor material includes pentacene, triphenylamine, fullerene, phthalocyanine, polythiophene, poly Aniline, polypyrrole, etc. can be used to form the above organic semiconductor materials by spin coating.
  • the thicknesses of the first active layer 104 and the second active layer 106 are respectively 5 nm ⁇ 200 nm.
  • the thickness of the first active layer 104 can be 50nm, 100nm, 150nm, or 200nm; the thickness of the second active layer 106 can be 50nm, 100nm, 150nm, or 200nm.
  • the base substrate 101 is formed of rigid material or flexible material.
  • the rigid material includes one of rigid glass and a silicon wafer.
  • the flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass.
  • the material of the first insulating layer 105 includes one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide and zirconium oxide.
  • the thickness of the first insulating layer 105 is 5 nm ⁇ 400 nm, such as 50 nm, 100 nm, 200 nm, 300 nm or 400 nm.
  • the TFT 100 further includes a source-drain electrode layer 110 , and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 .
  • the source-drain electrode layer 110 includes a source electrode 110 a and a drain electrode 110 b, both of which are electrically connected to the first active layer 104 and the second active layer 106 .
  • the form of the source-drain electrode layer 110 being electrically connected to the first active layer 104 and the second active layer 106 includes: the source-drain electrode layer 110 overlaps the first active layer 104, so that the source-drain electrode layer 110 It is electrically connected with the first active layer 104 and the second active layer 106; the source drain electrode layer 110 overlaps with the second active layer, so that the source drain electrode layer 110 is connected with the first active layer 104 and the second active layer The layer 106 is electrically connected; the source-drain electrode layer 110 is electrically connected to the first active layer 104 through the second via structure 113, so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 simultaneously. Connection: The source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113 so that the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 at the same time.
  • the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113 so that the source-drain electrode layer 110 is connected to the first active layer 104 and the second active layer 106.
  • the source layer 106 is electrically connected at the same time.
  • the orthographic projection of the first via structure 116 on the substrate 101 and the orthographic projection of the second via structure 113 on the substrate 101 at least partially overlap, and at least part of the source-drain electrode layer 110 extends to the first via hole Structure 116.
  • the width of the first via structure 116 close to the base substrate 101 is greater than the width of the second via structure 113 close to the base substrate 101, and the second via structure 113 close to the base substrate 101-
  • the side is sleeved in the first via hole structure 116 , so that the source-drain electrode layer 110 is electrically connected to the second active layer 106 more stably.
  • the material of the source-drain electrode layer 110 may include one or more combinations of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu). .
  • Mo molybdenum
  • Cr chromium
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source-drain electrode layer 110 is copper-based metal.
  • Copper metal has the characteristics of low resistivity and good conductivity, so it can increase the signal transmission rate of the source-drain electrode layer 110 (source electrode 110a, drain electrode 110b) and improve display quality.
  • the copper-based metal is a stable copper-based metal alloy such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi) or copper-zinc-nickel alloy (CuZnNi).
  • Cu copper
  • CuZn copper-zinc alloy
  • CuNi copper-nickel alloy
  • CuZnNi copper-zinc-nickel alloy
  • the thickness of the source-drain electrode layer 110 may be 200-400nm, for example, 200nm, 230nm, 250nm, 300nm, 350nm, 380nm and 400nm.
  • the source-drain electrode layer 110 is not limited to be formed on the side of the second active layer 106 away from the base substrate 101, and may also be formed on the side of the first active layer 104 close to the base substrate, or other positions , as long as the source-drain electrode layer 110 can be electrically connected to the first active layer 104 and the second active layer 106 at the same time.
  • the resistance is relatively large, and a dry etching process is used when forming the source-drain electrode layer 110, and a reducing gas is required to perform the dry etching process.
  • a reducing gas may be used first so that the part of the second active layer 106 exposed to the second via structure 113 is reduced to a metal element, Therefore, the resistivity of the second active layer 106 becomes smaller, and the overall resistance after the first active layer 104 and the second active layer 106 are electrically connected becomes smaller, that is, the first active layer 104 and the second active layer 106 can be reduced without adding new equipment and materials. Resistance when the first active layer 104 is connected to the second active layer 106 .
  • the thin film transistor 100 further includes a first gate 102 and a second gate 108, the first gate 102 is on the side of the first active layer 104 close to the base substrate 101, and A first gate insulating layer 103 is provided between the first gate 102 and the first active layer 104, the second gate 108 is on the side of the second active layer 106 away from the base substrate 101, and on the second A second gate insulating layer 107 is disposed between the gate 108 and the second active layer 106 .
  • the materials of the first grid 102 and the second grid 108 may respectively include molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, copper (Cu) and other metals One or more combinations.
  • the material of the first gate 102 and the second gate 108 may also include one of transparent conductive materials such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) and boron-doped zinc oxide (BZO), or Various combinations.
  • the first gate 102 and the second gate 108 can be a single-layer structure or a double-layer structure respectively.
  • the first grid 102 and the second grid 108 of the double-layer structure may be composite conductive layers composed of metal and transparent conductive material, respectively.
  • the thicknesses of the first grid 102 and the second grid 108 can be 50nm-300nm respectively, for example, the thickness of the first grid 102 can be 50nm, 100nm, 200nm or 300nm; The thickness can be 50nm, 100nm, 200nm or 300nm.
  • methods such as magnetron sputtering, electron beam evaporation, or thermal evaporation can be used to form the first grid of metal materials, and methods such as magnetron sputtering or optical coating can also be used to form the first grid of transparent conductive materials.
  • the materials of the first gate insulating layer 103 and the second gate insulating layer 107 can be silicon oxide (SiO 2 ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), a combination of one or more of tantalum oxide (Ta 2 O 5 ) and zirconium oxide (ZrO 2 ).
  • the thicknesses of the first gate insulating layer 103 and the second gate insulating layer 107 may be 5nm ⁇ 400nm respectively, for example, the thickness of the first gate insulating layer 103 may be 50nm, 100nm, 150nm, 200nm, 250nm or 300nm, The thickness of the second gate insulating layer 107 may be 50nm, 100nm, 150nm, 200nm, 250nm or 300nm.
  • oxide insulating materials such as silicon oxide (SiO 2 ) or silicon nitride (SiN x ) can be deposited by plasma enhanced chemical vapor deposition (PECVD) to form the first gate insulating layer 103 and the second gate insulating layer 107
  • PECVD plasma enhanced chemical vapor deposition
  • the first gate insulating layer 103 and the second gate insulating layer 107 may also be formed by methods such as spin-coating an organic insulating material.
  • an interlayer insulating layer 109 is disposed on the side of the second gate 108 away from the base substrate 101 , and the source-drain electrode layer 110 is disposed on the side of the interlayer insulating layer 109 far away from the base substrate 101 .
  • the second via structure 113 penetrates through the interlayer insulating layer 109 , the second gate insulating layer 107 and part of the first insulating layer 105 in sequence.
  • a first gate insulating layer 103, a first active layer 104, a first insulating layer 105, a second active layer 106, and a second gate insulating layer 107 are provided between the first gate 102 and the second gate 108. , so that the distance between the first grid 102 and the second grid 108 is larger, and the number of insulating film layers is larger, so that the electric field of the first grid 102 and the second grid The electric fields of 108 are not prone to crosstalk.
  • the double gate and double active layer structure in Figure 2 doubles the on-state current of the thin film transistor, and reduces the process steps of forming the source and drain electrode layers once compared with the formation of two complete thin film transistors. Therefore, the number of masks used is significantly reduced, thereby reducing the production cost, and there is a second gate insulating layer 107 and an interlayer insulating layer 109 between the second active layer 106 and the source-drain electrode layer 110, so that When forming the source and drain electrode layers, no etching damage will be caused to the second active layer 106 and the first active layer 104, so that the stability of the thin film transistor 100 is significantly improved, and at the same time due to the first gate 102 and the second gate
  • the electrode 108 controls the first active layer 104 and the second active layer 106 respectively, thereby improving the control capability of the first gate 102 and the second gate 108, so that when the on-state current is doubled, it is ensured that Characteristics of the thin film transistor 101.
  • a passivation layer 111 is provided on the side of the source-drain electrode layer 110 away from the base substrate 101, and the passivation layer 111 can prevent external impurities or water vapor from entering the thin-film transistor 100, thus affecting the thin-film transistor. performance.
  • FIG. 3 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • the drain electrode layer 110 is in direct contact with the surface of the second active layer 106 away from the base substrate 101 through the second via hole structure 113 .
  • the structure in Fig. 3 can make the second active layer 106 completely fill the first via hole structure 116, to ensure that the second active layer 106 is not easy to break in the first via hole structure 116, and can also make the formed second
  • the depth of the via structure 113 becomes shallower, making it easier to form the second via structure 113 .
  • a dry etching process is used when forming the source-drain electrode layer 110, and a reducing gas is required to perform the dry etching process.
  • a reducing gas can be used first to reduce the part of the second active layer 106 far away from the base substrate 101 into simple metal, so that the resistivity of the second active layer 106 becomes smaller, and then the first active layer 104 and After the second active layer 106 is electrically connected, the overall resistance becomes smaller, that is, there is no need to add new equipment and materials to reduce the resistance when the first active layer 104 and the second active layer 106 are connected.
  • the orthographic projection of the surface of the source-drain electrode layer 110 in contact with the second active layer 106 on the base substrate 101 is at least partly the same as the orthographic projection of the first via hole structure 116 on the base substrate 101 Overlapping, this can make the electrode structure more compact, which is more conducive to improving the on-state current. If the source 110a is shifted to the left and the drain 110b is shifted to the right, it is difficult to exhibit the characteristics of the thin film transistor 100 .
  • the structure in FIG. 3 can increase the contact area between the source-drain electrode layer 110 and the second active layer 106 to realize the electrical connection between the source-drain electrode layer 110 and the first active layer 104 and the second active layer 106 .
  • the material and thickness of the source-drain electrode layer 110 may refer to the relevant description of FIG. 2 above, which will not be repeated here.
  • FIG. 4 is a cross-sectional schematic diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • the side of the second gate 108 away from the base substrate 101, and the third active layer 112 is electrically connected to the source-drain electrode layer 110, and the interlayer insulating layer 109 is arranged on the third active layer 112 and the second gate 108 between.
  • the source-drain electrode layer 110 is overlapped on both sides of the third active layer 112, that is, the source electrode 110a is overlapped on the left side of the third active layer 112, and the drain electrode 110b is overlapped on the third active layer 112.
  • the right side of the active layer 112 , and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 through the second via structure 113 .
  • the addition of the third active layer 112 further increases the on-state current of the TFT. Compared with the structure in FIG. 1 , the on-state current of the TFT in FIG. 4 is three times that of the TFT in FIG. 1 .
  • FIG. 5 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • the first active layer 104 includes a stacked first sub-active layer 104a and a second sub-active layer
  • the active layer 104b and the second active layer 106 include a third sub-active layer 106a and a fourth sub-active layer 106b which are stacked.
  • the first active layer 104 may also include a first sub-active layer 104a and a second sub-active layer 104b arranged in layers, and the second active layer 106 is a single-layer structure.
  • the second active layer 106 includes a third sub-active layer 106a and a fourth sub-active layer 106b that are stacked, and the first active layer 104 has a single-layer structure.
  • the materials of the first sub-active layer 104a and the second sub-active layer 104b are the same or different, and the materials of the first sub-active layer 104a are zinc oxide (ZnO), indium oxide (In 2 O 3 ), Indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), boron doped zinc oxide (BZO), magnesium doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), oxide Indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), tin oxide (SnO 2 ), tin oxide (SnO) and cuprous oxide (Cu 2 O ), the material of the second sub-active layer 104b is one of the above-mentioned metal oxides or another one of the above-mentioned materials that is different from the material of the first sub-active layer 104a.
  • the first sub-active layer 104a is used to prevent the diffusion of elements, for example, to prevent the elements in the first gate 102 from diffusing to the second sub-active layer 104b, and the carrier concentration of the second sub-active layer 104b is greater than
  • the carrier concentration of the first sub-active layer 104a and the bandgap of the second sub-active layer 104b are smaller than the bandgap of the first sub-active layer 104a, and the second sub-active layer 104b is mainly used for transporting carriers.
  • the materials of the third sub-active layer 106a and the fourth sub-active layer 106b are the same or different, and the materials of the third sub-active layer 106a are zinc oxide (ZnO), indium oxide (In 2 O 3 ), Indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), boron doped zinc oxide (BZO), magnesium doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), oxide Indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), tin oxide (SnO 2 ), tin oxide (SnO) and cuprous oxide (Cu 2 O ), the material of the fourth sub-active layer 106b is one of the above-mentioned metal oxides or another material among the above-mentioned materials that is different from the material of the third sub-active layer 106a.
  • the fourth sub-active layer 106b is used to prevent the diffusion of elements, for example, to prevent the elements in the second gate 108 from diffusing to the third sub-active layer 106a, and the carrier concentration of the third sub-active layer 106a is greater than
  • the carrier concentration of the fourth sub-active layer 106b, the bandgap of the third sub-active layer 106a is smaller than the bandgap of the fourth sub-active layer 106b, and the third sub-active layer 106a is mainly used for transporting carriers.
  • the materials of the source layer and the sixth sub-active layer are the same or different, and the materials of the fifth sub-active layer and the sixth sub-active layer can be referred to above about the first sub-active layer 104a and the second sub-active layer 104b. Relevant descriptions will not be repeated here.
  • the material can also be a silicon-based material or an organic semiconductor material.
  • the silicon-based material or the organic semiconductor material can refer to the relevant description above, and will not be repeated here.
  • FIG. 6 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure. As shown in FIG. Between the two active layers 106, that is, the gate 114 is between the layer where the first active layer 104 is located and the layer where the second active layer 106 is located, and the gate 114 is configured to control the first active layer 104 and the second active layer 104 simultaneously. Two active layers 106, so that the structure of the thin film transistor 100 becomes simple, and at the same time, the on-state current of the thin film transistor 100 can be multiplied.
  • the layer where the second active layer 106 is located does not include the part where the second active layer 106 is located in the second via hole structure.
  • a gate insulating layer 115 is provided on the side of the gate 114 away from the first insulating layer 105, and the first via structure 116 penetrates the first insulating layer 105 and the gate insulating layer 115 at the same time.
  • the active layer 106 is electrically connected to the first active layer 104 through the first via structure 116 .
  • a second insulating layer 118 is provided between the second active layer 106 and the source-drain electrode layer 110, the second via hole structure 113 penetrates the second insulating layer 118, and the source-drain electrode layer 110
  • the second via hole structure 113 is electrically connected to the second active layer 106.
  • the second active layer 106 completely fills the first via hole structure 116, and the source and drain electrode layer 110 does not extend to the first via hole.
  • the source-drain electrode layer 110 may extend into the first via structure 116 with reference to the structure in FIG. 2 .
  • FIG. 7 is a schematic cross-sectional structure diagram of another thin film transistor provided by an embodiment of the present disclosure.
  • An interlayer insulating layer 109 is disposed on a side close to the base substrate 101 , and the second via structure 113 penetrates the interlayer insulating layer 109 , the second gate insulating layer 107 and part of the first insulating layer 105 in sequence.
  • a passivation layer 111 is provided on the side of the source-drain electrode layer 100 and the interlayer insulating layer 109 away from the base substrate 101, and the passivation layer 111 can prevent external impurities or water vapor from entering the thin film transistor. 100, thus affecting the performance of thin film transistors.
  • FIG. 8 is a block diagram of an array substrate provided by an embodiment of the present disclosure
  • the array substrate 200 includes a thin film Transistor 100.
  • the array substrate can be used for a display device, and the display device can be any product with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. part.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a thin film transistor, the method includes: providing a base substrate; sequentially forming a first active layer, a first insulating layer, and a second active layer on the base substrate, Wherein, the first active layer is in contact with the second active layer through the first via structure in the first insulating layer, and the part of the first active layer that is not in contact with the second active layer is separated by the first insulating layer. open.
  • FIG. 9 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 9 , the method includes the following steps.
  • S15 Form a second active layer on the side of the first insulating layer away from the base substrate, wherein the second active layer is in contact with the first active layer through the first via structure, and the first active layer is in contact with the first active layer.
  • the uncontacted parts of the two active layers are separated by the first insulating layer.
  • FIGS. 10A-10E are process diagrams of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • a base substrate 101 is provided, and the base substrate 101 is made of a rigid material or a flexible material.
  • the rigid material includes one of rigid glass and a silicon wafer.
  • the flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass.
  • the first active layer 104 is formed on the base substrate 101 .
  • the material of the first active layer 104 may be a silicon-based material, or a metal oxide semiconductor material, or an organic semiconductor material.
  • the metal oxide semiconductor material includes zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium zinc oxide (IZO), aluminum doped Heterogeneous zinc oxide (AZO), boron doped zinc oxide (BZO), magnesium doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium oxide n-type semiconductor materials such as zinc (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO) and tin oxide (SnO 2 ) , and p type semiconductor material.
  • the first active layer 104 of metal oxide semiconductor material can be formed by magnetron sputtering, reactive sputtering, anodic oxidation or spin coating.
  • the material of the first active layer 104 may also be silicon, germanium, a silicon-germanium mixed material, and the like.
  • the first active layer 104 of the above-mentioned semiconductor material may be formed by magnetron sputtering or spin coating.
  • the material of the first active layer 104 can also be an organic semiconductor material
  • the organic semiconductor material includes pentacene, triphenylamine, fullerene, phthalocyanine, polythiophene, polyaniline, polypyrrole, etc.
  • the above organic semiconductor material is formed by spin coating.
  • the thickness of the first active layer 104 is 5nm-200nm, for example, the thickness of the first active layer 104 is 50nm, 100nm, 150nm, or 200nm.
  • a first insulating film 105' is applied on the side of the first active layer 104 away from the base substrate 101.
  • the first insulating layer film 105' is patterned to form the first insulating layer 105 with the first via structure 116.
  • patterning the first insulating layer film 105' includes coating photoresist on the first insulating layer film 105', and using processes such as exposure, development, etching and stripping the photoresist to process the first insulating layer film 105'. 'Process to form the first insulating layer 105 with the first via structure 116.
  • the material of the first insulating layer 105 includes one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide and zirconium oxide.
  • the thickness of the first insulating layer 105 is 5 nm ⁇ 400 nm, such as 50 nm, 100 nm, 200 nm, 300 nm or 400 nm.
  • the second active layer 106 is formed on the side of the first insulating layer 105 away from the base substrate 101 .
  • the selection range of the material of the second active layer 106 is the same as the selection range of the material of the first active layer 104, and the thickness of the second active layer 106 is 5nm-200nm, for example, the second active layer 106 The thickness is 50nm, 100nm, 150nm, or 200nm.
  • the second active layer 106 is in contact with the first active layer 104 through the first via structure 116 in the first insulating layer 105, and the first active layer 104 and the second active layer 106 are not in contact with each other.
  • the contacted parts are separated by the first insulating layer 105 .
  • the first active layer 104 is in contact with the second active layer 106 through the first via structure 116 in the first insulating layer 105 to realize electrical connection.
  • the number of the first via structure 116 can be one or more.
  • there are two first via hole structures 116 the two first via hole structures 116 are spaced apart from each other, and the two first via hole structures 116 are close to the substrate.
  • the sum of the widths of one side of the substrate 101 is smaller than the maximum width of the first active layer 104 in the horizontal direction, and is smaller than the maximum width of the second active layer 106 in the horizontal direction.
  • each first via structure 116 close to the substrate 101 and the sidewall defining the first via structure 116 are covered with the second active layer 106, and each first via structure 116 Neither is filled by the second active layer 106 .
  • the orthographic projection of each first via hole structure 116 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101, and smaller than the orthographic projection of the second active layer 104.
  • Orthographic projection of 106 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101, and smaller than the orthographic projection of the second active layer 104.
  • each first via hole structure 116 on the base substrate 101 is smaller than the orthographic projection of the first active layer 104 on the base substrate 101 and smaller than the orthographic projection of the second active layer 106 on the base substrate 101
  • the embodiments of the present disclosure are not limited thereto, and the orthographic projection of each first via hole structure 116 on the base substrate 101 may also be greater than or equal to that of the first active layer 104 on the base substrate 101 orthographic projection of .
  • the materials of the first active layer 104 and the second active layer 106 can be the same or different.
  • the materials of the first active layer 104 and the second active layer 106 may both be silicon-based materials, or both be metal oxide semiconductor materials, or both be organic semiconductor materials.
  • the material of the first active layer 104 is one of silicon-based materials, metal oxide semiconductor materials and organic semiconductor materials, and the material of the second active layer 106 is two other materials different from the materials of the first active layer 104. one of the materials.
  • FIG. 11 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 11 , the method includes:
  • first gate film on the substrate, coat photoresist on the first gate film, and pattern the first gate film by exposure, development, etching and stripping photoresist. to form the first grid.
  • the photoresist can be coated by spin coating, blade coating or roller coating.
  • the material of the first gate includes one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy and copper (Cu).
  • the material of the first gate may also include one or a combination of transparent conductive materials such as indium tin oxide (ITO), aluminum doped zinc oxide (AZO) and boron doped zinc oxide (BZO).
  • ITO indium tin oxide
  • AZO aluminum doped zinc oxide
  • BZO boron doped zinc oxide
  • the first gate can be a single-layer structure or a double-layer structure.
  • the first gate of the double-layer structure may be a composite conductive layer composed of metal and transparent conductive material.
  • the material of the first gate can be a combination of copper and other metals, for example, copper/molybdenum (Cu/Mo), copper/titanium (Cu/Ti), copper/molybdenum-titanium alloy (Cu /MoTi), copper/molybdenum-tungsten alloy (Cu/MoW), copper/molybdenum-niobium alloy (Cu/MoNb), etc.; the material of the first gate can also be a combination of chromium-based metal or chromium and other metals, for example, Chromium/molybdenum (Cr/Mo), chromium/titanium (Cr/Ti), chromium/molybdenum-titanium alloy (Cr/MoTi), etc.
  • Cu/Mo copper/molybdenum
  • Cu/Ti copper/molybdenum-titanium alloy
  • Cu/MoW copper/molybdenum-tungsten alloy
  • the thickness of the first grid can be 50 nm ⁇ 300 nm, and the thickness of the first grid 102 is 50 nm, 100 nm, 200 nm or 300 nm and so on.
  • methods such as magnetron sputtering, electron beam evaporation or thermal evaporation can be used to form the first gate film, and methods such as magnetron sputtering or optical coating can also be used to form the first gate film.
  • a first gate insulating layer film is deposited on the first gate, and the first gate insulating layer film is patterned to form the first gate insulating layer.
  • the first gate insulating layer may be formed using at least one of insulating materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and the like, and It is formed by plasma enhanced chemical vapor deposition (PECVD), and an organic insulating material may also be formed by spin coating to form the first gate insulating layer.
  • insulating materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and the like.
  • PECVD plasma enhanced chemical vapor deposition
  • an organic insulating material may also be formed by spin coating to form the first gate insulating layer.
  • the first active layer thin film on the first gate insulating layer by magnetron sputtering, form a photoresist on the first active layer thin film, and use exposure, development, etching and stripping photoresist, etc.
  • the process patterns the first active layer thin film to form the first active layer.
  • a first insulating layer film is applied on a side of the first active layer away from the base substrate, and the first insulating layer film is patterned to form a first insulating layer having a first via hole structure.
  • patterning the first insulating layer film includes coating photoresist on the first insulating layer film, and using processes such as exposure, development, etching, and stripping the photoresist to process the first insulating layer film to form a The first insulating layer of the first via hole structure.
  • a second active layer film is applied on the first insulating layer by magnetron sputtering, a photoresist is formed on the second active layer film, and processes such as exposure, development, etching, and stripping of the photoresist are used.
  • the second active layer film is patterned to form a second active layer.
  • the second active layer fills a part of the first via structure, that is, the second active layer does not completely fill the first via structure.
  • a second gate insulating layer film is applied on the side of the second active layer away from the base substrate, and the second gate insulating layer film is patterned to form the second gate insulating layer.
  • the second gate insulating layer can be formed by at least one insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and can be It is formed by plasma enhanced chemical vapor deposition (PECVD), and an organic insulating material may also be formed by spin coating to form the second gate insulating layer.
  • insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN)
  • PECVD plasma enhanced chemical vapor deposition
  • an organic insulating material may also be formed by spin coating to form the second gate insulating layer.
  • a second gate film on the side of the second gate insulating layer away from the base substrate, form a photoresist on the second gate film, and use processes such as exposure, development, etching and stripping the photoresist to The second gate film is patterned to form a second gate.
  • the photoresist can be coated by spin coating, blade coating or roller coating.
  • the material of the second gate includes one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy and copper (Cu).
  • the material of the second gate may also include one or a combination of transparent conductive materials such as indium tin oxide (ITO), aluminum doped zinc oxide (AZO) and boron doped zinc oxide (BZO).
  • ITO indium tin oxide
  • AZO aluminum doped zinc oxide
  • BZO boron doped zinc oxide
  • the second gate can be a single-layer structure or a double-layer structure.
  • the second grid of the double-layer structure may be a composite conductive layer composed of metal and transparent conductive material.
  • the material of the second gate can be a combination of copper and other metals, for example, copper/molybdenum (Cu/Mo), copper/titanium (Cu/Ti), copper/molybdenum-titanium alloy (Cu /MoTi), copper/molybdenum-tungsten alloy (Cu/MoW), copper/molybdenum-niobium alloy (Cu/MoNb), etc.; the material of the second gate can also be a combination of chromium-based metal or chromium and other metals, for example, Chromium/molybdenum (Cr/Mo), chromium/titanium (Cr/Ti), chromium/molybdenum-titanium alloy (Cr/MoTi), etc.
  • Cu/Mo copper/molybdenum
  • Cu/Ti copper/molybdenum-titanium alloy
  • Cu/MoW copper/molybdenum-tungsten alloy
  • the thickness of the second gate can be 50nm ⁇ 300nm respectively, and the thickness of the second gate is 50nm, 100nm, 200nm or 300nm, etc.
  • methods such as magnetron sputtering, electron beam evaporation or thermal evaporation can be used to form the second gate film, and methods such as magnetron sputtering or optical coating can also be used to form the second gate film.
  • an interlayer insulating layer film on the side of the second grid far away from the base substrate coat a photoresist on the interlayer insulating layer film, and use processes such as exposure, development, etching, and stripping photoresist to
  • the thin film of the interlayer insulating layer and the second gate insulating layer are patterned to form the interlayer insulating layer and the second via hole structure penetrating through the interlayer insulating layer, the second gate insulating layer and part of the first insulating layer.
  • the material of the interlayer insulating layer includes at least one of insulating materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and
  • the interlayer insulating layer is formed by plasma enhanced chemical vapor deposition (PECVD), and an organic insulating material may also be formed by spin coating to form the interlayer insulating layer.
  • a source-drain electrode layer film is applied on the side of the interlayer insulating layer away from the substrate by magnetron sputtering, a photoresist is formed on the source-drain electrode layer film, and exposure, development, etching and stripping The thin film of the source-drain electrode layer is patterned by photoresist and other processes to form the source-drain electrode layer.
  • the material and thickness of the source-drain electrode layer can refer to the relevant description above, and will not be repeated here.
  • the resistance when the first active layer is connected to the second active layer is relatively large, and a dry etching process is used when forming the source and drain electrode layers, and a reducing gas is required to perform the dry etching process.
  • a reducing gas can be used first to reduce the part of the second active layer exposed to the second via hole structure into a simple metal substance, so that the second active layer The resistivity becomes smaller, and then the overall resistance after the first active layer and the second active layer are electrically connected becomes smaller, that is, the first active layer and the second active layer can be reduced without adding new equipment and materials. resistance when connected.
  • the passivation layer can be formed by plasma chemical vapor deposition, and the material of the passivation layer is silicon nitride (SiN x ), silicon oxide (SiO x ), acrylic resin, etc., and the passivation layer can prevent external impurities from Or water vapor enters the thin film transistor, thereby affecting the performance of the thin film transistor.
  • a passivation layer film on the side of the source-drain electrode layer away from the base substrate, coat a photoresist on the passivation layer film, and use processes such as exposure, development, etching and stripping photoresist to The passivation layer film is processed to form a passivation layer.
  • FIGS. 12A-12K are process diagrams of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • the method includes:
  • a base substrate 101 is provided.
  • the material of the base substrate 101 reference may be made to relevant descriptions above, and details are not repeated here.
  • the first gate 102 is formed on the base substrate 101 .
  • the specific process of forming the first gate 102 is: forming a first gate material layer on the base substrate 101 , and patterning the first gate material layer to form the first gate 102 .
  • the material and formation method of the first gate 102 can refer to the relevant description above, and will not be repeated here.
  • a first gate insulating layer 103 is formed on the first gate 102 .
  • the material and thickness of the first gate insulating layer 103 refer to the relevant description above, which will not be repeated here.
  • silicon oxide (SiO 2 ) or silicon nitride (SiN x ) can be deposited by plasma enhanced chemical vapor deposition (PECVD) to form the first gate insulating layer 103, or an organic insulating material can be spin-coated and other methods to form the first gate insulating layer 103 .
  • PECVD plasma enhanced chemical vapor deposition
  • the first active layer 104 is formed on the first gate insulating layer 103 .
  • the first active layer material is deposited on the first gate insulating layer 103 and patterned to form the first active layer 104.
  • the material, formation method and thickness of the first active layer 104 please refer to the related description and will not be repeated here.
  • a first insulating layer 105 is formed on the first active layer 104 , and a first via structure 116 is formed in the first insulating layer 105 .
  • a first via structure 116 is formed in the first insulating layer 105 .
  • the second active layer 106 is formed on the first insulating layer 105 .
  • the first active layer 104 is in contact with the second active layer 106 through the first via hole structure 116 in the first insulating layer 105, and the part of the first active layer 104 that is not in contact with the second active layer 106 is through the first The insulating layers 105 are spaced apart.
  • the second active layer material is deposited on the patterned first insulating layer 105 and patterned to form the second active layer 106.
  • the number of the first via hole structure 116 is multiple, such as two One, the bottom and sidewalls of each first via structure 116 in the first insulating layer 105 are covered with the second active layer 106, and each first via structure 116 is not covered by the second active layer 106 fill up.
  • a second gate insulating layer 107 is formed on the second active layer 106 .
  • a second gate 108 is formed on the second gate insulating layer 107 .
  • the material and formation method of the second gate 108 can refer to the relevant description above, and will not be repeated here.
  • an interlayer insulating layer 109 is formed on the second gate electrode 108 .
  • the second via structure 113 is formed in the interlayer insulating layer 109 and the second gate insulating layer 107 , and the material of the interlayer insulating layer 109 can refer to the relevant description above, and will not be repeated here.
  • a source-drain electrode layer 110 is formed on the interlayer insulating layer 109 .
  • a conductive material is deposited and patterned on the interlayer insulating layer 109 and in the second via hole structure 113 to form the source-drain electrode layer 110 (including the source electrode 110a and the drain electrode 110b), and the source electrode 110a and the drain electrode 110b are simultaneously It is electrically connected with the first active layer 104 and the second active layer 106 .
  • the source-drain electrode layer 110 is electrically connected to the second active layer 106 through the second via structure 113.
  • the orthographic projection of the first via structure 116 on the base substrate 101 and the second via structure Orthographic projections of 113 on the base substrate 101 at least partially overlap, and at least part of the source-drain electrode layer 110 extends into the first via hole structure 116 .
  • a part of the second via structure 113 is formed in the first via structure 116, and the orthographic projection of the second via structure 113 on the base substrate 101 is located on the substrate of the first via structure 116. In the orthographic projection on the base substrate 101 .
  • the material of the source-drain electrode layer 110 may include one or more of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloy, and copper (Cu). combination.
  • Mo molybdenum
  • Cr chromium
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source-drain electrode layer 110 is copper-based metal.
  • Copper metal has the characteristics of low resistivity and good conductivity, so it can increase the signal transmission rate of the source and drain electrodes and improve the display quality.
  • the copper-based metal is a stable copper-based metal alloy such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi) or copper-zinc-nickel alloy (CuZnNi).
  • Cu copper
  • CuZn copper-zinc alloy
  • CuNi copper-nickel alloy
  • CuZnNi copper-zinc-nickel alloy
  • the thickness of the source-drain electrode layer 110 may be 200-400nm, for example, 200nm, 230nm, 250nm, 300nm, 350nm, 380nm and 400nm.
  • the source-drain electrode layer material deposit the source-drain electrode layer material on the interlayer insulating layer 109, coat photoresist on the source-drain electrode layer material, and process the source-drain electrode layer material by exposing, developing, etching, and stripping photoresist. Patterning is performed to form the source-drain electrode layer, for example, the source-drain electrode layer may also be formed by dry etching using a reducing gas.
  • a passivation layer 111 is formed on the side of the source-drain electrode layer away from the base substrate 101 .
  • the passivation layer 111 may be formed by plasma chemical vapor deposition.
  • the second active layer 106 completely fills the first via structure 116, so as to ensure that the second active layer 106 is not easily broken in the first via structure 116, and also makes the depth of the second via structure 113 formed shallower. , making it easier to form the second via structure 113 .
  • the formed second via hole structure 113 penetrates the interlayer insulating layer 109 and part of the second gate insulating layer 107, and the source and drain electrode layer 110 passes through the second via hole structure 113 and the surface of the second active layer 106 away from the substrate 101 direct contact.
  • a third active layer 112 is formed on the side of the interlayer insulating layer 109 away from the base substrate 101, the third active layer 112 is electrically connected to the source-drain electrode layer 110, and the interlayer insulating layer 109 is set between the third active layer 112 and the second gate 108 .
  • the source-drain electrode layer 110 is overlapped on both sides of the third active layer 112, that is, the source electrode 110a is overlapped on the left side of the third active layer 112, and the drain electrode 110b is overlapped on the third active layer 112.
  • the right side of the source layer 112 , and the source-drain electrode layer 110 is electrically connected to the first active layer 104 and the second active layer 106 through the second via structure 113 .
  • the addition of the third active layer 112 further increases the on-state current of the TFT. Compared with the structure in FIG. 1 , the on-state current of the TFT in FIG. 4 is three times that of the TFT in FIG. 1 .
  • the second active layer 106 when forming the structure of the thin film transistor shown in FIG. 104a and a second sub-active layer 104b, and the second active layer 106 includes a third sub-active layer 106a and a fourth sub-active layer 106b that are stacked.
  • the materials and preparation methods of the first sub-active layer 104a, the second sub-active layer 104b, the third sub-active layer 106a, and the fourth sub-active layer 106b can refer to the relevant description above, and will not be repeated here.
  • the gate 114 is configured to simultaneously control the first active layer 104 and the second active layer 106, so that the structure of the thin film transistor 100 becomes simple, and at the same time it can The on-state current of the thin film transistor 100 is multiplied.
  • a gate insulating layer 115 is formed on the side of the gate 114 away from the first insulating layer 105, and the first via structure 116 penetrates the first insulating layer 105 and the gate insulating layer simultaneously.
  • the second active layer 106 is electrically connected to the first active layer 104 through the first via structure 116 .
  • a second insulating layer 118 is formed between the second active layer 106 and the source-drain electrode layer 110, the second via hole structure 113 penetrates the second insulating layer 118, and the source-drain electrode layer 110 passes through the second via hole structure 113 and the second insulating layer 118.
  • the second active layer 106 is electrically connected.
  • the manufacturing method differs from the process shown in FIGS. 12A-12K in that the second gate 108 is not directly formed after the second gate insulating layer 107 is formed, Instead, the interlayer insulating layer 109 is formed directly, the source-drain electrode layer 110 and the second gate 108 are formed in the same process step after the interlayer insulating layer 109 is formed, and the second via structure 113 penetrates the interlayer insulating layer 109 and the the second gate insulating layer 107 .
  • the thin film transistor, the array substrate, and the manufacturing method of the thin film transistor provided by the embodiments of the present disclosure have at least one of the following beneficial technical effects:
  • the thin film transistor provided by at least one embodiment of the present disclosure has a double active layer structure, so that charges are respectively accumulated on the two surfaces of the two active layers, so that the amount of charges accumulated on the surfaces of the active layers is equal to times, so that the on-state current of the thin film transistor is doubled.
  • the thin film transistor provided by at least one embodiment of the present disclosure further includes a third active layer, and the third active layer further increases the on-state current of the thin film transistor.
  • a reducing gas can be used first to expose the second active layer Part of the second via hole structure is reduced to simple metal, so that the resistivity of the second active layer becomes smaller, and then the overall resistance after the first active layer and the second active layer are electrically connected becomes smaller, that is, The resistance when the first active layer is connected to the second active layer is reduced without adding new equipment and materials.

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Abstract

一种薄膜晶体管、阵列基板以及薄膜晶体管的制备方法，该薄膜晶体管包括：衬底基板(101)；依次层叠设置在衬底基板(101)上的第一有源层(104)、第一绝缘层(105)和第二有源层(106)；其中，第一有源层(104)通过位于第一绝缘层(105)中的第一过孔结构(116)与第二有源层(106)接触，第一有源层(104)与第二有源层(106)未接触的部分通过第一绝缘层(105)间隔开，该薄膜晶体管具有多个有源层结构，使得电荷分别聚集在每个有源层的两个表面，从而使得聚集在有源层的表面的电荷的数量成倍地增加，进而使得薄膜晶体管的开态电流成倍地增加。

Description

薄膜晶体管及其制备方法、阵列基板
相关申请的交叉引用
本申请要求于2021年05月28日递交的第202110591152.3号中国专利申请的优先权，在此出于所有目的全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种薄膜晶体管、阵列基板以及薄膜晶体管的制备方法。
背景技术
根据薄膜晶体管的栅电极和有源层的相对位置，可以将薄膜晶体管分为顶栅结构和底栅结构，根据源漏电极层相对于有源层的位置可以将薄膜晶体管分为顶接触型结构和底接触型结构，即薄膜晶体管包括底栅顶接触、底栅底接触、顶栅顶接触和顶栅底接触四种结构。
薄膜晶体管包括硅基薄膜晶体管、金属氧化物薄膜晶体管以及有机薄膜晶体管等。硅基薄膜晶体管因其具有较好的性能和能大面积制备而广泛用于显示面板。随着显示技术的发展，硅基薄膜晶体管的固有缺点，例如非晶硅薄膜晶体管的迁移率低、稳定性差，多晶硅薄膜晶体管的均匀性差和成本高，使硅基薄膜晶体管难以满足发展的需要。有机薄膜晶体管虽然能够有效的降低成本，但是其性能远不能满足显示技术的需要。相对于硅基薄膜晶体管，金属氧化物薄膜晶体管的技术优势明显，其具有更高的迁移率、更陡的亚阈值摆幅、更小的关态泄漏电流、更好的器件性能一致性，制备金属氧化物半导体的工艺简单、工艺温度低、稳定性好，且形成的金属氧化物薄膜晶体管对于可见光的透过率高、在弯曲状态下金属氧化物薄膜晶体管器件的特性无明显退化。
发明内容
本公开至少一实施例提供一种薄膜晶体管，该薄膜晶体管包括：衬底基板；依次层叠设置在所述衬底基板上的第一有源层、第一绝缘层和第二有源层；其中，所述第一有源层通过位于所述第一绝缘层中的第一过孔结构与所述第二有源层接触，所述第一有源层与所述第二有源层未接触的部分通过所述第一绝缘层间隔开。
例如，本公开至少一实施例提供的薄膜晶体管，还包括源漏电极层，其中，所述源漏电极层与所述第一有源层和所述第二有源层电连接。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述源漏电极层通过第二过孔结构与所述第二有源层电连接，所述第一过孔结构在所述衬底基板上的正投影和所述第二过孔结构在所述衬底基板上的正投影至少部分重叠，且至少部分所述源漏电极层延伸至所述 第一过孔结构中。
例如，本公开至少一实施例提供的薄膜晶体管，还包括第一栅极和第二栅极，其中，所述第一栅极在所述第一有源层的靠近所述衬底基板的一侧，且在所述第一栅极和所述第一有源层之间设置有第一栅绝缘层；所述第二栅极在所述第二有源层的远离所述衬底基板的一侧，且在所述第二栅极和所述第二有源层之间设置有第二栅绝缘层。
例如，在本公开至少一实施例提供的薄膜晶体管中，在所述第二栅极的远离所述衬底基板的一侧设置有层间绝缘层，所述源漏电极层设置在所述层间绝缘层的远离所述衬底基板的一侧，所述第二过孔结构依次贯穿所述层间绝缘层、所述第二栅绝缘层和部分所述第一绝缘层。
例如，本公开至少一实施例提供的薄膜晶体管，还包括第三有源层，其中，所述第三有源层设置在所述第二栅极的远离所述衬底基板的一侧，所述层间绝缘层设置在所述第三有源层和所述第二栅极之间，且所述第三有源层和所述源漏电极层电连接。
例如，本公开至少一实施例提供的薄膜晶体管，还包括栅极，其中，所述栅极在所述第一有源层和所述第二有源层之间。
例如，在本公开至少一实施例提供的薄膜晶体管中，在所述栅极的远离所述第一绝缘层的一侧设置有栅绝缘层，所述第一过孔结构同时贯穿所述第一绝缘层和所述栅绝缘层。
例如，在本公开至少一实施例提供的薄膜晶体管中，在所述第二有源层和所述源漏电极层之间设置有第二绝缘层，所述第二过孔结构贯穿所述第二绝缘层。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述源漏电极层和所述第二栅极设置在同一层，在所述第二栅极的靠近所述衬底基板的一侧设置有层间绝缘层，所述第二过孔结构依次贯穿所述层间绝缘层、所述第二栅绝缘层和部分所述第一绝缘层。
例如，在本公开至少一实施例提供的薄膜晶体管中，所述第一有源层包括层叠设置的第一子有源层和第二子有源层，和/或所述第二有源层包括层叠设置的第三子有源层和第四子有源层。
本公开至少一实施例还提供一种阵列基板，该阵列基板包括上述任一项所述的薄膜晶体管。
本公开至少一实施例还提供一种薄膜晶体管的制备方法，该制备方法包括：提供衬底基板；在所述衬底基板上形成第一有源层；在所述第一有源层的远离所述衬底基板的一侧施加第一绝缘层薄膜；对所述第一绝缘层薄膜进行图案化以形成具有第一过孔结构的第一绝缘层；在所述第一绝缘层的远离所述衬底基板的一侧形成第二有源层，其中，所述第二有源层通过所述第一过孔结构与所述第一有源层接触，所述第一有源层与所述第二有源层未接触的部分通过所述第一绝缘层间隔开。
例如，本公开至少一实施例提供的制备方法，还包括形成源漏电极层，其中，所述源漏电极层与所述第一有源层和所述第二有源层电连接。
例如，在本公开至少一实施例提供的制备方法中，所述源漏电极层通过第二过孔结构与所述第二有源层电连接，所述第一过孔结构在所述衬底基板上的正投影和所述第二过孔 结构在所述衬底基板上的正投影至少部分重叠，且至少部分源漏电极层延伸至所述第一过孔结构中。
例如，本公开至少一实施例提供的制备方法，还包括：在所述第一有源层的靠近所述衬底基板的一侧形成第一栅极；在所述第一栅极和所述第一有源层之间形成第一栅绝缘层；在所述第二有源层的远离所述衬底基板的一侧形成第二栅极；在所述第二栅极和所述第二有源层之间形成第二栅绝缘层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种薄膜晶体管的截面结构示意图；
图2为本公开一实施例提供的一种薄膜晶体管的截面结构示意图；
图3为本公开一实施例提供的再一种薄膜晶体管的截面结构示意图；
图4为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图；
图5为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图；
图6为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图；
图7为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图；
图8为本公开一实施例提供的一种阵列基板的框图；
图9为本公开一实施例提供的一种薄膜晶体管的制备方法的流程图；
图10A-10E为本公开一实施例提供的一种薄膜晶体管的制备方法的过程图；
图11为本公开一实施例提供的一种薄膜晶体管的制备方法的流程图；以及
图12A-12K为本公开一实施例提供的一种薄膜晶体管的制备方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
由于显示面板趋于高分辨率、大尺寸的方向发展，显示面板中的薄膜晶体管需要高的开态电流。例如，图1为一种薄膜晶体管的截面结构示意图，如图1所示，在基底01上设置有依次层叠的缓冲层02、底部栅极03、底部栅绝缘层04、有源层05、顶部栅绝缘层06、顶部栅极07、绝缘层08和源极09a/漏极09b，即图1所示的为双栅极单有源层的结构，图1所示的结构中采用底部栅极03和顶部栅极07同时对一个有源层05进行作用，从而可以提升薄膜晶体管的开态电流。
但是，图1所示的结构还存在如下缺陷：由于顶部栅极07与底部栅极03之间仅存在底部栅绝缘层04、顶部栅绝缘层06和有源层05进行隔离，一方面当顶部栅极07与底部栅极03之间的距离较近时，容易导致顶部栅极07的电场与底部栅极03的电场之间形成串扰，从而导致有源层05中载流子的稳定性变差，薄膜晶体管的特性控制变得困难。例如，图1所示薄膜晶体管的结构的电压容易受到顶部栅极07的电压的改变而发生正负偏移，从而使得薄膜晶体管的特性变差；另一方面，图1所示的薄膜晶体管无法实现开态电流的成倍提升，目前图1所示的结构对开态电流的提升仅能达到50％左右，图1所示的薄膜晶体管对开态电流的提升很小，将其用于显示面板中时，不能满足显示面板对开态电流、分辨率的需求。
本公开的发明人注意到，可以设计具有多个有源层的薄膜晶体管，使得电荷分别聚集在每个有源层的两个表面，从而使得聚集在有源层的表面的电荷的数量成倍地增加，进而使得薄膜晶体管的开态电流成倍地增加。
例如，图2为本公开一实施例提供的一种薄膜晶体管的截面结构示意图，如图2所示，该薄膜晶体管100包括：衬底基板101，依次层叠设置在衬底基板101上的第一有源层104、第一绝缘层105和第二有源层106，第一有源层104通过位于第一绝缘层105中的第一过孔结构116与第二有源层106接触，第一有源层104与第二有源层106未接触的部分通过第一绝缘层105间隔开。例如，该第一有源层104通过第一过孔结构116与第二有源层106接触可以实现第一有源层104和第二有源层106之间的电连接；第一有源层104与第二有源层106未接触的部分通过第一绝缘层105间隔开，可以使得第一有源层104的靠近衬底基板101的表面和第一有源层104的靠近第二有源层的表面均聚集有电荷，第二有源层106的靠近衬底基板101的表面和第二有源层106的远离衬底基板101的表面均聚集有电荷，从而可以使得在有源层(包括第一有源层104和第二有源层106)的表面聚集的电荷的数量成倍地增加，从而可以使得开态电流成倍的提升。
例如，如图2所示，该第一有源层104通过位于第一绝缘层105中的第一过孔结构116与第二有源层106接触并实现电连接。
例如，该第一过孔结构116的个数可以为一个或者多个。在图2所示的薄膜晶体管的截面结构中，第一过孔结构116的个数为两个，两个第一过孔结构116相互间隔开，两个第一过孔结构116的靠近衬底基板101一侧的宽度之和小于第一有源层104的最大水平宽度，且小于第二有源层106的最大水平宽度。
例如，每个第一过孔结构116的靠近衬底基板101的一侧和限定第一过孔结构116 的侧壁上都覆盖有第二有源层106，且每个第一过孔结构116都未被第二有源层106填满。
例如，如图2所示，每个第一过孔结构116在衬底基板101上的正投影均小于第一有源层104在衬底基板101上的正投影，且小于第二有源层106在衬底基板101上的正投影。多个第一过孔结构116在衬底基板101上的正投影之和小于第一有源层104在衬底基板101上的正投影，且小于第二有源层106在衬底基板101上的正投影，当然，本公开的实施例也不限于此，每个第一过孔结构116在衬底基板101上的正投影还可以大于或者等于第一有源层104在衬底基板101上的正投影。
例如，该第一有源层104和第二有源层106的材料可以相同或者不同。第一有源层104和第二有源层106的材料可以均为硅基材料，或者均为金属氧化物半导体材料，或者均为有机半导体材料。第一有源层104的材料为硅基材料、金属氧化物半导体材料和有机半导体材料中的一种，第二有源层106的材料为不同于第一有源层104的材料的另外两种材料中的一种。
例如，当第一有源层104和第二有源层106的材料均为金属氧化物半导体材料时，该金属氧化物半导体材料包括氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铟锌(IZO)、铝掺杂氧化锌(AZO)、硼掺杂氧化锌(BZO)、镁掺杂氧化锌(MZO)、氧化锌锡(ZTO)、氧化铟镓锌(IGZO)、氧化铟锡锌(ITZO)、氧化镓锌(GZO)、氧化铟锡(ITO)、氧化铪铟锌(HIZO)和氧化锡(SnO 2)等n型半导体材料，以及氧化亚锡(SnO)和氧化亚铜(Cu 2O)等p型半导体材料。例如，可以采用磁控溅射、反应溅射、阳极氧化或旋涂等方法形成金属氧化物半导体材料的第一有源层104和第二有源层106。
例如，该第一有源层104和第二有源层106的材料也可以为硅、锗、硅锗混合材料等。可以采用磁控溅射或旋涂等方法形成上述半导体材料的第一有源层104和第二有源层106。
例如，该第一有源层104和第二有源层106的材料也可以为有机半导体材料，该有机半导体材料包括并五苯、三苯基胺、富勒烯、酞箐、聚噻吩、聚苯胺、聚吡咯等，可以采用旋涂的方式形成上述有机半导体材料。
例如，该第一有源层104和第二有源层106的厚度分别为5nm～200nm。例如，该第一有源层104的厚度可以为50nm、100nm、150nm、或者200nm等；该第二有源层106的厚度可以为50nm、100nm、150nm、或者200nm等。
例如，衬底基板101采用刚性材料或者柔性材料形成。例如，刚性材料包括刚性玻璃和硅片中的一种。柔性材料包括聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚酰亚胺中和柔性玻璃中的一种。
例如，该第一绝缘层105的材料包括氧化硅、氮化硅、氧化铝、氧化铪、氧化钽和氧化锆中的一种或者多种。
例如，该第一绝缘层105的厚度为5nm～400nm，例如为50nm、100nm、200nm、300nm或者400nm。
例如，如图2所示，该薄膜晶体管100还包括源漏电极层110，该源漏电极层110与 第一有源层104和第二有源层106电连接。该源漏电极层110包括源极110a和漏极110b，该源极110a和漏极110b均与第一有源层104和第二有源层106电连接。
例如，该源漏电极层110与第一有源层104和第二有源层106电连接的形式包括：源漏电极层110与第一有源层104搭接，以使得源漏电极层110与第一有源层104和第二有源层106电连接；源漏电极层110与第二有源层搭接，以使得源漏电极层110与第一有源层104和第二有源层106电连接；源漏电极层110与第一有源层104通过第二过孔结构113电连接，以使得源漏电极层110与第一有源层104和第二有源层106同时电连接；源漏电极层110与第二有源层106通过第二过孔结构113电连接以使得源漏电极层110与第一有源层104和第二有源层106同时电连接。
例如，在图2所示的结构中，源漏电极层110与第二有源层106通过第二过孔结构113电连接以使得源漏电极层110与第一有源层104和第二有源层106同时电连接。该第一过孔结构116在衬底基板101上的正投影和第二过孔结构113在衬底基板101上的正投影至少部分重叠，且至少部分源漏电极层110延伸至第一过孔结构116中。
例如，第一过孔结构116的靠近衬底基板101一侧的宽度大于第二过孔结构113的靠近衬底基板101一侧的宽度，且第二过孔结构113的靠近衬底基板101一侧套设在第一过孔结构116中，这样可以使得源漏电极层110更稳定地与第二有源层106电连接。
例如，该源漏电极层110的材料可以包括钼(Mo)、铬(Cr)、钛(Ti)、铝(Al)、铝合金和铜(Cu)等金属中的一种或者多种的组合。
例如，在一个示例中，该源漏电极层110的材料为铜基金属。铜金属具有电阻率低、导电性好的特点，因而可以提高源漏电极层110(源极110a、漏极110b)的信号传输速率，提高显示质量。
例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
例如，该源漏电极层110的厚度可以为200-400nm，例如，可以为200nm、230nm、250nm、300nm、350nm、380nm以及400nm。
例如，源漏电极层110不限于形成在第二有源层106的远离衬底基板101的一侧，还可以形成在第一有源层104的靠近衬底基板的一侧，或者其他的位置，只要满足源漏电极层110能够与第一有源层104和第二有源层106同时电连接即可。
例如，第一有源层104和第二有源层106连接时的电阻较大，形成源漏电极层110时会采用干刻工艺，执行干刻工艺时需要采用还原性气体，当第一有源层104和第二有源层106的材料为金属氧化物半导体材料时，可以先采用还原性气体使得第二有源层106的暴露于第二过孔结构113的部分被还原成金属单质，从而使得第二有源层106的电阻率变小，进而使得第一有源层104和第二有源层106电连接后整体的电阻变小，即可以不用增加新的设备和材料减小第一有源层104和第二有源层106连接时的电阻。
例如，如图2所示，该薄膜晶体管100还包括第一栅极102和第二栅极108，该第一栅极102在第一有源层104的靠近衬底基板101的一侧，且在第一栅极102和第一有源层 104之间设置有第一栅绝缘层103，第二栅极108在第二有源层106的远离衬底基板101的一侧，且在第二栅极108和第二有源层106之间设置有第二栅绝缘层107。
例如，该第一栅极102和第二栅极108的材料可以分别包括钼(Mo)、铬(Cr)、钛(Ti)、铝(Al)、铝合金和铜(Cu)等金属中的一种或者多种的组合。该第一栅极102和第二栅极108的材料还可以包括氧化铟锡(ITO)、铝掺杂氧化锌(AZO)和硼掺杂氧化锌(BZO)等透明导电材料中的一种或者多种的组合。该第一栅极102和第二栅极108可以分别为单层结构，也可以分别为双层结构。该双层结构的第一栅极102和第二栅极108可以分别为金属和透明导电材料构成的复合导电层。
例如，该第一栅极102和第二栅极108的厚度可以分别为50nm～300nm，例如，该第一栅极102的厚度可以为50nm、100nm、200nm或者300nm；该第二栅极108的厚度可以为50nm、100nm、200nm或者300nm。
例如，可以采用磁控溅射、电子束蒸发或者热蒸发等方法形成金属材料的第一栅极，也可以采用磁控溅射或光学镀膜等方法形成透明导电材料的第一栅极。
例如，该第一栅绝缘层103和第二栅绝缘层107的材料可以分别为氧化硅(SiO 2)、氮化硅(SiN x)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化钽(Ta 2O 5)和氧化锆(ZrO 2)中的一种或多种的组合。
例如，该第一栅绝缘层103和第二栅绝缘层107的厚度可以分别为5nm～400nm，例如，该第一栅绝缘层103的厚度可以为50nm、100nm、150nm、200nm、250nm或者300nm，该第二栅绝缘层107的厚度可以为50nm、100nm、150nm、200nm、250nm或者300nm。
例如，可以采用等离子体增强化学气相淀积(PECVD)的方法沉积氧化硅(SiO 2)或者氮化硅(SiN x)等氧化物绝缘材料以形成第一栅绝缘层103和第二栅绝缘层107，或者，也可以通过旋涂有机绝缘材料等方法形成第一栅绝缘层103和第二栅绝缘层107。
例如，如图2所示，在第二栅极108的远离衬底基板101的一侧设置有层间绝缘层109，源漏电极层110设置在层间绝缘层109的远离衬底基板101的一侧，第二过孔结构113依次贯穿层间绝缘层109、第二栅绝缘层107和部分第一绝缘层105。
例如，在第一栅极102和第二栅极108之间具有第一栅绝缘层103、第一有源层104、第一绝缘层105、第二有源层106和第二栅绝缘层107，从而使得第一栅极102和第二栅极108之间间隔的距离较大，且间隔的具有绝缘性质的膜层的数量较多，从而使得第一栅极102的电场和第二栅极108的电场之间不容易串扰。
例如，图2中双栅极和双有源层的结构，使得薄膜晶体管的开态电流成倍增加，且相对于形成两个完整的薄膜晶体管，减少了一次形成源漏电极层的工艺步骤，从而使得所采用的掩膜板的数量显著减少，从而降低了生产成本，且在第二有源层106和源漏电极层110之间具有第二栅绝缘层107和层间绝缘层109，这样在形成源漏电极层时，不会对第二有源层106和第一有源层104造成刻蚀损伤，使得薄膜晶体管100的稳定性显著提升，同时由于第一栅极102和第二栅极108分别控制第一有源层104和第二有源层106，从而提高了第一栅极102和第二栅极108的控制能力，使得能确保开态电流成倍提升的情况下， 保证薄膜晶体管101的特性。相对于图1中的结构，图2中薄膜晶体管的开态电流是图1中薄膜晶体管的开态电流的2倍。
例如，如图2所示，在源漏电极层110的远离衬底基板101的一侧设置有钝化层111，该钝化层111可以防止外界杂质或者水汽进入薄膜晶体管100，从而影响薄膜晶体管的性能。
例如，图3为本公开一实施例提供的再一种薄膜晶体管的截面结构示意图，如图3所示，第二过孔结构113贯穿层间绝缘层109和部分第二栅绝缘层107，源漏电极层110通过第二过孔结构113与第二有源层106的远离衬底基板101的表面直接接触。图3中的结构可以使得第二有源层106将第一过孔结构116完全填充，以保证第二有源层106不容易在第一过孔结构116中断裂，还可以使得形成的第二过孔结构113的深度变浅，使得第二过孔结构113更容易形成。
例如，形成源漏电极层110时会采用干刻工艺，执行干刻工艺时需要采用还原性气体，当第一有源层104和第二有源层106的材料为金属氧化物半导体材料时，可以先采用还原性气体使得第二有源层106的远离衬底基板101的部分被还原成金属单质，从而使得第二有源层106的电阻率变小，进而使得第一有源层104和第二有源层106电连接后整体的电阻变小，即可以不用增加新的设备和材料以减小第一有源层104和第二有源层106连接时的电阻。
例如，在图3中，源漏电极层110的与第二有源层106接触的表面在衬底基板101上的正投影与第一过孔结构116在衬底基板101上的正投影至少部分重叠，这样可以使得电极结构更紧凑，更有利于提高开态电流。如果源极110a向左侧偏移，漏极110b向右侧偏移，则难以表现出薄膜晶体管100的特性。图3中的结构可以增大源漏电极层110与第二有源层106的接触面积，以实现源漏电极层110与第一有源层104和第二有源层106电连接。
例如，该源漏电极层110的材料和厚度可以参见上述对于图2的相关描述，在此不再赘述。
例如，图4为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图，如图4所示，该薄膜晶体管100还包括第三有源层112，该第三有源层112设置在第二栅极108的远离衬底基板101的一侧，且第三有源层112和源漏电极层110电连接，层间绝缘层109设置在第三有源层112和第二栅极108之间。例如，在图4中，源漏电极层110搭接在第三有源层112的两侧，即源极110a搭接在第三有源层112的左侧，漏极110b搭接在第三有源层112的右侧，且源漏电极层110通过第二过孔结构113与第一有源层104和第二有源层106电连接。该第三有源层112的增加使得薄膜晶体管的开态电流进一步增加，相对于图1中的结构，图4中薄膜晶体管的开态电流是图1中薄膜晶体管的开态电流的3倍。
例如，图5为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图，如图5所示，第一有源层104包括层叠设置的第一子有源层104a和第二子有源层104b，第二有 源层106包括层叠设置的第三子有源层106a和第四子有源层106b。在一个示例中，还可以是第一有源层104包括层叠设置的第一子有源层104a和第二子有源层104b，第二有源层106为单层结构。在又一个示例中，第二有源层106包括层叠设置的第三子有源层106a和第四子有源层106b，第一有源层104为单层结构。
例如，该第一子有源层104a和第二子有源层104b的材料相同或者不同，该第一子有源层104a的材料为氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铟锌(IZO)、铝掺杂氧化锌(AZO)、硼掺杂氧化锌(BZO)、镁掺杂氧化锌(MZO)、氧化锌锡(ZTO)、氧化铟镓锌(IGZO)、氧化铟锡锌(ITZO)、氧化镓锌(GZO)、氧化铟锡(ITO)、氧化铪铟锌(HIZO)、氧化锡(SnO 2)、氧化亚锡(SnO)和氧化亚铜(Cu 2O)中的一种，该第二子有源层104b的材料为上述金属氧化物中的一种或者上述材料中不同于第一子有源层104a的材料的另一种。
例如，第一子有源层104a用于阻止元素的扩散，例如，阻止第一栅极102中的元素扩散至第二子有源层104b，第二子有源层104b的载流子浓度大于第一子有源层104a的载流子浓度，第二子有源层104b的带隙小于第一子有源层104a的带隙，第二子有源层104b主要用于传输载流子。
例如，该第三子有源层106a和第四子有源层106b的材料相同或者不同，该第三子有源层106a的材料为氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铟锌(IZO)、铝掺杂氧化锌(AZO)、硼掺杂氧化锌(BZO)、镁掺杂氧化锌(MZO)、氧化锌锡(ZTO)、氧化铟镓锌(IGZO)、氧化铟锡锌(ITZO)、氧化镓锌(GZO)、氧化铟锡(ITO)、氧化铪铟锌(HIZO)、氧化锡(SnO 2)、氧化亚锡(SnO)和氧化亚铜(Cu 2O)中的一种，该第四子有源层106b的材料为上述金属氧化物中的一种或者上述材料中不同于第三子有源层106a的材料的另一种。
例如，第四子有源层106b用于阻止元素的扩散，例如，阻止第二栅极108中的元素扩散至第三子有源层106a，第三子有源层106a的载流子浓度大于第四子有源层106b的载流子浓度，第三子有源层106a的带隙小于第四子有源层106b的带隙，第三子有源层106a主要用于传输载流子。
例如，根据图5，需要说明的是，在图4所示的结构中，第三有源层112也可以包括层叠设置的第五子有源层和第六子有源层，第五子有源层和第六子有源层的材料相同或者不同，第五子有源层和第六子有源层的材料可以参见上述关于第一子有源层104a和第二子有源层104b的相关描述，在此不再赘述。
需要说明的是，第一子有源层104a、第二子有源层104b、第三子有源层106a、第四子有源层106b、第五子有源层和第六子有源层的材料还可以是硅基材料或者有机半导体材料，该硅基材料或者有机半导体材料可以参见上述中的相关描述，在此不再赘述。
例如，图6为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图，如图6所示，该薄膜晶体管100包括栅极114，该栅极114在第一有源层104和第二有源层106之间，即该栅极114在第一有源层104所在层和第二有源层106所在层之间，该栅极114配置为同时控制第一有源层104和第二有源层106，从而使得薄膜晶体管100的结构变得简单，同时可以使得薄膜晶体管100的开态电流成倍提升。
需要说明的是，第二有源层106所在层不包括第二有源层106位于第二过孔结构中的部分。
例如，如图6所示，在栅极114的远离第一绝缘层105的一侧设置有栅绝缘层115，第一过孔结构116同时贯穿第一绝缘层105和栅绝缘层115，第二有源层106通过第一过孔结构116与第一有源层104电连接。
例如，如图6所示，在第二有源层106和源漏电极层110之间设置有第二绝缘层118，第二过孔结构113贯穿该第二绝缘层118，源漏电极层110通过第二过孔结构113与第二有源层106电连接，在图6中，第二有源层106将第一过孔结构116填充完全，源漏电极层110没有延伸至第一过孔结构116中，但是本公开的实施例不限于此，源漏电极层110可以参照图2中的结构延伸至第一过孔结构116中。
例如，图7为本公开一实施例提供的又一种薄膜晶体管的截面结构示意图，如图7所示，源漏电极层110和第二栅极108设置在同一层，在第二栅极108的靠近衬底基板101的一侧设置有层间绝缘层109，第二过孔结构113依次贯穿层间绝缘层109、第二栅绝缘层107和部分第一绝缘层105。
例如，如图7所示，在源漏电极层100和层间绝缘层109的远离衬底基板101的一侧设置有钝化层111，该钝化层111可以防止外界杂质或者水汽进入薄膜晶体管100，从而影响薄膜晶体管的性能。
本公开至少一实施例还提供一种阵列基板，该阵列基板包括上述任一实施例中的薄膜晶体管，例如，图8为本公开一实施例提供的阵列基板的框图，该阵列基板200包括薄膜晶体管100。该阵列基板可以用于显示装置，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例还提供一种薄膜晶体管的制备方法，该制备方法包括：提供衬底基板；在衬底基板上依次形成第一有源层、第一绝缘层和第二有源层，其中，第一有源层通过位于第一绝缘层中的第一过孔结构与第二有源层接触，第一有源层与第二有源层未接触的部分通过第一绝缘层间隔开。
例如，图9为本公开一实施例提供的一种薄膜晶体管的制备方法的流程图，如图9所示，该制备方法包括以下步骤。
S11：提供衬底基板。
S12：在衬底基板上形成第一有源层。
S13：在第一有源层的远离衬底基板的一侧施加第一绝缘层薄膜。
S14：对第一绝缘层薄膜进行图案化以形成具有第一过孔结构的第一绝缘层。
S15：在第一绝缘层的远离衬底基板的一侧形成第二有源层，其中，第二有源层通过第一过孔结构与第一有源层接触，第一有源层与第二有源层未接触的部分通过第一绝缘层间隔开。
例如，图10A-10E为本公开一实施例提供的一种薄膜晶体管的制备方法的过程图。
如图10A所示，提供衬底基板101，该衬底基板101采用刚性材料或者柔性材料。例如，刚性材料包括刚性玻璃和硅片中的一种。柔性材料包括聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚酰亚胺中和柔性玻璃中的一种。
如图10B所示，在衬底基板101上形成第一有源层104。例如，该第一有源层104的材料可以为硅基材料，或者金属氧化物半导体材料，或者为有机半导体材料。
例如，当第一有源层104的材料为金属氧化物半导体材料时，该金属氧化物半导体材料包括氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铟锌(IZO)、铝掺杂氧化锌(AZO)、硼掺杂氧化锌(BZO)、镁掺杂氧化锌(MZO)、氧化锌锡(ZTO)、氧化铟镓锌(IGZO)、氧化铟锡锌(ITZO)、氧化镓锌(GZO)、氧化铟锡(ITO)、氧化铪铟锌(HIZO)和氧化锡(SnO 2)等n型半导体材料，以及氧化亚锡(SnO)和氧化亚铜(Cu 2O)等p型半导体材料。例如，可以采用磁控溅射、反应溅射、阳极氧化或旋涂等方法形成金属氧化物半导体材料的第一有源层104。
例如，该第一有源层104的材料也可以为硅、锗、硅锗混合材料等。可以采用磁控溅射或旋涂等方法形成上述半导体材料的第一有源层104。
例如，该第一有源层104的材料也可以为有机半导体材料，该有机半导体材料包括并五苯、三苯基胺、富勒烯、酞箐、聚噻吩、聚苯胺、聚吡咯等，可以采用旋涂的方式形成上述有机半导体材料。
例如，该第一有源层104的厚度为5nm～200nm，例如，该第一有源层104的厚度为50nm、100nm、150nm、或者200nm等。
如图10C所示，在第一有源层104的远离衬底基板101的一侧施加第一绝缘层薄膜105’。
如图10D所示，对第一绝缘层薄膜105’进行图案化以形成具有第一过孔结构116的第一绝缘层105。
例如，对第一绝缘层薄膜105’进行图案化包括在第一绝缘层薄膜105’上涂覆光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第一绝缘层薄膜105’进行处理以形成具有第一过孔结构116的第一绝缘层105。
例如，该第一绝缘层105的材料包括氧化硅、氮化硅、氧化铝、氧化铪、氧化钽和氧化锆中的一种或者多种。
例如，该第一绝缘层105的厚度为5nm～400nm，例如为50nm、100nm、200nm、300nm或者400nm。
如图10E所示，在第一绝缘层105的远离衬底基板101的一侧形成第二有源层106。该第二有源层106的材料的选择范围和第一有源层104的材料的选择范围相同，且第二有源层106的厚度为5nm～200nm，例如，该第二有源层106的厚度为50nm、100nm、150nm、或者200nm等。
如图10E所示，第二有源层106通过位于第一绝缘层105中的第一过孔结构116与第一有源层104接触，第一有源层104与第二有源层106未接触的部分通过第一绝缘层105间隔开。
例如，该第一有源层104通过位于第一绝缘层105中的第一过孔结构116与第二有源层106接触并实现电连接。
例如，该第一过孔结构116的个数可以为一个或者多个。在图10D所示的薄膜晶体管的截面结构中，第一过孔结构116的个数为两个，两个第一过孔结构116相互间隔开，两个第一过孔结构116的靠近衬底基板101一侧的宽度之和小于第一有源层104的水平方向的最大宽度，且小于第二有源层106的水平方向的最大宽度。
例如，每个第一过孔结构116的靠近衬底基板101的一侧和限定第一过孔结构116的侧壁上都覆盖有第二有源层106，且每个第一过孔结构116都未被第二有源层106填满。
例如，如图10E所示，每个第一过孔结构116在衬底基板101上的正投影均小于第一有源层104在衬底基板101上的正投影，且小于第二有源层106在衬底基板101上的正投影。每个第一过孔结构116在衬底基板101上的正投影之和小于第一有源层104在衬底基板101上的正投影，且小于第二有源层106在衬底基板101上的正投影，当然，本公开的实施例也不限于此，每个第一过孔结构116在衬底基板101上的正投影还可以大于或者等于第一有源层104在衬底基板101上的正投影。
例如，该第一有源层104和第二有源层106的材料可以相同或者不同。第一有源层104和第二有源层106的材料可以均为硅基材料，或者均为金属氧化物半导体材料，或者均为有机半导体材料。第一有源层104的材料为硅基材料、金属氧化物半导体材料和有机半导体材料中的一种，第二有源层106的材料为不同于第一有源层104的材料的另外两种材料中的一种。
例如，图11为本公开一实施例提供的一种薄膜晶体管的制备方法的流程图，如图11所示，该制备方法包括：
S21：提供衬底基板。
S22：在衬底基板上形成第一栅极。
例如，在衬底基板上施加第一栅极薄膜，在第一栅极薄膜上涂覆光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第一栅极薄膜进行图案化以形成第一栅极。
例如，光刻胶的涂覆可以采用旋涂、刮涂或者辊涂的方式。
例如，该第一栅极的材料包括钼(Mo)、铬(Cr)、钛(Ti)、铝(Al)、铝合金和铜(Cu)等金属中的一种或者多种的组合。该第一栅极的材料还可以包括氧化铟锡(ITO)、铝掺杂氧化锌(AZO)和硼掺杂氧化锌(BZO)等透明导电材料中的一种或者多种的组合。该第一栅极可以为单层结构，也可以为双层结构。该双层结构的第一栅极可以为金属和透明导电材料构成的复合导电层。
例如，在一个示例中，该第一栅极的材料可以为铜与其他金属的组合，例如，铜/钼(Cu/Mo)、铜/钛(Cu/Ti)、铜/钼钛合金(Cu/MoTi)、铜/钼钨合金(Cu/MoW)、铜/钼铌合金(Cu/MoNb)等；该第一栅极的材料也可以为铬基金属或铬与其他金属的组合，例如，铬/钼(Cr/Mo)、铬/钛(Cr/Ti)、铬/钼钛合金(Cr/MoTi)等。
例如，该第一栅极的厚度可以分别为50nm～300nm，该第一栅极102的厚度为50nm、 100nm、200nm或者300nm等。
例如，可以采用磁控溅射、电子束蒸发或者热蒸发等方法形成第一栅极薄膜，也可以采用磁控溅射或光学镀膜等方法形成第一栅极薄膜。
S23：在第一栅极上形成第一栅绝缘层。
例如，在第一栅极上沉积第一栅绝缘层薄膜，并对第一栅绝缘层薄膜进行图案化以形成第一栅绝缘层。
例如，第一栅绝缘层可以采用氧化硅(SiO x)、氮化硅(SiN x)、氧化铝(Al 2O 3)、氮化铝(AlN)等绝缘材料中的至少之一形成，并通过等离子体增强化学气相淀积(PECVD)的方法形成，也可以通过旋涂方法形成有机绝缘材料以形成第一栅绝缘层。
S24：在第一栅绝缘层上形成第一有源层。
例如，采用磁控溅射的方式在第一栅绝缘层上施加第一有源层薄膜，在第一有源层薄膜上形成光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第一有源层薄膜进行图案化以形成第一有源层。
例如，该第一有源层的材料可以参见上述关于薄膜晶体管的实施例中的相关描述，在此不再赘述。
S25：在第一有源层上形成第一绝缘层。
例如，在第一有源层的远离衬底基板的一侧施加第一绝缘层薄膜，对第一绝缘层薄膜进行图案化以形成具有第一过孔结构的第一绝缘层。
例如，对第一绝缘层薄膜进行图案化包括在第一绝缘层薄膜上涂覆光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第一绝缘层薄膜进行处理以形成具有第一过孔结构的第一绝缘层。
S26：在第一绝缘层上形成第二有源层。
例如，采用磁控溅射的方式在第一绝缘层上施加第二有源层薄膜，在第二有源层薄膜上形成光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第二有源层薄膜进行图案化以形成第二有源层。
例如，第二有源层填充一部分第一过孔结构，即第二有源层未将第一过孔结构填充完全。
例如，该第二有源层的材料可以参见上述关于薄膜晶体管的实施例中的相关描述，在此不再赘述。
S27：在第二有源层上形成第二栅绝缘层。
例如，在第二有源层的远离衬底基板的一侧施加第二栅绝缘层薄膜，对第二栅绝缘层薄膜进行图案化以形成第二栅绝缘层。
例如，第二栅绝缘层可以采用氧化硅(SiO x)、氮化硅(SiN x)、氧化铝(Al 2O 3)、氮化铝(AlN)等绝缘材料中的至少之一形成，可以通过等离子体增强化学气相淀积(PECVD)的方法形成，也可以通过旋涂方法形成有机绝缘材料以形成第二栅绝缘层。
S28：在第二栅绝缘层上形成第二栅极。
例如，在第二栅绝缘层的远离衬底基板的一侧施加第二栅极薄膜，在第二栅极薄膜上形成光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对第二栅极薄膜进行图案化以形成第二栅极。
例如，光刻胶的涂覆可以采用旋涂、刮涂或者辊涂的方式。
例如，该第二栅极的材料包括钼(Mo)、铬(Cr)、钛(Ti)、铝(Al)、铝合金和铜(Cu)等金属中的一种或者多种的组合。该第二栅极的材料还可以包括氧化铟锡(ITO)、铝掺杂氧化锌(AZO)和硼掺杂氧化锌(BZO)等透明导电材料中的一种或者多种的组合。该第二栅极可以为单层结构，也可以为双层结构。该双层结构的第二栅极可以为金属和透明导电材料构成的复合导电层。
例如，在一个示例中，该第二栅极的材料可以为铜与其他金属的组合，例如，铜/钼(Cu/Mo)、铜/钛(Cu/Ti)、铜/钼钛合金(Cu/MoTi)、铜/钼钨合金(Cu/MoW)、铜/钼铌合金(Cu/MoNb)等；该第二栅极的材料也可以为铬基金属或铬与其他金属的组合，例如，铬/钼(Cr/Mo)、铬/钛(Cr/Ti)、铬/钼钛合金(Cr/MoTi)等。
例如，该第二栅极的厚度可以分别为50nm～300nm，该第二栅极的厚度为50nm、100nm、200nm或者300nm等。
例如，可以采用磁控溅射、电子束蒸发或者热蒸发等方法形成第二栅极薄膜，也可以采用磁控溅射或光学镀膜等方法形成第二栅极薄膜。
S29：在第二栅极上形成层间绝缘层。
例如，在第二栅极的远离衬底基板的一侧施加层间绝缘层薄膜，在层间绝缘层薄膜上涂覆光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对层间绝缘层薄膜、第二栅绝缘层进行图案化处理，以形成层间绝缘层以及贯穿层间绝缘层、第二栅绝缘层和部分第一绝缘层的第二过孔结构。
例如，该层间绝缘层的材料包括氧化硅(SiO x)、氮化硅(SiN x)、氧化铝(Al 2O 3)、氮化铝(AlN)等绝缘材料中的至少之一，并通过等离子体增强化学气相淀积(PECVD)的方法形成层间绝缘层，也可以通过旋涂方法形成有机绝缘材料以形成层间绝缘层。
S30：在层间绝缘层上形成源漏电极层。
例如，采用磁控溅射的方式在层间绝缘层的远离衬底基板的一侧施加源漏电极层薄膜，在源漏电极层薄膜上形成光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对源漏电极层薄膜进行图案化以形成源漏电极层，该源漏电极层的材料和厚度可以参见上述中的相关描述，在此不再赘述。
例如，第一有源层和第二有源层连接时的电阻较大，形成源漏电极层时会采用干刻工艺，执行干刻工艺时需要采用还原性气体，当第一有源层和第二有源层的材料为金属氧化物半导体材料时，可以先采用还原性气体使得第二有源层的暴露于第二过孔结构的部分被还原成金属单质，从而使得第二有源层的电阻率变小，进而使得第一有源层和第二有源层电连接后整体的电阻变小，即可以不用增加新的设备和材料减小第一有源层和第二有源层连接时的电阻。
S31：在源漏电极层的远离衬底基板的一侧形成钝化层。
例如，可以采用等离子体化学气相沉积的方式形成钝化层，钝化层的材料为氮化硅(SiN x)、氧化硅(SiO x)、丙烯酸类树脂等，该钝化层可以防止外界杂质或者水汽进入薄膜晶体管，从而影响薄膜晶体管的性能。
例如，也可以在源漏电极层的远离衬底基板的一侧沉积钝化层薄膜，在钝化层薄膜上涂覆光刻胶，采用曝光、显影、刻蚀和剥离光刻胶等工艺对钝化层薄膜进行处理以形成钝化层。
例如，图12A-12K为本公开一实施例提供的一种薄膜晶体管的制备方法的过程图，该制备方法包括：
如图12A所示，提供衬底基板101，该衬底基板101的材料可以参见上述中的相关描述，在此不再赘述。
如图12B所示，在衬底基板101上形成第一栅极102。形成该第一栅极102的具体过程为：在衬底基板101上形成第一栅极材料层，并对第一栅极材料层进行图案化以形成第一栅极102。
例如，该第一栅极102的材料和形成方法可以参见上述中的相关描述，在此不再赘述。
如图12C所示，在第一栅极102上形成第一栅绝缘层103，该第一栅绝缘层103的材料和厚度可以参见上述中的相关描述，在此不再赘述。
例如，可以采用等离子体增强化学气相淀积(PECVD)的方法沉积氧化硅(SiO 2)或者氮化硅(SiN x)以形成第一栅绝缘层103，或者，也可以通过旋涂有机绝缘材料等方法形成第一栅绝缘层103。
如图12D所示，在第一栅绝缘层103上形成第一有源层104。
例如，在第一栅绝缘层103上沉积第一有源层材料并进行图形化以形成第一有源层104，该第一有源层104的材料、形成方法和厚度可以参见上述中的相关描述，在此不再赘述。
如图12E所示，在第一有源层104上形成第一绝缘层105，该第一绝缘层105中形成有第一过孔结构116。该第一绝缘层105的材料以及第一过孔结构116的形成方法可以参见上述中的相关描述，在此不再赘述。
如图12F所示，在第一绝缘层105上形成第二有源层106。第一有源层104通过位于第一绝缘层105中的第一过孔结构116与第二有源层106接触，第一有源层104与第二有源层106未接触的部分通过第一绝缘层105间隔开。
例如，在图形化后的第一绝缘层105上沉积第二有源层材料并图形化以形成第二有源层106，例如，第一过孔结构116的个数为多个，例如为两个，第一绝缘层105中的每个第一过孔结构116的底部和侧壁都覆盖有第二有源层106，且每个第一过孔结构116都未被第二有源层106填满。
例如，第二有源层106的材料和结构可以参见上述中的相关描述，在此不再赘述。
如图12G所示，在第二有源层106上形成第二栅绝缘层107。
例如，第二栅绝缘层107的形成方法、材料可以参见上述关于第一栅绝缘层103的相关描述，在此不再赘述。
如图12H所示，在第二栅绝缘层107上形成第二栅极108。
例如，该第二栅极108的材料和形成方法可以参见上述中的相关描述，在此不再赘述。
如图12I所示，在第二栅极108上形成层间绝缘层109。
例如，该层间绝缘层109和第二栅绝缘层107中形成有第二过孔结构113，该层间绝缘层109的材料可以参见上述中的相关描述，在此不再赘述。
如图12J所示，在层间绝缘层109上形成源漏电极层110。
例如，在层间绝缘层109上和第二过孔结构113中沉积导电材料并图形化以形成源漏电极层110(包括源极110a和漏极110b)，该源极110a和漏极110b同时与第一有源层104和第二有源层106电连接。
例如，源漏电极层110通过第二过孔结构113与第二有源层106电连接，在一个示例中，第一过孔结构116在衬底基板101上的正投影和第二过孔结构113在衬底基板101上的正投影至少部分重叠，且至少部分源漏电极层110延伸至第一过孔结构116中。
例如，在一个示例中，第二过孔结构113的一部分形成在第一过孔结构116中，且第二过孔结构113在衬底基板101上的正投影位于第一过孔结构116在衬底基板101上的正投影之中。
例如，该源漏电极层110的材料可以分别包括钼(Mo)、铬(Cr)、钛(Ti)、铝(Al)、铝合金和铜(Cu)等金属中的一种或者多种的组合。
例如，该源漏电极层110的材料为铜基金属。铜金属具有电阻率低、导电性好的特点，因而可以提高源极、漏极的信号传输速率，提高显示质量。
例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
例如，该源漏电极层110的厚度可以为200-400nm，例如，可以为200nm、230nm、250nm、300nm、350nm、380nm以及400nm。
例如，在层间绝缘层109上沉积源漏电极层材料，在源漏电极层材料上涂覆光刻胶，并通过曝光、显影、刻蚀和剥离光刻胶等工艺对源漏电极层材料进行图形化以形成源漏电极层，例如，还可以采用还原性气体以干刻的方式形成源漏电极层。
如图12K所示，在源漏电极层的远离衬底基板101的一侧形成钝化层111。
例如，可以采用等离子体化学气相沉积的方式形成钝化层111。
例如，相比于形成图2中薄膜晶体管的过程图，在形成图3所示的薄膜晶体管的结构时，每个第一过孔结构116都被第二有源层106填满，以使得第二有源层106将第一过孔结构116完全填充，以保证第二有源层106不容易在第一过孔结构116中断裂，还可以使得形成的第二过孔结构113的深度变浅，使得第二过孔结构113更容易形成。形成的第二过孔结构113贯穿层间绝缘层109和部分第二栅绝缘层107，源漏电极层110通过第二过孔结构113与第二有源层106的远离衬底基板101的表面直接接触。
例如，相比于形成图2中薄膜晶体管的过程图，在形成图4所示的薄膜晶体管的结构时，该制备方法还包括：在形成层间绝缘层109之后，在形成源漏电极层110之前或者之后，在层间绝缘层109的远离衬底基板101的一侧形成第三有源层112，该第三有源层112和源漏电极层110电连接，该层间绝缘层109设置在第三有源层112和第二栅极108之间。例如，结合图4，源漏电极层110搭接在第三有源层112的两侧，即源极110a搭接在第三有源层112的左侧，漏极110b搭接在第三有源层112的右侧，且源漏电极层110通过第二过孔结构113与第一有源层104和第二有源层106电连接。该第三有源层112的增加使得薄膜晶体管的开态电流进一步增加，相对于图1中的结构，图4中薄膜晶体管的开态电流是图1中薄膜晶体管的开态电流的3倍。
例如，相比于形成图2中薄膜晶体管的过程图，在形成图5所示的薄膜晶体管的结构时，该制备方法中形成的第一有源层104包括层叠设置的第一子有源层104a和第二子有源层104b，第二有源层106包括层叠设置的第三子有源层106a和第四子有源层106b。第一子有源层104a、第二子有源层104b、第三子有源层106a和第四子有源层106b的材料、制备方法可以参见上述中的相关描述，在此不再赘述。
例如，相比于形成图2中薄膜晶体管的过程图，在形成图6所示的薄膜晶体管的结构时，该制备方法中只形成一个栅极114，该栅极114形成在第一有源层104所在层和第二有源层106所在层之间，该栅极114配置为同时控制第一有源层104和第二有源层106，从而使得薄膜晶体管100的结构变得简单，同时可以使得薄膜晶体管100的开态电流成倍提升。
例如，在形成图6所示的薄膜晶体管时，在栅极114的远离第一绝缘层105的一侧形成有栅绝缘层115，第一过孔结构116同时贯穿第一绝缘层105和栅绝缘层115，第二有源层106通过第一过孔结构116与第一有源层104电连接。在第二有源层106和源漏电极层110之间形成有第二绝缘层118，第二过孔结构113贯穿该第二绝缘层118，源漏电极层110通过第二过孔结构113与第二有源层106电连接。
例如，在形成图7所示的薄膜晶体管的结构时，该制备方法与图12A-12K所示过程的不同之处在于，在形成第二栅绝缘层107之后不直接形成第二栅极108，而是直接形成层间绝缘层109，在形成层间绝缘层109之后在同一工艺步骤中形成源漏电极层110和第二栅极108，且第二过孔结构113贯穿层间绝缘层109和第二栅绝缘层107。
例如，本公开的实施例提供的薄膜晶体管、阵列基板以及薄膜晶体管的制备方法，至少具有以下一项有益技术效果：
(1)本公开至少一实施例提供的薄膜晶体管，具有双有源层结构，使得电荷分别聚集在两个有源层的两个表面，从而使得聚集在有源层的表面的电荷的数量成倍地增加，从而使得薄膜晶体管的开态电流成倍地增加。
(2)本公开至少一实施例提供的薄膜晶体管，还包括第三有源层，该第三有源层使得薄膜晶体管的开态电流进一步增加。
(3)本公开至少一实施例提供的薄膜晶体管，当第一有源层和第二有源层的材料为 金属氧化物半导体材料时，可以先采用还原性气体使得第二有源层的暴露于第二过孔结构的部分被还原成金属单质，从而使得第二有源层电阻率变小，进而使得第一有源层和第二有源层电连接后整体的电阻变小，即可以不用增加新的设备和材料减小第一有源层和第二有源层连接时的电阻。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种薄膜晶体管，包括：
    衬底基板；
    依次层叠设置在所述衬底基板上的第一有源层、第一绝缘层和第二有源层；其中，
    所述第一有源层通过位于所述第一绝缘层中的第一过孔结构与所述第二有源层接触，所述第一有源层与所述第二有源层未接触的部分通过所述第一绝缘层间隔开。
  2. 根据权利要求1所述的薄膜晶体管，还包括源漏电极层，其中，所述源漏电极层与所述第一有源层和所述第二有源层电连接。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述源漏电极层通过第二过孔结构与所述第二有源层电连接，所述第一过孔结构在所述衬底基板上的正投影和所述第二过孔结构在所述衬底基板上的正投影至少部分重叠，且至少部分所述源漏电极层延伸至所述第一过孔结构中。
  4. 根据权利要求3所述的薄膜晶体管，还包括第一栅极和第二栅极，其中，
    所述第一栅极在所述第一有源层的靠近所述衬底基板的一侧，且在所述第一栅极和所述第一有源层之间设置有第一栅绝缘层；
    所述第二栅极在所述第二有源层的远离所述衬底基板的一侧，且在所述第二栅极和所述第二有源层之间设置有第二栅绝缘层。
  5. 根据权利要求4所述的薄膜晶体管，其中，在所述第二栅极的远离所述衬底基板的一侧设置有层间绝缘层，所述源漏电极层设置在所述层间绝缘层的远离所述衬底基板的一侧，所述第二过孔结构依次贯穿所述层间绝缘层、所述第二栅绝缘层和部分所述第一绝缘层。
  6. 根据权利要求5所述的薄膜晶体管，还包括第三有源层，其中，所述第三有源层设置在所述第二栅极的远离所述衬底基板的一侧，所述层间绝缘层设置在所述第三有源层和所述第二栅极之间，且所述第三有源层和所述源漏电极层电连接。
  7. 根据权利要求3所述的薄膜晶体管，还包括栅极，其中，所述栅极在所述第一有源层和所述第二有源层之间。
  8. 根据权利要求7所述的薄膜晶体管，其中，在所述栅极的远离所述第一绝缘层的一侧设置有栅绝缘层，所述第一过孔结构同时贯穿所述第一绝缘层和所述栅绝缘层。
  9. 根据权利要求8所述的薄膜晶体管，其中，在所述第二有源层和所述源漏电极层之间设置有第二绝缘层，所述第二过孔结构贯穿所述第二绝缘层。
  10. 根据权利要求3所述的薄膜晶体管，其中，所述源漏电极层和所述第二栅极设置在同一层，在所述第二栅极的靠近所述衬底基板的一侧设置有层间绝缘层，所述第二过孔结构依次贯穿所述层间绝缘层、所述第二栅绝缘层和部分所述第一绝缘层。
  11. 根据权利要求1-10中任一项所述的薄膜晶体管，其中，所述第一有源层包括层叠设置的第一子有源层和第二子有源层，和/或所述第二有源层包括层叠设置的第三子有 源层和第四子有源层。
  12. 一种阵列基板，包括权利要求1-11中任一项所述的薄膜晶体管。
  13. 一种薄膜晶体管的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成第一有源层；
    在所述第一有源层的远离所述衬底基板的一侧施加第一绝缘层薄膜；
    对所述第一绝缘层薄膜进行图案化以形成具有第一过孔结构的第一绝缘层；
    在所述第一绝缘层的远离所述衬底基板的一侧形成第二有源层，
    其中，所述第二有源层通过所述第一过孔结构与所述第一有源层接触，所述第一有源层与所述第二有源层未接触的部分通过所述第一绝缘层间隔开。
  14. 根据权利要求13所述的制备方法，还包括形成源漏电极层，其中，所述源漏电极层与所述第一有源层和所述第二有源层电连接。
  15. 根据权利要求14所述的制备方法，其中，所述源漏电极层通过第二过孔结构与所述第二有源层电连接，所述第一过孔结构在所述衬底基板上的正投影和所述第二过孔结构在所述衬底基板上的正投影至少部分重叠，且至少部分所述源漏电极层延伸至所述第一过孔结构中。
  16. 根据权利要求13-15中任一项所述的制备方法，还包括：
    在所述第一有源层的靠近所述衬底基板的一侧形成第一栅极；
    在所述第一栅极和所述第一有源层之间形成第一栅绝缘层；
    在所述第二有源层的远离所述衬底基板的一侧形成第二栅极；
    在所述第二栅极和所述第二有源层之间形成第二栅绝缘层。
PCT/CN2021/128401 2021-05-28 2021-11-03 薄膜晶体管及其制备方法、阵列基板 WO2022247148A1 (zh)

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