WO2022242002A1 - 建模方法、装置、计算机设备及存储介质 - Google Patents

建模方法、装置、计算机设备及存储介质 Download PDF

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Publication number
WO2022242002A1
WO2022242002A1 PCT/CN2021/120533 CN2021120533W WO2022242002A1 WO 2022242002 A1 WO2022242002 A1 WO 2022242002A1 CN 2021120533 W CN2021120533 W CN 2021120533W WO 2022242002 A1 WO2022242002 A1 WO 2022242002A1
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Prior art keywords
tsv
substructure
bump
die
simulation
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French (fr)
Inventor
翁坤
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/650,862 priority Critical patent/US12204841B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00—Three-dimensional [3D] modelling for computer graphics

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a modeling method, device, computer equipment and storage medium.
  • TSV through silicon via
  • Through silicon via technology forms a through silicon via structure between two adjacent semiconductor chips (also referred to as bare chips, Dies) to realize electrical connection between two adjacent dies.
  • the double rate (DDR, Double Data Rate) product of Dynamic Random Access Memory will use through-silicon via (TSV, through silicon via) technology to connect two or more DDR chips stack up.
  • TSV through silicon via
  • the through-silicon via structure is formed between two adjacent DDR chips to realize the electrical connection of adjacent DDR chips and form a 3D stack structure, thereby reducing the additional loss caused by packaging.
  • the present application provides a modeling method, including: obtaining the electrical parameters of each substructure in the TSV structure; obtaining an electrical topological network model according to the connection relationship of each TSV structure between two dies ; Obtain a simulation model according to the electrical topology network model and the electrical parameters for simulation.
  • Another aspect of the present application provides a computer device, including a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.
  • Another aspect of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.
  • Fig. 1 is the flowchart of the modeling method provided in one embodiment of the present application.
  • FIG. 2 is a schematic diagram of the internal structure of a three-dimensional integrated circuit provided in an embodiment of the present application
  • Fig. 3 is the flowchart of the modeling method provided in a specific embodiment of the present application.
  • FIG. 4 is a cross-sectional view of a raised pad substructure provided in an embodiment of the present application.
  • FIG. 5 is a cross-sectional view of a TSV structure provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an electrical topology network model provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a first circuit model provided in an embodiment of the present application.
  • FIG. 8 is a flow chart of specific steps of step S130 provided in another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a second circuit model provided in an embodiment of the present application.
  • Fig. 10 is a structural block diagram of a modeling device provided in an embodiment of the present application.
  • first doping type becomes the second doping type
  • second doping type can be referred to as the first doping type
  • first doping type and the second doping type are different doping types, for example,
  • the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.
  • Embodiments of the application are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, as variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are to be expected.
  • embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed.
  • the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the application.
  • this application provides a modeling method, including the following steps:
  • Step S110 acquiring electrical parameters of each substructure in the TSV structure.
  • step S120 an electrical topology network model is obtained according to the connection relationship of each TSV structure between the two dies.
  • step S130 a simulation model is obtained according to the electrical topology network model and electrical parameters for simulation.
  • the modeling method in the above embodiment by obtaining the electrical parameters of each substructure in the TSV structure and the overall electrical topological network model of each TSV structure between two dies, according to the electrical topological network model and the electrical parameters The simulation model of the three-dimensional integrated circuit is obtained, so that the three-dimensional integrated circuit including the through-silicon via structure can be simulated, so as to know the influence of the through-silicon via structure on the entire three-dimensional integrated circuit.
  • step S110 referring to step S110 in FIG. 1 , the electrical parameters of each substructure in the TSV structure are acquired.
  • two or more dies may be included in a three-dimensional integrated circuit.
  • Each bare chip can be the same type of chip or different types of chips.
  • the bare chip can be a DRAM chip, and further, it can be a DDR chip.
  • Two of the dies are called the first die 30 and the second die 20 respectively.
  • Each substructure may include a bump substructure 11 and a TSV substructure 12 .
  • One end of the bump substructure 11 is electrically connected to the second die 20 .
  • the other end of the raised pad substructure 11 is electrically connected to one end of the through-silicon hole structure 12, and a through hole is opened on the first die 30 for the through-silicon hole structure 12 to pass through so as to connect the other end of the through-silicon hole structure 12 to the second end of the through-silicon hole structure 12.
  • a die 30 is electrically connected, and the electrical parameters include the electrical parameters of the bump substructure 11 and the electrical parameters of the TSV substructure 12 .
  • the TSV structure 10 may include a first metal layer 111 , a second metal layer 112 , a solder ball 113 , a third metal layer 114 and a fourth metal layer 121 stacked in sequence. It may be configured that the bump substructure 11 includes the first metal layer 111 to the third metal layer 114 , and the TSV substructure 12 includes the fourth metal layer 121 .
  • each layer in the TSV structure 10 may also be divided into other substructures different from the bump pad substructure 11 and the TSV substructure 12 according to actual requirements.
  • the second die 20 may include a second substrate layer 21 and a plurality of metal layers stacked in sequence.
  • the first metal layer 111 of the TSV structure 10 can be electrically connected to any metal layer in the second die 20 .
  • the second die 20 may include a fifth metal layer 22 , a sixth metal layer 23 , a seventh metal layer 24 and an eighth metal layer 25 sequentially stacked under the second substrate layer 21 .
  • the first metal layer 111 can be electrically connected to the eighth metal layer 25 , so that one end of the bump substructure 11 is electrically connected to the second die 20 . Since the third metal layer 114 is in contact with the fourth metal layer 121 , the other end of the bump substructure 11 is electrically connected to one end of the TSV substructure 12 .
  • the first die 30 may include a substrate layer 31 and a plurality of metal layers, and the plurality of metal layers are sequentially stacked under the substrate layer 31 .
  • a through hole is opened on the substrate layer 31 for the TSV structure 12 to pass through, and the fourth metal layer 121 of the TSV structure 10 can be electrically connected to any metal layer in the first die 30 .
  • the first die 30 may include a ninth metal layer 32 , a tenth metal layer 33 , an eleventh metal layer 34 , and a twelfth metal layer 35 sequentially stacked under the substrate layer 31 , and the fourth metal layer 121 It may be electrically connected to the tenth metal layer 33 , so that the other end of the TSV structure 12 is electrically connected to the first die 30 .
  • step S110 specifically includes steps S111 to S113.
  • Step S111 obtaining a schematic structural view of the TSV structure.
  • the operator can use input devices such as a mouse, a keyboard, and a touch screen to construct a schematic diagram of the structure of the through-silicon via structure 10 between die-to-die (Die-to-Die), so as to obtain the structure of the through-silicon via structure 10
  • the structural schematic diagram can be a three-dimensional schematic diagram or a planar schematic diagram.
  • the number of through-silicon via structures 10 between die and die may be one or multiple.
  • each TSV structure 10 may be the same or different. In the following, description will be made by taking the same TSV structures 10 as an example.
  • step S112 according to the structural schematic diagram of the TSV structure, the cross-sectional view of the material composition of each substructure in the TSV structure is obtained; the material composition cross-sectional view of the substructure includes material information and size information of the substructure.
  • the TSV structure 10 a cross-sectional view of the material composition of each substructure in the TSV structure 10 can be constructed.
  • the TSV structure 10 may include a pad substructure 11 and a TSV substructure 12 .
  • the cross-sectional view of the material composition of the bump substructure 11 and the material composition cross-sectional view of the TSV sub-structure 12 are respectively obtained.
  • the material composition profile of the bump substructure 11 includes material information and size information of the bump substructure 11
  • the material composition profile of the TSV substructure 12 includes material information and size information of the TSV substructure 12 .
  • the cross-sectional view of the material composition of the bump substructure 11 includes a first metal layer 111, a second metal layer 112, and solder balls stacked in sequence. 113 and the third metal layer 114 (not shown in FIG. 4 ).
  • the first metal layer 111 may include a first copper layer 1111 and a second copper layer 1112 .
  • a first insulating layer 27 may also be provided on the periphery of the bottom of the first copper layer 1111, and the first insulating layer 27 may include a first silicon nitride layer to play an isolation and insulating role.
  • the second die 20 may further include a first silicon oxide substrate 28 which may be located above the first insulating layer 27 and wrap the eighth metal layer 25 .
  • the second metal layer 112 may include a first nickel layer.
  • the solder ball 113 may include a tin-silver alloy layer.
  • the third metal layer 114 may include a second nickel layer. That is, the bump substructure 11 may include a first copper layer 1111 , a second copper layer 1112 , a first nickel layer, a tin-silver alloy layer and a second nickel layer stacked in sequence.
  • the sectional view of the material composition of the bump substructure 11 also includes size information of each layer, which is not shown in FIG. 4 .
  • the TSV structure 12 includes a fourth metal layer 121 , and the fourth metal layer 121 may include a third copper layer.
  • a second insulating layer 38 may also be provided on the periphery of the bottom of the fourth metal layer 121, and the second insulating layer 38 includes a second silicon nitride layer, which plays the role of isolation and insulation.
  • the first die 30 may further include a second silicon oxide substrate 37 , and the second silicon oxide substrate 37 may be located above the second insulating layer 38 and cover part of the sides of the fourth metal layer 121 .
  • the cross-sectional view of the material composition of the TSV structure 12 also includes size information of each layer, which is not shown in FIG. 5 .
  • Step S113 obtaining electrical parameters according to the material information and size information of each substructure.
  • the electrical parameters of each layer can be obtained according to the material information and size information of each layer of each substructure in the TSV structure 10, and then the electrical parameters of the substructure can be calculated according to the electrical parameters of each layer in the substructure.
  • the electrical parameters of the raised pad substructure 11 are obtained according to the material information of the first copper layer 1111, the second copper layer 1112, the first nickel layer, the tin-silver alloy layer, and the second nickel layer and the size information of each layer .
  • the electrical parameters of the third copper layer that is, the electrical parameters of the TSV structure 12 can also be obtained according to the material information and size information of the third copper layer.
  • the electrical parameters include resistance parameters, capacitance parameters, and inductance parameters.
  • the resistance parameters and the bumps of the bump pad substructure 11 can be obtained according to the material information of the first copper layer 1111, the second copper layer 1112, the first nickel layer, the tin-silver alloy layer, and the second nickel layer and the size information of each layer.
  • the resistance parameter of the through-silicon hole structure 12 and the capacitance parameter of the through-silicon hole structure 12 can be obtained according to the material information and size information of the third copper layer. Specifically, the width of the first copper layer 1111 is 8-12 ⁇ m, and the height is 2-6 ⁇ m.
  • the second copper layer 1112 has a width of 20-40 ⁇ m and a height of 2-6 ⁇ m.
  • the first nickel layer has a width of 20-40 ⁇ m and a height of 1-4 ⁇ m.
  • the tin-silver alloy layer has a width of 20-40 ⁇ m and a height of 4-9 ⁇ m.
  • the second nickel layer has a width of 20-40 ⁇ m and a height of 3-8 ⁇ m.
  • the third copper layer has a width of 4-8 ⁇ m and a height of 40-70 ⁇ m.
  • the electrical parameters of the bump pad substructure 11 and the TSV substructure 12 can be calculated according to the following formula.
  • formula (1) is a formula for calculating resistance parameters
  • formula (2) is a formula for calculating inductance parameters
  • formula (3) is a formula for calculating capacitance parameters.
  • the parameters in formulas (1) to (3) can be calculated according to the material information and size information of each layer in the raised pad substructure 11 and the through-silicon hole structure 12, and the formulas (1) to (3) can be used First calculate the resistance parameter, inductance parameter and capacitance parameter of each layer in each substructure respectively, and then calculate the resistance parameter, inductance parameter and capacitance parameter of each substructure according to the electrical parameters of each layer in the substructure.
  • ⁇ is the resistivity of the resistor
  • L is the length of the resistor
  • S is the cross-sectional area of the resistor.
  • ⁇ 0 is the magnetic permeability of the solenoid
  • N is the total number of turns of the solenoid
  • S is the cross-sectional area of the solenoid
  • L is the length of the solenoid.
  • ⁇ is the dielectric constant of the capacitor
  • A is the facing area between the two plates of the capacitor
  • d is the distance between the two plates of the capacitor.
  • step S120 referring to step S120 in FIG. 1 , an electrical topological network model is obtained according to the connection relationship of each TSV structure between the two dies.
  • the number of TSV structures 10 between two dies may be one or multiple.
  • each TSV structure 10 can be the same or different, and the same TSV structure 10 can also be connected to the two dies in the same way.
  • the number of TSV structures 10 between two dies is 2, and the two TSV structures 10 both include bump substructures 11 and TSV substructures 12, and both of them have bump substructures 11
  • the TSV structure 12 is electrically connected to the second die 20 and is electrically connected to the first die 30 .
  • the electrical topology network model is a total equivalent circuit model of each TSV structure 10 between two dies.
  • each TSV structure 10 when there are multiple TSV structures 10 between two dies, each TSV structure 10 is the same.
  • the electrical topology network model includes a plurality of sub-network models, and the number of sub-network models is equal to the number of TSV structures 10 .
  • Each sub-network model includes bump sub-resistance R_bp, TSV resistance R_tsv, bump sub-capacitance C_bp, TSV capacitance C_tsv, bump sub-inductance L_bp, and TSV inductance L_tsv.
  • the bump sub-resistance R_bp, the bump sub-inductance L_bp, the TSV inductance L_tsv and the TSV resistance R_tsv are sequentially connected in series between the second die 20 and the first die 30 .
  • One terminal of the bump subcapacitor C_bp is connected between the second die 20 and the bump subresistor R_bp, and the other terminal of the bump subcapacitor C_bp is connected to a predetermined remote terminal.
  • the preset far end can be infinity.
  • TSV capacitor C_tsv One end of the TSV capacitor C_tsv is connected between the bump pad sub-inductance L_bp and the TSV inductance L_tsv, and the other end of the TSV capacitor C_tsv is connected to the TSV capacitor C_tsv in another sub-network model.
  • the TSV capacitors C_tsv of the two TSV structures 10 are connected through the substrate resistor Rsub and the substrate capacitor Csub.
  • the substrate resistance Rsub may be the equivalent resistance of the substrate layer 31
  • the substrate capacitance Csub may be the equivalent capacitance of the substrate layer 31 . Both ends of the parallel connection of the substrate resistance Rsub and the substrate capacitance Csub are respectively connected to the TSV capacitance C_tsv of the two TSV structures 10 .
  • the substrate resistance Rsub is approximately infinite compared to the bump pad sub-resistance R_bp and the TSV resistance R_tsv
  • the substrate capacitance Csub is comparable to the bump pad sub-capacitance C_bp and the TSV capacitance C_tsv. Approximate to infinitesimal, so the substrate resistance Rsub and substrate capacitance Csub are ignored in the electrical topological network model, thereby simplifying the electrical topological network model.
  • step S130 referring to step S130 in FIG. 1, a simulation model is obtained according to the electrical topology network model and electrical parameters for simulation.
  • the electrical parameters include parameter values of each equivalent electronic component in the electrical topology network model.
  • the electrical topology network model is a total equivalent circuit model of each TSV structure 10 between two dies.
  • the simulation model is a simulation model of a three-dimensional integrated circuit. According to the electrical topology network model and the electrical parameters, a simulation model of a three-dimensional integrated circuit can be obtained for simulation so that the influence of the TSV structure on the three-dimensional integrated circuit can be obtained.
  • step S130 specifically includes steps S131 to S133.
  • Step S131 obtaining a simulation model file according to the subnetwork model and electrical parameters.
  • this embodiment takes the same TSV structure 10 as an example, that is, the same sub-network model in the electrical topology network model.
  • the parameters to get the corresponding simulation model file can define the connection point between the electrical network topology model and the second die 20 (ie, the top Top) and the connection point between the electrical network topology model and the first die 30 (ie, the bottom Bottom) according to a predefined format.
  • the parameter identification of each equivalent electronic component and the parameter value of each equivalent electronic component can be used to a predefined format.
  • the simulation model file may include the parameter identification C_bp of the bump sub-capacitance and its parameter value a, the parameter identification R_bp of the bump sub-resistance and its parameter value b, the parameter identification L_bp of the bump sub-inductance and its parameter value c.
  • the simulation model file can also calculate the resistance value tsv_r, the inductance value tsv_l and the capacitance value tsv_c of the TSV structure according to these parameter identifiers and parameter values.
  • Step S132 according to the number of TSV structures between the two dies, arrange the TSV structure symbols between the circuit model of the first die and the circuit model of the second die, so as to obtain a first circuit model.
  • the first circuit model is an equivalent circuit model of a three-dimensional integrated circuit.
  • the number of TSV structures 10 between the first die 30 and the second die 20 configure the TSV structure symbol 13 between the circuit model 36 of the first die and the circuit model 26 of the second die, so as to A first circuit model is obtained.
  • the number of TSV structures 10 between the first die 30 and the second die 20 is six.
  • the first die 30 may also be called a master (Master) die
  • the second die 20 may also be called a slave (Slave) die.
  • Step S133 obtaining a simulation model according to the first circuit model and the simulation model file for simulation.
  • the symbol of the through-silicon via structure 10 in the first circuit model can be associated with the simulation model file, so that the first circuit model after the association operation can be used for simulation, so that the effect of the through-silicon via structure 10 on the three-dimensional integrated circuit can be obtained. influences.
  • the first circuit model includes the circuit model 36 of the first die, the circuit model 26 of the second die, and the TSV structure symbol 13 arranged between these two circuit models.
  • the simulation model obtained from the model and simulation model files is aimed at the simulation of the entire three-dimensional integrated circuit. Compared with the simulation performed only on the first die 30 or the second die 20, it can better reflect the impact of the TSV structure 10 on the entire three-dimensional integrated circuit. circuit effects.
  • step S130 specifically includes steps S134 to S136.
  • Step S134 obtaining a simulation model file according to the subnetwork model and electrical parameters.
  • step S134 may be the same as that of step S131.
  • Step S135 according to the number of TSV structures 10 between two adjacent dies, arrange TSV structure symbols between all two adjacent dies, so as to obtain a second circuit model.
  • the number of dies is greater than two.
  • the three-dimensional integrated circuit may include a first die 30 , a second die 20 . . . an Xth die, where X is an integer greater than 2.
  • the first die 30 may also be called a master die
  • the second die 20 to the Xth die may be called slave dies.
  • the number of TSVs between adjacent dies may be the same or different.
  • the circuit model 36 of the first die to the circuit model 50 of the Xth die can be constructed, and silicon via structures 10 are arranged between all the circuit models of two adjacent dies. Via structure symbol 13, resulting in a second circuit model.
  • the second circuit model is an equivalent circuit model of a three-dimensional integrated circuit.
  • the number of TSV structures 10 between all adjacent dies is six.
  • the circuit model 36 of the first die to the circuit model 50 of the Xth die can be replaced by corresponding symbols, and each symbol is the same as that of the corresponding die information is associated.
  • step S136 a simulation model is obtained according to the second circuit model and the simulation model file for simulation.
  • each TSV structure symbol 13 in the second circuit model can be associated with the simulation model file, so that the second circuit model after the association operation can be used for simulation, so that the TSV structure 10 for the three-dimensional integrated circuit can be obtained. influences.
  • the modeling method further includes step S140.
  • step S140 an optimized structure of the TSV structure is obtained according to the simulation result.
  • the simulation results may include current parameters, voltage parameters and the like of each bare chip in the three-dimensional integrated circuit. For example, if the voltage value of the bare chip is too small, it can be understood that the resistance value of the TSV structure 10 is too high, so the factors affecting the resistance parameter of the TSV structure 10 can be adjusted. In this way, the TSV structure 10 can be optimized based on the simulation results, so as to avoid the negative impact of the TSV structure 10 on the functions of the three-dimensional integrated circuit.
  • step S140 includes optimizing the height and/or width of the bump substructure 11, optimizing the width and/or height of the TSV substructure 12, and optimizing the material composition of the bump substructure 11. At least one of optimizing the ratio and optimizing the spacing between the TSV structures 10 between the two dies.
  • the first metal layer 111, the second metal layer 112, the solder ball 113 and the third metal layer 111 in the bump substructure 11 can be changed.
  • the height of any one or more layers of the metal layer 114 when optimizing the width of the bump substructure 11, the thickness of any one or more layers of the first metal layer 111, the second metal layer 112, the solder ball 113, and the third metal layer 114 in the bump substructure 11 can be changed.
  • the width of the fourth metal layer 121 can be changed when optimizing the width of the TSV substructure 12 .
  • the height of the fourth metal layer 121 can be changed when optimizing the height of the TSV substructure 12 .
  • the materials and ratios of any one or more layers of the first metal layer 111 , the second metal layer 112 , the solder ball 113 and the third metal layer 114 can be changed.
  • the spacing between the TSV structures 10 between two dies only the spacing between some of the TSV structures 10 can be changed; the spacing between all TSV structures 10 can also be changed at the same time so that each The spacing between the TSV structures 10 is equal, so that the manufacturing process of the TSV structures 10 is simplified.
  • step S140 may include re-determining the metal layer electrically connected to the TSV substructure 12 .
  • the first bare chip 30 includes a substrate layer 31 and a plurality of metal layers, and the plurality of metal layers are sequentially stacked under the substrate layer 31, and a through hole is opened on the substrate layer 31 for through-silicon.
  • the hole structure 12 passes through, and the through-silicon hole structure 12 is electrically connected to one of the metal layers.
  • the TSV structure 12 is electrically connected to the tenth metal layer 33 .
  • it may be determined according to the simulation structure that the metal layer in contact and electrical connection with the TSV substructure 12 is the ninth metal layer 32 , the eleventh metal layer 34 or the twelfth metal layer 35 .
  • the metal layer that is in contact with the through-silicon hole structure 12 is re-determined, which is beneficial to minimize the parasitic effect and is most beneficial to the layout of the three-dimensional integrated circuit, and changes the metal layer that is in contact with the through-silicon hole structure 12 It is also possible to change the layout of the metal layer (Layout).
  • the three-dimensional integrated circuit may also have a bottom bump structure 40 on the bottom of the first die 30 .
  • the bottom bump structure 40 may include a thirteenth metal layer 41 and a fourteenth metal layer 42 .
  • the model of the bottom bump structure 40 may also be considered, so as to obtain the influence of the bump structure 40 on the three-dimensional integrated circuit.
  • the specific manner of establishing the model of the bump structure 40 may be similar to the modeling manner of the TSV structure 40 , which will not be repeated here.
  • the present application also provides a modeling device 60 .
  • the modeling device 60 includes: an acquisition module 61 , an electrical topology network model processing module 62 and a simulation model processing module 63 .
  • the acquisition module 61 is used to obtain the electrical parameters of each substructure in the TSV structure;
  • the electrical topology network model processing module 62 is used to obtain the electrical topology network model according to the connection relationship of each TSV structure between two dies;
  • the processing module 63 is used to obtain a simulation model according to the electrical topology network model and electrical parameters for simulation.
  • the two dies are respectively a first die and a second die
  • each substructure includes a bump substructure and a through-silicon hole substructure
  • one end of the bump substructure is electrically connected to the second die
  • the other end of the bump pad substructure is electrically connected to one end of the through-silicon hole structure
  • a through hole is opened on the first die for the through-silicon hole structure to pass through to electrically connect the other end of the through-silicon hole structure to the first die
  • the electrical parameters include the electrical parameters of the bump substructure and the electrical parameters of the TSV substructure.
  • the obtaining module 61 includes: a structural diagram obtaining unit, a cross-sectional view obtaining unit, and an electrical parameter obtaining unit.
  • the structural schematic diagram acquisition unit is used to obtain the structural schematic diagram of the TSV structure;
  • the profile acquisition unit is used to obtain the material composition profile of each substructure in the TSV structure according to the structural schematic diagram of the TSV structure;
  • the composition profile of the substructure material The map includes material information and size information of substructures;
  • the electrical parameter acquisition unit is used to obtain electrical parameters according to the material information and size information of each substructure.
  • the electrical parameters include resistance parameters, capacitance parameters, and inductance parameters.
  • each TSV structure is the same, and the electrical topology network model includes multiple sub-network models, and the number of sub-network models is the same as the number of TSV structures.
  • the numbers are equal; each subnetwork model includes bump pad sub-resistance, TSV resistance, bump pad sub-capacitance, TSV capacitance, bump pad sub-inductance and TSV inductance, bump pad sub-resistance,
  • the bump sub-inductance, TSV inductance and TSV resistance are serially connected between the second die and the first die, and one end of the bump sub-capacitance is connected between the second die and the bump sub-resistance , the other end of the bump sub-capacitor is connected to the preset remote end, one end of the TSV capacitor is connected between the bump sub-inductance and the TSV inductor, and the other end of the TSV capacitor is connected to another sub-network TSV capacitive connections in the model.
  • the simulation model processing module 63 includes: a simulation model file processing unit, a TSV symbol processing unit, and a simulation model processing unit.
  • the simulation model file processing unit obtains the simulation model file according to the sub-network model and the electrical parameters;
  • the TSV symbol processing unit is based on the number of TSV structures between the two dies in the circuit model of the first die and the number of the second die.
  • TSV structure symbols are arranged between the circuit models to obtain the first circuit model; the simulation model processing unit obtains the simulation model according to the first circuit model and the simulation model file for simulation.
  • the simulation model processing module 63 includes: a simulation model file processing unit, a TSV symbol processing unit, and a simulation model processing unit.
  • the simulation model file processing unit is used to obtain the simulation model file according to the subnetwork model and electrical parameters; TSV structure symbols are arranged between the chips to obtain a second circuit model; the simulation model processing unit is used to obtain the simulation model according to the second circuit model and the simulation model file for simulation.
  • the bump substructure includes a first copper layer, a second copper layer, a first nickel layer, a tin-silver alloy layer, and a second nickel layer stacked in sequence;
  • the TSV substructure includes a third copper layer;
  • the parameter acquisition unit obtains the electrical parameters of the raised pad substructure according to the material information and size information of the first copper layer, the second copper layer, the first nickel layer, the tin-silver alloy layer, and the second nickel layer, and obtains the electrical parameters of the raised pad substructure according to the third copper layer
  • the electrical parameters of the through-silicon hole structure are obtained from the material information and size information.
  • an optimization module is also included, configured to obtain an optimized structure of the TSV structure according to a simulation result.
  • the optimization module is used to optimize the height and/or width of the bump substructure, optimize the width and/or height of the TSV substructure, and optimize the composition and ratio of materials in the bump substructure. At least one of optimizing, optimizing the spacing between the TSV structures between the two dies.
  • the first die includes a substrate layer and a plurality of metal layers, and the plurality of metal layers are sequentially stacked under the substrate layer, and a through hole is opened on the substrate layer for the through-silicon hole structure to pass through.
  • the TSV substructure is electrically connected to one of the metal layers; the optimization module is used to redefine which metal layer is electrically connected to the TSV substructure.
  • the present application also provides a computer device, including a memory and a processor, the memory stores a computer program, and the processor implements the steps of the method described in any one of the above embodiments when executing the computer program.
  • the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.
  • Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory or optical memory, etc.
  • Volatile memory can include Random Access Memory (RAM) or external cache memory.
  • RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

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Abstract

一种建模方法、装置、计算机设备及存储介质，所述方法包括：获取硅通孔结构中各子结构的电参数（S110）；根据两个裸片之间各所述硅通孔结构的连接关系得到电拓扑网络模型（S120）；根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真（S130）。

Description

建模方法、装置、计算机设备及存储介质
本申请要求于2021年05月20日提交的申请号为202110554254.8、名称为“建模方法、装置、计算机设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种建模方法、装置、计算机设备及存储介质。
背景技术
目前，硅通孔(TSV，through silicon via)技术是三维集成电路中堆叠芯片实现互联的一种新的技术解决方案。硅通孔技术通过在相邻两个半导体芯片(也称为裸片，Die)之间形成硅通孔结构以实现相邻两个Die之间的电性连接。
譬如，动态随机存取存储器(DRAM，Dynamic Random Access Memory)的双倍速率(DDR，Double Data Rate)产品会用到硅通孔(TSV，through silicon via)技术，将两片甚至多片DDR芯片叠加起来。硅通孔结构形成于相邻两片DDR芯片之间使得实现相邻DDR芯片电性连接，形成3D堆叠结构，从而减小因为封装带来的额外损耗。
然而，传统技术无法对包含硅通孔结构的三维集成电路进行仿真，从而无法知晓硅通孔结构对三维集成电路的影响。
发明内容
一方面，本申请提供了一种建模方法，包括：获取硅通孔结构中各子结构的电参数；根据两个裸片之间各所述硅通孔结构的连接关系得到电拓扑网络模型；根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真。
本申请另一方面提供一种建模装置，包括：获取模块，用于获取硅通孔结构中各子结构的电参数；电拓扑网络模型处理模块，用于根据两个裸片之间各所述硅通孔结构的连接关系得到电拓扑网络模型；仿真模型处理模块，用于根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真。
本申请再一方面提供一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现如上所述的方法的步骤。
本申请再一方面提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的方法的步骤。
本申请的各个实施例的细节将在下面的附图和描述中进行说明。根据说明书、附图以及权利要求书的记载，本领域技术人员将容易理解本申请的其它特征、解决的问题以及技术效果。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为本申请一实施例中提供的建模方法的流程图；
图2为本申请一实施例中提供的三维集成电路的内部结构示意图；
图3为本申请一具体实施例中提供的建模方法的流程图；
图4为本申请一实施例中提供的凸起焊盘子结构的剖面图；
图5为本申请一实施例中提供的硅通孔子结构的剖面图；
图6为本申请一实施例中提供的电拓扑网络模型的示意图；
图7为本申请一实施例中提供的第一电路模型的示意图；
图8为本申请另一实施例中提供的步骤S130的具体步骤流程图；
图9为本申请一实施例中提供的第二电路模型的示意图；
图10为本申请一实施例中提供的建模装置的结构框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直 接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本申请的范围。
请参阅图1，本申请提供一种建模方法，包括如下步骤：
步骤S110，获取硅通孔结构中各子结构的电参数。
步骤S120，根据两个裸片之间各硅通孔结构的连接关系得到电拓扑网络模型。
步骤S130，根据电拓扑网络模型和电参数得到仿真模型，以进行仿真。
在上述实施例中的建模方法通过获取硅通孔结构中各子结构的电参数和两个裸片之间各硅通孔结构的总的电拓扑网络模型，根据电拓扑网络模型和电参数得到三维集成电路的仿真模型，使得能够对包含硅通孔结构的三维集成电路进行仿真，从而知晓硅通孔结构对整个三维集成电路的影响。
在步骤S110中，请参阅图1中的S110步骤，获取硅通孔结构中各子结构的电参数。
在一些示例中，请参阅图2，三维集成电路中可以包括两个或大于两个裸片。各裸片可以为同种类型的芯片，也可以为不同类型的芯片。譬如裸片可以为DRAM芯片，进一步的，可以为DDR芯片。其中两个裸片分别称为第一裸片30和第二裸片20。
各子结构可以包括凸起焊盘子结构11及硅通孔子结构12。凸起焊盘子结构11的一端与第二裸片20电连接。凸起焊盘子结构11的另一端与硅通孔子结构12的一端电连接，第一裸片30上开设有通孔供硅通孔子结构12穿过以将硅通孔子结构12的另一端与第一裸片30电连接，电参数包括凸起焊盘子结构11的电参数和硅通孔子结构12的电参数。
在一些示例中，请参阅图2，硅通孔结构10可以包括依次叠置的第一金属层111、第二金属层112、焊球113、第三金属层114及第四金属层121。可以配置凸起焊盘子结构11包括第一金属层111至第三金属层114，硅通孔子结构12包括第四金属层121。
在其他示例中，还可以根据实际需求将硅通孔结构10中各层划分为不同于凸起焊盘子结构11和硅通孔子结构12的其他子结构。
在一些示例，请参阅图2，第二裸片20可以包括依次叠置的第二基材层21及多个金属层。硅通孔结构10的第一金属层111可以与第二裸片20中的任意一个金属层电性连接。譬如，第二裸片20可以包括依次叠置于第二基材层21下方的第五金属层22、第六金属层23、第七金属层24及第八金属层25。第一金属层111可以与第八金属层25接触电性连接，使得凸起焊盘子结构11的一端与第二裸片20接触电性连接。由于第三金属层114与第四金属层121接触，使得凸起焊盘子结构11的另一端与硅通孔子结构12的一端接触电性连接。
在一些示例，请参阅图2，第一裸片30可以包括基材层31及多个金属层，多个金属层依次叠置于基材层31的下方。基材层31上开设有通孔供硅通孔子结构12穿过，硅通孔结构10的第四金属层121可以与第一裸片30中的任意一个金属层电性连接。譬如，第一裸片30可以包括依次叠置于基材层31下方的第九金属层32、第十金属层33、第十一金属层34及第十二金属层35，第四金属层121可以与第十金属层33接触电性连接，使得硅通孔子结构12的另一端与第一裸片30接触电性连接。
在一些示例中，请参阅图3，步骤S110具体包括步骤S111至步骤S113。
步骤S111，获取硅通孔结构的结构示意图。
具体的，操作人员可以利用鼠标、键盘、触控屏等输入设备构建裸片至裸片(Die-to-Die)之间硅通孔结构10的结构示意图，从而获取硅通孔结构10的结构示意图，该结构示意图可以为立体示意图也可以为平面示意图。裸片至裸片之间的硅通孔结构10的数量可以为一个，也可以为多个。当裸片至裸片之间的硅通孔结构10的数量为多个时，各硅通孔结构10可以相同也可以不同。下面以各硅通孔结构10相同为例进行说明。
步骤S112，根据硅通孔结构的结构示意图得到硅通孔结构中各子结构的材料组成剖面图；子结构的材料组成剖面图包括子结构的材料信息及尺寸信息。
具体的，根据硅通孔结构10的结构示意图可以构建硅通孔结构10中各子结构的材料组成剖面图。本实施例中，硅通孔结构10可以包括凸起焊盘子结构11及硅通孔子结构12。请参阅图4和图5，根据硅通孔结构10的结构示意图分别得到凸起焊盘子结构11的材料组成剖面图及硅通孔子结构12的材料组成剖面图。凸起焊盘子结构11的材料组成剖面图包括凸起焊盘子结构11的材料信息及尺寸信息，硅通孔子结构12的材料组成剖面图包括硅通孔子结构12的材料信息及尺寸信息。
在一些示例中，请参阅图2和图4，凸起焊盘子结构11的材料组成剖面图中，凸起焊盘子结构11包括依次堆叠的第一金属层111、第二金属层112、焊球113及第三金属层114(图4未示出)。第一金属层111可以包括第一铜层1111及第二铜层1112。在三维集成电路中第一铜层1111的底部外围还可以设置第一绝缘层27，第一绝缘层27可以包括第一氮化硅层，起到隔离绝缘作用。第二裸片20还可以包括第一氧化硅衬底28，第一氧化硅衬底28可以位于第一绝缘层27上方并包覆第八金属层25。第二金属层112可以包括第一镍层。焊球113可以包括锡银合金层。第三金属层114可以包括第二镍层。也即凸起焊盘子结构11可以包括依次堆叠的第一铜层1111、第二铜层1112、第一镍层、锡银合金层及第二镍层。凸起焊盘子结构11的材料组成剖面图中还包括各层的尺寸信息，图4中未示出尺寸信息。
请参阅图2和5，硅通孔子结构12的材料组成剖面图中，硅通孔子结构12包括第四金属层121，第四金属层121可以包括第三铜层。在三维集成电路中第四金属层121的底部外围还可以设置第二绝缘层38，第二绝缘层38包括第二氮化硅层，起到隔离绝缘作用。第一裸片30还可以包括第二氧化硅衬底37，第二氧化硅衬底37可以位于第二绝缘层38上方并包覆于第四金属层121的部分侧面。硅通孔子结构12的材料组成剖面图中还包括各层的尺寸信息，图5中未示出尺寸信息。
步骤S113，根据每个子结构的材料信息及尺寸信息得到电参数。
具体的，可以先根据硅通孔结构10中各子结构每层的材料信息及尺寸信息得到每层的电 参数，再根据子结构中每层的电参数计算该子结构的电参数。本实施例中，根据第一铜层1111、第二铜层1112、第一镍层、锡银合金层及第二镍层的材料信息及各层尺寸信息得到凸起焊盘子结构11的电参数。本实施例中，还可以根据第三铜层的材料信息及尺寸信息得到第三铜层的电参数即硅通孔子结构12的电参数。
在一些示例中，电参数包括电阻参数、电容参数及电感参数。譬如，可以根据第一铜层1111、第二铜层1112、第一镍层、锡银合金层及第二镍层的材料信息及各层尺寸信息得到凸起焊盘子结构11的电阻参数和凸起焊盘子结构11的电容参数。可以根据第三铜层的材料信息及尺寸信息得到硅通孔子结构12的电阻参数和硅通孔子结构12的电容参数。具体的，第一铜层1111的宽度为8-12μm，高度为2-6μm。第二铜层1112的宽度为20-40μm，高度为2-6μm。第一镍层的宽度为20-40μm，高度为1-4μm。锡银合金层的宽度为20-40μm，高度为4-9μm。第二镍层的宽度为20-40μm，高度为3-8μm。第三铜层的宽度为4-8μm，高度为40-70μm。
在一些示例中，在计算凸起焊盘子结构11及硅通孔子结构12的电参数时可以根据下式计算。其中，式(1)为计算电阻参数的公式，式(2)为计算电感参数的公式，式(3)为计算电容参数的公式。式(1)至式(3)中的参数均可以根据凸起焊盘子结构11及硅通孔子结构12中各层材料信息及各层尺寸信息计算得到，可以利用式(1)至(3)先分别计算各子结构中每层的电阻参数、电感参数及电容参数，再根据子结构中每层的电参数计算各子结构的电阻参数、电感参数及电容参数。
R＝ρL/S     (1)
其中，ρ为电阻的电阻率，L表示电阻的长度，S表示电阻的横截面积。
L＝μ 0N 2S/L    (2)
其中，μ 0为螺线管的磁导率，N为螺线管的总匝数，S为螺线管的截面积，L为螺线管的长度。
C＝εA/d     (3)
其中，ε为电容的介电常数，A为电容的两个极板间正对面积，d为电容的两个极板间距离。
在步骤S120中，请参阅图1中的步骤S120，根据两个裸片之间各硅通孔结构的连接关系得到电拓扑网络模型。
具体的，两个裸片之间的硅通孔结构10的数量可以为一个，也可以为多个。当两个裸片之间硅通孔结构10的数量为多个时，各硅通孔结构10可以相同也可以不同，并且相同的硅通孔结构10与两个裸片的连接方式也可以相同。譬如，两个裸片之间的硅通孔结构10的数量为2，两个硅通孔结构10均包括凸起焊盘子结构11和硅通孔子结构12，并且都是凸起焊 盘子结构11与第二裸片20接触电性连接且硅通孔子结构12与第一裸片30接触电性连接。电拓扑网络模型为两个裸片之间的各硅通孔结构10的总的等效电路模型。
在一些示例中，请参阅图6，两个裸片之间硅通孔结构10的数量为多个时，各硅通孔结构10相同。电拓扑网络模型包括多个子网络模型，子网络模型的数量与硅通孔结构10的数量相等。每个子网络模型均包括凸起焊盘子电阻R_bp、硅通孔电阻R_tsv、凸起焊盘子电容C_bp、硅通孔电容C_tsv、凸起焊盘子电感L_bp及硅通孔电感L_tsv。凸起焊盘子电阻R_bp、凸起焊盘子电感L_bp、硅通孔电感L_tsv及硅通孔电阻R_tsv依次串联于第二裸片20和第一裸片30之间。凸起焊盘子电容C_bp的一端连接于第二裸片20和凸起焊盘子电阻R_bp之间，凸起焊盘子电容C_bp的另一端连接于预设远端。预设远端可以为无穷远处。硅通孔电容C_tsv的一端连接于凸起焊盘子电感L_bp和硅通孔电感L_tsv之间，硅通孔电容C_tsv的另一端与另一个子网络模型中的硅通孔电容C_tsv连接。
本实施例中，通过设置各个子结构的等效电气元件，能够实现在不需要布局版图的情况下得到精确的仿真结果。
在一些示例中，两个硅通孔结构10的硅通孔电容C_tsv之间通过基材电阻Rsub和基材电容Csub连接。基材电阻Rsub可以为基材层31的等效电阻，基材电容Csub可以为基材层31的等效电容。基材电阻Rsub和基材电容Csub并联后的两端分别与两个硅通孔结构10的硅通孔电容C_tsv连接。发明人创造性的发现基材电阻Rsub相比于凸起焊盘子电阻R_bp和硅通孔电阻R_tsv均近似于无限大且基材电容Csub相比于凸起焊盘子电容C_bp和硅通孔电容C_tsv均近似于无限小，故在电拓扑网络模型中忽略基材电阻Rsub和基材电容Csub，从而简化电拓扑网络模型。
在步骤S130中，请参阅图1中的S130步骤，根据电拓扑网络模型和电参数得到仿真模型，以进行仿真。
具体的，电参数包括了电拓扑网络模型中各等效电子元器件的参数值。电拓扑网络模型为两个裸片之间的各硅通孔结构10的总的等效电路模型。仿真模型为三维集成电路的仿真模型。根据电拓扑网络模型及电参数即能够得到三维集成电路的仿真模型进行仿真使得能够得到硅通孔结构对于三维集成电路的影响。
在一些示例中，请参阅图3，步骤S130具体包括步骤S131至步骤S133。
步骤S131，根据子网络模型和电参数得到仿真模型文件。
具体的，本实施例以各个硅通孔结构10相同即电拓扑网络模型中各子网络模型相同为例进行说明，在其他示例中若各子网络模型不同，可以根据子网络模型和对应的电参数得到对应的仿真模型文件。仿真模型文件可以根据预定义的格式定义电网络拓扑模型与第二裸片20 的连接点(即顶部Top)和电网络拓扑模型与第一裸片30的连接点(即底部Bottom)之间的各个等效电子元器件的参数标识及各个等效电子元器件的参数值。譬如，仿真模型文件可以包括凸起焊盘子电容的参数标识C_bp及其参数值a、凸起焊盘子电阻的参数标识R_bp及其参数值b、凸起焊盘子电感的参数标识L_bp及其参数值c、硅通孔电容的参数标识C_tsv及其参数值d、硅通孔电感的参数标识L_tsv及其参数值e、硅通孔电阻的参数标识R_tsv及其参数值f。仿真模型文件还可以根据这些参数标识和参数值计算硅通孔结构的电阻值tsv_r、电感值tsv_l和电容值tsv_c等等。
步骤S132，根据两个裸片之间硅通孔结构的数量在第一裸片的电路模型和第二裸片的电路模型之间配置硅通孔结构符号，以得到第一电路模型。
具体的，请参阅图7，第一电路模型为三维集成电路的等效电路模型。根据第一裸片30和第二裸片20之间硅通孔结构10的数量在第一裸片的电路模型36和第二裸片的电路模型26之间配置硅通孔结构符号13，以得到第一电路模型。图7实施例中，第一裸片30和第二裸片20之间硅通孔结构10的数量为6。本实施例中，第一裸片30也可以叫做主(Master)裸片，第二裸片20也可以叫做从(Slave)裸片。
步骤S133，根据第一电路模型和仿真模型文件得到仿真模型，以进行仿真。
具体的，可以将第一电路模型中的硅通孔结构10符号与仿真模型文件相关联，使得利用关联操作后的第一电路模型进行仿真，从而可以得到硅通孔结构10对于三维集成电路的影响。
本实施例中，第一电路模型中包含第一裸片的电路模型36、第二裸片的电路模型26及在这两个电路模型之间配置的硅通孔结构符号13，利用第一电路模型及仿真模型文件得到仿真模型进行仿真是针对整个三维集成电路的仿真，相比于仅针对第一裸片30或第二裸片20进行的仿真更能够体现硅通孔结构10对整个三维集成电路的影响。
在另一些示例中，请参阅图8，步骤S130具体包括步骤S134至步骤S136。
步骤S134，根据子网络模型和电参数得到仿真模型文件。
具体的，步骤S134可以与步骤S131的具体执行过程相同。
步骤S135，根据相邻两个裸片之间硅通孔结构10的数量分别在所有相邻两个裸片之间配置硅通孔结构符号，以得到第二电路模型。
本实施例中，裸片的数量大于两个。三维集成电路可以包括第一裸片30、第二裸片20……第X裸片，X为大于2的整数。本实施例中，第一裸片30也可以叫做主裸片，第二裸片20至第X裸片均可以叫做从裸片。各相邻的裸片之间硅通孔的数量可以相同也可以不同。请参阅图9，可以构建第一裸片的电路模型36至第X裸片的电路模型50，并在所有的相邻两个 裸片的电路模型之间根据硅通孔结构10的数量设置硅通孔结构符号13，从而得到第二电路模型。第二电路模型为三维集成电路的等效电路模型。图9实施例中，所有相邻裸片之间的硅通孔结构10数量均为6。
在一些示例中，在第一电路模型和第二电路模型中，第一裸片的电路模型36至第X裸片的电路模型50均可以分别用对应的符号代替，各个符号与对应的裸片的信息相关联。
步骤S136，根据第二电路模型和仿真模型文件得到仿真模型，以进行仿真。
具体的，可以将第二电路模型中各硅通孔结构符号13与仿真模型文件相关联，使得利用关联操作后的第二电路模型进行仿真，从而可以得到硅通孔结构10对于三维集成电路的影响。
在一些示例中，请参阅图3，建模方法还包括步骤S140。
步骤S140，根据仿真结果得到硅通孔结构的优化结构。
具体的，仿真结果可以包括三维集成电路中各裸片的电流参数、电压参数等等。譬如，在裸片的电压值偏小时，可以理解为硅通孔结构10的电阻值偏大，从而可以通过调节影响硅通孔结构10的电阻参数的因素。如此，可以通过仿真结果对硅通孔结构10进行优化，避免硅通孔结构10对三维集成电路的功能造成负面影响。
在一些示例中，步骤S140包括对凸起焊盘子结构11的高度和/或宽度进行优化、对硅通孔子结构12的宽度和/或高度进行优化、对凸起焊盘子结构11中的材料组成及比例进行优化、对两个裸片之间各硅通孔结构10之间的间距进行优化中的至少一个。
在一些示例中，请参阅图2，对凸起焊盘子结构11的高度进行优化时具体可以改变凸起焊盘子结构11中第一金属层111、第二金属层112、焊球113及第三金属层114任意一层或多层的高度。对凸起焊盘子结构11的宽度进行优化时具体可以改变凸起焊盘子结构11中第一金属层111、第二金属层112、焊球113及第三金属层114任意一层或多层的宽度。对硅通孔子结构12的宽度进行优化时可以改变第四金属层121的宽度。对硅通孔子结构12的高度进行优化时可以改变第四金属层121的高度。对凸起焊盘子结构11中的材料组成及比例进行优化时可以改变第一金属层111、第二金属层112、焊球113及第三金属层114任一层或多层的材料及比例。对两个裸片之间各硅通孔结构10之间的间距进行优化时可以仅改变部分硅通孔结构10之间的间距；也可以同时改变所有硅通孔结构10之间的间距使得各硅通孔结构10之间的间距相等，从而便于简化硅通孔结构10的制程。
在另一些示例中，步骤S140可以包括重新确定与硅通孔子结构12电连接的金属层。
具体的，请参阅图2，第一裸片30包括基材层31及多个金属层，多个金属层依次叠置于基材层31下方，基材层31上开设有通孔供硅通孔子结构12穿过，硅通孔子结构12与其 中一个金属层电连接。图2示例中，硅通孔子结构12与第十金属层33接触电连接。在其他示例中，可以根据仿真结构确定与硅通孔子结构12接触电连接的金属层为第九金属层32、第十一金属层34或第十二金属层35。本实施例中根据仿真结果重新确定与硅通孔子结构12接触连接的金属层，有利于使得寄生效应最小，且对三维集成电路的布局最有利，并且改变硅通孔子结构12接触连接的金属层也能够改变金属层的布局(Layout)。
在一些示例中，请参阅图2，三维集成电路还可以在第一裸片30的底部设置底部凸起焊盘结构40。底部凸起焊盘结构40可以包括第十三金属层41和第十四金属层42。在上述实施例中建立仿真模型时，还可以考虑底部凸起焊盘结构40的模型，从而得到凸起焊盘结构40对于三维集成电路的影响。具体的建立凸起焊盘结构40的模型的方式可以与硅通孔结构40的建模方式类似，此处不再赘述。
应该理解的是，虽然图1、3及8的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、3及8中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请参阅图10，本申请还提供一种建模装置60。建模装置60包括：获取模块61、电拓扑网络模型处理模块62及仿真模型处理模块63。获取模块61用于获取硅通孔结构中各子结构的电参数；电拓扑网络模型处理模块62用于根据两个裸片之间各硅通孔结构的连接关系得到电拓扑网络模型；仿真模型处理模块63用于根据电拓扑网络模型和电参数得到仿真模型，以进行仿真。
在一些示例中，两个裸片分别为第一裸片和第二裸片，各子结构包括凸起焊盘子结构及硅通孔子结构，凸起焊盘子结构的一端与第二裸片电连接，凸起焊盘子结构的另一端与硅通孔子结构的一端电连接，第一裸片上开设有通孔供硅通孔子结构穿过以将硅通孔子结构的另一端与第一裸片电连接，电参数包括凸起焊盘子结构的电参数和硅通孔子结构的电参数。
在一些示例中，获取模块61包括：结构示意图获取单元、剖面图获取单元及电参数获取单元。结构示意图获取单元用于获取硅通孔结构的结构示意图；剖面图获取单元用于根据硅通孔结构的结构示意图得到硅通孔结构中各子结构的材料组成剖面图；子结构材料的组成剖面图包括子结构的材料信息及尺寸信息；电参数获取单元用于根据每个子结构的材料信息及尺寸信息得到电参数。
在一些示例中，电参数包括电阻参数、电容参数及电感参数。
在一些示例中，两个裸片之间硅通孔结构的数量为多个时，各硅通孔结构相同，电拓扑网络模型包括多个子网络模型，子网络模型的数量与硅通孔结构的数量相等；每个所述子网络模型包括凸起焊盘子电阻、硅通孔电阻、凸起焊盘子电容、硅通孔电容、凸起焊盘子电感及硅通孔电感，凸起焊盘子电阻、凸起焊盘子电感、硅通孔电感及硅通孔电阻依次串联于第二裸片和第一裸片之间，凸起焊盘子电容的一端连接于第二裸片和凸起焊盘子电阻之间，凸起焊盘子电容的另一端连接于预设远端，硅通孔电容的一端连接于凸起焊盘子电感和硅通孔电感之间，硅通孔电容的另一端与另一个子网络模型中的硅通孔电容连接。
在一些示例中，仿真模型处理模块63包括：仿真模型文件处理单元、硅通孔符号处理单元及仿真模型处理单元。仿真模型文件处理单元根据子网络模型和电参数得到仿真模型文件；硅通孔符号处理单元根据两个裸片之间硅通孔结构的数量在第一裸片的电路模型和第二裸片的电路模型之间配置硅通孔结构符号，以得到第一电路模型；仿真模型处理单元根据第一电路模型和仿真模型文件得到仿真模型，以进行仿真。
在一些示例中，当裸片的数量大于两个时，仿真模型处理模块63包括：仿真模型文件处理单元、硅通孔符号处理单元及仿真模型处理单元。仿真模型文件处理单元用于根据子网络模型和电参数得到仿真模型文件；硅通孔符号处理单元用于根据相邻两个裸片之间硅通孔结构的数量分别在所有相邻两个裸片之间配置硅通孔结构符号，以得到第二电路模型；仿真模型处理单元用于根据第二电路模型和仿真模型文件得到所述仿真模型，以进行仿真。
在一些示例中，凸起焊盘子结构包括依次堆叠的第一铜层、第二铜层、第一镍层、锡银合金层及第二镍层；硅通孔子结构包括第三铜层；电参数获取单元根据第一铜层、第二铜层、第一镍层、锡银合金层及第二镍层的材料信息及尺寸信息得到凸起焊盘子结构的电参数，并根据第三铜层的材料信息及尺寸信息得到硅通孔子结构的电参数。
在一些示例中，还包括优化模块，用于根据仿真结果得到所述硅通孔结构的优化结构。
在一些示例中，优化模块用于对凸起焊盘子结构的高度和/或宽度进行优化、对硅通孔子结构的宽度和/或高度进行优化、对凸起焊盘子结构中的材料组成及比例进行优化、对两个裸片之间各硅通孔结构之间的间距进行优化中的至少一个。
在另一些示例中，第一裸片包括基材层及多个金属层，多个金属层依次叠置于基材层下方，基材层上开设有通孔供硅通孔子结构穿过，硅通孔子结构与其中一个金属层电连接；优化模块用于重新确定与硅通孔子结构电连接的金属层。
本申请还提供一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现如上任一项实施例所述的方法的步骤。
本申请还提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处 理器执行时实现如上任一项实施例所述的方法的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和易失性存储器中的至少一种。非易失性存储器可包括只读存储器(Read-Only Memory，ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory，RAM)或外部高速缓冲存储器。作为说明而非局限，RAM可以是多种形式，比如静态随机存取存储器(Static Random Access Memory，SRAM)或动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种建模方法，包括：
    获取硅通孔结构中各子结构的电参数；
    根据两个裸片之间各所述硅通孔结构的连接关系得到电拓扑网络模型；
    根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真。
  2. 根据权利要求1所述的建模方法，其中，所述两个裸片分别为第一裸片和第二裸片，各所述子结构包括凸起焊盘子结构及硅通孔子结构，所述凸起焊盘子结构的一端与所述第二裸片电连接，所述凸起焊盘子结构的另一端与所述硅通孔子结构的一端电连接，所述第一裸片上开设有通孔供所述硅通孔子结构穿过以将所述硅通孔子结构的另一端与所述第一裸片电连接，所述电参数包括所述凸起焊盘子结构的电参数和所述硅通孔子结构的电参数。
  3. 根据权利要求2所述的建模方法，其中，所述获取硅通孔结构中各子结构的电参数，包括：
    获取所述硅通孔结构的结构示意图；
    根据所述硅通孔结构的结构示意图得到所述硅通孔结构中各所述子结构的材料组成剖面图；所述子结构的材料组成剖面图包括所述子结构的材料信息及尺寸信息；
    根据每个所述子结构的材料信息及尺寸信息得到所述电参数。
  4. 根据权利要求3所述的建模方法，其中，所述电参数包括电阻参数、电容参数及电感参数。
  5. 根据权利要求4所述的建模方法，其中，所述两个裸片之间硅通孔结构的数量为多个时，各所述硅通孔结构相同，所述电拓扑网络模型包括多个子网络模型，所述子网络模型的数量与所述硅通孔结构的数量相等；
    每个所述子网络模型包括凸起焊盘子电阻、硅通孔电阻、凸起焊盘子电容、硅通孔电容、凸起焊盘子电感及硅通孔电感，所述凸起焊盘子电阻、所述凸起焊盘子电感、所述硅通孔电感及所述硅通孔电阻依次串联于所述第二裸片和所述第一裸片之间，所述凸起焊盘子电容的一端连接于所述第二裸片和所述凸起焊盘子电阻之间，所述凸起焊盘子电容的另一端连接于预设远端，所述硅通孔电容的一端连接于所述凸起焊盘子电感和所述硅通孔电感之间，所述硅通孔电容的另一端与另一个所述子网络模型中的硅通孔电容连接。
  6. 根据权利要求5所述的建模方法，其中，所述根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真，包括：
    根据所述子网络模型和所述电参数得到仿真模型文件；
    根据两个裸片之间所述硅通孔结构的数量在所述第一裸片的电路模型和所述第二裸片 的电路模型之间配置硅通孔结构符号，以得到第一电路模型；
    根据所述第一电路模型和所述仿真模型文件得到所述仿真模型，以进行仿真。
  7. 根据权利要求5所述的建模方法，其中，当所述裸片的数量大于两个时，所述根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真，包括：
    根据所述子网络模型和所述电参数得到仿真模型文件；
    根据相邻两个裸片之间所述硅通孔结构的数量分别在所有相邻两个所述裸片之间配置硅通孔结构符号，以得到第二电路模型；及
    根据所述第二电路模型和所述仿真模型文件得到所述仿真模型，以进行仿真。
  8. 根据权利要求3所述的建模方法，其中，所述凸起焊盘子结构包括依次堆叠的第一铜层、第二铜层、第一镍层、锡银合金层及第二镍层；所述硅通孔子结构包括第三铜层；
    所述根据每个所述子结构的材料信息及尺寸信息得到所述电参数的步骤中根据所述第一铜层、所述第二铜层、所述第一镍层、所述锡银合金层及所述第二镍层的材料信息及尺寸信息得到所述凸起焊盘子结构的电参数，并根据所述第三铜层的材料信息及尺寸信息得到所述硅通孔子结构的电参数。
  9. 根据权利要求8所述的建模方法，还包括：
    根据仿真结果得到所述硅通孔结构的优化结构。
  10. 根据权利要求9所述的建模方法，其中，所述根据仿真结果得到所述硅通孔结构的优化结构包括对所述凸起焊盘子结构的高度和/或宽度进行优化、对所述硅通孔子结构的宽度和/或高度进行优化、对所述凸起焊盘子结构中的材料组成及比例进行优化、对两个所述裸片之间各所述硅通孔结构之间的间距进行优化中的至少一个。
  11. 根据权利要求9所述的建模方法，其中，所述第一裸片包括基材层及多个金属层，所述多个金属层依次叠置于所述基材层下方，所述基材层上开设有通孔供所述硅通孔子结构穿过，所述硅通孔子结构与其中一个所述金属层电连接；所述根据仿真结果得到所述硅通孔结构的优化结构包括：重新确定与所述硅通孔子结构电连接的金属层。
  12. 一种建模装置，包括：
    获取模块，用于获取硅通孔结构中各子结构的电参数；
    电拓扑网络模型处理模块，用于根据两个裸片之间各所述硅通孔结构的连接关系得到电拓扑网络模型；
    仿真模型处理模块，用于根据所述电拓扑网络模型和所述电参数得到仿真模型，以进行仿真。
  13. 根据权利要求12所述的建模装置，其中，所述两个裸片分别为第一裸片和第二裸片， 各所述子结构包括凸起焊盘子结构及硅通孔子结构，所述凸起焊盘子结构的一端与所述第二裸片电连接，所述凸起焊盘子结构的另一端与所述硅通孔子结构的一端电连接，所述第一裸片上开设有通孔供所述硅通孔子结构穿过以将所述硅通孔子结构的另一端与所述第一裸片电连接，所述电参数包括所述凸起焊盘子结构的电参数和所述硅通孔子结构的电参数。
  14. 一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现权利要求1至11中任一项所述的方法的步骤。
  15. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至11中任一项所述的方法的步骤。
PCT/CN2021/120533 2021-05-20 2021-09-26 建模方法、装置、计算机设备及存储介质 Ceased WO2022242002A1 (zh)

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