WO2022241735A1 - 自旋逻辑器件、存算一体器件、半加器和全加器 - Google Patents

自旋逻辑器件、存算一体器件、半加器和全加器 Download PDF

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Publication number
WO2022241735A1
WO2022241735A1 PCT/CN2021/094983 CN2021094983W WO2022241735A1 WO 2022241735 A1 WO2022241735 A1 WO 2022241735A1 CN 2021094983 W CN2021094983 W CN 2021094983W WO 2022241735 A1 WO2022241735 A1 WO 2022241735A1
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Prior art keywords
magnetic unit
port
gate
spin
logic
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PCT/CN2021/094983
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English (en)
French (fr)
Inventor
章晓中
蒲宇辰
卢子尧
牟鸿铭
李文静
叶力
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华为技术有限公司
清华大学
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Application filed by 华为技术有限公司, 清华大学 filed Critical 华为技术有限公司
Priority to PCT/CN2021/094983 priority Critical patent/WO2022241735A1/zh
Priority to CN202180093546.4A priority patent/CN116830198A/zh
Publication of WO2022241735A1 publication Critical patent/WO2022241735A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices

Definitions

  • Embodiments of the present disclosure relate generally to logic devices, and more particularly to spin logic devices, store-and-operate devices, half adders, and full adders.
  • CMOS Complementary Metal Oxide Semiconductor
  • data is volatile, and when logic operations are performed, the operation results need to be stored in memory separately. Since the computer's data calculation and storage are separated, the transmission of data between the processor and the memory becomes a major limiting factor that limits the speed and performance of the computer.
  • in-memory computing or integration of storage and computing can be realized, in which in-memory computing requires logic devices to have both data computing and storage capabilities.
  • Spin logic devices also known as magnetic logic devices, can be used to realize storage-computing integration technology.
  • a spin logic device is a digital logic device designed using the spin characteristics of electrons in magnetic materials.
  • this device Compared with conventional semiconductor logic devices, this device has the advantages of fast speed, low power consumption, non-volatile logic information, radiation protection, and CMOS technology is compatible and other advantages, so it is considered to be very promising to replace traditional semiconductor logic devices.
  • the existing spin logic device is a current mode logic device, and its output signal is a current signal, which consumes a lot of power, and there is still room for further improvement.
  • Embodiments of the present disclosure provide a spin logic device, a memory-computing integrated device, a half adder and a full adder.
  • the first magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along a stacking direction.
  • the magnetization direction of the ferromagnetic layer is along the stacking direction, ie, parallel or antiparallel to the stacking direction.
  • the first magnetic unit includes a first port on a first side of the first magnetic unit, a second port on a second side opposite the first side, and is located between the first port and the second port of the first magnetic unit and A third port on the third side of the first magnetic unit.
  • the first port of the first magnetic unit is coupled to the first terminal of the spin logic device
  • the second port of the first magnetic unit is coupled to the second terminal of the spin logic device
  • the third port of the first magnetic unit is coupled to the second terminal of the spin logic device.
  • the third end of the spin logic device is coupled.
  • the first negative differential resistor is coupled between the first terminal and the third terminal of the spin logic device.
  • the second negative differential resistor is coupled between the second terminal and the third terminal of the spin logic device.
  • the first to third ports of the first magnetic unit are all disposed at a side of the first magnetic unit.
  • the spin Hall effect layer can generate a spin-orbit torque when there is an electric current from the first port to the second port of the first magnetic unit.
  • a Hall voltage can be generated in the plane of the ferromagnetic layer, so that the Hall voltage can be embodied at the third port of the first magnetic unit . Due to the existence of the Hall voltage, an asymmetry is generated between the left voltage and the right voltage, where the left voltage and the right voltage respectively represent the voltage between the first terminal and the third terminal of the spin logic device and the self The voltage between the second terminal and the third terminal of the spin logic device.
  • Negative differential resistance has the effect of further increasing large voltages and further reducing small voltages, therefore, asymmetry between voltages can be amplified.
  • the spin logic device can generate significantly different output voltages across the first negative differential resistance and/or the second negative differential resistance to identify different logic outputs. In this way, voltage-mode spin logic devices can be realized.
  • Current-mode spin logic devices represent different logic outputs through different current magnitudes. In order to distinguish between different logics, a larger current is required, so the device consumes more power. In contrast, voltage-mode spin logic devices do not require high current operation, thereby reducing device power consumption and improving device performance.
  • the first magnetic unit is symmetrical with respect to the axis of symmetry perpendicular to the stacking direction
  • the second port of the first magnetic unit is symmetrical to the first port with respect to the axis of symmetry
  • the third port of the first magnetic unit is located symmetrically on axis.
  • the first terminal of the spin logic device is configured to be coupled to a first voltage
  • the second terminal of the spin logic device is configured to be coupled to a second voltage to generate a second voltage in the spin logic device.
  • the spin logic device is used to output a third voltage representing the first logic output between the first terminal and the third terminal of the spin logic device.
  • the spin logic device is used to output a fourth voltage representing the second logic output between the second terminal and the third terminal of the spin logic device.
  • the current between the first end and the second end of the spin logic device can generate a Hall effect in the direction of the symmetry axis.
  • the Er voltage causes an imbalance between the third voltage and the fourth voltage, so that the spin logic device can use the third voltage and/or the fourth voltage to realize a logic output.
  • the magnetization direction represents the logic input of the first magnetic unit.
  • the first negative differential resistance and/or the second negative differential resistance may be realized by complementary junction field effect transistors or resonant tunneling diodes.
  • the spin Hall effect layer includes a heavy metal layer and/or a topological insulator layer.
  • the magnetization direction is flipped in response to a magnetic field applied to the first magnetic unit and a write current between the first port and the second port of the first magnetic unit.
  • the direction of the magnetic field is parallel or antiparallel to the direction of the write current.
  • the reversal of the magnetization direction is related to the relative orientation of the direction of the write current and the magnetic field.
  • the first negative differential resistance and the second negative differential resistance are the same.
  • the spin logic device may further include a second magnetic unit, the second magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along the stacking direction of the second magnetic unit, the second magnetic unit The magnetization direction of the ferromagnetic layer is along the stacking direction of the second magnetic unit.
  • the second magnetic unit includes a first port on a first side of the second magnetic unit, a second port on a second side opposite to the first side of the second magnetic unit, and a first port located between the first port of the second magnetic unit and the second magnetic unit.
  • a third port between the two ports and on a third side of the second magnetic unit wherein the first port of the second magnetic unit is coupled to the first end of the spin logic device, and the second port of the second magnetic unit is coupled to the spin logic device.
  • the second terminal of the spin logic device is coupled, and the third port of the second magnetic unit is coupled with the third terminal of the spin logic device.
  • the second magnetic unit may have the same arrangement as the first magnetic unit above.
  • the spin logic device may further include a third magnetic unit, the third magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along the stacking direction of the third magnetic unit, and the magnetization of the ferromagnetic layer of the third magnetic unit The direction is along the stacking direction of the third magnetic unit, wherein the third magnetic unit includes a first port on a first side of the third magnetic unit, a second port on a second side opposite to the first side of the third magnetic unit.
  • the first port of the third magnetic unit is coupled to the first end of the spin logic device connected
  • the second port of the third magnetic unit is coupled to the second terminal of the spin logic device
  • the third port of the third magnetic unit is coupled to the third terminal of the spin logic device.
  • the third magnetic unit may have the same arrangement as the first magnetic unit described above. Through the first magnetic unit to the third magnetic unit, the spin logic device can realize various logic gates.
  • the magnetization direction of the first magnetic unit is indicative of a logic input of the first magnetic unit.
  • the magnetization direction of the second magnetic unit represents the logic input of the second magnetic unit.
  • the spin logic device is configured to output a third voltage representing a first logic output of the spin logic device between the first terminal and the third terminal thereof. If the magnetization direction of the third magnetic unit is the first magnetization direction, the first logic output acts as a first logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit. If the magnetization direction of the third magnetic unit is the second magnetization direction, the first logic output acts as a second logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit.
  • the spin logic device is configured to output a fourth voltage representing a second logic output of the spin logic device between the second terminal and the third terminal thereof. If the magnetization direction of the third magnetic unit is the first magnetization direction, the second logic output acts as a third logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit. If the magnetization direction of the third magnetic unit is the second magnetization direction, the second logic output operates as a fourth logic operation representing the logic inputs of the first magnetic unit and the second magnetic unit.
  • the first logical operation and the second logical operation include “AND” and "NOR”
  • the third logical operation and the fourth logical operation include “AND” and "OR”.
  • an integrated storage and calculation device includes the logic gate in the first aspect.
  • the control terminal of the transistor is coupled to the third terminal of the logic gate
  • the fourth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along the stacking direction of the fourth magnetic unit, and the fourth magnetic unit
  • the magnetization direction of the ferromagnetic layer is along the stacking direction of the fourth magnetic unit
  • the fourth magnetic unit includes a first port on a first side of the fourth magnetic unit and a second port on a second side opposite to the first side
  • a first port of the fourth magnetic unit is coupled to the first terminal of the transistor
  • a second port of the fourth magnetic unit is coupled to a power source.
  • logic operations are performed through logic gates, and the results of logic operations are stored in the fourth magnetic unit.
  • the fourth magnetic unit is symmetrical with respect to a symmetry axis perpendicular to the stacking direction of the fourth magnetic unit, and the second port of the fourth magnetic unit is the same as the first port of the fourth magnetic unit with respect to the symmetry axis of the fourth magnetic unit.
  • One port is symmetrical.
  • the write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit, and the direction of the magnetic field applied to the fourth magnetic unit is parallel or antiparallel in the direction of the write current.
  • a half adder includes a first NOR gate and a second NOR gate implemented by the first aspect of the present disclosure.
  • the first end of the first NOR gate is coupled to the first end of the second NOR gate
  • the second end of the first NOR gate is coupled to the second end of the second NOR gate
  • the first NOR gate is coupled to the second end of the second NOR gate.
  • Logic inputs of the first magnetic unit and the first magnetic unit of the second NOR gate are complementary
  • logic inputs of the second magnetic unit of the first NOR gate and the second magnetic unit of the second NOR gate are complementary.
  • the control terminal of the first switch is coupled to the third terminal of the first NOR gate.
  • the control terminal of the second switch is coupled to the third terminal of the second NOR gate.
  • the fifth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along the stacking direction of the fifth magnetic unit, the magnetization direction of the ferromagnetic layer of the fifth magnetic unit is along the stacking direction of the fifth magnetic unit, and the fifth The magnetic unit includes a first port on a first side of the fifth magnetic unit and a second port on a second side opposite to the first side, the first port of the fifth magnetic unit is coupled to a power supply, and the fifth magnetic unit’s The second port is coupled to the first switch and the second switch.
  • the write current of the fifth magnetic unit has a direction from the first port of the fifth magnetic unit to the second port of the fifth magnetic unit, and the direction of the magnetic field applied to the fifth magnetic unit is parallel or antiparallel in the direction of the write current.
  • a full adder includes a first NOR gate, a second NOR gate, a third NOR gate and a fourth NOR gate implemented by the first aspect of the present disclosure.
  • the logic input of the first magnetic unit of the first NOR gate is a first addend, and the logic input of the second magnetic unit of the first NOR gate is a second addend.
  • the first end of the first NOR gate is coupled to the first end of the second NOR gate, and the second end of the first NOR gate is coupled to the second end of the second NOR gate, wherein the second NOR gate
  • the logic input of the first magnetic unit of the NOR gate is the complement of the first addend
  • the logic input of the second magnetic unit of the second NOR gate is the complement of the second addend.
  • the control terminal of the first switch is coupled to the third terminal of the first NOR gate.
  • the control terminal of the second switch is coupled to the third terminal of the second NOR gate, and the first terminal of the second switch is coupled to the first terminal of the first switch to provide a first logic output.
  • the logic input of the second magnetic unit of the third NOR gate is the carry number of adjacent lower bits.
  • the first end of the third NOR gate is coupled to the first end of the fourth NOR gate, the second end of the third NOR gate is coupled to the second end of the fourth NOR gate, and the third NOR gate is coupled to the second end of the fourth NOR gate.
  • the second port of the first magnetic unit is coupled to the second port of the first magnetic unit of the fourth NOR gate, and the first port of the first magnetic unit of the fourth NOR gate is coupled to the first logic output, wherein
  • the logic input of the second magnetic unit of the fourth NOR gate is the complement number of the carry number of the adjacent low bit.
  • the control terminal of the third switch is coupled to the third terminal of the third NOR gate.
  • the control terminal of the fourth switch is coupled to the third terminal of the fourth NOR gate.
  • the sixth magnetic unit includes a spin Hall effect layer and a ferromagnetic layer arranged along the stacking direction of the sixth magnetic unit, the magnetization direction of the ferromagnetic layer of the sixth magnetic unit is along the stacking direction of the sixth magnetic unit, and the sixth
  • the magnetic unit includes a first port on a first side of the sixth magnetic unit and a second port on a second side opposite to the first side, the first port of the sixth magnetic unit is coupled to a power source, and the sixth magnetic unit The second port of is coupled to the third switch and the fourth switch.
  • a sixth magnetic unit is used for storage and bits.
  • the switch circuit is used for activating the first NOR gate and the second NOR gate for a first period of time to store the first logic output in the first magnetic unit of the third NOR gate and to store the second NOR gate complementary to the first logic output.
  • Two logic outputs are stored in the first storage unit of the fourth NOR gate, and during a second time period, the third NOR gate and the fourth NOR gate are activated to store the logic output in the sixth magnetic unit.
  • the full adder also includes the memory-computing integrated device according to the second aspect of the present disclosure.
  • the logic input of the first magnetic unit of the storage-calculation integrated device is the value of the first addend
  • the logic input of the second magnetic unit of the storage-calculation integrated device is the value of the second addend
  • the logic input of the third magnetic unit of the storage-calculation integrated device is The logic input is the carry number of the adjacent low bit
  • the fourth magnetic unit of the memory-calculation integrated device stores the carry number to the adjacent high bit.
  • the write current of the sixth magnetic unit has a direction from the first port of the sixth magnetic unit to the second port of the sixth magnetic unit, and the direction of the magnetic field applied to the sixth magnetic unit is parallel or antiparallel in the direction of the write current.
  • the write current of the fourth magnetic unit has a direction from the second port of the fourth magnetic unit to the first port of the fourth magnetic unit, and the direction of the magnetic field applied to the fourth magnetic unit is parallel or antiparallel to the direction of the write current.
  • an apparatus includes a printed circuit board, and further includes a spin logic device according to the first aspect of the present disclosure.
  • the spin logic device is arranged on a printed circuit board.
  • an apparatus includes a printed circuit board, and further includes the integrated storage and calculation device according to the second aspect of the present disclosure.
  • the storage and calculation integrated device is arranged on the printed circuit board.
  • an apparatus includes a printed circuit board, and further includes a half adder according to the third aspect of the present disclosure.
  • the half adder is provided on the printed circuit board.
  • an apparatus includes a printed circuit board, and further includes a full adder according to the fourth aspect of the present disclosure.
  • the full adder is arranged on the printed circuit board.
  • Figure 1A shows a schematic diagram of a spin logic device according to some embodiments of the present disclosure.
  • FIG. 1B shows a perspective view of a magnetic unit of the spin logic device in FIG. 1A .
  • FIG. 1C is a graph showing the relationship between the output voltage and the input voltage of the spin logic device in FIG. 1A .
  • FIG. 2 shows a schematic diagram of a spin logic device according to some embodiments of the present disclosure.
  • Fig. 3A shows a schematic diagram of an integrated storage and computing device according to some embodiments of the present disclosure.
  • FIG. 3B shows the variation relationship between the current in the magnetic unit of the memory-computing integrated device in FIG. 3A and the input voltage.
  • FIG. 3C shows the variation relationship of the Hall resistance of the magnetic unit of the memory-computing integrated device in FIG. 3A with the writing current.
  • FIG. 4 shows a schematic diagram of a half adder according to some embodiments of the present disclosure.
  • FIG. 5 shows a schematic diagram of a carry calculation part of a full adder according to some embodiments of the present disclosure.
  • FIG. 6 shows a schematic diagram of a sum bit calculation part of a half adder according to some embodiments of the present disclosure.
  • FIG. 7 shows an equivalent circuit of a sum bit calculation part of a half adder in a first mode according to some embodiments of the present disclosure.
  • FIG. 8 shows an equivalent circuit of a sum bit calculation part of a half adder in a second mode according to some embodiments of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it.
  • the term “coupled” may indicate a direct connection between one component and another component, and may also include an indirect connection via other components.
  • a and/or B means A, B, or A and B.
  • Other definitions, both express and implied, may also be included below.
  • Embodiments of the present disclosure provide an improved spin logic device, which can be implemented in various logic circuits, for example, processors, etc., and can also be implemented in a memory-computing integrated device.
  • spin logic devices can be used to implement logic operations for applications in computing devices such as processors or controllers.
  • Spin logic devices can be combined with each other to form various logic gates to realize logic operations. Further, by combining logic gates, duplicated computing functions can be realized to implement a processor or controller.
  • Spin logic devices, logic gates, and processors or controllers can be arranged on a printed circuit board (PCB) to be incorporated in a variety of devices, such as computers, servers, laptops, desktops, mobile phones , cellular phones, personal digital assistants, wearables, or electronic devices such as set-top boxes, and can also be used in applications such as self-driving cars.
  • a spin logic device that performs computation functions can be combined with a memory device for storing computation results to realize a memory-computing integrated device.
  • PCB printed circuit board
  • FIG. 1A shows a schematic diagram of a spin logic device 10 according to some embodiments of the present disclosure.
  • the spin logic device 10 includes a magnetic unit 5 , wherein FIG. 1B shows a perspective view of the magnetic unit 5 .
  • Fig. 1A shows a section of the magnetic unit 5 perpendicular to the z-axis direction, i.e., a section in the x-y plane.
  • FIG. 1B shows a perspective perspective view of the magnetic unit 5 in FIG. 1A .
  • the magnetic unit 5 includes a spin Hall effect (Spin Hall Effect, SHE) layer 52 and a ferromagnetic layer 53 arranged along a stacking direction, wherein the stacking direction is the z-axis direction, and the magnetization of the ferromagnetic layer 53 The direction is along the stacking direction.
  • the SHE layer 52 may include metal materials with spin Hall effect, for example, heavy metal materials such as Ta and Pt. Alternatively, the SHE layer 52 may also include a topological insulator material.
  • the ferromagnetic layer 53 may include various ferromagnetic materials such as Fe, Co, Ni and alloys thereof such as CoFeB and the like. As shown in FIG.
  • a SHE layer 52 is formed over a substrate 51
  • a ferromagnetic layer 53 is formed over the SHE layer 52
  • an optional protective layer 54 may be formed over the ferromagnetic layer 53 .
  • the protection layer 54 may include an oxide layer, such as MgO and other materials.
  • the thicknesses of the SHE layer 52, the ferromagnetic layer 53 and the protective layer 54 may be in the range of several nanometers.
  • the magnetic unit 5 includes a first port 1 on a first side, a second port 2 on a second side opposite to the first port, and between the first port 1 and the second port 3 and at the Third port 3 on the third side.
  • the first port 1 is coupled to the first terminal 11 of the spin logic device 10
  • the second port 2 is coupled to the second terminal 12 of the spin logic device 10
  • the third port 3 is coupled to the third terminal of the spin logic device 13 coupling.
  • the first port 1 , the second port 2 and the third port 3 may be respectively coupled to the first terminal 11 , the second terminal 12 and the third terminal 13 through metal electrodes.
  • Figure 1B shows a first electrode 55, a second electrode 56 and a third electrode 57, wherein the first electrode 55 is used to couple the first port (not shown) of the magnetic unit 5 with the first end (not shown)
  • the second electrode 56 is used to couple the second port (not shown) of the magnetic unit 5 with the second terminal (not shown)
  • the third electrode 57 is used to couple the third port (not shown) of the magnetic unit 5 Out) is coupled with a third terminal (not shown).
  • the first port of the magnetic unit 5 may be the portion of the SHE layer 52 in contact with the first electrode 55
  • the first end of the spin logic device may be the first electrode 55. The part that connects with the external circuit.
  • the first port to the third port are in contact with the corresponding electrodes, it can be seen that the first port and the third port are respectively on one side of the magnetic unit 5 , rather than on the upper surface or the lower surface of the magnetic unit 5 .
  • the first electrode 55 - the third electrode 57 are only in contact with the SHE layer 52 in FIG. 1B
  • the first electrode 55 - the third electrode 57 may also have other configurations.
  • the first electrode 55 -third electrode 57 may have the same height as the SHE layer 52 -protection layer 54 stack.
  • the first electrode 55 - the third electrode 57 may have the same height as the stack of the SHE layer 52 and the ferromagnetic layer 53 .
  • the height of a part of the first electrode 55 - the third electrode 57 is different from that of the other part of the electrodes.
  • the SHE layer 52 includes a metal layer
  • both the SHE layer 52 and the ferromagnetic layer 53 are conductive, therefore, the first electrode 55-the third electrode 57 can be in contact with at least a part of the SHE layer 52 and the ferromagnetic layer 53 .
  • the inside of the SHE layer 52 may not conduct electricity, but only generate current on the surface, which may require the first electrode 55 - the third electrode 57 to be in contact with the ferromagnetic layer 53 .
  • the first terminal 11 of the spin logic device 10 is connected to a first voltage (for example, an input voltage Vin), and the second terminal 12 of the spin logic device 10 is coupled to a second voltage (for example, ground). catch.
  • a first voltage may be applied to the first electrode 55 and a second voltage may be applied to the second electrode 56 . In this way, a voltage difference can be generated between the first electrode 55 and the second electrode 56 , thereby generating a write current in the SHE layer 52 .
  • the SHE layer 52 can generate spin-orbit torque by virtue of the spin Hall effect.
  • the anomalous Hall effect Anomalous Hall Effect, AHE
  • AHE anomalous Hall Effect
  • asymmetry between voltages can be amplified by negative differential resistance.
  • Negative differential resistance has the effect of further increasing large voltages and further reducing small voltages, therefore, asymmetry between voltages can be amplified.
  • a first negative differential resistance (Negative Differential Resistance, NDR) 4 is coupled between the first terminal 11 and the third terminal 13 of the spin logic device 10 .
  • the second negative differential resistor 6 is coupled between the second terminal 12 and the third terminal 13 of the spin logic device 10 .
  • the first NDR 4 and the second NDR 6 may be the same, or may have the same resistance characteristics.
  • the first NDR 4 and the second NDR 6 can be realized by elements having a negative differential resistance effect such as complementary junction field effect transistors or resonant tunneling transistors.
  • a Hall voltage is generated in the y direction, resulting in an asymmetry between the voltage V13 across the first NDR 4 and the voltage V23 across the second NDR 6, that is, one of V13 and V23 is high voltage, one for low voltage. If the magnetization direction of the magnetic unit 5 is changed, the Hall voltage is reversed, so that one of V 13 and V 23 is a low voltage and the other is a high voltage.
  • the magnetization direction of the magnetic unit 5 is used as a logic input.
  • the magnetization direction perpendicular to the substrate surface can be defined as a logic input "1” and the magnetization direction perpendicular to the substrate surface can be defined as a logic input "0".
  • the voltage magnitude of V 13 and V 23 may correspond to a logic output, for example, a high voltage is a logic output "1", and a low voltage is a logic output "0".
  • the asymmetry of the output voltage caused by the abnormal Hall effect is not high, therefore, the first NDR 4 and the second NDR 6 can be used to amplify the asymmetry of the output voltage, so as to achieve the purpose of identifying the logic output.
  • the magnetic unit 5 is symmetrical about an axis of symmetry that lies in the xy plane and is parallel to the y axis.
  • the first port 1 and the second port 2 are symmetrical with respect to the axis of symmetry, and the third port 3 is located on the axis of symmetry.
  • this symmetrical structure when no Hall voltage is generated in the magnetic unit 5, there is no asymmetry in the voltages V 13 and V 23 .
  • this symmetrical structure is more conducive to creating a clear asymmetry in the voltages V 13 and V 23 , making it easier to identify the logic output.
  • FIG. 1A and FIG. 1B show that the magnetic unit 5 has a T-shaped structure, the magnetic unit 5 may also have other shapes, especially other symmetrical shapes.
  • a spin logic device 10 as shown in FIG. 1A and FIG. 1B is prepared, wherein the magnetic material structure of the magnetic unit 5 is: Ta/CoFeB/MgO grown on thermally oxidized on a silicon substrate.
  • the first NDR 4 and the second NDR 6 are realized by complementary junction field effect transistors.
  • FIG. 1C shows a graph of the relationship between the output voltage and the input voltage of this embodiment. As shown in FIG. 1C , no matter whether the magnetization direction M is upward or downward, the voltage difference between the logic output "1" and the logic output "0" is relatively obvious in a large input voltage range.
  • the asymmetry between V 13 and V 23 is the largest, and the ratio of the output voltage V 13 to V 23 can reach 500%. Due to the asymmetry of the output voltage, the logic output can be remarkably identified.
  • FIG. 2 shows a schematic diagram of a spin logic device 100 according to some embodiments of the present disclosure.
  • the spin logic device 100 includes a first magnetic unit 101 , a second magnetic unit 102 and a third magnetic unit 103 , and each magnetic unit can be realized by the magnetic unit 5 shown in FIG. 1 .
  • the logic states of the first magnetic unit 101 , the second magnetic unit 102 and the third magnetic unit 103 may be represented by bits a, b and c, respectively.
  • the first magnetic unit 101 , the second magnetic unit 102 and the third magnetic unit 103 are coupled in parallel.
  • the first port 1 of the first magnetic unit 101, the second magnetic unit 102, and the third magnetic unit 103 is coupled to the first terminal 111 of the spin logic device 100
  • the first magnetic unit 101, the second magnetic unit 102, and The second port 2 of the third magnetic unit 103 is coupled to the second terminal 112 of the spin logic device 100
  • the third port 3 of the first magnetic unit 101, the second magnetic unit 102, and the third magnetic unit 103 is coupled to the spin logic device 100.
  • the third terminal 113 of the logic device 100 is coupled.
  • first NDR 104 is coupled between the first terminal 111 and the third terminal 113 of the spin logic device 100
  • second NDR 106 is coupled between the first terminal 112 and the third terminal 113 of the spin logic device 100 between.
  • the first terminal 111 of the spin logic device 100 is coupled to the input voltage Vin, and the second terminal 112 of the spin logic device 100 is grounded.
  • the spin logic device 100 can implement four logic operations of "AND”, “OR”, “NAND” and “NOR".
  • the magnetization directions of the first magnetic unit 101 and the second magnetic unit 102 may be logic inputs.
  • the magnetization direction of the third magnetic unit 103 can be used as a bias condition to implement different logic operations.
  • Voltages V 13 and V 23 may be logic outputs, where an output high voltage is a logic "1" and an output low voltage is a logic "0".
  • an input voltage Vin of 0.4V is provided, and Table 1 shows the logic table of this embodiment.
  • the logic inputs (a, b) of the first magnetic unit 101 and the second magnetic unit 102 are (1,1), (1,0), respectively, (0,1), (0,0)
  • the voltage V 13 is 0.3892V (high potential "1"), 0.0104V (low potential “0"), 0.0105V (low potential “0”), 0.0104V (Low potential “0"), corresponding to AND logic operation.
  • the voltage V 23 is 0.0107V (low potential “0"), 0.3895V (high potential “1"), 0.3894V (high potential “1”), 0.3895V (high potential “1”), corresponding to NAND logic operation.
  • the logic inputs (a, b) of the first magnetic unit 101 and the second magnetic unit 102 are (1,1), (1,0) respectively , (0,1), (0,0)
  • the voltage V 13 is 0.3898V (high potential "1"), 0.3895V (high potential "1"), 0.3894V (high potential "1"), 0.0081 V (low potential "0”), corresponding to OR logic operation.
  • the output voltages of the input voltage V 23 are 0.0101V (low potential “0"), 0.0104V (low potential “0"), 0.0105V (low potential “0”), 0.3910V (high potential “1”) , corresponding to the NOR logical operation. It should be understood that the above numbers are provided as examples only and that different devices may achieve different data results.
  • FIG. 3A shows a schematic diagram of an integrated storage and calculation device 200 according to some embodiments of the present disclosure.
  • the storage-computing integrated device 200 can implement logic operations and storage of output results at the same time.
  • a memory-computing integrated device 200 can be formed.
  • the first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 can all be realized by the magnetic unit 10 shown in FIG. 1 .
  • the first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 are represented by bits a, b and c, respectively.
  • the first magnetic unit 201 , the second magnetic unit 202 and the third magnetic unit 203 are coupled in parallel.
  • the first NDR 204 is coupled between the first terminal 211 and the third terminal 213 of the integrated storage and calculation device 200
  • the second NDR 206 is coupled between the second terminal 212 and the third terminal 213 of the integrated storage and calculation device 200 .
  • the first terminal 211 of the integrated storage and calculation device 200 is coupled to the input voltage Vin
  • the second terminal 212 of the integrated storage and calculation device 200 is grounded.
  • the third terminal 213 of the integrated storage and calculation device 200 is coupled to the control terminal (ie, the gate) of the transistor 207, and the first terminal (eg, the source terminal or the drain terminal) of the transistor 207 is connected to the first terminal of the magnetic unit 205 (state d).
  • One terminal 1 is coupled, and the second terminal (for example, the drain terminal or the source terminal) of the transistor 207 is grounded.
  • the second terminal 2 of the magnetic unit 205 is coupled to the power supply V DD to form a loop from the power supply V DD to the ground.
  • the initial state of the magnetic unit 205 may be set to logic "0".
  • the logic part of the integrated storage and calculation device 200 outputs "0"
  • the output voltage of the logic part is less than the turn-on voltage of the transistor 207
  • the transistor 207 is not conducting, and there is no current in the loop from the power supply V DD to the ground, and the magnetic unit 205
  • the magnetization direction does not change and is "0”.
  • the logic part of the integrated storage and calculation device 200 outputs "1”
  • the output voltage of the logic part is greater than the turn-on voltage of the transistor 207, the transistor 207 is turned on, and there is a write current I O flowing through the magnetic circuit in the loop from the power supply V DD to the ground.
  • Unit 205 When the logic part of the integrated storage and calculation device 200 outputs "1”, the output voltage of the logic part is greater than the turn-on voltage of the transistor 207, the transistor 207 is turned on, and there is a write current I O flowing through the magnetic circuit in the loop from the power
  • the magnetization direction of the magnetic unit 205 is reversed and becomes “1”, thereby completing the storage of the logic output result in the magnetic unit 205 .
  • the direction of the magnetic field H is antiparallel to the direction of the write current IO .
  • the logic operation on the magnetic unit 205 can be changed.
  • the power supply V DD can be coupled to the first port 1 of the magnetic unit 205
  • the second port 2 of the magnetic unit 205 can be connected to the transistor 207 to change the direction of the write current I O .
  • the relative relationship between the direction of the magnetic field H and the direction of the write current I0 can be changed.
  • the heavy metals in the magnetic unit 205 are Pt and Ta
  • the relative relationship between the writing current and the direction of the magnetic field is opposite.
  • transistor 207 is shown in FIG. 3A as a field effect transistor, any other suitable switch may be used to implement transistor 207 .
  • FIG. 3B shows the variation relationship of the current I O generated in the magnetic unit 205 in the storage-computing integrated device 200 of FIG. 3A with the input voltage Vin.
  • FIG. 3C shows the variation relationship of the Hall resistance of the magnetic unit 205 with the write current I O when the applied magnetic field is 10 mT.
  • the critical switching current of the magnetic unit 205 is -0.7 mA. Therefore, when the voltage V 23 outputs “1”, the generated write current I0 can reverse the magnetization direction of the magnetic unit 205 and write the result of the logic output into the magnetic unit 205 .
  • FIG. 4 shows a schematic diagram of a half adder 300 according to some embodiments of the present disclosure.
  • the half adder 300 includes two instances of the spin logic device 100 shown in FIG. Three magnetic units 303 and first NDR 304 and second NDR 306, the second example of spin logic device 100 includes first magnetic unit 351, second magnetic unit 352 and third magnetic unit 353 and first NDR 354 and second NDR 356.
  • the logic input of the first magnetic unit 301 is bit a
  • the logic input of the first magnetic unit 351 is bit a, which is complementary to bit a.
  • the logic input of the second magnetic unit 302 is bit b
  • the logic input of the second magnetic unit 352 is bit b, which is complementary to bit b.
  • the logic state of the third magnetic unit 303 is bit c 1
  • the logic state of the third magnetic unit 353 is bit c 2 .
  • an instance of spin logic device 100 can be used as a logic gate.
  • the first instance of the spin logic device 100 is referred to as a first logic gate
  • the second instance of the spin logic device 100 is referred to as a second logic gate.
  • an "exclusive OR" (XOR) of bits a and b can be realized, thereby realizing a half adder.
  • Both the first logic gate and the second logic gate can be used to realize the "NOR” gate, wherein the logic input of one "NOR” gate is bit a and bit b, and the magnetization direction of the control bit c 1 is downward (logic “1 "), so as to realize a NOR b; the logic input of another "NOR” gate is a bit with bit The magnetization direction of the two is opposite to bit a and bit b, and the magnetization direction of control bit c2 is downward (logic “ 1 "), thus realizing
  • the third terminal 313 of the first logic gate (aNORb) is coupled to the control terminal (eg, gate) of the transistor 307, and the second logic gate
  • the third terminal 363 of is coupled to the control terminal (eg, gate) of the transistor 309 .
  • Transistors 307 and 309 are coupled in parallel between magnetic unit 305 (bit d) and ground.
  • First terminals (eg, source or drain) of transistors 307 and 309 are connected in series with second port 2 of magnetic unit 305, second terminals (eg, drain or source) of transistors 307 and 309 are grounded and the magnetic unit
  • the first port 1 of 305 is coupled to the power supply V DD so as to form a loop between the power supply and the ground.
  • both the first logic gate and the second logic gate output "0"
  • the transistors 307 and 309 are not turned on, and there is no current in the loop.
  • one of the logic gates outputs “1”
  • at least one of the transistors 307 and 309 is turned on, and a write current flows through the magnetic unit 305 in the loop.
  • the preset magnetization direction of the magnetic unit 305 is vertical film facing down (logic “1”).
  • the write current I O passes through the magnetic unit 305 . As shown in FIG.
  • the direction of the magnetic field H is the same as that of the write current IO .
  • the magnetization direction of the magnetic unit 305 is reversed, and the vertical film faces upward, that is, the "0" state.
  • the transistors 307 and 309 are both off, no write current I O passes through the magnetic unit 305, and the magnetization direction of the magnetic unit 305 remains "1". Therefore, the transistors 307 and 309 and the magnetic unit 305 realize the "NOR" NOR of the output results of the two logic gates, thereby realizing (a NOR b)NOR That is, the magnetic unit 305 stores the XOR operation result of bit a and bit b.
  • Table 2 shows a logical table according to some embodiments of the present disclosure.
  • the spin logic devices 100 shown in FIG. 2 can be combined to form a full adder.
  • the full adder can realize the addition operation of two binary digits (referred to as the first addend and the second addend respectively), and output the sum bit and the carry bit.
  • the carry function can be realized.
  • the logic inputs Ai and Bi represent the first addend and the second addend
  • the logic input Ci-1 represents the carry number of the adjacent low bit
  • the logic output C i represents the carry number to the adjacent high bit.
  • FIG. 5 shows a schematic diagram of a carry calculation part 400 of a full adder according to some embodiments of the present disclosure.
  • the carry calculation part 400 includes a first magnetic unit 401, a second magnetic unit 402 and a third magnetic unit 403, wherein the first magnetic unit 401, the second magnetic unit 402 and the third magnetic unit 403 are respectively Receives logic inputs Ai, Bi, and Ci-1.
  • the first NDR 404 is coupled between the first terminal 411 and the third terminal 413
  • the second NDR 406 is coupled between the second terminal 412 and the third terminal 413.
  • the third terminal 413 is coupled to the control terminal (for example, the gate) of the transistor 407, and the first terminal (for example, the source terminal or the drain terminal) of the transistor 407 is coupled to the second port 2 of the magnetic unit 405. connected, the second terminal (eg, the drain terminal or the source terminal) of the transistor 407 is grounded, and the first port 1 of the magnetic unit 405 is coupled to the power supply V DD .
  • the initial state of the magnetic unit 405 may be set to logic "0".
  • the carry calculation part 400 outputs "0"
  • the output voltage is lower than the turn-on voltage of the transistor 407, the transistor 407 is not turned on, and there is no current in the loop from the power supply V DD to the ground, and the logic state of the magnetic unit 405 remains unchanged, which is "0”.
  • the carry calculation part 400 outputs "1”
  • the output voltage is greater than the turn-on voltage of the transistor 407, the transistor 407 is turned on, and a write current flows through the magnetic unit 405 in the loop from the power supply V DD to the ground.
  • the magnetization direction of the magnetic unit 405 is reversed, corresponding to a logic "1", thereby completing information storage.
  • the direction of the magnetic field H is parallel to the direction of the write current.
  • FIG. 6 shows a schematic diagram of a sum bit calculation part 500 of a full adder according to some embodiments of the present disclosure.
  • the sum bit of the full adder can be realized by combining the half adder 300 ("exclusive OR" XOR) shown in Figure 4:
  • the sum bit calculation part 500 includes a first magnetic unit 501 (logic input Ai), a second magnetic unit 502 (logic input Bi), a third magnetic unit 503 (control bit c 1 ), a first NDR 504 , second NDR 506, first magnetic unit 551 (logic input Complement of logic input Ai), second magnetic unit 552 (logic input Complement of logic input Bi), third magnetic unit 553 (control bit c 2 ), first NDR 554 and second NDR 556 .
  • the sum bit calculation part 500 also includes a first magnetic unit 521 (logic input is Ii), a second magnetic unit 522 (logic input Ci-1), a third magnetic unit 523 (control bit c 3 ), a first NDR 524 , second NDR 526, first magnetic unit 571 (logic input Complement of logic input Ii), second magnetic unit 572 (logic input Complement of logic inputs Ci ⁇ 1), third magnetic unit 573 (control bit c 4 ), first NDR 574 and second NDR 576 .
  • the initial state of bit I i and bit S i may be logic "1", ie, the magnetization direction is downward perpendicular to the substrate surface.
  • the logical operations shown in Table 3 are similar to the logical operations described in conjunction with FIG. 4 , and will not be repeated here.
  • sum bit calculation section 500 also includes transistors 505 , 525 , 555 and 575 , which may operate as described in connection with FIG. 4 .
  • the sum bit calculation part 500 may further include a switch circuit for switching the sum bit calculation part 500 between the first mode and the second mode.
  • the switching circuit includes transistors 531-542.
  • the second port 2 of the first magnetic unit 521 is selectively coupled to the second port 2 of the first magnetic unit 571 via the transistor 537 .
  • FIG. 7 shows an equivalent circuit 600 of the first mode of the sum bit calculation section 500
  • FIG. 8 shows an equivalent circuit 700 of the second mode of the sum bit calculation section 500 .
  • the calculation of the sum bit can be realized by operating the sum bit calculating section 500 alternately in the first mode and the second mode.
  • the sum bit calculation part 500 further includes a controller 510 to realize automatic switching between the first mode and the second mode.
  • the controller 510 may operate under the control of a clock CLK, and may include a first output Q 1 and a second output Q 2 .
  • the first output Q1 is coupled to control terminals (eg, gates) of the transistors 531 , 533 , 537 and 538 for turning on and off the transistors 531 , 533 , 537 and 538 .
  • the second output Q2 is coupled to the control terminals (eg, gates) of the transistors 532, 534, 535, 536, 539, 541, and 542 for turning on and off the transistors 532, 534, 535, 536, 539, 541 and 542.
  • FIG. 7 shows a schematic diagram of the sum bit calculation section 500 in this state.
  • FIG. 8 shows a schematic diagram of the sum bit calculation section 500 in this state.

Abstract

本公开的实施例提供了一种自旋逻辑器件、存算一体器件、半加器和全加器。在该自旋逻辑器件中，磁性单元包括沿堆叠方向布置的自旋霍尔效应层和铁磁层。铁磁层的磁化方向沿着堆叠方向。磁性单元包括在第一侧的第一端口、在与第一侧相对的第二侧的第二端口以及位于第一端口与第二端口之间并且在第三侧的第三端口。第一负微分电阻耦接在第一端口与第三端口之间。第二负微分电阻耦接在第二端口与第三端口之间。该自旋逻辑器件可以在第一负微分电阻和/或第二负微分电阻两端产生显著不同的输出电压，以识别不同的逻辑输出。通过这种方式，可以实现电压型自旋逻辑器件，从而降低器件功耗，提高器件性能。

Description

自旋逻辑器件、存算一体器件、半加器和全加器 技术领域
本公开的实施例一般地涉及逻辑器件，并且更具体地涉及自旋逻辑器件、存算一体器件、半加器以及全加器。
背景技术
目前，通过使用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)器件进行逻辑运算。然而，在CMOS器件中，数据具有易失性，在进行逻辑运算时，需要将运算结果单独存放在存储器中。由于计算机的数据运算和存储是分离的，数据在处理器和存储器之间的传输成为限制计算机速度和性能提高的一个很大限制因素。通过将存储和逻辑运算单元相融合，可以实现存内计算或存算一体，其中存内计算要求逻辑器件兼具数据运算和存储的能力。自旋逻辑器件，又称为磁逻辑器件，可以用于实现存算一体技术。自旋逻辑器件是利用磁性材料中电子的自旋特性设计的数字逻辑器件，这种器件相比常规半导体逻辑器件，具有速度快、功耗低、逻辑信息的非易失性、防辐射、与CMOS工艺相兼容等优点，因此被认为很有希望替代传统的半导体逻辑器件。然而，现有的自旋逻辑器件是电流型逻辑器件，其输出信号为电流信号，功耗较大，仍然存在进一步改进的空间。
发明内容
本公开的实施例提供了一种自旋逻辑器件、存算一体器件、半加器和全加器。
根据本公开的第一方面，提供了一种自旋逻辑器件。在该自旋逻辑器件中，第一磁性单元包括沿着堆叠方向布置的自旋霍尔效应层和铁磁层。铁磁层的磁化方向沿着堆叠方向，即，与堆叠方向平行或反平行。第一磁性单元包括在第一磁性单元的第一侧的第一端口、在与第一侧相对的第二侧的第二端口以及位于第一磁性单元的第一端口与第二端口之间并且在第一磁性单元的第三侧的第三端口。第一磁性单元的第一端口与自旋逻辑器件的第一端耦接，第一磁性单元的第二端口与自旋逻辑器件的第二端耦接，并且第一磁性单元的第三端口与自旋逻辑器件的第三端耦接。第一负微分电阻耦接在自旋逻辑器件的第一端与第三端之间。第二负微分电阻耦接在自旋逻辑器件的第二端与第三端之间。
第一磁性单元的第一端口至第三端口均设置在第一磁性单元的侧面处。在从第一磁性单元的第一端口至第二端口之间存在电流时，自旋霍尔效应层可以产生自旋轨道力矩。在自旋轨道力矩和磁场的共同作用下，借助于自旋霍尔效应，可以在铁磁层的平面内中产生霍尔电压，从而在第一磁性单元的第三端口处可以体现霍尔电压。由于霍尔电压的存在，在左侧电压和右侧电压之间产生不对称性，其中左侧电压与右侧电压分别表示自旋逻辑器件的第一端与第三端之间的电压以及自旋逻辑器件的第二端与第三端之间的电压。负微分电阻具有将大电压进一步增大，并将小电压进一步减小的效果，因此，可以放大电压之间的不对称性。该自旋逻辑器件可以在第一负微分电阻和/或第二负微分电阻两端产生显著不同的输出电压，以识别不同的逻辑输出。通过这种方式，可以实现电压型自旋逻辑器件。电流型自旋逻辑器件通过不同的电流大小来表示不同的逻辑输出。为了区分不同的逻辑，需要使用较大的电流，因此，器件功耗较高。与之相比，电压型自旋逻辑器件不需要大电流操作，从而降低器件功耗，提高器件性能。
在一些实施例中，第一磁性单元相对于与堆叠方向垂直的对称轴对称，第一磁性单元的第二端口与第一端口相对于对称轴对称，并且第一磁性单元的第三端口位于对称轴上。通过这种对称结构，可以尽可能地放大不同逻辑输出对应的电压的不对称性，从而更加容易识别不同的逻辑输出。
在一些实施例中，自旋逻辑器件的第一端用于耦接到第一电压，并且自旋逻辑器件的第二端用于耦接到第二电压，以产生在自旋逻辑器件的第一端与第二端之间的电流。自旋逻辑器件用于在自旋逻辑器件的第一端与第三端之间输出表示第一逻辑输出的第三电压。自旋逻辑器件用于在自旋逻辑器件的第二端与第三端之间输出表示第二逻辑输出的第四电压。借助于电流方向、磁化方向和对称轴方向之间的垂直正交关系，由于自旋霍尔效应，自旋逻辑器件的第一端与第二端之间的电流可以在对称轴方向上产生霍尔电压，从而导致第三电压和第四电压之间的不平衡，从而自旋逻辑器件可以使用第三电压和/或第四电压来实现逻辑输出。
在一些实施例中，磁化方向表示第一磁性单元的逻辑输入。
在一些实施例中，第一负微分电阻和/或第二负微分电阻可以通过互补结型场效应晶体管或共振隧穿二极管来实现。
在一些实施例中，自旋霍尔效应层包括重金属层和/或拓扑绝缘体层。
在一些实施例中，响应于施加到第一磁性单元的磁场以及在第一磁性单元的第一端口与第二端口之间的写电流，磁化方向发生翻转。磁场的方向与写电流的方向平行或者反平行。磁化方向的翻转与写电流和磁场的方向的相对取向有关。
在一些实施例中，第一负微分电阻和第二负微分电阻相同。
在一些实施例中，该自旋逻辑器件还可以包括第二磁性单元，第二磁性单元包括沿着第二磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，第二磁性单元的铁磁层的磁化方向沿着第二磁性单元的堆叠方向。第二磁性单元包括在第二磁性单元的第一侧的第一端口、在与第二磁性单元的第一侧相对的第二侧的第二端口以及位于第二磁性单元的第一端口与第二端口之间并且在第二磁性单元的第三侧的第三端口，其中第二磁性单元的第一端口与自旋逻辑器件的第一端耦接，第二磁性单元的第二端口与自旋逻辑器件的第二端耦接，并且第二磁性单元的第三端口与自旋逻辑器件的第三端耦接。例如，第二磁性单元可以与如上的第一磁性单元具有相同的布置。该自旋逻辑器件还可以包括第三磁性单元，第三磁性单元包括沿着第三磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，第三磁性单元的铁磁层的磁化方向沿着第三磁性单元的堆叠方向，其中，第三磁性单元包括在第三磁性单元的第一侧的第一端口、在与第三磁性单元的第一侧相对的第二侧的第二端口以及位于第三磁性单元的第一端口与第二端口之间并且在第三磁性单元的第三侧的第三端口，第三磁性单元的第一端口与自旋逻辑器件的第一端耦接，第三磁性单元的第二端口与自旋逻辑器件的第二端耦接，并且第三磁性单元的第三端口与自旋逻辑器件的第三端耦接。例如，第三磁性单元可以与如上所述的第一磁性单元具有相同的布置。通过第一磁性单元至第三磁性单元，该自旋逻辑器件可以实现各种不同的逻辑门。
在一些实施例中，第一磁性单元的磁化方向表示第一磁性单元的逻辑输入。第二磁性单元的磁化方向表示第二磁性单元的逻辑输入。自旋逻辑器件用于在其第一端与第三端之间输出表示自旋逻辑器件的第一逻辑输出的第三电压。如果第三磁性单元的磁化方向为第一磁化方向，则第一逻辑输出作为表示第一磁性单元和第二磁性单元的逻辑输入的第一逻辑操作。如果第三磁性单元的磁化方向为第二磁化方向，则第一逻辑输出作为表示第一磁性单元和第 二磁性单元的逻辑输入的第二逻辑操作。自旋逻辑器件用于在其第二端与第三端之间输出表示自旋逻辑器件的第二逻辑输出的第四电压。如果第三磁性单元的磁化方向为第一磁化方向，则第二逻辑输出作为表示第一磁性单元和第二磁性单元的逻辑输入的第三逻辑操作。如果第三磁性单元的磁化方向为第二磁化方向，则第二逻辑输出作为表示第一磁性单元和第二磁性单元的逻辑输入的第四逻辑操作。
在一些实施例中，第一逻辑操作和第二逻辑操作包括“与非”和“或非”，第三逻辑操作和第四逻辑操作包括“与”和“或”。
根据本公开的第二方面，提供了一种存算一体器件。该存算一体器件包括第一方面中的逻辑门。另外，晶体管的控制端耦接到该逻辑门的第三端，并且第四磁性单元包括沿着第四磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，第四磁性单元的铁磁层的磁化方向沿着第四磁性单元的堆叠方向，第四磁性单元包括在第四磁性单元的第一侧的第一端口以及在与第一侧相对的第二侧的第二端口，第四磁性单元的第一端口耦接到晶体管的第一端，并且第四磁性单元的第二端口耦接到电源。在该存算一体器件中，通过逻辑门进行逻辑运算，并将逻辑运算的结果保存在第四磁性单元中。
在一些实施例中，第四磁性单元相对于与第四磁性单元的堆叠方向垂直的对称轴对称，第四磁性单元的第二端口相对于第四磁性单元的对称轴与第四磁性单元的第一端口对称。
在一些实施例中，第四磁性单元的写电流具有从第四磁性单元的第二端口向第四磁性单元的第一端口的方向，并且施加到第四磁性单元的磁场的方向平行或反平行于写电流的方向。
根据本公开的第三方面，提供了一种半加器。该半加器包括通过本公开的第一方面实现第一或非门和第二或非门。第一或非门的第一端与第二或非门的第一端耦接，第一或非门的第二端与第二或非门的第二端耦接，第一或非门的第一磁性单元和第二或非门的第一磁性单元的逻辑输入互补，并且第一或非门的第二磁性单元和第二或非门的第二磁性单元的逻辑输入互补。第一开关的控制端耦接到第一或非门的第三端。第二开关的控制端耦接到第二或非门的第三端。第五磁性单元包括沿着第五磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，第五磁性单元的铁磁层的磁化方向沿着第五磁性单元的堆叠方向，第五磁性单元包括在第五磁性单元的第一侧的第一端口以及在与第一侧相对的第二侧的第二端口，第五磁性单元的第一端口与电源耦接，第五磁性单元的第二端口与第一开关和第二开关耦接。
在一些实施例中，第五磁性单元的写电流具有从第五磁性单元的第一端口到第五磁性单元的第二端口的方向，并且施加到第五磁性单元的磁场的方向平行或反平行于写电流的方向。
根据本公开的第四方面，提供了一种全加器。该全加器包括通过本公开的第一方面实现的第一或非门、第二或非门、第三或非门和第四或非门。第一或非门的第一磁性单元的逻辑输入为第一加数，并且第一或非门的第二磁性单元的逻辑输入为第二加数。第一或非门的第一端与第二或非门的第一端耦接，第一或非门的第二端与第二或非门的第二端耦接，其中第二或非门的第一磁性单元的逻辑输入为第一加数的补数，并且第二或非门的第二磁性单元的逻辑输入为第二加数的补数。第一开关的控制端耦接到第一或非门的第三端。第二开关的控制端耦接到第二或非门的第三端，第二开关的第一端与第一开关的第一端耦接以提供第一逻辑输出。第三或非门的第二磁性单元的逻辑输入为相邻低位的进位数。第三或非门的第一端与第四或非门的第一端耦接，第三或非门的第二端与第四或非门的第二端耦接，第三或非门的第一磁性单元的第二端口与第四或非门的第一磁性单元的第二端口耦接，并且第四或非门的第一磁性单元的第一端口与第一逻辑输出耦接，其中第四或非门的第二磁性单元的逻辑输 入为相邻低位的进位数的补数。第三开关的控制端耦接到第三或非门的第三端。第四开关的控制端耦接到第四或非门的第三端。第六磁性单元包括沿着第六磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，第六磁性单元的铁磁层的磁化方向沿着第六磁性单元的堆叠方向，第六磁性单元包括在第六磁性单元的第一侧的第一端口以及在与第一侧相对的第二侧的第二端口，第六磁性单元的第一端口与电源耦接，并且第六磁性单元的第二端口与第三开关和第四开关耦接。第六磁性单元用于存储和位。开关电路用于在第一时间段激活第一或非门和第二或非门，以将第一逻辑输出存储在第三或非门的第一磁性单元并且将与第一逻辑输出互补的第二逻辑输出存储在第四或非门的第一存储单元，并且在第二时间段，激活第三或非门和第四或非门，以将逻辑输出存储在第六磁性单元。全加器还包括根据本公开的第二方面的存算一体器件。存算一体器件的第一磁性单元的逻辑输入为第一加数的值，存算一体器件的第二磁性单元的逻辑输入为第二加数的值，存算一体器件的第三磁性单元的逻辑输入为相邻低位的进位数，存算一体器件的第四磁性单元存储向相邻高位的进位数。
在一些实施例中，第六磁性单元的写电流具有从第六磁性单元的第一端口到第六磁性单元的第二端口的方向，并且施加到第六磁性单元的磁场的方向平行或反平行于写电流的方向。第四磁性单元的写电流具有从第四磁性单元的第二端口向第四磁性单元的第一端口的方向，并且施加到第四磁性单元的磁场的方向平行或反平行于写电流的方向。
根据本公开的第五方面，提供了一种设备。该设备包括印刷电路板，并且还包括根据本公开的第一方面所述的自旋逻辑器件。该自旋逻辑器件设置在印刷电路板上。
根据本公开的第六方面，提供了一种设备。该设备包括印刷电路板，并且还包括根据本公开的第二方面所述的存算一体器件。该存算一体器件设置在印刷电路板上。
根据本公开的第七方面，提供了一种设备。该设备包括印刷电路板，并且还包括根据本公开的第三方面所述的半加器。该半加器设置在印刷电路板上。
根据本公开的第八方面，提供了一种设备。该设备包括印刷电路板，并且还包括根据本公开的第四方面所述的全加器。该全加器设置在印刷电路板上。
提供发明内容部分是为了以简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开的关键特征或主要特征，也无意限制本公开的范围。
附图说明
通过结合附图对本公开示例性实施例进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显，其中，在本公开示例性实施例中，相同的附图标记通常代表相同部件。
图1A示出了根据本公开的一些实施例的自旋逻辑器件的示意图。
图1B示出了图1A中的自旋逻辑器件的磁性单元的立体图。
图1C示出了图1A中的自旋逻辑器件的输出电压与输入电压之间的关系图。
图2示出了根据本公开的一些实施例的自旋逻辑器件的示意图。
图3A示出了根据本公开的一些实施例的存算一体器件的示意图。
图3B示出了图3A的存算一体器件的磁性单元中的电流随输入电压的变化关系。
图3C示出了图3A的存算一体器件的磁性单元的霍尔电阻随写电流的变化关系。
图4示出了根据本公开的一些实施例的半加器的示意图。
图5示出了根据本公开的一些实施例的全加器的进位计算部分的示意图。
图6示出了根据本公开的一些实施例的半加器的和位计算部分的示意图。
图7示出了根据本公开的一些实施例的半加器的和位计算部分在第一模式中的等效电路。
图8示出了根据本公开的一些实施例的半加器的和位计算部分在第二模式中的等效电路。
根据通常的做法，附图中示出的各种特征部可能未按比例绘制。因此，为了清楚起见，可以任意地扩展或减小各种特征部的尺寸。另外，一些附图可能未描绘给定的系统、方法或设备的所有部件。最后，在整个说明书和附图中，类似的附图标号可用于表示类似的特征部。
具体实施例
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。术语“耦接”可以表示一个部件与另一部件之间的直接连接，也可以包括经由其他部件的间接连接。例如“A和/或B”表示A、B，或者A和B。下文还可能包括其他明确的和隐含的定义。
对方向或方位的任何参考仅旨在便于描述，而不以任何方式限制本公开的范围。例如“下部”、“上部”、“水平”、“竖直”、“上方”、“下方”、“朝上”、“朝下”、“顶部”和“底部”及其派生(例如“水平地”、“向上”、“向下”等)等相关术语在讨论中用来指代下文描述的或者在附图中示出的方位。这些相关术语仅仅是为了便于描述，而不要求装置以特定方位构造或操作。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
本公开的实施例提供了改进的自旋逻辑器件，该自旋逻辑器件可以在各种逻辑电路中实现，例如，处理器等，也可以在存算一体器件中实现。例如，自旋逻辑器件可以用于实现逻辑操作，以应用在处理器或控制器等计算装置中。自旋逻辑器件可以相互组合，以形成各种逻辑门，从而实现逻辑运算。进一步，将逻辑门进行组合，可以实现复制的计算功能，以实现处理器或控制器。自旋逻辑器件、逻辑门以及处理器或控制器可以布置在印刷电路板(Printed Circuit Board,PCB)上，从而合并在各种设备中，例如，计算机、服务器、便携式计算机、桌面计算机、移动电话、蜂窝电话、个人数字助理、可穿戴设备或机顶盒等电子设备，并且也可以用于自动驾驶汽车等应用。此外，可以将执行计算功能的自旋逻辑器件与用于存储计算结果的存储器件相结合，以实现存算一体器件。存算一体器件可以布置在印刷电路板(PCB)上，从而合并到各种设备中，例如，计算机、服务器、便携式计算机、桌面计算机、移动电话、蜂窝电话、个人数字助理、可穿戴设备或机顶盒等电子设备，并且也可以用于自动驾驶汽车等应用。
图1A示出了根据本公开的一些实施例的自旋逻辑器件10的示意图。如图1A所示，自旋逻辑器件10包括磁性单元5，其中图1B示出了磁性单元5的立体透视图。图1A示出了磁 性单元5垂直于z轴方向的截面，即，在x-y平面中的截面。图1B示出了图1A中的磁性单元5的立体透视图。如图1B所示，磁性单元5包括沿着堆叠方向布置的自旋霍尔效应(Spin Hall Effect,SHE)层52和铁磁层53，其中堆叠方向为z轴方向，铁磁层53的磁化方向沿着堆叠方向。SHE层52可以包括具有自旋霍尔效应的金属材料，例如，Ta、Pt等重金属材料。备选地，SHE层52也可以包括拓扑绝缘体材料。铁磁层53可以包括各种铁磁材料，例如，Fe、Co、Ni及其合金，例如，CoFeB等。如图1B所示，SHE层52形成在衬底51之上，铁磁层53形成在SHE层52之上，并且可选的保护层54可以形成在铁磁层53之上。保护层54可以包括氧化层，例如，MgO等材料。例如，SHE层52、铁磁层53和保护层54的厚度可以在几纳米的范围内。
如图1A所示，磁性单元5包括在第一侧的第一端口1、在与第一端口相对的第二侧的第二端口2以及位于第一端口1与第二端口3之间并且在第三侧的第三端口3。第一端口1与自旋逻辑器件10的第一端11耦接，第二端口2与自旋逻辑器件10的第二端12耦接，并且第三端口3与自旋逻辑器件的第三端13耦接。例如，第一端口1、第二端口2和第三端口3可以分别通过金属电极与第一端11、第二端12和第三端13耦接。
图1B示出了第一电极55、第二电极56和第三电极57，其中第一电极55用于将磁性单元5的第一端口(未示出)与第一端(未示出)耦接，第二电极56用于将磁性单元5的第二端口(未示出)与第二端(未示出)耦接，第三电极57用于将磁性单元5的第三端口(未示出)与第三端(未示出)耦接。尽管未明确示出，在图1B的实施例中，磁性单元5的第一端口可以是SHE层52与第一电极55相接触的部分，自旋逻辑器件的第一端可以是第一电极55与外部电路进行连接的部分。对于磁性单元5的第二端口和第三端口以及自旋逻辑器件的第二端和第三端，这里不再赘述。由于第一端口至第三端口与相应的电极接触，可以看出，第一端口与第三端口分别在磁性单元5的一侧，而不是在磁性单元5的上表面或下表面。应当理解，尽管在图1B中第一电极55-第三电极57仅与SHE层52接触，第一电极55-第三电极57也可以具有其他配置。例如，第一电极55-第三电极57可以具有与SHE层52-保护层54的堆叠相同的高度。又例如，第一电极55-第三电极57可以具有与SHE层52和铁磁层53的堆叠相同的高度。再例如，第一电极55-第三电极57中的一部分电极的高度与另一部分电极的高度不同。在SHE层52包含金属层的实施例中，SHE层52和铁磁层53均导电，因此，第一电极55-第三电极57与SHE层52和铁磁层53中的至少一部分接触即可。在SHE层52包含拓扑绝缘体的实施例中，SHE层52内部可能不导电，而只能在表面产生电流，这可能需要将第一电极55-第三电极57与铁磁层53接触。
如图1A所示，自旋逻辑器件10的第一端11与第一电压(例如，输入电压Vin)连接，并且自旋逻辑器件10的第二端12与第二电压(例如，接地)耦接。应当理解，第二电压也可以是接地之外的其他电压。为了方便讨论，以下将以输入电压Vin和接地电压为基础来描述本公开的实施例。如图1B所示，可以向第一电极55施加第一电压，并且向第二电极56施加第二电压。以这种方式，可以在第一电极55与第二电极56之间产生电压差，从而在SHE层52中产生写电流。在写电流的作用下，借助于自旋霍尔效应，SHE层52可以产生自旋轨道力矩。在自旋轨道力矩和磁场的共同作用下，由于铁磁层53中的反常霍尔效应(Anomalous Hall Effect,AHE)，在y轴方向上产生霍尔电压，导致左侧电压V 13和右侧电压V 23之间产生不对称性，其中左侧电压V 13与右侧电压V 23分别表示第一端与第三端之间的电压以及第二端与第三端之间的电压。
通常，反常霍尔效应产生的电压不对称性非常微小，难以进行检测。可以通过负微分电阻来放大电压之间的不对称性。负微分电阻具有将大电压进一步增大，并将小电压进一步减小的效果，因此，可以放大电压之间的不对称性。如图1A所示，第一负微分电阻(Negative Differential Resistance,NDR)4耦接在自旋逻辑器件10的第一端11与第三端13之间。第二负微分电阻6耦接在自旋逻辑器件10的第二端12与第三端13之间。例如，第一NDR 4和第二NDR 6可以相同，或者可以具有相同的电阻特性。第一NDR 4和第二NDR 6可以由互补结型场效应晶体管或共振隧穿晶体管等具有负微分电阻效应的元件来实现。当在第一端11施加输入电压Vin时，电流在磁性单元5中沿着x轴方向流动。由于反常霍尔效应，在y方向会产生霍尔电压，导致第一NDR 4两端的电压V 13和第二NDR 6两端的电压V 23出现不对称，即，V 13和V 23中一个为高电压，一个为低电压。如果改变磁性单元5的磁化方向，则霍尔电压反向，从而V 13和V 23中一个为低电压，一个为高电压。在逻辑操作时，以磁性单元5的磁化方向作为逻辑输入。例如，可以将磁化方向垂直于衬底表面向下定义为逻辑输入“1”，并且将磁化方向垂直于衬底表面向上定义为逻辑输入“0”。备选地，也可以将磁化方向垂直于衬底表面向下定义为逻辑输入“0”，并且将磁化方向垂直于衬底表面向上定义为逻辑输入“1”。V 13和V 23的电压大小可以对应于逻辑输出，例如，高电压为逻辑输出“1”，低电压为逻辑输出“0”。反常霍尔效应导致的输出电压的不对称性不高，因此，第一NDR 4和第二NDR 6可以用于放大这种输出电压的不对称性，从而达到识别逻辑输出的目的。
在图1A和图1B所示的实施例中，磁性单元5相对于对称轴对称，该对称轴位于x-y平面内，并且与y轴平行。第一端口1与第二端口2相对于对称轴对称，并且第三端口3位于对称轴上。根据该对称结构，当在磁性单元5中没有产生霍尔电压时，电压V 13和V 23不存在任何不对称性。因而，当在磁性单元5中产生霍尔电压时，这种对称结构更加有助于在电压V 13和V 23中产生明显的不对称，从而更容易识别逻辑输出。应当理解，尽管图1A和图1B示出了磁性单元5具有T字型结构，磁性单元5也可以具有其他形状，特别是其他对称的形状。
在一个实施例中，制备了如图1A和图1B所示的自旋逻辑器件10，其中，磁性单元5的磁性材料结构为：Ta/CoFeB/MgO，通过磁控溅射生长在热氧化的硅衬底上。第一NDR 4和第二NDR 6由互补结型场效应晶体管实现。图1C示出了该实施例的输出电压与输入电压之间的关系图。如图1C所示，无论磁化方向M向上还是向下，逻辑输出“1”与逻辑输出“0”之间的电压差在较大的输入电压范围内都比较明显。在该实施例中，当输入电压约3.7V时，V 13和V 23的不对称性最大，输出电压V 13和V 23比值可以达到500％。由于输出电压的不对称性，可以显著识别逻辑输出。
图2示出了根据本公开的一些实施例的自旋逻辑器件100的示意图。如图2所示，自旋逻辑器件100包括第一磁性单元101、第二磁性单元102和第三磁性单元103，每一个磁性单元可以由如图1所示的磁性单元5来实现。第一磁性单元101、第二磁性单元102和第三磁性单元103的逻辑状态可以分别由位a、b和c来表示。
如图2所示，第一磁性单元101、第二磁性单元102和第三磁性单元103并联耦接。换言之，第一磁性单元101、第二磁性单元102和第三磁性单元103的第一端口1与自旋逻辑器件100的第一端111耦接，第一磁性单元101、第二磁性单元102和第三磁性单元103的第二端口2与自旋逻辑器件100的第二端112耦接，并且第一磁性单元101、第二磁性单元102和第三磁性单元103的第三端口3与自旋逻辑器件100的第三端113耦接。另外，第一 NDR 104耦接在自旋逻辑器件100的第一端111与第三端113之间，并且第二NDR 106耦接在自旋逻辑器件100的第一端112与第三端113之间。自旋逻辑器件100的第一端111与输入电压Vin耦接，并且自旋逻辑器件100的第二端112接地。
通过控制位c，自旋逻辑器件100可以实现“与”、“或”、“与非”和“或非”四种逻辑运算。对每一个磁性单元101-103，电流从第一端1流入，从第二端2流出至接地。第一磁性单元101和第二磁性单元102的磁化方向可以是逻辑输入。例如，可以定义磁化方向垂直膜面向下为逻辑输入“1”，向上为逻辑输入“0”。第三磁性单元103的磁化方向可以作为用于偏置条件来实现不同的逻辑运算。电压V 13和V 23可以是逻辑输出，其中输出高电压为逻辑“1”，输出低电压为逻辑“0”。
通过控制不同的逻辑输入、偏置条件和逻辑输出通道，可以实现“与”(AND)、“或”(OR)、“与非”(NAND)和“或非”(NOR)。将第三磁性单元103的逻辑状态为“0”时，电压V 13对应“与”(AND)逻辑，电压V 23对应于“与非”(NAND)逻辑；将第三磁性单元103的逻辑状态为“1”时，电压V 13对应“或”(OR)逻辑，电压V 23对应于“或非”(NOR)逻辑。
在一个实施例中，提供0.4V输入电压Vin，表1示出了该实施例的逻辑表。当第三磁性单元103的状态(c)为“0”时，第一磁性单元101和第二磁性单元102的逻辑输入(a,b)分别为(1,1)，(1,0)，(0,1)，(0,0)时，电压V 13分别为0.3892V(高电位“1”)，0.0104V(低电位“0”)，0.0105V(低电位“0”)，0.0104V(低电位“0”)，对应AND逻辑运算。另外，电压V 23分别为0.0107V(低电位“0”)，0.3895V(高电位“1”)，0.3894V(高电位“1”)，0.3895V(高电位“1”)，对应NAND逻辑运算。当第三磁性单元(位c)的逻辑状态为“1”时，第一磁性单元101和第二磁性单元102的逻辑输入(a,b)分别为(1,1)，(1,0)，(0,1)，(0,0)时，电压V 13分别为0.3898V(高电位“1”)，0.3895V(高电位“1”)，0.3894V(高电位“1”)，0.0081V(低电位“0”)，对应OR逻辑运算。同时，输电压V 23的输出电压分别为0.0101V(低电位“0”)，0.0104V(低电位“0”)，0.0105V(低电位“0”)，0.3910V(高电位“1”)，对应NOR逻辑运算。应当理解，以上数字仅作为示例提供，不同的器件可以实现不同的数据结果。
表1
Figure PCTCN2021094983-appb-000001
图3A示出了根据本公开的一些实施例的存算一体器件200的示意图。如图3A所示，存算一体器件200可以同时实现逻辑操作和输出结果的存储。通过将如图2所示的自旋逻辑器 件100与存储部分相结合，可以形成存算一体器件200。第一磁性单元201、第二磁性单元202和第三磁性单元203均可以由如图1所示的磁性单元10来实现。第一磁性单元201、第二磁性单元202和第三磁性单元203分别由位a、b和c来表示。
如图3A所示，第一磁性单元201、第二磁性单元202和第三磁性单元203并联耦接。第一NDR 204耦接在存算一体器件200的第一端211与第三端213之间，并且第二NDR 206耦接在存算一体器件200的第二端212与第三端213之间。存算一体器件200的第一端211与输入电压Vin耦接，并且存算一体器件200的第二端212接地。存算一体器件200的第三端213与晶体管207的控制端(即，栅极)耦接，晶体管207的第一端(例如，源端或漏端)与磁性单元205(状态d)的第一端1耦接，晶体管207的第二端(例如，漏端或源端)接地。另外，磁性单元205的第二端2与电源V DD耦接，从而形成从电源V DD至接地的回路。
例如，可以将磁性单元205的初始状态设置为逻辑“0”。当存算一体器件200的逻辑部分输出“0”时，逻辑部分的输出电压小于晶体管207的开启电压，晶体管207不导通，在从电源V DD至接地的回路中无电流，磁性单元205的磁化方向不变，为“0”。当存算一体器件200的逻辑部分输出“1”时，逻辑部分的输出电压大于晶体管207的开启电压，晶体管207导通，在从电源V DD至接地的回路中有写电流I O流过磁性单元205。在写电流I O引起的自旋轨道力矩和磁场H的共同作用下，磁性单元205的磁化方向发生翻转，变为“1”，从而完成将逻辑输出结果存储在磁性单元205中。如图3A所示，磁场H的方向反平行于写电流I O的方向。通过改变磁场H或者写电流I O的方向，可以改变对磁性单元205的逻辑操作。例如，电源V DD可以与磁性单元205的第一端口1耦接，磁性单元205的第二端口2与晶体管207连接，从而改变写电流I O的方向。
另外，在向磁性单元205写入相同的信息时，通过调整磁性单元205中的重金属的类型，可以改变磁场H的方向和写电流I O的方向之间的相对关系。例如，当磁性单元205中的重金属为Pt和Ta时，在写入相同的信息时，写电流和磁场的方向之间的相对关系相反。
尽管在图3A中晶体管207表示为场效应晶体管，也可以使用任何其他合适的开关来实现晶体管207。
图3B示出了图3A的存算一体器件200中的磁性单元205中产生的电流I O随输入电压Vin的变化关系。如图3B所示，当输入电压Vin＝0.4V时，参考表1，当输出逻辑“1”时，电压V 23>0.38V，足以开启晶体管207，从而在磁性单元205中产生写电流I O＝0.9mA。图3C示出了当外加磁场为10mT时，磁性单元205的霍尔电阻随写电流I O的变化关系。如图3C所示，磁性单元205的临界翻转电流为～0.7mA。因此，当电压V 23输出“1”时，产生的写电流I O可以将磁性单元205的磁化方向翻转，将逻辑输出的结果写入到磁性单元205中。
图4示出了根据本公开的一些实施例的半加器300的示意图。如图4所示，半加器300包括如图2所示的自旋逻辑器件100的两个实例，自旋逻辑器件100的第一实例包括第一磁性单元301、第二磁性单元302和第三磁性单元303以及第一NDR 304和第二NDR 306，自旋逻辑器件100的第二实例包括第一磁性单元351、第二磁性单元352和第三磁性单元353以及第一NDR 354和第二NDR 356。第一磁性单元301的逻辑输入为位a，第一磁性单元351的逻辑输入为位a，其与位a互补。第二磁性单元302的逻辑输入为位b，第二磁性单元352的逻辑输入为位b，其与位b互补。第三磁性单元303的逻辑状态为位c 1，第三磁性单元353的逻辑状态为位c 2。如图2所示，自旋逻辑器件100的一个实例可以作为一个逻辑门。为了方便讨论，将自旋逻辑器件100的第一实例称为第一逻辑门，将自旋逻辑器件100的第二实 例称为第二逻辑门。通过第三逻辑单元303和353的控制位，可以实现位a和b的“异或”(XOR)，从而实现半加器。
如结合图2所述，通过改变第三逻辑单元的控制位c可产生“与非”和“或非”两种逻辑门。“异或”可以通过“或非”逻辑门的组合实现：
Figure PCTCN2021094983-appb-000002
第一逻辑门和第二逻辑门均可以用于实现“或非”门，其中一个“或非”门的逻辑输入为位a与位b，控制位c 1的磁化方向向下(逻辑“1”)，从而实现a NOR b；另一个“或非”门的逻辑输入为位
Figure PCTCN2021094983-appb-000003
与位
Figure PCTCN2021094983-appb-000004
二者的磁化方向与位a和位b相反，控制位c 2的磁化方向向下(逻辑“1”)，从而实现
Figure PCTCN2021094983-appb-000005
第一逻辑门(aNORb)的第三端313耦接至晶体管307的控制端(例如，栅极)，第二逻辑门
Figure PCTCN2021094983-appb-000006
的第三端363耦接至晶体管309的控制端(例如，栅极)。晶体管307和309并联耦接在磁性单元305(位d)与接地之间。晶体管307和309的第一端(例如，源端或漏端)与磁性单元305的第二端口2串联连接，晶体管307和309的第二端(例如，漏端或源端)接地并且磁性单元305的第一端口1与电源V DD耦接，从而在电源与地之间形成回路。
当第一逻辑门和第二逻辑门均输出“0”时，晶体管307和309均不导通，回路中无电流。当其中有一个逻辑门输出“1”时，晶体管307和309中至少一个晶体管导通，回路中有写电流流过磁性单元305。在写电流引起的自旋轨道力矩和磁场H的共同作用下，磁性单元305的磁化方向发生翻转。磁性单元305的预置磁化方向为垂直膜面向下(逻辑“1”)，当晶体管307和309中至少一个晶体管导通时，写电流I O通过磁性单元305。如图4所示，磁场方向H与写电流I O的方向相同。在由写电流引起的自旋轨道力矩和磁场H的作用下，磁性单元305的磁化方向发生翻转，变为垂直膜面向上，即“0”状态。当晶体管307和309均不导通时，无写电流I O通过磁性单元305，磁性单元305的磁化方向不变，仍为“1”。因此，晶体管307和309与磁性单元305实现了两个逻辑门的输出结果的“或非”NOR，从而实现(a NOR b)NOR
Figure PCTCN2021094983-appb-000007
即磁性单元305存储了位a与位b的“异或”XOR运算结果。表2示出了根据本公开的一些实施例的逻辑表。
表2
Figure PCTCN2021094983-appb-000008
根据本公开的一些实施例，可以将如图2所示的自旋逻辑器件100进行组合，以形成全加器。全加器可以实现两位二进制数字(分别称为第一加数和第二加数)的加法运算，并输出和位与进位。在如图2所示的自旋逻辑器件100中，如果将第三磁性单元103作为逻辑输入位，而非控制位，则可以实现进位的功能。如表3所示，逻辑输入Ai和Bi表示第一加数 和第二加数，逻辑输入Ci-1表示相邻低位的进位数，逻辑输出C i表示向相邻高位的进位数。
表3
Figure PCTCN2021094983-appb-000009
图5示出了根据本公开的一些实施例的全加器的进位计算部分400的示意图。与自旋逻辑器件100相同，进位计算部分400包括第一磁性单元401、第二磁性单元402和第三磁性单元403，其中第一磁性单元401、第二磁性单元402和第三磁性单元403分别接收逻辑输入Ai、Bi和Ci-1。第一NDR 404耦接在第一端411与第三端413之间，第二NDR 406耦接在第二端412与第三端413之间。
如图5所示，第三端413与晶体管407的控制端(例如，栅极)耦接，晶体管407的第一端(例如，源端或漏端)与磁性单元405的第二端口2耦接，晶体管407的第二端(例如，漏端或源端)接地，并且磁性单元405的第一端口1与电源V DD耦接。
如表3所示，可以将磁性单元405的初始状态设置为逻辑“0”。当进位计算部分400输出“0”时，输出电压小于晶体管407的开启电压，晶体管407不导通，在从电源V DD至接地的回路中无电流，磁性单元405的逻辑状态不变，为“0”。当进位计算部分400输出“1”时，输出电压大于晶体管407的开启电压，晶体管407导通，在从电源V DD至接地的回路中有写电流流过磁性单元405。在写电流引起的自旋轨道力矩和磁场H的共同作用下，磁性单元405的磁化方向发生翻转，对应逻辑“1”，从而完成信息存储。如图5所示，磁场H的方向平行于写电流的方向。
图6示出了根据本公开的一些实施例的全加器的和位计算部分500的示意图。全加器的和位可以通过组合如图4所示中的半加器300(“异或”XOR)实现：
Si＝SUM(Ai,Bi,Ci-1)＝(Ai XOR Bi)XOR Ci-1。
如图6所示，和位计算部分500包括第一磁性单元501(逻辑输入Ai)、第二磁性单元502(逻辑输入Bi)、第三磁性单元503(控制位c 1)、第一NDR 504、第二NDR 506、第一磁性单元551(逻辑输入
Figure PCTCN2021094983-appb-000010
逻辑输入Ai的补数)、第二磁性单元552(逻辑输入
Figure PCTCN2021094983-appb-000011
逻辑输入Bi的补数)、第三磁性单元553(控制位c 2)、第一NDR 554和第二NDR 556。另外，和位计算部分500还包括第一磁性单元521(逻辑输入为Ii)、第二磁性单元522(逻辑输入Ci-1)、第三磁性单元523(控制位c 3)、第一NDR 524、第二NDR 526、第一磁性单元571(逻辑输入
Figure PCTCN2021094983-appb-000012
逻辑输入Ii的补数)、第二磁性单元572(逻辑输入
Figure PCTCN2021094983-appb-000013
逻辑输入Ci-1的补数)、第三磁性单元573(控制位c 4)、第一NDR 574和第二NDR 576。
在该实施例中，如表3所示，位I i和位S i的初始状态可以是逻辑“1”，即，磁化方向为垂 直于衬底表面向下。如表3所示的逻辑运算与结合图4所述的逻辑运算相似，不再赘述。
另外，和位计算部分500还包括晶体管505、525、555和575，其可以与结合图4所述进行操作。和位计算部分500还可以包括开关电路，用于将和位计算部分500在第一模式和第二模式之间进行切换。在图6所示的示例中，开关电路包括晶体管531-542。例如，第一磁性单元521的第二端口2经由晶体管537有选择地耦接到第一磁性单元571的第二端口2。图7示出了和位计算部分500的第一模式的等效电路600，图8示出了和位计算部分500的第二模式的等效电路700。等效电路600实现位A i与位B i的“异或”运算，并将运算结果存储在中间位I i与
Figure PCTCN2021094983-appb-000014
即，I i＝A i XOR B i。等效电路700实现位I i与位C i-1的“异或”运算，并将运算结果存储在和位S i，即，S i＝I i XOR C i-1＝(A i XOR B i)XOR C i-1。通过将和位计算部分500交替地工作在第一模式和第二模式中，可以实现和位的计算。
在一些实施例中，和位计算部分500还包括控制器510，以实现第一模式和第二模式之间的自动切换。控制器510可以在时钟CLK控制下进行操作，并且可以包括第一输出Q 1和第二输出Q 2。第一输出Q 1与晶体管531、533、537和538的控制端(例如，栅极)耦接，用于导通和关断晶体管531、533、537和538。第二输出Q 2与晶体管532、534、535、536、539、541和542的控制端(例如，栅极)耦接，用于导通和关断晶体管532、534、535、536、539、541和542。
在第一时间段(例如，一个时钟周期的第一部分)，第一输出Q 1可以将晶体管531、533、537和538导通，并且第二输出Q 2将晶体管532、534、535、536、539、541和542关断。图7示出了在该状态下的和位计算部分500的示意图。如图7所示，电路600实现位A i与位B i的“异或”运算，并将运算结果存储在中间位I i与
Figure PCTCN2021094983-appb-000015
即，I i＝A i XOR B i。
在第二时间段(例如，一个时钟周期的另一部分)，第一输出Q 1可以将晶体管531、533、537和538关断，并且第二输出Q 2将晶体管532、534、535、536、539、541和542导通。图8示出了在该状态下的和位计算部分500的示意图。如图8所示，电路图700实现位I i与位C i-1的“异或”运算，并将运算结果存储在和位S i，即，S i＝I i XOR C i-1＝(A i XOR B i)XOR C i-1。
尽管已经详细地描述了本公开的实施例及其优势，但应该理解，在不脱离所附权利要求所限定的本公开的范围的情况下，可对本公开做出各种改变、替代和变化。而且，本申请的范围不旨在限于本说明书中所述的工艺、机器装置、制造、物质组成、工具、方法和步骤的具体实施例。本领域的技术人员通过本公开容易理解，根据本公开，可以利用已有的或今后将开发的、与本公开所述相应实施例执行基本相同的功能或者实现基本相同的结果的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、物质组成、工具、方法或步骤包括在它们的保护范围内。另外，每个权利要求组成单独的实施例，并且各个权利要求和实施例的组合都在本公开的范围内。

Claims (21)

  1. 一种自旋逻辑器件，包括：
    第一磁性单元，所述第一磁性单元包括沿着堆叠方向布置的自旋霍尔效应层和铁磁层，所述铁磁层的磁化方向沿着所述堆叠方向，所述第一磁性单元包括在所述第一磁性单元的第一侧的第一端口、在与所述第一侧相对的第二侧的第二端口以及位于所述第一磁性单元的第一端口与所述第一磁性单元的第二端口之间并且在所述第一磁性单元的第三侧的第三端口，所述第一磁性单元的第一端口与所述自旋逻辑器件的第一端耦接，所述第一磁性单元的第二端口与所述自旋逻辑器件的第二端耦接，并且所述第一磁性单元的第三端口与所述自旋逻辑器件的第三端耦接；
    第一负微分电阻，耦接在所述自旋逻辑器件的第一端与第三端之间；以及
    第二负微分电阻，耦接在所述自旋逻辑器件的第二端与第三端之间。
  2. 根据权利要求1所述的自旋逻辑器件，其特征在于，所述第一磁性单元相对于垂直于所述堆叠方向的对称轴对称，所述第一磁性单元的第二端口与所述第一磁性单元的第一端口相对于所述对称轴对称，并且所述第一磁性单元的第三端口位于所述对称轴上。
  3. 根据权利要求1所述的自旋逻辑器件，其特征在于，
    所述自旋逻辑器件的第一端用于耦接到第一电压，并且所述自旋逻辑器件的第二端用于耦接到第二电压，以产生在所述自旋逻辑器件的第一端与所述自旋逻辑器件的第二端之间的电流；以及
    所述自旋逻辑器件用于在所述自旋逻辑器件的第一端与所述自旋逻辑器件的第三端之间输出表示第一逻辑输出的第三电压，和/或所述自旋逻辑器件用于在所述自旋逻辑器件的第二端与所述自旋逻辑器件的第三端之间输出表示第二逻辑输出的第四电压。
  4. 根据权利要求1所述的自旋逻辑器件，其特征在于，所述磁化方向表示所述第一磁性单元的逻辑输入。
  5. 根据权利要求1所述的自旋逻辑器件，其特征在于，所述第一负微分电阻和所述第二负微分电阻中的至少一个包括：互补结型场效应晶体管或共振隧穿二极管。
  6. 根据权利要求1所述的自旋逻辑器件，其特征在于，所述自旋霍尔效应层包括以下至少一项：重金属层或拓扑绝缘体层。
  7. 根据权利要求1所述的自旋逻辑器件，其特征在于，响应于施加到所述第一磁性单元的磁场以及在所述第一磁性单元的第一端口与所述第一磁性单元的第二端口之间的写电流，所述磁化方向发生翻转，其中所述磁场的方向与所述写电流的方向平行或反平行。
  8. 根据权利要求1-7中任一项所述的自旋逻辑器件，其特征在于，还包括：
    第二磁性单元，所述第二磁性单元包括沿着所述第二磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，所述第二磁性单元的铁磁层的磁化方向沿着所述第二磁性单元的堆叠方向，其中，所述第二磁性单元包括在所述第二磁性单元的第一侧的第一端口、在与所述第二磁性单元的第一侧相对的第二侧的第二端口以及位于所述第二磁性单元的第一端口与所述第二磁性单元的第二端口之间并且在所述第二磁性单元的第三侧的第三端口，其中所述第二磁性单元的第一端口与所述自旋逻辑器件的第一端耦接，所述第二磁性单元的第二端口与所述自旋逻辑器件的第二端耦接，并且所述第二磁性单元的第三端口与所述自旋逻辑器件的第三端耦接；以及
    第三磁性单元，所述第三磁性单元包括沿着所述第三磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，所述第三磁性单元的铁磁层的磁化方向沿着所述第三磁性单元的堆叠方向，其中，所述第三磁性单元包括在所述第三磁性单元的第一侧的第一端口、在与所述第三磁性单元的第一侧相对的第二侧的第二端口以及位于所述第三磁性单元的第一端口与所述第三磁性单元的第二端口之间并且在所述第三磁性单元的第三侧的第三端口，所述第三磁性单元的第一端口与所述自旋逻辑器件的第一端耦接，所述第三磁性单元的第二端口与所述自旋逻辑器件的第二端耦接，并且所述第三磁性单元的第三端口与所述自旋逻辑器件的第三端耦接。
  9. 根据权利要求8所述的自旋逻辑器件，其特征在于，
    所述第一磁性单元的磁化方向表示所述第一磁性单元的逻辑输入；
    所述第二磁性单元的磁化方向表示所述第二磁性单元的逻辑输入；以及
    所述自旋逻辑器件用于在所述自旋逻辑器件的第一端与所述自旋逻辑器件的第三端之间输出表示所述自旋逻辑器件的第一逻辑输出的第三电压，其中如果所述第三磁性单元的磁化方向为第一磁化方向，则所述第一逻辑输出作为表示所述第一磁性单元和所述第二磁性单元的逻辑输入的第一逻辑操作，并且如果所述第三磁性单元的磁化方向为第二磁化方向，则所述第一逻辑输出作为表示所述第一磁性单元和所述第二磁性单元的逻辑输入的第二逻辑操作，和/或所述自旋逻辑器件用于在所述自旋逻辑器件的第二端与所述自旋逻辑器件的第三端之间输出表示所述自旋逻辑器件的第二逻辑输出的第四电压，其中如果所述第三磁性单元的磁化方向为第一磁化方向，则所述第二逻辑输出作为表示所述第一磁性单元和所述第二磁性单元的逻辑输入的第三逻辑操作，并且如果所述第三磁性单元的磁化方向为第二磁化方向，则所述第二逻辑输出作为表示所述第一磁性单元和所述第二磁性单元的逻辑输入的第四逻辑操作。
  10. 根据权利要求9所述的自旋逻辑器件，其特征在于，所述第一逻辑操作和所述第二逻辑操作包括“与非”和“或非”，所述第三逻辑操作和所述第四逻辑操作包括“与”和“或”。
  11. 一种存算一体器件，包括：
    根据权利要求8-10中任一项所述的自旋逻辑器件；
    晶体管，所述晶体管的控制端耦接到所述自旋逻辑器件的第三端；
    第四磁性单元，所述第四磁性单元包括沿着所述第四磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，所述第四磁性单元的铁磁层的磁化方向沿着所述第四磁性单元的堆叠方向，所述第四磁性单元包括在所述第四磁性单元的第一侧的第一端口以及在与所述第四磁性单元的第一侧相对的第二侧的第二端口，所述第四磁性单元的第一端口耦接到所述晶体管的第一端，并且所述第四磁性单元的第二端口耦接到电源。
  12. 根据权利要求11所述的存算一体器件，其特征在于，
    所述第四磁性单元相对于与所述第四磁性单元的堆叠方向垂直的对称轴对称，所述第四磁性单元的第二端口相对于所述第四磁性单元的对称轴与所述第四磁性单元的第一端口对称。
  13. 根据权利要求12所述的存算一体器件，其特征在于，
    所述第四磁性单元的写电流具有从所述第四磁性单元的第二端口向所述第四磁性单元的第一端口的方向，并且施加到所述第四磁性单元的磁场的方向平行或反平行于所述写电流的方向。
  14. 一种半加器，包括：
    第一或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件；
    第二或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件，所述第一或非门的第一端与所述第二或非门的第一端耦接，所述第一或非门的第二端与所述第二或非门的第二端耦接，所述第一或非门的第一磁性单元和所述第二或非门的第一磁性单元的逻辑输入互补，并且所述第一或非门的第二磁性单元和所述第二或非门的第二磁性单元的逻辑输入互补；
    第一开关，所述第一开关的控制端耦接到所述第一或非门的第三端；
    第二开关，所述第二开关的控制端耦接到所述第二或非门的第三端；以及
    第五磁性单元，所述第五磁性单元包括沿着所述第五磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，所述第五磁性单元的铁磁层的磁化方向沿着所述第五磁性单元的堆叠方向，所述第五磁性单元包括在所述第五磁性单元的第一侧的第一端口以及在与所述第五磁性单元的第一侧相对的第二侧的第二端口，所述第五磁性单元的第一端口与电源耦接，所述第五磁性单元的第二端口与所述第一开关和所述第二开关耦接。
  15. 根据权利要求14所述的半加器，其特征在于，
    所述第五磁性单元的写电流具有从所述第五磁性单元的第一端口到所述第五磁性单元的第二端口的方向，并且施加到所述第五磁性单元的磁场的方向平行或反平行于所述写电流的方向。
  16. 一种全加器，包括：
    第一或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件，其中所述第一或非门的第一磁性单元的逻辑输入为第一加数，并且所述第一或非门的第二磁性单元的逻辑输入为第二加数；
    第二或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件，所述第一或非门的第一端与所述第二或非门的第一端耦接，所述第一或非门的第二端与所述第二或非门的第二端耦接，其中所述第二或非门的第一磁性单元的逻辑输入为第一加数的补数，并且所述第二或非门的第二磁性单元的逻辑输入为第二加数的补数；
    第一开关，所述第一开关的控制端耦接到所述第一或非门的第三端；
    第二开关，所述第二开关的控制端耦接到所述第二或非门的第三端，所述第二开关的第一端与所述第一开关的第一端耦接以提供第一逻辑输出；
    第三或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件，其中所述第三或非门的第二磁性单元的逻辑输入为相邻低位的进位数；
    第四或非门，包括根据权利要求8-10中任一项所述的自旋逻辑器件，所述第三或非门的第一端与所述第四或非门的第一端耦接，所述第三或非门的第二端与所述第四或非门的第二端耦接，所述第三或非门的第一磁性单元的第二端口与所述第四或非门的第一磁性单元的第二端口耦接，并且所述第四或非门的第一磁性单元的第一端口与所述第一逻辑输出耦接，其中所述第四或非门的第二磁性单元的逻辑输入为相邻低位的进位数的补数；
    第三开关，所述第三开关的控制端耦接到所述第三或非门的第三端；
    第四开关，所述第四开关的控制端耦接到所述第四或非门的第三端；
    第六磁性单元，所述第六磁性单元包括沿着所述第六磁性单元的堆叠方向布置的自旋霍尔效应层和铁磁层，所述第六磁性单元的铁磁层的磁化方向沿着所述第六磁性单元的堆叠方向，所述第六磁性单元包括在所述第六磁性单元的第一侧的第一端口以及在与所述第六磁性单元的第一侧相对的第二侧的第二端口，所述第六磁性单元的第一端口与电源耦接，并且所 述第六磁性单元的第二端口与所述第三开关和所述第四开关耦接，所述第六磁性单元用于存储和位；
    开关电路，用于在第一时间段激活所述第一或非门和所述第二或非门，以将第一逻辑输出存储在所述第三或非门的第一磁性单元并且将与所述第一逻辑输出互补的第二逻辑输出存储在所述第四或非门的第一存储单元，并且在第二时间段，激活所述第三或非门和所述第四或非门，以将逻辑输出存储在所述第六磁性单元；以及
    根据权利要求11-13中任一项所述的存算一体器件，其中所述存算一体器件的第一磁性单元的逻辑输入为第一加数的值，所述存算一体器件的第二磁性单元的逻辑输入为第二加数的值，所述存算一体器件的第三磁性单元的逻辑输入为相邻低位的进位数，所述存算一体器件的第四磁性单元存储向相邻高位的进位数。
  17. 根据权利要求16所述的全加器，其特征在于，
    所述第六磁性单元的写电流具有从所述第六磁性单元的第一端口到所述第六磁性单元的第二端口的方向，并且施加到所述第六磁性单元的磁场的方向平行或反平行于所述写电流的方向；以及
    所述第四磁性单元的写电流具有从所述第四磁性单元的第二端口向所述第四磁性单元的第一端口的方向，并且施加到所述第四磁性单元的磁场的方向平行或反平行于所述写电流的方向。
  18. 一种设备，包括：
    印刷电路板；以及
    根据权利要求1-10中任一项所述的自旋逻辑器件，所述自旋逻辑器件设置在所述印刷电路板上。
  19. 一种设备，包括：
    印刷电路板；以及
    根据权利要求11-13中任一项所述的存算一体器件，所述存算一体器件设置在所述印刷电路板上。
  20. 一种设备，包括：
    印刷电路板；以及
    根据权利要求14-15中任一项所述的半加器，所述半加器设置在所述印刷电路板上。
  21. 一种设备，包括：
    印刷电路板；以及
    根据权利要求16-17中任一项所述的全加器，所述全加器设置在所述印刷电路板上。
PCT/CN2021/094983 2021-05-20 2021-05-20 自旋逻辑器件、存算一体器件、半加器和全加器 WO2022241735A1 (zh)

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