WO2023044813A1 - 计算电路和电子设备 - Google Patents

计算电路和电子设备 Download PDF

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Publication number
WO2023044813A1
WO2023044813A1 PCT/CN2021/120476 CN2021120476W WO2023044813A1 WO 2023044813 A1 WO2023044813 A1 WO 2023044813A1 CN 2021120476 W CN2021120476 W CN 2021120476W WO 2023044813 A1 WO2023044813 A1 WO 2023044813A1
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magnetic unit
voltage
terminal
magnetic
coupled
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PCT/CN2021/120476
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English (en)
French (fr)
Inventor
章晓中
卢子尧
蒲宇辰
牟鸿铭
李文静
叶力
Original Assignee
华为技术有限公司
清华大学
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Application filed by 华为技术有限公司, 清华大学 filed Critical 华为技术有限公司
Priority to CN202180101765.2A priority Critical patent/CN117940999A/zh
Priority to PCT/CN2021/120476 priority patent/WO2023044813A1/zh
Publication of WO2023044813A1 publication Critical patent/WO2023044813A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Definitions

  • Embodiments of the present disclosure relate generally to magnetic logic devices, and more particularly to computing circuits and electronic devices incorporating magnetic logic devices.
  • Spin logic devices also known as magnetic logic devices, are digital logic devices designed using the spin characteristics of electrons in magnetic materials. Compared with conventional semiconductor logic devices, this kind of device has the advantages of fast speed, low power consumption, non-volatility of logic information, radiation protection, etc., so it is considered to be very promising to replace traditional semiconductor logic devices.
  • the logic input and the logic gate are integrated, so that one magnetic bit can only be used as the logic input of one logic gate at the same time, which is not conducive to parallel computing.
  • each operation requires connecting the called magnetic bits to each other. Therefore, in an array containing a large number of storage bits, a relatively more complex addressing system is required to implement arithmetic functions.
  • Embodiments of the present disclosure provide a computing circuit and an electronic device.
  • a computing circuit in a first aspect, includes a memory array including a first magnetic cell configured to store a first bit and output a first voltage representative of the first bit, configured to store a second bit and output a second voltage representative of the second bit and a third magnetic unit configured to store a third bit and output a third voltage indicative of the third bit.
  • the computing circuit also includes a write circuit including a plurality of inputs configured to receive the first voltage, the second voltage, and the third voltage and an output configured to output the first write voltage.
  • the calculation circuit also includes an operation array including a fourth magnetic unit, a fifth magnetic unit and a sixth magnetic unit.
  • the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit are configured to generate a first write current in the fourth magnetic unit and a second write current in the fifth magnetic unit in response to the first write voltage , and a third write current is generated in the sixth magnetic unit.
  • the first write current and the third write current have the same direction, and the second write current has an opposite direction to the first write current and the third write current.
  • the critical switching voltages of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit increase sequentially.
  • the write circuit includes: a pull-down circuit configured to selectively pull down the first write voltage in response to the first voltage, the second voltage, and the third voltage.
  • a pull-down circuit configured to selectively pull down the first write voltage in response to the first voltage, the second voltage, and the third voltage.
  • the pull-down circuit includes a first switch including a control terminal, a first terminal, and a second terminal.
  • the control terminal of the first switch is configured to receive the first voltage, the first terminal of the first switch is coupled to the first reference voltage, and the second terminal of the first switch is coupled to the output.
  • the pull-down circuit also includes a second switch including a control terminal, a first terminal and a second terminal.
  • the control terminal of the second switch is configured to receive the second voltage, the first terminal of the second switch is coupled to the first reference voltage, and the second terminal of the second switch is coupled to the output.
  • the pull-down circuit also includes a third switch including a control terminal, a first terminal and a second terminal. The control terminal of the third switch is configured to receive a third voltage, the first terminal of the third switch is coupled to the first reference voltage, and the second terminal of the third switch is coupled to the output.
  • the pull-down circuit further includes a first resistor coupled between the second terminal of the first switch and the output terminal.
  • the pull-down circuit further includes a second resistor coupled between the second terminal of the second switch and the output terminal.
  • the pull-down circuit further includes a third resistor coupled between the second terminal of the third switch and the output terminal.
  • the first port of the fourth magnetic unit is coupled to the second reference voltage, and the second port of the fourth magnetic unit is coupled to the output terminal.
  • the first port of the fifth magnetic unit is coupled to the output terminal, and the second port of the fifth magnetic unit is coupled to the second reference voltage.
  • the first port of the sixth magnetic unit is coupled to the second reference voltage, and the second port of the sixth magnetic unit is coupled to the output terminal.
  • the first write current and the third write current have the same direction
  • the second write current has the same direction as the first write current.
  • the current and the third write current have opposite directions.
  • the calculation circuit further includes: a switch circuit configured to couple the first ports of the fourth magnetic unit, the fifth magnetic unit, and the sixth magnetic unit to each other, and connect the fourth magnetic unit, the fifth magnetic unit Second ports of the cell and the sixth magnetic cell are coupled to each other for applying a read voltage between the first port and the second port.
  • the switch circuit is further configured to couple the third ports of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit to each other to output a fourth voltage.
  • the computing circuit also includes a readout circuit including an input configured to receive the fourth voltage and an output configured to output the second write voltage.
  • the memory array also includes a seventh magnetic unit configured to generate a fourth write current in the seventh magnetic unit in response to the second write voltage.
  • the magnetic unit in the arithmetic array needs to be reconnected. Since the storage array and computing array are separated, this reconnection does not affect the connections within the storage array, thereby simplifying circuit design and control.
  • the reading circuit includes: a fourth switch including a control terminal, a first terminal and a second terminal.
  • the control terminal of the fourth switch is configured to receive a fourth voltage
  • the first terminal of the fourth switch is coupled to the first reference voltage
  • the second terminal of the fourth switch is coupled to the output of the readout circuit.
  • the switching circuit is configured such that the first port of each of the fourth magnetic unit, the fifth magnetic unit, and the sixth magnetic unit is connected to the fourth magnetic unit, the fifth magnetic unit, and the sixth magnetic unit.
  • the first negative differential resistance is coupled between the third ports of the corresponding magnetic units in the magnetic units, and the second port of each magnetic unit in the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit is connected to the first magnetic unit.
  • a second negative differential resistor is coupled between the third ports of the corresponding magnetic units of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit.
  • the asymmetry of the output voltage can be amplified, so as to achieve the purpose of identifying the logic output.
  • the first to third magnetic units each include a first port, a second port, and a third port configured as The first voltage, the second voltage and the third voltage are output.
  • the calculation circuit also includes: a third negative differential resistor coupled between the first port and the third port of the first magnetic unit to the third magnetic unit; and a fourth negative differential resistor coupled between the first magnetic unit to the third magnetic unit Between the second port and the third port of the three magnetic units.
  • Each magnetic unit in the memory array can be connected with its own negative differential resistance to amplify the asymmetry of its respective output voltage.
  • the widths of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit are the same, and the lengths of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit increase sequentially.
  • the critical switching voltages of the fourth magnetic unit, the fifth magnetic unit and the sixth magnetic unit can be increased sequentially.
  • an electronic device in a second aspect, includes a printed circuit board; and the computing circuit according to the first aspect, the computing circuit being arranged on the printed circuit board.
  • Figure 1A shows a schematic diagram of a spin logic device according to some embodiments of the present disclosure.
  • FIG. 1B shows a perspective view of a magnetic unit of the spin logic device in FIG. 1A .
  • FIG. 1C is a graph showing the relationship between the output voltage and the input voltage of the spin logic device in FIG. 1A .
  • Figure 2A shows a schematic diagram of a computing circuit according to some embodiments of the present disclosure.
  • Figure 2B shows a schematic diagram of a computing circuit according to some embodiments of the present disclosure.
  • FIG. 3A shows the variation of the write voltage with the input voltage according to some embodiments of the present disclosure.
  • FIG. 3B shows the variation relationship of Hall resistance with writing voltage according to some embodiments of the present disclosure.
  • FIG. 3C shows the logic operation result of the computing circuit shown in FIG. 2 .
  • Figure 4 shows a schematic diagram of a computing circuit according to some embodiments of the present disclosure.
  • FIG. 5 shows the results of logical operations of the calculation circuit according to some embodiments of the present disclosure.
  • FIG. 6A shows output voltage as a function of read voltage according to some embodiments of the present disclosure.
  • FIG. 6B shows the relationship between the write voltage of a memory cell and the read voltage according to some embodiments of the present disclosure.
  • Figure 7 shows a schematic diagram of a computing circuit according to some embodiments of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it.
  • the term “coupled” may mean a direct connection between one component and another component, and may also include an indirect connection via other components.
  • a and/or B means A, B, or A and B.
  • Other definitions, both express and implied, may also be included below.
  • Embodiments of the present disclosure provide improved spin logic devices that can be implemented in various logic circuits, for example, computing devices such as processors.
  • spin logic devices can be used to implement logic operations for applications in computing devices such as processors or controllers.
  • Spin logic devices can implement logic gates or adders, etc. Further, combining logic gates or adders can realize more complex computing functions to implement processors or controllers.
  • Spin logic devices, logic gates, and processors or controllers can be arranged on a printed circuit board (PCB) to be incorporated in a variety of devices, such as computers, servers, laptops, desktops, mobile phones , cellular phones, personal digital assistants, wearables, or electronic devices such as set-top boxes, and can also be used in applications such as self-driving cars.
  • PCB printed circuit board
  • FIG. 1A shows a schematic diagram of a spin logic device 10 according to some embodiments of the present disclosure.
  • the spin logic device 10 includes a magnetic unit 5 , wherein FIG. 1B shows a perspective view of the magnetic unit 5 .
  • FIG. 1A shows a section of the magnetic unit 5 perpendicular to the z-axis direction, ie, a section in the x-y plane.
  • the magnetic unit 5 includes a spin Hall effect (Spin Hall Effect, SHE) layer 52 and a ferromagnetic layer 53 arranged along a stacking direction, wherein the stacking direction is the z-axis direction, and the magnetization of the ferromagnetic layer 53 The direction is along the stacking direction.
  • SHE spin Hall Effect
  • the SHE layer 52 may include metal materials with spin Hall effect, for example, heavy metal materials such as Ta and Pt. Alternatively, the SHE layer 52 may also include a topological insulator material.
  • the ferromagnetic layer 53 may include various ferromagnetic materials such as Fe, Co, Ni and alloys thereof such as CoFeB and the like. As shown in FIG. 1B , a SHE layer 52 is formed over a substrate 51 , a ferromagnetic layer 53 is formed over the SHE layer 52 , and an optional protective layer 54 may be formed over the ferromagnetic layer 53 .
  • the protection layer 54 may include an oxide layer, such as MgO and other materials. For example, the thicknesses of the SHE layer 52, the ferromagnetic layer 53 and the protective layer 54 may be in the range of several nanometers.
  • the magnetic unit 5 includes a first port 1 on a first side, a second port 2 on a second side opposite to the first port 1, and between the first port 1 and the second port 3 and The third port 3 on the third side.
  • the first port 1 is coupled to the first node 11 of the spin logic device 10
  • the second port 2 is coupled to the second node 12 of the spin logic device 10
  • the third port 3 is coupled to the third node of the spin logic device 13 coupling.
  • the first port 1 , the second port 2 and the third port 3 may be respectively coupled to the first node 11 , the second node 12 and the third node 13 through metal electrodes.
  • FIG. 1B shows a first electrode 55, a second electrode 56 and a third electrode 57, wherein the first electrode 55 is used to couple a first port (not shown) of the magnetic unit 5 to a first node (not shown).
  • the second electrode 56 is used to couple the second port (not shown) of the magnetic unit 5 with the second node (not shown), and the third electrode 57 is used to couple the third port (not shown) of the magnetic unit 5 Out) is coupled to a third node (not shown).
  • the first port of the magnetic unit 5 may be the portion of the SHE layer 52 in contact with the first electrode 55, and the first node of the spin logic device may be the first electrode 55. The part that connects with the external circuit.
  • first port to the third port are in contact with the corresponding electrodes, it can be seen that the first port and the third port are respectively on one side of the magnetic unit 5 , rather than on the upper surface or the lower surface of the magnetic unit 5 .
  • first electrode 55 , second electrode 56 and third electrode 57 are only in contact with SHE layer 52 in FIG. 1B , first electrode 55 , second electrode 56 and third electrode 57 may have other configurations.
  • the first electrode 55 , the second electrode 56 and the third electrode 57 may have the same height as the stack of the SHE layer 52 , the ferromagnetic layer 53 and the protective layer 54 .
  • the first electrode 55 , the second electrode 56 and the third electrode 57 may have the same height as the stack of the SHE layer 52 and the ferromagnetic layer 53 .
  • the height of a part of the first electrode 55 , the second electrode 56 and the third electrode 57 is different from that of the other part of the electrodes.
  • both the SHE layer 52 and the ferromagnetic layer 53 are conductive, therefore, the first electrode 55, the second electrode 56 and the third electrode 57 are compatible with the SHE layer 52 and the ferromagnetic layer 53. At least a partial contact is sufficient.
  • the inside of the SHE layer 52 may not conduct electricity, but only generate current on the surface, which may require the first electrode 55, the second electrode 56 and the third electrode 57 to be connected with the ferromagnetic layer. 53 contacts.
  • the first node 11 of the spin logic device 10 is connected to a first voltage (for example, an input voltage Vin), and the second node 12 of the spin logic device 10 is coupled to a second voltage (for example, ground). catch.
  • a first voltage may be applied to the first electrode 55 and a second voltage may be applied to the second electrode 56 . In this way, a voltage difference can be generated between the first electrode 55 and the second electrode 56 , thereby generating a write current in the SHE layer 52 .
  • the SHE layer 52 can generate spin-orbit torque by virtue of the spin Hall effect.
  • spin-orbit torque due to the anomalous Hall Effect (Anomalous Hall Effect, AHE) in the ferromagnetic layer 53, a Hall voltage is generated in the y-axis direction, resulting in a left voltage V 13 and a right voltage V 23 There is an asymmetry between them, wherein the left voltage V 13 and the right voltage V 23 represent the voltage between the first node and the third node and the voltage between the second node and the third node, respectively.
  • AHE anomalous Hall Effect
  • asymmetry between voltages can be amplified by negative differential resistance.
  • Negative differential resistance has the effect of further increasing large voltages and further reducing small voltages, therefore, asymmetry between voltages can be amplified.
  • a first negative differential resistance (Negative Differential Resistance, NDR) 4 is coupled between the first node 11 and the third node 13 of the spin logic device 10 .
  • the second negative differential resistor 6 is coupled between the second node 12 and the third node 13 of the spin logic device 10 .
  • the first NDR 4 and the second NDR 6 may be the same, or may have the same resistance characteristics.
  • the first NDR 4 and the second NDR 6 can be realized by elements having a negative differential resistance effect such as complementary junction field effect transistors or resonant tunneling transistors.
  • a Hall voltage is generated in the y direction, resulting in an asymmetry between the voltage V13 across the first NDR 4 and the voltage V23 across the second NDR 6, that is, one of V13 and V23 is high voltage, one for low voltage. If the magnetization direction of the magnetic unit 5 is changed, the Hall voltage is reversed, so that one of V 13 and V 23 is a low voltage and the other is a high voltage.
  • the magnetization direction of the magnetic unit 5 is used as a logic input.
  • the magnetization direction perpendicular to the substrate surface can be defined as a logic input "1” and the magnetization direction perpendicular to the substrate surface can be defined as a logic input "0".
  • the voltage magnitude of V 13 and V 23 may correspond to a logic output, for example, a high voltage is a logic output "1", and a low voltage is a logic output "0".
  • the asymmetry of the output voltage caused by the abnormal Hall effect is not high, therefore, the first NDR 4 and the second NDR 6 can be used to amplify the asymmetry of the output voltage, so as to achieve the purpose of identifying the logic output.
  • the magnetic unit 5 is symmetrical about an axis of symmetry that lies in the xy plane and is parallel to the y axis.
  • the first port 1 and the second port 2 are symmetrical with respect to the axis of symmetry, and the third port 3 is located on the axis of symmetry.
  • this symmetrical structure when no Hall voltage is generated in the magnetic unit 5, there is no asymmetry in the voltages V 13 and V 23 .
  • this symmetrical structure is more conducive to creating a clear asymmetry in the voltages V 13 and V 23 , making it easier to identify the logic output.
  • FIG. 1A and FIG. 1B show that the magnetic unit 5 has a T-shaped structure, the magnetic unit 5 may also have other shapes, especially other symmetrical shapes.
  • a spin logic device 10 as shown in FIG. 1A and FIG. 1B is prepared, wherein the magnetic material structure of the magnetic unit 5 is: Ta/CoFeB/MgO grown on thermally oxidized on a silicon substrate.
  • the first NDR 4 and the second NDR 6 are realized by complementary junction field effect transistors.
  • Fig. 1C shows the change relationship between the output voltage Vo (ie, V 23 ) and the input voltage Vin when the spin logic device 10 of this embodiment is in different magnetization states, where the square point curve represents the magnetization direction perpendicular to the substrate surface Up (logic input "0"), the circular point curve represents the magnetization direction perpendicular to the substrate surface down (logic input "1").
  • the square point curve represents the magnetization direction perpendicular to the substrate surface Up (logic input "0")
  • the circular point curve represents the magnetization direction perpendicular to the substrate surface down (logic input "1").
  • FIG. 2A shows a schematic diagram of computing circuitry 50 according to some embodiments of the present disclosure.
  • computing circuit 50 includes a memory array 52, which includes an array of spin logic devices, wherein each spin logic device may be a spin logic device as shown in FIG. 1A or other suitable voltage output type spin logic devices.
  • the calculation circuit 50 also includes an arithmetic array 54 comprising an array of magnetic units, each of which may be a magnetic unit 5 as shown in FIGS. 1A and 1B .
  • the operational array 54 is programmable, for example, the operational array 54 may have different connection structures in a write state and a read state.
  • the operational array 54 may also include a negative differential resistance for reading data from the magnetic units in the operational array 54 .
  • the calculation circuit 50 may further include a read/write circuit 56 , wherein the read/write circuit 56 may include a write circuit 58 and a read circuit 60 .
  • An input terminal of the write circuit 58 may be coupled to the memory array 52 to receive an output voltage of a spin logic device or a magnetic unit in the memory array 52 .
  • the write circuit 58 generates a write voltage based on the output voltage, and outputs the write voltage at its output terminal.
  • An output terminal of the write circuit 58 may be coupled to the operational array 54 to provide a write voltage to the magnetic cells in the operational array 54 to generate a write current in the magnetic cells.
  • An input terminal of the readout circuit 60 may be coupled to the operational array 54 to receive the output voltages of the magnetic units in the operational array 54 .
  • the read circuit 60 generates a write voltage based on the output voltage, and outputs the write voltage at its output terminal.
  • the output terminal of the read circuit 60 can be coupled to the memory array 52 to provide a write voltage to the magnetic unit in the memory array 52 to generate a write current in the magnetic unit.
  • the calculation circuit 20 further includes a switch circuit 62 , which can be coupled with the storage array 52 , the operation array 54 and/or the read/write circuit 56 for switching the state of the calculation circuit 20 .
  • the switch circuit 62 may be distributed in the storage array 52 , the operation array 54 and/or the read/write circuit 56 .
  • Switch circuit 62 may have a first state and a second state. In the first state, write circuit 58 reads data from memory array 62 and writes data into arithmetic array 54 . In the second state, read circuit 60 reads data from arithmetic array 54 and writes data into memory array 52 .
  • the arithmetic array 54 can have different configurations, which can also be realized by the switching circuit 62 .
  • the controller 64 is coupled to the switch circuit 62 for controlling the switch circuit 62 to switch between the first state and the second state.
  • FIG. 2B shows a schematic diagram of a computing circuit 100 according to some embodiments of the present disclosure.
  • Computing circuit 100 may be part of computing circuit 50 as shown in FIG. 2A .
  • computing circuit 100 includes logic input group 110, which may be part of memory array 52 in FIG. 2A.
  • the logic input group 110 includes a first magnetic unit 111 , a second magnetic unit 112 and a third magnetic unit 113 , and each magnetic unit can be realized by the magnetic unit 5 as shown in FIG. 1A and FIG. 1B .
  • the logic states of the first magnetic unit 111, the second magnetic unit 112 and the third magnetic unit 113 can be represented by bits a, b and c, respectively, so that the first magnetic unit 111, the second magnetic unit 112 and the third magnetic unit 113 They may also be referred to as logical input bits a, b, and c, respectively. It should be understood that the magnetic unit may also be realized by other magnetic units than those shown in FIG. 1A and FIG. 1B , especially a voltage output type magnetic unit.
  • the first port 1 of the first magnetic unit 111, the second magnetic unit 112 and the third magnetic unit 113 are respectively coupled with the input voltage Vin, and the first magnetic unit 111, the second magnetic unit 112 and the first magnetic unit 112
  • the second ports 2 of the three magnetic units 113 are respectively grounded.
  • the third port 3 of the first magnetic unit 111, the second magnetic unit 112 and the third magnetic unit 113 is respectively connected to the control terminals of the transistors 141, 142 and 143, that is, the gates, respectively to the control terminals of the transistors 141, 142 and 143.
  • the terminals provide output voltages V O1 , V O2 and V O3 .
  • the output voltages V O1 , V O2 and V O3 are respectively referred to as the first voltage, the second voltage and the third voltage below, wherein the first voltage represents the first bit stored in the first magnetic unit 111 (ie, bit a), the second voltage represents the second bit stored in the second magnetic unit 112 (ie, bit b), and the third voltage represents the third bit stored in the third magnetic unit 113 (ie, bit c).
  • the sources of the transistor 141, the transistor 142 and the transistor 143 are grounded, the drains of the transistor 141, the transistor 142 and the transistor 143 are respectively coupled with the resistor 131, the resistor 132 and the resistor 133, and the resistor 131, the resistor 132 and the resistor Device 133 is coupled to node 150. It should be understood that other types of switches may also be used instead of transistor 141 , transistor 142 and transistor 143 .
  • Transistor 141 , transistor 142 and transistor 143 and resistor 131 , resistor 132 and resistor 133 may be part of write circuit 58 in FIG. 2A . Therefore, the write circuit includes a plurality of input terminals, each of which is coupled to the output terminals of the first magnetic unit 111, the second magnetic unit 112 and the third magnetic unit 113 to receive the first voltage, the second voltage and a third voltage.
  • the first input terminal of the write circuit corresponds to the control terminal of the transistor 141
  • the second input terminal of the write circuit corresponds to the control terminal of the transistor 141
  • the third input terminal of the write circuit corresponds to the transistor 141 control terminals.
  • the output terminal of the writing circuit is a node 150 for outputting the first writing voltage.
  • the writing circuit is a pull-down circuit, and the pull-down circuit selectively pulls down the first writing voltage in response to the first voltage, the second voltage and the third voltage.
  • the transistor 141 when the first voltage V O1 is greater than the threshold voltage of the transistor 141 , the transistor 141 is turned on; otherwise, when the first voltage V O1 is lower than the threshold voltage of the transistor 141 , the transistor 141 is turned off.
  • the transistor 142 when the second voltage V O2 is greater than the threshold voltage of the transistor 142 , the transistor 142 is turned on; otherwise, when the second voltage V O2 is smaller than the threshold voltage of the transistor 142 , the transistor 142 is turned off.
  • the transistor 143 When the third voltage V O3 is greater than the threshold voltage of the transistor 143 , the transistor 143 is turned on; otherwise, when the third voltage V O3 is smaller than the threshold voltage of the transistor 143 , the transistor 143 is turned off. Therefore, by controlling the magnetization states of the magnetic cells of the logic input group 110 , the corresponding transistors can be controlled to be turned on and off. The more the number of transistors turned on, the more the pull-down circuit pulls down the first writing voltage, so the first writing voltage is lower.
  • the first magnetic unit 111 , the second magnetic unit 112 and the third magnetic unit 113 can be realized by the embodiment shown in FIG. 1C .
  • the first voltage V O1 , the second voltage V O2 or the third voltage V O3 is 2.2V (logic input “0”) or 0.3V (logic input “1”).
  • the threshold voltage V GS(th) of the transistor may be equal to 1.5V.
  • the calculation circuit 100 also includes a write bit group 120 , which may be a part of the operation array 54 in FIG. 2A .
  • the write bit group 120 includes a fourth magnetic unit 121, a fifth magnetic unit 122 and a sixth magnetic unit 123.
  • the fourth magnetic unit 121 may also be referred to as an "upper bit”
  • the fifth magnetic unit 122 may be referred to as an "upper bit”.
  • the sixth magnetic unit 123 is called a "lower bit”.
  • the resistor 131, the resistor 132 and the resistor 133 are coupled to the second port 2 of the fourth magnetic unit 121, the resistor 131, the resistor 132 and the resistor 133 are coupled to the first port 1 of the fifth magnetic unit 122, And the resistor 131 , the resistor 132 and the resistor 133 are coupled to the second port 2 of the sixth magnetic unit 123 .
  • the first port 1 of the fourth magnetic unit 121 is coupled to the power source V DD
  • the second port 2 of the fifth magnetic unit 121 is coupled to the power source V DD
  • the first port 1 of the sixth magnetic unit 123 is coupled to the power source V DD .
  • the voltage across the write bit group 120 ie, the voltage difference between the power supply V DD and the first write voltage at the node 150 is the write voltage V write . It should be understood that although the description is made here in conjunction with the power supply V DD and ground, other suitable reference voltages may also be used instead.
  • the fourth magnetic unit 121, the fifth magnetic unit 122, and the sixth magnetic unit 123 have different sizes.
  • the fourth magnetic unit 121, the fifth magnetic unit 122 and the sixth magnetic unit 123 have the same width but different lengths.
  • the lengths of the fourth magnetic unit 121, the fifth magnetic unit 122 and the sixth magnetic unit 123 increase sequentially, The critical switching voltages of the fourth magnetic unit 121 , the fifth magnetic unit 122 and the sixth magnetic unit 123 increase as the length increases. As shown in FIG.
  • the fourth magnetic unit 121 and the sixth magnetic unit 123 share port 1 and port 2
  • the fifth magnetic unit 122 is connected to the fourth magnetic unit 121 and sixth magnetic unit 123 in opposite directions. Therefore, the write current flowing through the fifth magnetic unit 122 is always opposite to the write current flowing through the fourth magnetic unit 121 and the sixth magnetic unit 123 .
  • the horizontal magnetic field H in FIG. 2B can be used to assist writing bit magnetization switching.
  • the magnetization states of the logic input bits a, b, and c determine the output voltages V o1 , V o2 , and V o3 , control the number of transistors 141 , 142 , and 143 turned on, and then determine the write voltage V write .
  • the write voltage V write affects the magnetization state of the written bits (ie, the fourth magnetic unit 121 , the fifth magnetic unit 122 and the sixth magnetic unit 123 ) through the spin-orbit coupling effect.
  • each spin logic device includes a magnetic unit and corresponding two NDRs. Therefore, each spin logic device can be used as a storage unit independently, and the spin logic device can be directly addressed and used in the operation without connecting the magnetic bits inside the spin logic device to each other. Thus, a relatively simpler addressing system is allowed.
  • Figure 3A shows that the magnetization states of logic input bits a, b, c are (0, 0, 0), (0, 0, 1) (0, 1, 0), (1, 0, 0), ( 0, 1, 1) (1, 0, 1), (1, 1, 0), (1, 1, 1), the write voltage V write varies with the input voltage Vin.
  • the input voltage Vin 2.5V
  • the value of the write voltage V Write is related to the number of "0"s in the logic input bits a, b, and c.
  • the write voltage V Write rises stepwise, presenting four stable values 10 -5 V, 2.4V, 4.0V, 5.1 V.
  • 3B is the measured voltage reversal curve of the fourth magnetic unit 121, the fifth magnetic unit 122 and the sixth magnetic unit 123 in the write bit group 120, that is, the Hall resistance (R xy ) varies with the write voltage (V Write ) change area.
  • the critical flipping voltages of the fourth magnetic unit 121 (ie, the upper bit), the fifth magnetic unit 122 (ie, the middle bit) and the sixth magnetic unit 123 (ie, the lower bit) are 2.3V, 2.3V, 3.2V and 4.3V, wherein, the writing current of the middle bit is always opposite to that of the upper bit and the lower bit, and the polarity of the reversal curve is also opposite.
  • FIG. 3C shows the logical operation result of the calculation circuit 100 shown in FIG. 2B.
  • the magnetization state of the logic input bit a, b is used as the logic input
  • the magnetization state of the logic input bit c is used as the control bit
  • the magnetization state of the write bit group 120 can correspond to AND (AND), or (OR), and NOT (NAND) and NOR (NOR) four Boolean logic gates.
  • the control bit c is "0"
  • the middle bit and the lower bit correspond to AND and NOR operations respectively
  • the control bit c is "1”
  • the upper bit and the middle bit correspond to NAND and OR operations respectively.
  • the magnetization state of the middle bit corresponds to the "Carry" function of the full adder.
  • the logical value of the upper bit is the logical NOR of the logical input bits a, b, c
  • the logical value of the lower bit is the logical NOR of the logical input bits a, b, c.
  • FIG. 4 shows a schematic diagram of a computing circuit 200 according to some embodiments of the present disclosure.
  • Calculation circuit 200 may be used to implement the "sum" bit of a full adder.
  • Computing circuit 200 may be part of computing circuit 50 shown in FIG. 2A .
  • the first port 1 of the fourth magnetic unit 121, the first port 1 of the fifth magnetic unit 122 and the first port 1 of the sixth magnetic unit 123 are coupled to each other and to the read voltage V read .
  • the second port 2 of the fourth magnetic unit 121 , the second port 2 of the fifth magnetic unit 122 and the second port 2 of the sixth magnetic unit 123 are coupled to each other and to the ground.
  • the third port 3 of the fourth magnetic unit 121 , the third port 3 of the fifth magnetic unit 122 and the third port 3 of the sixth magnetic unit 123 are coupled to each other and provide an output voltage V out .
  • the NDR 204 is coupled between the first port 1 and the third port 3 of the fourth magnetic unit 121, is coupled between the first port 1 and the third port 3 of the fifth magnetic unit 122, and is coupled between Between the first port 1 and the third port 3 of the sixth magnetic unit 123 .
  • the NDR 206 is coupled between the second port 2 and the third port 3 of the fourth magnetic unit 121, is coupled between the second port 2 and the third port 3 of the fifth magnetic unit 122, and is coupled between the sixth Between the second port 2 and the third port 3 of the magnetic unit 123 .
  • the fourth magnetic unit 121, the fifth magnetic unit 122, and the sixth magnetic unit 123, as well as the NDR 204 and the NDR 206 may be part of the operational array 54 shown in FIG. 2A.
  • the switching circuit 62 shown in FIG. 2A can reconnect the write bit group 120 shown in FIG. 2B to form the fourth magnetic unit 121, the fifth magnetic unit 122 and the sixth magnetic unit 120 as shown in FIG. Unit 123 and NDR 204 and NDR 206.
  • the output voltage V out is provided to the control terminal, ie gate, of the transistor 202 .
  • the source of the transistor 202 is grounded, and the drain of the transistor 202 is coupled to the second port 2 of the seventh magnetic unit 201 .
  • the logic state of the seventh magnetic unit 201 is represented by bit d.
  • the first port 1 of the seventh magnetic unit 201 is coupled to the power supply V DD .
  • the output voltage V out is the superposition of the output signals of the fourth magnetic unit 121, the fifth magnetic unit 122 and the sixth magnetic unit 123, and controls the on or off of the transistor 202, thereby controlling the writing voltage across the seventh magnetic unit 201 Vs and the magnetization state (logic bit d) of the seventh magnetic unit 201 .
  • Transistor 202 may be part of read circuit 60 as shown in FIG. 2A
  • seventh magnetic unit 201 may be part of memory array 52 as shown in FIG. 2A
  • the control terminal of transistor 202 corresponds to the input of the readout circuit
  • the drain terminal of transistor 202 corresponds to the output of the readout circuit.
  • the read circuit outputs the second write voltage at its output, ie at the drain terminal of the transistor 202 .
  • the write voltage Vs of the seventh magnetic unit 201 is equal to the difference between the power supply V DD and the second write voltage at the output of the read circuit.
  • FIG. 6A and 6B show the relationship between the measured output voltage V out and the write voltage Vs of the logic bit d of the seventh magnetic unit 201 along with the read voltage V read in the four states of the write bit group. .
  • the magnetization state of the first magnetic unit 111 to the third magnetic unit 113 (bit a, b, c) is used as a logic input
  • the magnetization state of the seventh logic unit 201 (bit d) is used as a logic output to form The "and" (sum) bit operation of the full adder.
  • the "and" bit operation of the adder is divided into two steps.
  • the circuit shown in Figure 2B is activated, the write bit group 120 is in the write state, the logic input bit group 110 inputs a logic signal, and the logic operation result is stored in the three bits of the write bit group 120 middle.
  • the circuit shown in Figure 4 is activated, the write-in bit group 120 is in the read state, and the bits stored therein are read from the write-in bit group 120, during the read process, the "and" bit operation result, and store the operation result in the seventh magnetic unit 201 (bit d).
  • FIG. 7 shows a schematic diagram of a computing circuit 300 according to some embodiments of the present disclosure.
  • the computing circuit 300 includes a storage array 310 and an operation array 320, wherein the storage array 310 can correspond to the storage array 52 as shown in Figure 2A, and the operation array 320 can correspond to the operation array 320 as shown in Figure 2A 54 corresponds.
  • the addressing system can select the input bits in the storage array 310, and input the information stored in the storage array 310 into the write bit group (also called "adder") in the operation array 320 in the form of a voltage after NDR enhancement.
  • the write bit group also called "adder”
  • the addition operation is complete and the result is buffered in the write bit group.
  • this can be achieved by the circuit shown in Figure 2B.
  • a pair of NDRs is used to convert the cached information written in the bit group into the magnetization of a single storage bit in the storage array 310 , so as to facilitate long-term storage or perform subsequent operations. For example, this can be achieved by a circuit as shown in FIG. 4 .
  • the magnetic unit 311 stores the bit a 1
  • the magnetic unit 312 stores the bit b 1
  • the magnetic unit 313 stores the bit c 1
  • the magnetic unit 311 , the magnetic unit 312 and the magnetic unit 313 may correspond to the first magnetic unit 111 , the second magnetic unit 112 and the third magnetic unit 113 as shown in FIG. 2B .
  • the magnetic units 311 , 312 and 313 are respectively coupled to the magnetic units 331 , 332 and 333 in the adder 330 .
  • the magnetic unit 331 , the magnetic unit 332 and the magnetic unit 333 may respectively correspond to the fourth magnetic unit 121 , the fifth magnetic unit 122 and the sixth magnetic unit 123 as shown in FIG. 2B . Therefore, the magnetic unit 311 , the magnetic unit 312 , the magnetic unit 313 and the magnetic unit 331 , the magnetic unit 332 and the magnetic unit 333 can be coupled in a manner as shown in FIG. 2B . Combining with the logic table shown in FIG.
  • the magnetic unit 331 stores the logical NAND among the bits a 1 , b 1 and c 1
  • the magnetic unit 332 stores the Carry of the summation between the bits a 1 , b 1 and c 1 (a 1 , b 1 , c 1 )
  • the magnetic unit 333 stores a logical NOR between bits a 1 , b 1 and c 1
  • the magnetic unit 314 may correspond to the seventh magnetic unit 201 as shown in FIG. 4 .
  • the magnetic unit 331 , the magnetic unit 332 , the magnetic unit 333 and the magnetic unit 314 may be coupled as shown in FIG. 4 .
  • magnetic unit 315 stores bit a 2
  • magnetic unit 316 stores bit b 2
  • the magnetic unit 313, the magnetic unit 315, and the magnetic unit 316 are respectively coupled to the magnetic unit 341, the magnetic unit 342, and the magnetic unit 343, wherein the magnetic unit 313, the magnetic unit 315, and the magnetic unit 316 and
  • the magnetic unit 341 , the magnetic unit 342 and the magnetic unit 343 may be coupled as shown in FIG. 2B . Combining with the logic table shown in FIG.
  • the magnetic unit 341 stores the logical NAND among the bits c 1 , a 2 and b 2
  • the magnetic unit 342 stores the Carry of the summation between the bits c 1 , a 2 and b 2 (c 1 , a 2 , b 2 )
  • the magnetic unit 343 stores a logical NOR between bits c 1 , a 2 and b 2
  • the magnetic unit 317 stores the bit d 2
  • the magnetic unit 341 , the magnetic unit 342 and the magnetic unit 343 can be coupled with the magnetic unit 317 as shown in FIG. 4 .
  • the information of each input bit is independently converted into a high or low level, so as to participate in the calculation process.
  • the operation process will not reversely affect the level of this level, therefore, a single input bit can participate in multiple operations in parallel at the same time.
  • the bit c 1 stored in the magnetic unit 313 serves as an input to two parallel adders 330 and 340 at the same time.
  • the logic input and the logic gate are integrated.
  • the input bit of this design is contained in a single logic gate, so one magnetic bit can only be used as the logic input of one logic gate at the same time.
  • conducive to parallel computing each operation requires connecting the called bits to each other. Therefore, in an array containing a large number of storage bits, a relatively more complex addressing system is required to implement arithmetic functions.
  • the embodiments of the present disclosure can realize parallel computing, and the addressing control logic is simpler.
  • the embodiments of the present disclosure can use fewer magnetic units to simultaneously implement the addition operation and the four Boolean logic operations of AND, OR, NAND, or NOT.

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Abstract

本公开的实施例提供了一种计算电路和电子设备。该计算电路包括存储阵列和运算阵列。存储阵列包括多个磁性单元，分别存储相应的比特，并且输出表示相应的比特的输出电压。写入电路接收这些输出电压，并且基于这些输出电压产生写入电压。运算阵列包括至少三个磁性单元，并且响应于写入电压而产生写入电流。三个磁性单元的临界翻转电压依次增大。通过存储阵列与运算阵列分开，在同一时间多个逻辑门可以从一个磁性单元来读取磁性比特，有利于并行计算，并且能够简化对存储比特的寻址系统。

Description

计算电路和电子设备 技术领域
本公开的实施例一般地涉及磁性逻辑器件，并且更具体地涉及包含磁性逻辑器件的计算电路和电子设备。
背景技术
自旋逻辑器件，又称为磁逻辑器件，是利用磁性材料中电子的自旋特性设计的数字逻辑器件。这种器件相比常规半导体逻辑器件，具有速度快、功耗低、逻辑信息的非易失性、防辐射等优点，因此被认为很有希望替代传统的半导体逻辑器件。然而，在通常的自旋逻辑器件中，逻辑输入与逻辑门是合为一体的，从而导致同一时间一个磁性比特只能作为一个逻辑门的逻辑输入，不利于并行计算。另外，每一步运算都需要将所调用的磁性比特彼此之间相连。因此，在包含大量存储比特的阵列中，实现运算功能需要相对更加复杂的寻址系统。
发明内容
本公开的实施例提供了一种计算电路和电子设备。
在第一方面，提供了一种计算电路。该计算电路包括存储阵列，存储阵列包括被配置为存储第一比特并且输出表示第一比特的第一电压的第一磁性单元、被配置为存储第二比特并且输出表示第二比特的第二电压的第二磁性单元以及被配置为存储第三比特并且输出表示第三比特的第三电压的第三磁性单元。该计算电路还包括写入电路，写入电路包括被配置为接收第一电压、第二电压和第三电压的多个输入端和被配置为输出第一写入电压的输出端。该计算电路还包括运算阵列，运算阵列包括第四磁性单元、第五磁性单元和第六磁性单元。第四磁性单元、第五磁性单元和第六磁性单元被配置为响应于第一写入电压，在第四磁性单元中产生第一写入电流，在第五磁性单元中产生第二写入电流，并且在第六磁性单元中产生第三写入电流。第一写入电流和第三写入电流具有相同的方向，第二写入电流与第一写入电流和第三写入电流具有相反的方向。第四磁性单元、第五磁性单元和第六磁性单元的临界翻转电压依次增大。
在这种计算电路中，通过对运算阵列的设计，对于一个写入电压可以实现不同的逻辑运算，从而允许将存储阵列与运算阵列分开。在存储阵列中的每一个磁性单元可以彼此独立存取，而不需要在存储阵列内将这些磁性单元彼此互连。因此，在从存储阵列读取数据时，在同一时间多个逻辑门可以从一个磁性单元来读取磁性比特，有利于并行计算。另外，在从存储阵列的磁性单元读取数据时，由于不需要将要读取的磁性单元彼此之间相连，可以简化对存储比特的寻址系统。
在一些实施例中，写入电路包括：下拉电路，被配置为响应于第一电压、第二电压和第三电压，有选择地下拉第一写入电压。以这种方式，可以实现多输入单输出的写入电路，以与存储阵列中的彼此独立的磁性单元相适配。
在一些实施例中，下拉电路包括第一开关，第一开关包括控制端子、第一端子和第二端子。第一开关的控制端子被配置为接收第一电压，第一开关的第一端子耦接至第一参考电压， 并且第一开关的第二端子耦接至输出端。下拉电路还包括第二开关，第二开关包括控制端子、第一端子和第二端子。第二开关的控制端子被配置为接收第二电压，第二开关的第一端子耦接至第一参考电压，并且第二开关的第二端子耦接至输出端。下拉电路还包括第三开关，第三开关包括控制端子、第一端子和第二端子。第三开关的控制端子被配置为接收第三电压，第三开关的第一端子耦接至第一参考电压，并且第三开关的第二端子耦接至输出端。
在一些实施例中，下拉电路还包括第一电阻器，第一电阻器耦接在第一开关的第二端子与输出端之间。下拉电路还包括第二电阻器，第二电阻器耦接在第二开关的第二端子与输出端之间。下拉电路还包括第三电阻器，第三电阻器耦接在第三开关的第二端子与输出端之间。
在一些实施例中，第四磁性单元的第一端口耦接至第二参考电压，并且第四磁性单元的第二端口耦接至输出端。第五磁性单元的第一端口耦接至输出端，并且第五磁性单元的第二端口耦接至第二参考电压。第六磁性单元的第一端口耦接至第二参考电压，并且第六磁性单元的第二端口耦接至输出端。
通过第四磁性单元、第五磁性单元和第六磁性单元的端口之间的连接，可以实现第一写入电流和第三写入电流具有相同的方向，第二写入电流与第一写入电流和第三写入电流具有相反的方向。
在一些实施例中，计算电路还包括：开关电路，被配置为将第四磁性单元、第五磁性单元和第六磁性单元的第一端口彼此耦接，并且将第四磁性单元、第五磁性单元和第六磁性单元的第二端口彼此耦接，以用于在第一端口与第二端口之间施加读取电压。开关电路还被配置为将第四磁性单元、第五磁性单元和第六磁性单元的第三端口彼此耦接，以输出第四电压。计算电路还包括读取电路，读取电路包括被配置为接收第四电压的输入端和被配置为输出第二写入电压的输出端。存储阵列还包括第七磁性单元，第七磁性单元被配置为响应于第二写入电压，在第七磁性单元中产生第四写入电流。
在从运算阵列读取数据时，需要对运算阵列中的磁性单元进行重新连接。由于存储阵列和运算阵列分开，这种重新连接不会影响存储阵列内的连接，从而简化了电路设计和控制。
在一些实施例中，读取电路包括：第四开关，第四开关包括控制端子、第一端子和第二端子。第四开关的控制端子被配置为接收第四电压，第四开关的第一端子耦接至第一参考电压，并且第四开关的第二端子耦接至读取电路的输出端。
在一些实施例中，开关电路被配置为：在第四磁性单元、第五磁性单元和第六磁性单元中的每一个磁性单元的第一端口与第四磁性单元、第五磁性单元和第六磁性单元中的相应的磁性单元的第三端口之间耦接第一负微分电阻，并且在第四磁性单元、第五磁性单元和第六磁性单元中的每一个磁性单元的第二端口与第四磁性单元、第五磁性单元和第六磁性单元中的相应的磁性单元的第三端口之间耦接第二负微分电阻。
通过负微分电阻，可以放大输出电压的不对称性，从而达到识别逻辑输出的目的。
在一些实施例中，第一磁性单元至第三磁性单元各自包括被配置为第一端口、第二端口和第三端口，其中第一磁性单元至第三磁性单元的第三端口分别被配置为输出第一电压、第二电压和第三电压。计算电路还包括：第三负微分电阻，耦接在第一磁性单元至第三磁性单元的第一端口与第三端口之间；以及第四负微分电阻，耦接在第一磁性单元至第三磁性单元的第二端口与第三端口之间。
存储阵列中的每一个磁性单元可以连接各自的负微分电阻，用于放大各自输出电压的不对称性。
在一些实施例中，第四磁性单元、第五磁性单元和第六磁性单元的宽度相同，并且第四磁性单元、第五磁性单元和第六磁性单元的长度依次增加。
通过第四磁性单元、第五磁性单元和第六磁性单元的尺寸的设置，可以实现第四磁性单元、第五磁性单元和第六磁性单元的临界翻转电压依次增大。
在第二方面，提供了一种电子设备。该电子设备包括印刷电路板；以及根据第一方面的计算电路，计算电路设置在印刷电路板上。
提供发明内容部分是为了以简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开的关键特征或主要特征，也无意限制本公开的范围。
附图说明
通过结合附图对本公开示例性实施例进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显，其中，在本公开示例性实施例中，相同的附图标记通常代表相同部件。
图1A示出了根据本公开的一些实施例的自旋逻辑器件的示意图。
图1B示出了图1A中的自旋逻辑器件的磁性单元的立体图。
图1C示出了图1A中的自旋逻辑器件的输出电压与输入电压之间的关系图。
图2A示出了根据本公开的一些实施例的计算电路的示意图。
图2B示出了根据本公开的一些实施例的计算电路的示意图。
图3A示出了根据本公开的一些实施例的写入电压随输入电压的变化关系。
图3B示出了根据本公开的一些实施例的霍尔电阻随写入电压的变化关系。
图3C示出了如图2所示的计算电路的逻辑运算结果。
图4示出了根据本公开的一些实施例的计算电路的示意图。
图5示出了根据本公开的一些实施例的计算电路的逻辑运算结果。
图6A示出了根据本公开的一些实施例的输出电压随着读电压的变化关系。
图6B示出了根据本公开的一些实施例的存储单元的写入电压随着读电压的变化关系。
图7示出了根据本公开的一些实施例的计算电路的示意图。
根据通常的做法，附图中示出的各种特征部可能未按比例绘制。因此，为了清楚起见，可以任意地扩展或减小各种特征部的尺寸。另外，一些附图可能未描绘给定的系统、方法或设备的所有部件。最后，在整个说明书和附图中，类似的附图标号可用于表示类似的特征部。
具体实施例
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。术语“耦接”可以表示一个部件与另 一部件之间的直接连接，也可以包括经由其他部件的间接连接。例如“A和/或B”表示A、B，或者A和B。下文还可能包括其他明确的和隐含的定义。
对方向或方位的任何参考仅旨在便于描述，而不以任何方式限制本公开的范围。例如“下部”、“上部”、“水平”、“竖直”、“上方”、“下方”、“朝上”、“朝下”、“顶部”和“底部”及其派生(例如“水平地”、“向上”、“向下”等)等相关术语在讨论中用来指代下文描述的或者在附图中示出的方位。这些相关术语仅仅是为了便于描述，而不要求装置以特定方位构造或操作。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
本公开的实施例提供了改进的自旋逻辑器件，该自旋逻辑器件可以在各种逻辑电路中实现，例如，处理器等计算设备。例如，自旋逻辑器件可以用于实现逻辑操作，以应用在处理器或控制器等计算装置中。自旋逻辑器件可以实现逻辑门或加法器等。进一步，将逻辑门或加法器进行组合，可以实现更加复杂的计算功能，以实现处理器或控制器。自旋逻辑器件、逻辑门以及处理器或控制器可以布置在印刷电路板(Printed Circuit Board,PCB)上，从而合并在各种设备中，例如，计算机、服务器、便携式计算机、桌面计算机、移动电话、蜂窝电话、个人数字助理、可穿戴设备或机顶盒等电子设备，并且也可以用于自动驾驶汽车等应用。
图1A示出了根据本公开的一些实施例的自旋逻辑器件10的示意图。如图1A所示，自旋逻辑器件10包括磁性单元5，其中图1B示出了磁性单元5的立体透视图。图1A示出了磁性单元5垂直于z轴方向的截面，即，在x-y平面中的截面。如图1B所示，磁性单元5包括沿着堆叠方向布置的自旋霍尔效应(Spin Hall Effect,SHE)层52和铁磁层53，其中堆叠方向为z轴方向，铁磁层53的磁化方向沿着堆叠方向。SHE层52可以包括具有自旋霍尔效应的金属材料，例如，Ta、Pt等重金属材料。备选地，SHE层52也可以包括拓扑绝缘体材料。铁磁层53可以包括各种铁磁材料，例如，Fe、Co、Ni及其合金，例如，CoFeB等。如图1B所示，SHE层52形成在衬底51之上，铁磁层53形成在SHE层52之上，并且可选的保护层54可以形成在铁磁层53之上。保护层54可以包括氧化层，例如，MgO等材料。例如，SHE层52、铁磁层53和保护层54的厚度可以在几纳米的范围内。
如图1A所示，磁性单元5包括在第一侧的第一端口1、在与第一端口1相对的第二侧的第二端口2以及位于第一端口1与第二端口3之间并且在第三侧的第三端口3。第一端口1与自旋逻辑器件10的第一节点11耦接，第二端口2与自旋逻辑器件10的第二节点12耦接，并且第三端口3与自旋逻辑器件的第三节点13耦接。例如，第一端口1、第二端口2和第三端口3可以分别通过金属电极与第一节点11、第二节点12和第三节点13耦接。
图1B示出了第一电极55、第二电极56和第三电极57，其中第一电极55用于将磁性单元5的第一端口(未示出)与第一节点(未示出)耦接，第二电极56用于将磁性单元5的第二端口(未示出)与第二节点(未示出)耦接，第三电极57用于将磁性单元5的第三端口(未示出)与第三节点(未示出)耦接。尽管未明确示出，在图1B的实施例中，磁性单元5的第一端口可以是SHE层52与第一电极55相接触的部分，自旋逻辑器件的第一节点可以是第一电极55与外部电路进行连接的部分。对于磁性单元5的第二端口和第三端口以及自旋逻辑器件的第二节点和第三节点，这里不再赘述。由于第一端口至第三端口与相应的电极接触，可以看出，第一端口与第三端口分别在磁性单元5的一侧，而不是在磁性单元5的上表面或下表面。应当理解，尽管在图1B中第一电极55、第二电极56和第三电极57仅与SHE层52 接触，第一电极55、第二电极56和第三电极57也可以具有其他配置。例如，第一电极55、第二电极56和第三电极57可以具有与SHE层52、铁磁层53和保护层54的堆叠相同的高度。又例如，第一电极55、第二电极56和第三电极57可以具有与SHE层52和铁磁层53的堆叠相同的高度。再例如，第一电极55、第二电极56和第三电极57中的一部分电极的高度与另一部分电极的高度不同。在SHE层52包含金属层的实施例中，SHE层52和铁磁层53均导电，因此，第一电极55、第二电极56和第三电极57与SHE层52和铁磁层53中的至少一部分接触即可。在SHE层52包含拓扑绝缘体的实施例中，SHE层52内部可能不导电，而只能在表面产生电流，这可能需要将第一电极55、第二电极56和第三电极57与铁磁层53接触。
如图1A所示，自旋逻辑器件10的第一节点11与第一电压(例如，输入电压Vin)连接，并且自旋逻辑器件10的第二节点12与第二电压(例如，接地)耦接。应当理解，第二电压也可以是接地之外的其他电压。为了方便讨论，以下将以输入电压Vin和接地电压为基础来描述本公开的实施例。如图1B所示，可以向第一电极55施加第一电压，并且向第二电极56施加第二电压。以这种方式，可以在第一电极55与第二电极56之间产生电压差，从而在SHE层52中产生写入电流。在写入电流的作用下，借助于自旋霍尔效应，SHE层52可以产生自旋轨道力矩。在自旋轨道力矩的作用下，由于铁磁层53中的反常霍尔效应(Anomalous Hall Effect,AHE)，在y轴方向上产生霍尔电压，导致左侧电压V 13和右侧电压V 23之间产生不对称性，其中左侧电压V 13与右侧电压V 23分别表示第一节点与第三节点之间的电压以及第二节点与第三节点之间的电压。
通常，反常霍尔效应产生的电压不对称性非常微小，难以进行检测。可以通过负微分电阻来放大电压之间的不对称性。负微分电阻具有将大电压进一步增大，并将小电压进一步减小的效果，因此，可以放大电压之间的不对称性。如图1A所示，第一负微分电阻(Negative Differential Resistance,NDR)4耦接在自旋逻辑器件10的第一节点11与第三节点13之间。第二负微分电阻6耦接在自旋逻辑器件10的第二节点12与第三节点13之间。例如，第一NDR 4和第二NDR 6可以相同，或者可以具有相同的电阻特性。第一NDR 4和第二NDR 6可以由互补结型场效应晶体管或共振隧穿晶体管等具有负微分电阻效应的元件来实现。当在第一节点11施加输入电压Vin时，电流在磁性单元5中沿着x轴方向流动。由于反常霍尔效应，在y方向会产生霍尔电压，导致第一NDR 4两端的电压V 13和第二NDR 6两端的电压V 23出现不对称，即，V 13和V 23中一个为高电压，一个为低电压。如果改变磁性单元5的磁化方向，则霍尔电压反向，从而V 13和V 23中一个为低电压，一个为高电压。在逻辑操作时，以磁性单元5的磁化方向作为逻辑输入。例如，可以将磁化方向垂直于衬底表面向下定义为逻辑输入“1”，并且将磁化方向垂直于衬底表面向上定义为逻辑输入“0”。备选地，也可以将磁化方向垂直于衬底表面向下定义为逻辑输入“0”，并且将磁化方向垂直于衬底表面向上定义为逻辑输入“1”。V 13和V 23的电压大小可以对应于逻辑输出，例如，高电压为逻辑输出“1”，低电压为逻辑输出“0”。反常霍尔效应导致的输出电压的不对称性不高，因此，第一NDR 4和第二NDR 6可以用于放大这种输出电压的不对称性，从而达到识别逻辑输出的目的。
在图1A和图1B所示的实施例中，磁性单元5相对于对称轴对称，该对称轴位于x-y平面内，并且与y轴平行。第一端口1与第二端口2相对于对称轴对称，并且第三端口3位于对称轴上。根据该对称结构，当在磁性单元5中没有产生霍尔电压时，电压V 13和V 23不存在任何不对称性。因而，当在磁性单元5中产生霍尔电压时，这种对称结构更加有助于在电压V 13和V 23中产生明显的不对称，从而更容易识别逻辑输出。应当理解，尽管图1A和图1B 示出了磁性单元5具有T字型结构，磁性单元5也可以具有其他形状，特别是其他对称的形状。
在一个实施例中，制备了如图1A和图1B所示的自旋逻辑器件10，其中，磁性单元5的磁性材料结构为：Ta/CoFeB/MgO，通过磁控溅射生长在热氧化的硅衬底上。第一NDR 4和第二NDR 6由互补结型场效应晶体管实现。图1C示出了该实施例的自旋逻辑器件10在不同磁化状态时，输出电压Vo(即，V 23)与输入电压Vin之间的变化关系，其中方形点曲线代表磁化方向垂直衬底表面向上(逻辑输入“0”)，圆形点曲线代表磁化方向垂直衬底表面向下(逻辑输入“1”)。如图1C所示，在该实施例中，当输入电压Vin＝2.5V时，在两种不同逻辑输入下，输出电压Vo差异最大。具体而言，当输入电压Vin＝2.5V时，对于逻辑输入“0”，输出电压Vo约为2.2V，对于逻辑输入“1”，输出电压Vo约为0.3V。
图2A示出了根据本公开的一些实施例的计算电路50的示意图。如图2A所示，计算电路50包括存储阵列52，存储阵列52包括自旋逻辑器件的阵列，其中每一个自旋逻辑器件可以是如图1A所示的自旋逻辑器件或者其他适当的电压输出型的自旋逻辑器件。计算电路50还包括运算阵列54，运算阵列54包括磁性单元的阵列，其中每一个磁性单元可以是如图1A和图1B所示的磁性单元5。在一些实施例中，运算阵列54可编程，例如，在写入状态和读取状态中，运算阵列54可以具有不同的连接结构。此外，运算阵列54还可以包括负微分电阻，以用于从运算阵列54中的磁性单元中读取数据。
如图2A所示，计算电路50还可以包括读写电路56，其中，读写电路56可以包括写入电路58和读取电路60。写入电路58的输入端可以与存储阵列52耦接，以接收存储阵列52中的自旋逻辑器件或者磁性单元的输出电压。写入电路58基于该输出电压来产生写入电压，并且在其输出端处输出该写入电压。写入电路58的输出端可以与运算阵列54耦接，以将写入电压提供给运算阵列54中的磁性单元，从而在磁性单元中产生写入电流。读取电路60的输入端可以与运算阵列54耦接，以接收运算阵列54中的磁性单元的输出电压。读取电路60基于该输出电压来产生写入电压，并且在其输出端出输出该写入电压。读取电路60的输出端可以与存储阵列52耦接，以写入电压提供给存储阵列52中的磁性单元，从而在该磁性单元中产生写入电流。
计算电路20还包括开关电路62，开关电路62可以与存储阵列52、运算阵列54和/或读写电路56耦接，以用于实现计算电路20的状态切换。在一些实施例中，开关电路62可以分布于存储阵列52、运算阵列54和/或读写电路56中。开关电路62可以具有第一状态和第二状态。在第一状态中，写入电路58从存储阵列62中读取数据，并且将数据写入到运算阵列54中。在第二状态中，读取电路60从运算阵列54读取数据，并且将数据写入到存储阵列52中。在第一状态和第二状态中，运算阵列54可以具有不同的配置，这也可以由开关电路62来实现。此外，控制器64与开关电路62耦接，以用于控制开关电路62在第一状态和第二状态之间切换。
图2B示出了根据本公开的一些实施例的计算电路100的示意图。计算电路100可以是如图2A所示的计算电路50的一部分。如图2B所示，计算电路100包括逻辑输入组110，逻辑输入组110可以是图2A中的存储阵列52的一部分。逻辑输入组110包括第一磁性单元111、第二磁性单元112和第三磁性单元113，每一个磁性单元可以由如图1A和图1B所示的磁性单元5来实现。第一磁性单元111、第二磁性单元112和第三磁性单元113的逻辑状态可以分别由位a、b和c来表示，因而第一磁性单元111、第二磁性单元112和第三磁性单元113也 可以分别称为逻辑输入比特a、b和c。应当理解，磁性单元也可以由图1A和图1B所示的磁性单元之外的其他磁性单元，特别是电压输出型磁性单元来实现。
如图2B所示，第一磁性单元111、第二磁性单元112和第三磁性单元113的第一端口1各自与输入电压Vin耦接，并且第一磁性单元111、第二磁性单元112和第三磁性单元113的第二端口2各自接地。第一磁性单元111、第二磁性单元112和第三磁性单元113的第三端口3分别连接到晶体管141、142和143的控制端子，即，栅极，分别向晶体管141、142和143的控制端子提供输出电压V O1、V O2和V O3。为了方便描述，以下将输出电压V O1、V O2和V O3分别称为第一电压、第二电压和第三电压，其中第一电压表示第一磁性单元111中存储的第一比特(即，比特a)，第二电压表示第二磁性单元112中存储的第二比特(即，比特b)，并且第三电压表示第三磁性单元113中存储的第三比特(即，比特c)。晶体管141、晶体管142和晶体管143的源极接地，晶体管141、晶体管142和晶体管143的漏极分别与电阻器131、电阻器132和电阻器133耦接，并且电阻器131、电阻器132和电阻器133与节点150耦接。应当理解，也可以使用其他类型的开关来代替晶体管141、晶体管142和晶体管143。
晶体管141、晶体管142和晶体管143以及电阻器131、电阻器132和电阻器133可以是图2A中的写入电路58的一部分。因此，该写入电路包括多个输入端，其中每一个输入端分别与第一磁性单元111、第二磁性单元112和第三磁性单元113的输出端耦接，以接收第一电压、第二电压和第三电压。在图2B中，写入电路的第一输入端对应于晶体管141的控制端子，写入电路的第二输入端对应于晶体管141的控制端子，并且写入电路的第三输入端对应于晶体管141的控制端子。写入电路的输出端为节点150，用于输出第一写入电压。
如图2B所示，该写入电路为下拉电路，该下拉电路响应于第一电压、第二电压和第三电压，有选择地下拉第一写入电压。例如，当第一电压V O1大于晶体管141的阈值电压时，晶体管141处于打开状态；反之，当第一电压V O1小于晶体管141的阈值电压时，晶体管141处于关闭状态。类似地，当第二电压V O2大于晶体管142的阈值电压时，晶体管142处于打开状态；反之，当第二电压V O2小于晶体管142的阈值电压时，晶体管142处于关闭状态。当第三电压V O3大于晶体管143的阈值电压时，晶体管143处于打开状态；反之，当第三电压V O3小于晶体管143的阈值电压时，晶体管143处于关闭状态。因此，可以通过控制逻辑输入组110的磁性单元的磁化状态来控制相应的晶体管的打开和关闭。晶体管导通的个数越多，下拉电路将第一写入电压下拉得越多，从而第一写入电压越低。
第一磁性单元111、第二磁性单元112和第三磁性单元113可以由图1C所示的实施例实现。在输入电压Vin＝2.5V时，第一电压V O1、第二电压V O2或第三电压V O3为2.2V(逻辑输入“0”)或0.3V(逻辑输入“1”)。在该实施例中，晶体管的阈值电压V GS(th)可以等于1.5V。
如图2B所示，计算电路100还包括写入比特组120，写入比特组120可以是图2A中的运算阵列54的一部分。写入比特组120包括第四磁性单元121、第五磁性单元122和第六磁性单元123，为了方便起见，也可以将第四磁性单元121称为“上比特”，将第五磁性单元122称为“中比特”，并且将第六磁性单元123称为“下比特”。电阻器131、电阻器132和电阻器133与第四磁性单元121的第二端口2耦接，电阻器131、电阻器132和电阻器133与第五磁性单元122的第一端口1耦接，并且电阻器131、电阻器132和电阻器133与第六磁性单元123的第二端口2耦接。另外，第四磁性单元121的第一端口1与电源V DD耦接，第五磁性单元121的第二端口2与电源V DD耦接，并且第六磁性单元123的第一端口1与电源V DD 耦接。写入比特组120两端的电压，即，电源V DD与节点150处的第一写入电压之间的电压差为写入电压V write。应当理解，尽管这里结合电源V DD和地进行描述，也可以使用其他适当的参考电压来进行替代。
晶体管141、晶体管142和晶体管143导通的数量越多，节点150与地之间并联的电阻器的数量越多，从而节点150的电压越低，写入比特组120两端的写入电压V write越大。第四磁性单元121、第五磁性单元122和第六磁性单元123具有不同的尺寸。例如，第四磁性单元121、第五磁性单元122和第六磁性单元123的宽度相同，长度不同，例如，第四磁性单元121、第五磁性单元122和第六磁性单元123的长度依次增加，第四磁性单元121、第五磁性单元122和第六磁性单元123的临界翻转电压随着长度的增加而增大。如图2B所示，第四磁性单元121和第六磁性单元123共用端口1和端口2，第五磁性单元122与第四磁性单元121和第六磁性单元123反向连接。因此，流经第五磁性单元122的写入电流与流经第四磁性单元121和第六磁性单元123的写入电流总是反向。
由于第四磁性单元121、第五磁性单元122和第六磁性单元123的长度不同，第四磁性单元121、第五磁性单元122和第六磁性单元123的临界翻转电压随着长度的增加而增大。因此，当写入电压V write逐渐增加时，第四磁性单元121、第五磁性单元122和第六磁性单元123会依次翻转。图2B中的水平磁场H可以用来辅助写入比特磁化翻转。
逻辑输入比特a、b和c的磁化状态决定输出电压V o1、V o2和V o3的大小，控制晶体管141、晶体管142和晶体管143的开启个数，进而决定写入电压V write的大小。写入电压V write通过自旋轨道耦合作用影响写入比特(即，第四磁性单元121、第五磁性单元122和第六磁性单元123)的磁化状态。
在计算电路200中，通过将逻辑输入与逻辑运算分开，有利于实现并行计算。例如，磁性单元111可以同时用于另外一个写入比特组以执行逻辑运算。另外，逻辑输入组110中的基本单元为如图1A所示的自旋逻辑器件，其中每一个自旋逻辑器件包括一个磁性单元和相应的两个NDR。因此，每一个自旋逻辑器件可以单独作为一个存储单元，在运算中可以直接对自旋逻辑器件进行寻址和使用，而无需将自旋逻辑器件内部的磁性比特彼此相连。因此，允许使用相对更加简单的寻址系统。
图3A示出了逻辑输入比特a、b、c的磁化状态分别为(0，0，0)，(0，0，1)(0，1，0)，(1，0，0)，(0，1，1)(1，0，1)，(1，1，0)，(1，1，1)时，写入电压V write随着输入电压Vin的变化关系。在逻辑操作时，输入电压Vin＝2.5V，写入电压V Write的值与逻辑输入比特a、b、c中“0”的个数有关。随着逻辑输入比特a、b、c中“0”的个数从0增加为3，写入电压V Write呈阶梯式上升，呈现四个稳定值10 -5V，2.4V，4.0V，5.1V。图3B为测量的写入比特组120中的第四磁性单元121、第五磁性单元122和第六磁性单元123的电压翻转曲线，即，霍尔电阻(R xy)随写入电压(V Write)的变化区域。如图3B所示，第四磁性单元121(即，上比特)、第五磁性单元122(即，中比特)和第六磁性单元123(即，下比特)的临界翻转电压分别为2.3V、3.2V和4.3V，其中，中比特的写入电流总是与上比特和下比特相反，其翻转曲线的极性也相反。因此，当逻辑输入比特a、b、c全为“1”时，V Write～10 -5V，此时写入比特组120的上比特、中比特和下比特都不翻转，维持预设的磁化状态(0，1，0)；当逻辑输入比特a、b、c有一个“0”时，V Write＝2.4V，只能翻转上比特，此时写入比特组变为(1，1，0)；当逻辑输入比特a、b、c有两个“0”时，V Write＝4.0V，可以翻转上比特和中比特，此时写入比特组变为(1，0，0)；当逻辑输入比特a、b、c全为“0”时，V Write＝5.1V，可以翻 转上比特、中比特和下比特的磁化，此时写入比特组变为(1，0，1)。
图3C示出了图2B所示的计算电路100的逻辑运算结果。当将逻辑输入比特a、b的磁化状态作为逻辑输入，逻辑输入比特c的磁化状态作为控制比特时，则写入比特组120的磁化状态可以对应与(AND)、或(OR)、与非(NAND)和或非(NOR)四种布尔逻辑门。具体地，当控制比特c为“0”时，中比特和下比特分别对应AND和NOR运算；控制比特c为“1”时，上比特和中比特分别对应NAND和OR运算。此外，将逻辑输入比特a、b、c的磁化状态作为全加器的三个逻辑输入时，则中比特的磁化状态对应全加器的“进位”(Carry)功能。此外，上比特的逻辑值为逻辑输入比特a、b、c的逻辑与非，下比特的逻辑值为逻辑输入比特a、b、c的逻辑或非。
图4示出了根据本公开的一些实施例的计算电路200的示意图。计算电路200可以用于实现全加器的“和”位。计算电路200可以是图2A所示的计算电路50的一部分。如图4所示，第四磁性单元121的第一端口1、第五磁性单元122的第一端口1和第六磁性单元123的第一端口1彼此耦接，并耦接到读取电压V read。第四磁性单元121的第二端口2、第五磁性单元122的第二端口2和第六磁性单元123的第二端口2彼此耦接，并耦接到地。第四磁性单元121的第三端口3、第五磁性单元122的第三端口3和第六磁性单元123的第三端口3彼此耦接，并提供输出电压V out。另外，NDR 204耦接在第四磁性单元121的第一端口1和第三端口3之间，耦接在第五磁性单元122的第一端口1和第三端口3之间，并且耦接在第六磁性单元123的第一端口1和第三端口3之间。NDR 206耦接在第四磁性单元121的第二端口2和第三端口3之间，耦接在第五磁性单元122的第二端口2和第三端口3之间，并且耦接在第六磁性单元123的第二端口2和第三端口3之间。
第四磁性单元121、第五磁性单元122和第六磁性单元123以及NDR 204和NDR 206可以是图2A所示的运算阵列54的一部分。例如，如图2A所示的开关电路62可以将如图2B所示的写入比特组120重新连接，以形成如图4所示的第四磁性单元121、第五磁性单元122和第六磁性单元123以及NDR 204和NDR 206。
输出电压V out提供给晶体管202的控制端子，即，栅极。晶体管202的源极接地，晶体管202的漏极与第七磁性单元201的第二端口2耦接。第七磁性单元201的逻辑状态由比特d来表示。第七磁性单元201的第一端口1与电源V DD耦接。输出电压V out为第四磁性单元121、第五磁性单元122和第六磁性单元123的输出信号的叠加，并且控制晶体管202的导通或关闭，从而控制第七磁性单元201两端的写入电压Vs以及第七磁性单元201的磁化状态(逻辑比特d)。如图5所示，当逻辑输入比特a、b、c中逻辑输入“0”的个数从0向3增加时，写入比特组120的磁化状态将变为：(0，1，0)，(1，1，0)，(1，0，0)以及(1，0，1)。
晶体管202可以是如图2A所示的读取电路60的一部分，并且第七磁性单元201可以是如图2A所示的存储阵列52的一部分。在该实施例中，晶体管202的控制端子对应于读取电路的输入端，并且晶体管202的漏极端子对应于读取电路的输出端。读取电路在其输出端处输出第二写入电压，即，在晶体管202的漏极端子处输出第二写入电压。因而，第七磁性单元201的写入电压Vs等于电源V DD与读取电路的输出端处的第二写入电压之间的差值。
图6A和图6B示出了在写入比特组的四种状态下，测量的输出电压V out和第七磁性单元201的逻辑位d的写入电压Vs随着读取电压V read的变化关系。图5进一步示出了在读取电压V read＝2.2V时输出电压V out和Vs的值以及位d的逻辑值。如图5所示，以第一磁性单元111至第三磁性单元113(比特a、b、c)的磁化状态作为逻辑输入，第七逻辑单元201(比特d) 的磁化状态作为逻辑输出，形成了全加器的“和”(sum)位运算。
结合图2A至图6B可知，加法器的“和”位运算分为两个步骤。在第一步骤中，激活如图2B所示的电路，写入比特组120处于写入状态，逻辑输入比特组110输入逻辑信号，并将逻辑运算结果存储在写入比特组120的三个比特中。在第二步骤中，激活如图4所示的电路，写入比特组120处于读取状态，从写入比特组120中读取其中存储的比特，在读取过程中，计算出“和”位运算结果，并将该运算结果存储在第七磁性单元201(比特d)中。
图7示出了根据本公开的一些实施例的计算电路300的示意图。如图7所示，计算电路300包括存储阵列310和运算阵列320，其中，存储阵列310可以与如图2A所示的存储阵列52相对应，运算阵列320可以与如图2A所示的运算阵列54相对应。
寻址系统可以选择存储阵列310中的输入比特，将存储阵列310中存储的信息通过NDR增强之后以电压形式输入到运算阵列320中的写入比特组(也称“加法器”)中。当写入比特组中的比特完成写入时，加法运算便已完成，其结果缓存在写入比特组中。例如，这可以通过如图2B所示的电路来实现。然后，再利用一对NDR将写入比特组中缓存的信息转化为存储阵列310中的单个存储比特的磁化，以便于长期存储或执行后续的运算。例如，这可以通过如图4所示的电路来实现。
如图7所示，磁性单元311存储比特a 1，磁性单元312存储比特b 1，磁性单元313存储比特c 1。磁性单元311、磁性单元312、磁性单元313可以与如图2B所示的第一磁性单元111、第二磁性单元112、第三磁性单元113对应。在向加法器330进行写入时，磁性单元311、312和313分别耦接至加法器330中的磁性单元331、332和333。磁性单元331、磁性单元332和磁性单元333可以分别与如图2B所示的第四磁性单元121、第五磁性单元122和第六磁性单元123相对应。因而，磁性单元311、磁性单元312、磁性单元313以及磁性单元331、磁性单元332和磁性单元333可以通过如图2B所示的方式耦接。结合图3C所示的逻辑表可知，磁性单元331存储比特a 1、b 1和c 1之间的逻辑与非，磁性单元332存储比特a 1、b 1和c 1之间求和的进位Carry(a 1,b 1,c 1)，磁性单元333存储比特a 1、b 1和c 1之间的逻辑或非。另外，磁性单元314可以与如图4所示的第七磁性单元201相对应。在从加法器330读取数据时，磁性单元331、磁性单元332和磁性单元333与磁性单元314可以通过如图4所示的方式耦接。结合如图5所示的逻辑表，可以实现比特a 1、b 1和c 1之间的和位运算SUM(a 1,b 1,c 1)，并将和位运算的结果存储在磁性单元314，即，d 1＝SUM(a 1,b 1,c 1)。
另外，磁性单元315存储比特a 2，磁性单元316存储比特b 2。在向加法器340进行写入时，磁性单元313、磁性单元315和磁性单元316分别耦接至磁性单元341、磁性单元342和磁性单元343，其中磁性单元313、磁性单元315和磁性单元316以及磁性单元341、磁性单元342和磁性单元343可以通过如图2B所示的方式耦接。结合图3C所示的逻辑表可知，磁性单元341存储比特c 1、a 2和b 2之间的逻辑与非，磁性单元342存储比特c 1、a 2和b 2之间求和的进位Carry(c 1,a 2,b 2)，磁性单元343存储比特c 1、a 2和b 2之间的逻辑或非。另外，磁性单元317存储比特d 2，磁性单元341、磁性单元342和磁性单元343与磁性单元317可以通过如图4所示的方式耦接。结合如图5所示的逻辑表，可以实现比特c 1、a 2和b 2之间的和位运算SUM(c 1,a 2,b 2)，并将和位运算的结果存储在磁性单元317，即，d 2＝SUM(c 1,a 2,b 2)。
如图7所示，在计算电路300中，每个输入比特的信息被独立转换为电平的高低，从而参与运算过程。运算过程不会反向影响到这一电平的高低，因此，同一时间单个输入比特能够并行参与多个运算。例如，磁性单元313存储的比特c 1同时作为两个并行加法器330和340 的输入。
在通常的磁逻辑器件中，逻辑输入与逻辑门是合为一体的，这种设计方案的输入比特包含在单个逻辑门内，因此同一时间一个磁性比特只能作为一个逻辑门的逻辑输入，不利于并行计算。另外，在这种方案中，每一步运算都需要将所调用的比特彼此之间相连。因此，在包含大量存储比特的阵列中，实现运算功能需要相对更加复杂的寻址系统。然而，本公开的实施例可以实现并行计算，寻址控制逻辑更简单。另外，本公开的实施例可以利用较少的磁性单元可以同时实现加法运算，以及与、或、与非、或非四种布尔逻辑运算。
尽管已经详细地描述了本公开的实施例及其优势，但应该理解，在不脱离所附权利要求所限定的本公开的范围的情况下，可对本公开做出各种改变、替代和变化。而且，本申请的范围不旨在限于本说明书中所述的工艺、机器装置、制造、物质组成、工具、方法和步骤的具体实施例。本领域的技术人员通过本公开容易理解，根据本公开，可以利用已有的或今后将开发的、与本公开所述相应实施例执行基本相同的功能或者实现基本相同的结果的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、物质组成、工具、方法或步骤包括在它们的保护范围内。另外，每个权利要求组成单独的实施例，并且各个权利要求和实施例的组合都在本公开的范围内。

Claims (11)

  1. 一种计算电路，包括：
    存储阵列，包括被配置为存储第一比特并且输出表示所述第一比特的第一电压的第一磁性单元、被配置为存储第二比特并且输出表示所述第二比特的第二电压的第二磁性单元以及被配置为存储第三比特并且输出表示第三比特的第三电压的第三磁性单元；
    写入电路，包括被配置为接收所述第一电压、所述第二电压和所述第三电压的多个输入端和被配置为输出第一写入电压的输出端；以及
    运算阵列，包括第四磁性单元、第五磁性单元和第六磁性单元，其中，所述第四磁性单元、所述第五磁性单元和所述第六磁性单元被配置为响应于所述第一写入电压，在所述第四磁性单元中产生第一写入电流，在所述第五磁性单元中产生第二写入电流，并且在所述第六磁性单元中产生第三写入电流，其中，所述第一写入电流和所述第三写入电流具有相同的方向，所述第二写入电流与所述第一写入电流和所述第三写入电流具有相反的方向，并且，所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的临界翻转电压依次增大。
  2. 根据权利要求1所述的计算电路，其中所述写入电路包括：
    下拉电路，被配置为响应于所述第一电压、所述第二电压和所述第三电压，有选择地下拉所述第一写入电压。
  3. 根据权利要求2所述的计算电路，其中所述下拉电路包括：
    第一开关，所述第一开关包括控制端子、第一端子和第二端子，其中，所述第一开关的控制端子被配置为接收所述第一电压，所述第一开关的第一端子耦接至第一参考电压，并且所述第一开关的第二端子耦接至所述输出端；
    第二开关，所述第二开关包括控制端子、第一端子和第二端子，其中，所述第二开关的控制端子被配置为接收所述第二电压，所述第二开关的第一端子耦接至所述第一参考电压，并且所述第二开关的第二端子耦接至所述输出端；以及
    第三开关，所述第三开关包括控制端子、第一端子和第二端子，其中，所述第三开关的控制端子被配置为接收所述第三电压，所述第三开关的第一端子耦接至所述第一参考电压，并且所述第三开关的第二端子耦接至所述输出端。
  4. 根据权利要求3所述的计算电路，其中所述下拉电路还包括：
    第一电阻器，所述第一电阻器耦接在所述第一开关的第二端子与所述输出端之间；
    第二电阻器，所述第二电阻器耦接在所述第二开关的第二端子与所述输出端之间；以及
    第三电阻器，所述第三电阻器耦接在所述第三开关的第二端子与所述输出端之间。
  5. 根据权利要求1至4中任一项所述的计算电路，其中：
    所述第四磁性单元的第一端口耦接至第二参考电压，并且所述第四磁性单元的第二端口耦接至所述输出端；
    所述第五磁性单元的第一端口耦接至所述输出端，并且所述第五磁性单元的第二端口耦接至所述第二参考电压；以及
    所述第六磁性单元的第一端口耦接至所述第二参考电压，并且所述第六磁性单元的第二端口耦接至所述输出端。
  6. 根据权利要求1至5中任一项所述的计算电路，还包括：
    开关电路，被配置为将所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的第 一端口彼此耦接，并且将所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的第二端口彼此耦接，以用于在所述第一端口与所述第二端口之间施加读取电压，并且所述开关电路还被配置为将所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的第三端口彼此耦接，以输出第四电压；
    所述计算电路还包括读取电路，所述读取电路包括被配置为接收所述第四电压的输入端和被配置为输出第二写入电压的输出端，
    所述存储阵列还包括第七磁性单元，所述第七磁性单元被配置为响应于所述第二写入电压，在所述第七磁性单元中产生第四写入电流。
  7. 根据权利要求6所述的计算电路，其中所述读取电路包括：
    第四开关，所述第四开关包括控制端子、第一端子和第二端子，所述第四开关的控制端子被配置为接收所述第四电压，所述第四开关的第一端子耦接至第一参考电压，并且所述第四开关的第二端子耦接至所述读取电路的输出端。
  8. 根据权利要求6或7中任一项所述的计算电路，其中，所述开关电路被配置为：
    在所述第四磁性单元、所述第五磁性单元和所述第六磁性单元中的每一个磁性单元的第一端口与所述第四磁性单元、所述第五磁性单元和所述第六磁性单元中的相应的磁性单元的第三端口之间耦接第一负微分电阻，并且
    在所述第四磁性单元、所述第五磁性单元和所述第六磁性单元中的每一个磁性单元的第二端口与所述第四磁性单元、所述第五磁性单元和所述第六磁性单元中的相应的磁性单元的第三端口之间耦接第二负微分电阻。
  9. 根据权利要求1至8中任一项所述的计算电路，其中，所述第一磁性单元至所述第三磁性单元各自包括被配置为第一端口、第二端口和第三端口，其中所述第一磁性单元至所述第三磁性单元的第三端口分别被配置为输出所述第一电压、所述第二电压和所述第三电压，所述计算电路还包括：
    第三负微分电阻，耦接在所述第一磁性单元至所述第三磁性单元的第一端口与第三端口之间；以及
    第四负微分电阻，耦接在所述第一磁性单元至所述第三磁性单元的第二端口与第三端口之间。
  10. 根据权利要求1至9中任一项所述的计算电路，其中，所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的宽度相同，并且所述第四磁性单元、所述第五磁性单元和所述第六磁性单元的长度依次增加。
  11. 一种电子设备，包括：
    印刷电路板；以及
    根据权利要求1至10中任一项所述的计算电路，所述计算电路设置在所述印刷电路板上。
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CN112581996A (zh) * 2020-12-21 2021-03-30 东南大学 基于磁性随机存储器的时域存内计算阵列结构
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