WO2022241630A1 - 环栅器件及其源漏制备方法、器件制备方法、电子设备 - Google Patents

环栅器件及其源漏制备方法、器件制备方法、电子设备 Download PDF

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Publication number
WO2022241630A1
WO2022241630A1 PCT/CN2021/094262 CN2021094262W WO2022241630A1 WO 2022241630 A1 WO2022241630 A1 WO 2022241630A1 CN 2021094262 W CN2021094262 W CN 2021094262W WO 2022241630 A1 WO2022241630 A1 WO 2022241630A1
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Prior art keywords
layer
source
drain
dummy gate
channel
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PCT/CN2021/094262
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English (en)
French (fr)
Inventor
刘桃
徐敏
张卫
汪大伟
王晨
陈鲲
杨静雯
孙新
潘哲成
吴春蕾
徐赛生
尹睿
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复旦大学
上海集成电路制造创新中心有限公司
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Priority to PCT/CN2021/094262 priority Critical patent/WO2022241630A1/zh
Publication of WO2022241630A1 publication Critical patent/WO2022241630A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductors, and in particular to a gate-all-around device, a source-drain preparation method thereof, a device preparation method, and electronic equipment.
  • a transistor device can be understood as a switch structure made of semiconductor materials, and one of the transistor devices is a gate-all-around device, which can also be understood as a GAA device or GAAFET. Among them, the full name of GAA is: Gate-All-Around, which means a wrap-around gate technology.
  • the source-drain silicon-germanium layer is epitaxially grown with the isolated silicon material extending from the side of the channel layer as the seed layer. Furthermore, epitaxy starts from multiple isolated surfaces, and the epitaxial SiGe crystal planes overlap between adjacent gates, which is easy to form stacking faults, resulting in stress relaxation. If it leads to complete relaxation, it will not be able to provide enough for the channel. stress.
  • the invention provides a gate-around device, its source and drain preparation method, the device preparation method, and electronic equipment to solve the problem of stress relaxation caused by stacking faults.
  • the present invention provides a source-drain preparation method of a gate-all-around device, comprising:
  • Fins are formed on the substrate, and dummy gate units across the fins are formed, the fins include alternately stacked preparatory channel layers and preparatory sacrificial layers; the number of the dummy gate units is multiple, many The dummy gate units are sequentially distributed along the channel direction of the preliminary channel layer;
  • Source and drain silicon germanium bulk layers Based on the seed layer, epitaxial source and drain silicon germanium bulk layers, and forming source and drain electrodes on the silicon germanium bulk layer.
  • the thickness of the seed layer is in the range of 2-10 nanometers.
  • etching away the part of the prepared sacrificial layer between two adjacent dummy gate stacks further include:
  • a first sidewall is formed on a designated side of the dummy gate unit; an orientation of the designated side of the dummy gate unit matches the channel direction.
  • etching and thinning the part of the prepared channel layer between two adjacent dummy gate units, and retaining part of the material of the channel layer as the seed layer it also includes:
  • a second sidewall is formed on a designated side of the preliminary sacrificial layer, and an orientation of the designated side of the prepared sacrificial layer matches the direction of the channel.
  • forming a fin on the substrate, and a dummy gate unit across the fin including:
  • the epitaxial layer includes alternately stacked epitaxial sacrificial layers and epitaxial channel layers;
  • etching the epitaxial layer and forming the fins further include:
  • An isolation oxide layer is formed on the remaining substrate on at least one side of the fin along the direction of the channel.
  • the material of the preliminary sacrificial layer is SiGe
  • the material of the preliminary channel layer is Si.
  • a device manufacturing method for a gate-all-around device including: the source-drain manufacturing method involved in the first aspect and its alternatives.
  • a gate-all-around device is provided, which is manufactured by using the device manufacturing method involved in the second aspect and its optional solutions.
  • an electronic device including the gate-all-around device related to the third aspect and alternative solutions thereof.
  • the seed layers can be respectively connected
  • the preparatory channel layer at the same level under the two dummy gate units effectively reduces the number of initial isolated surfaces for epitaxial SiGe bulk layer epitaxy of the source and drain, and there is no merging of epitaxial SiGe materials between the two dummy gates , reducing or even eliminating the stacking faults in the vertical direction, and the stacking faults are the most important dislocations that affect the channel stress imposed by the source and drain.
  • the present invention can effectively solve the stress relaxation problem caused by the epitaxy of germanium and silicon bulk layers of source and drain merged between dummy gates.
  • Fig. 1 is a principle schematic diagram 1 of a germanium-silicon bulk layer different from an epitaxial source and drain in a scheme of the present invention
  • Fig. 2 is a schematic diagram 2 of the principle of the silicon germanium layer of the epitaxial source and drain in a scheme different from that of the present invention
  • Fig. 3 is a schematic diagram three of the principle of the silicon germanium layer of the epitaxial source and drain in a scheme different from that of the present invention
  • Fig. 4 is a schematic flow diagram 1 of a source-drain preparation method of a gate-all-around device in an embodiment of the present invention
  • FIG. 5 is a schematic flow diagram II of a source-drain preparation method of a gate-all-around device in an embodiment of the present invention
  • FIG. 6 is a schematic flow chart of step S11 in an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram after step S114 in an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram after step S115 in an embodiment of the present invention.
  • Fig. 9 is a schematic structural diagram after step S15 in an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram after step S12 in an embodiment of the present invention.
  • Fig. 11 is a schematic structural diagram after step S16 in an embodiment of the present invention.
  • Fig. 12 is a schematic structural diagram after step S13 in an embodiment of the present invention.
  • FIG. 13 is a schematic structural view after forming a silicon-germanium layer in step S14 in an embodiment of the present invention.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • a plurality means a plurality, such as two, three, four, etc., unless otherwise specifically defined.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • SiGe source-drain that is, source-drain germanium-silicon bulk layer
  • selective epitaxy technology can provide effective compressive stress for the channel, thereby improving the mobility of holes in the PMOS device, thereby matching the mobility of electrons and improving the overall performance.
  • the channel stress technology based on SiGe source and drain that is, the germanium silicon bulk layer of the source and drain
  • SiGe source and drain that is, the germanium silicon bulk layer of the source and drain
  • the silicon germanium silicon The principle of body layer is described.
  • the epitaxy of SiGe source and drain (ie source and drain silicon germanium bulk layer 302 ) on a gate-all-around device (ie GAAFET device) starts from multiple isolated surfaces (isolated surfaces refer to the channel layer drain from the source part of the drain), the epitaxial structure of a certain silicon germanium material on an isolated surface can be shown in FIG.
  • the source-drain SiGe bulk layer 302 may have a structure as shown in FIG. 3 , where the epitaxial SiGe crystal planes overlap between adjacent gates, and stacking faults are easily formed to cause stress relaxation.
  • the structure before the epitaxial SiGe source and drain (that is, the germanium silicon bulk layer of the source and drain), the structure has a plurality of mutually isolated SiGe epitaxy starting surfaces (that is, the isolated surface 301).
  • the SiGe materials grown on the initial surface merge with each other, and may form a large number of stacking faults, which will cause the stress relaxation of the SiGe source and drain (that is, the germanium silicon bulk layer of the source and drain). provide sufficient stress.
  • the source-drain preparation method of a gate-all-around device including:
  • the fins include alternately stacked preparatory channel layers 203 and preparatory sacrificial layers 202; in the illustrated example, only
  • the structure of the fin is not limited to the above prepared channel layer 203 and prepared sacrificial layer 202 .
  • the material of the preliminary sacrificial layer is SiGe, and the material of the preliminary channel layer is Si.
  • the thicknesses of the preparation channel layers may be the same or different, and the thicknesses of the preparation sacrificial layers may be the same or different.
  • the materials of the prepared sacrificial layer and the prepared channel layer can also be changed arbitrarily according to requirements, and meanwhile, the thicknesses of the prepared sacrificial layer and the prepared channel layer can also be changed arbitrarily according to requirements.
  • the number of the dummy gate units 206 is multiple, and the dummy gate units 206 are distributed sequentially along the channel direction of the prepared channel layer, and the channel direction can be, for example, the left-right direction shown in FIG. 8 .
  • the dummy gate unit can use a metal gate material, specifically, different metal gate materials can be used according to the type of ions doped in the corresponding region.
  • the dummy gate unit 206 can be fabricated based on the dummy gate stack 205 mentioned later (ie shown in FIG. 7 ).
  • step S11 may include:
  • the structure etched in step S12 may be as shown in FIG. 10 , at this time, along the direction of the channel, the prepared sacrificial layers 202 are spaced apart from each other.
  • step S13 The structure etched in step S13 can be shown, for example, in FIG. 12 .
  • both ends of the seed layer 209 are respectively connected to the preparatory channel layer 203 of the same level.
  • the seed layer 209 can be understood as the remaining part after etching and thinning part of the preliminary channel layer 203.
  • its thickness can be uniform or non-uniform.
  • a gradient portion with a gradually changing thickness may be formed between the layer 209 and the preliminary channel layer 203, and the thicknesses of different seed layers 209 may be the same or different, as long as the same-level preliminary channel layer is realized through the seed layer 209.
  • the connection between 203 does not depart from the scope of the embodiment of the present invention.
  • the thickness of the seed layer is in the range of 2-10 nanometers.
  • step S13 may include:
  • S14 based on the seed layer, epitaxial source and drain silicon germanium bulk layers, and forming source and drain electrodes on the silicon germanium bulk layer.
  • the structure after forming the SiGe bulk layer 210 in step S14 may be shown in FIG. 13 , for example.
  • any manner of forming the source and the drain does not depart from the scope of the embodiments of the present invention.
  • the present invention can effectively solve the problem of stress relaxation caused by the epitaxy of the SiGe bulk layer of the source and drain being merged between the dummy gates.
  • step S12 it may also include;
  • the structure after step S15 may, for example, be as shown in FIG. 9 , wherein the first sidewall 207 may cover the sides of the left and right sides of the dummy gate unit 206 (that is, the corresponding designated side), and the orientation of the designated side of the dummy gate unit matched to the channel direction.
  • the channel direction can be understood as the left-right direction shown in FIG. 9 .
  • step S13 it may also include:
  • the structure after step S16 may, for example, be as shown in FIG. 11 , wherein the second side wall 208 may cover the sides on the left and right sides of the preparatory sacrificial layer 202 (that is, the corresponding designated side), and the orientation of the designated side of the preparatory sacrificial layer matches that of the channel direction.
  • the channel direction can be understood as the left-right direction shown in FIG. 11 .
  • the above-mentioned sidewalls can be characterized as Spacer, through which the sidewall can provide protection for the subsequent etching step, and avoid the etching process from affecting the corresponding preparation channel.
  • step S11 may specifically include:
  • the epitaxial layer includes alternately stacked epitaxial sacrificial layers and epitaxial channel layers;
  • S112 Etching the epitaxial layer and the substrate to form the fins
  • S114 Forming a dummy gate stack straddling the epitaxial layer on the substrate and the fin.
  • the structure after processing in step S114 may be as shown in FIG. 7 , for example.
  • the dummy gate stack 205 can be understood as a gate stack without electrical function, which provides a consistent process environment (such as a consistent shape) on the surface of the GAA transistor structure. Further, in the subsequent manufacturing process, an effective An electrically functional gate replaces the dummy gate stack.
  • step S114 may also include:
  • step S112 it may also include:
  • S113 forming an isolation oxide layer on the remaining substrate on at least one side of the fin along the direction of the channel.
  • the isolation oxide layer 204 can also be characterized as an STI oxide layer, wherein the STI is specifically: Shallow Trench Isolation, and further, can be understood as shallow trench isolation.
  • the SiGe preliminary sacrificial layer (as shown in FIG. 10 ) can be selectively etched, and then the second sidewall 208 (as shown in FIG. 10 ) can be formed.
  • Figure 11 the preliminary channel layer is etched, which can be understood as the etching and thinning of Si nanosheets (as shown in Figure 12), as the starting surface for the epitaxy of SiGe source and drain (that is, the germanium silicon bulk layer of source and drain) .
  • the part between the dummy gate units 206 on the substrate 201 and the gap surrounded by the adjacent two preliminary channel layers 203 and the adjacent two dummy gates 206 can also be filled.
  • the insulating layer (for example, can be filled with SiO 2 ), and the insulating layer is etched and thinned to a specified thickness (for example, a thickness less than 5 nm), so as to suppress the conduction of the bottom parasitic transistor.
  • the number of starting surfaces for SiGe source-drain (that is, the germanium-silicon bulk layer of source-drain) epitaxy is reduced, and there is no merging of epitaxial SiGe between two gates, which reduces the vertical direction.
  • Stacking faults this is the most important dislocation that affects the channel stress imposed by the source and drain.
  • the merged epitaxy between SiGe sources and drains starting from different Si channels may cause stacking faults in the horizontal direction of their overlapping positions, but it will not seriously affect the stress exerted by the SiGe sources and drains on the channel. Therefore, the specific solution of the embodiment of the present invention can effectively solve the stress relaxation problem caused by the epitaxial merging of the SiGe source and drain (ie, the SiGe bulk layer of the source and drain).
  • An embodiment of the present invention also provides a device manufacturing method for a gate-all-around device, including: the source-drain manufacturing method involved in the above optional solution.
  • An embodiment of the present invention also provides a gate-all-around device, which is manufactured by using the device manufacturing method involved in the above optional solution.
  • An embodiment of the present invention also provides an electronic device, including the gate-all-around device involved in the above optional solution.

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Abstract

本发明提供了一种环栅器件及其源漏制备方法、器件制备方法、电子设备，其中，环栅器件的源漏制备方法，包括：在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元，所述鳍片包括交替层叠的预备沟道层与预备牺牲层；所述伪栅极单元的数量为多个，多个所述伪栅极单元沿所述预备沟道层的沟道方向依次分布；刻蚀掉相邻两个伪栅极单元之间的预备牺牲层部分；对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层；基于所述种子层，外延源漏的锗硅体层，并在所述锗硅体层形成源极与漏极。

Description

环栅器件及其源漏制备方法、器件制备方法、电子设备 技术领域
本发明涉及领域半导体领域，尤其涉及一种环栅器件及其源漏制备方法、器件制备方法、电子设备。
背景技术
晶体管器件，可理解为用半导体材料制作的开关结构，其中一种晶体管器件为环栅器件，也可理解为GAA器件、GAAFET。其中，GAA的全称为：Gate-All-Around，表示一种环绕式栅极技术。
现有相关技术中，GAAFET器件上SiGe源漏外延的方案中，如图1所示，源漏的锗硅体层是以沟道层侧面延伸出的孤立的硅材料为种子层外延生长的，进而，外延起始于多个孤立表面，相邻栅极之间外延的SiGe晶面交叠，容易形成层错，从而造成应力弛豫，若导致完全弛豫，则无法给沟道提供足够的应力。
发明内容
本发明提供一种环栅器件及其源漏制备方法、器件制备方法、电子设备，以解决层错而造成的应力弛豫的问题。
本发明提供给了一种环栅器件的源漏制备方法，包括：
在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元，所述鳍片包括交替层叠的预备沟道层与预备牺牲层；所述伪栅极单元的数量为多个，多个所述伪栅极单元沿所述预备沟道层的沟道方向依次分布；
刻蚀掉相邻两个伪栅极单元之间的预备牺牲层部分；
对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层；
基于所述种子层，外延源漏的锗硅体层，并在所述锗硅体层形成源极与漏极。
可选的，所述种子层的厚度处于2-10纳米的区间范围内。
可选的，刻蚀掉相邻两个伪栅极堆叠件之间的预备牺牲层部分之前，还包括：
在所述伪栅极单元的指定侧面形成第一侧壁；所述伪栅极单元的指定侧面的朝向匹配于所述沟道方向。
可选的，对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层之前，还包括：
在所述预备牺牲层的指定侧面形成第二侧壁，所述预备牺牲层的指定侧面的朝向匹配于所述沟道方向。
可选的，在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元，包括：
在所述基底上形成所述外延层；所述外延层包括交替层叠的外延牺牲层与外延沟道层；
对所述外延层与所述基底进行刻蚀，形成所述鳍片；
在所述基底与所述鳍片上形成横跨所述外延层的伪栅极堆叠件；
图案化所述伪栅极堆叠件，得到所述伪栅极单元。
可选的，对所述外延层进行刻蚀，形成所述鳍片之后，还包括：
在所述鳍片沿所述沟道方向的至少一侧的剩余基底上制作隔离氧化层。
可选的，所述预备牺牲层的材料为SiGe，所述预备沟道层的材料为Si。
根据本发明的第二方面，提供了一种环栅器件的器件制备方法，包括：第一方面及其可选方案涉及的源漏制备方法。
根据本发明的第三方面，提供了一种环栅器件，采用第二方面及其可选方案涉及的器件制备方法制备而成。
根据本发明的第四方面，提供了一种电子设备，包括第三方面及其可选方案涉及的环栅器件。
本发明提供的环栅器件及其源漏制备方法、器件制备方法、电子设备中，通过对预备沟道层进行刻蚀减薄并保留部分沟道层材料作为种子层，可保障种子层分别连接两个伪栅极单元下同层级的预备沟道层，有效减少了源漏的锗硅体层外延的起始孤立表面数目，并且，不存在两个伪栅极之间外延锗硅材料的合并，减少甚至消除了竖直方向上的层错，而该层错恰是影响源漏施加给沟道应力最为主要的位错。进而，本发明能够有效解决由于源漏的锗硅 体层外延在伪栅极之间合并所造成的应力弛豫问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是区别于本发明的一种方案中外延源漏的锗硅体层的原理示意图一；
图2是区别于本发明的一种方案中外延源漏的锗硅体层的原理示意图二；
图3是区别于本发明的一种方案中外延源漏的锗硅体层的原理示意图三；
图4是本发明一实施例中环栅器件的源漏制备方法的流程示意图一；
图5是本发明一实施例中环栅器件的源漏制备方法的流程示意图二；
图6是本发明一实施例中步骤S11的流程示意图；
图7是本发明一实施例中步骤S114之后的结构示意图；
图8是本发明一实施例中步骤S115之后的结构示意图；
图9是本发明一实施例中步骤S15之后的结构示意图；
图10是本发明一实施例中步骤S12之后的结构示意图；
图11是本发明一实施例中步骤S16之后的结构示意图；
图12是本发明一实施例中步骤S13之后的结构示意图；
图13是本发明一实施例中步骤S14中形成锗硅体层之后的结构示意图；
附图标记说明：
301-孤立表面；
302-锗硅体层；
201-基底；
202-预备牺牲层；
203-预备沟道层；
204-隔离氧化层；
205-伪栅极堆叠件；
206-伪栅极单元；
207-第一侧壁；
208-第二侧壁；
209-种子层；
210-锗硅体层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明说明书的描述中，需要理解的是，术语“上部”、“下部”、“上端”、“下端”、“下表面”、“上表面”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明说明书的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本发明的描述中，“多个”的含义是多个，例如两个，三个，四个等，除非另有明确具体的限定。
在本发明说明书的描述中，除非另有明确的规定和限定，术语“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
SiGe源漏(即源漏的锗硅体层)选择性外延技术能够为沟道提供有效的压应力，从而提升PMOS器件中空穴的迁移率，从而达到与电子迁移率的匹配，提升整体性能。在先进节点的GAAFET器件中，基于SiGe源漏(即源漏的锗硅体层)的沟道应力技术对器件性能的提升不可或缺。
为便于说明本发明实施例提供的环栅器件及其源漏制备方法、器件制备方法、电子设备，以下将结合图1与图2对区别于本发明的一种方案中外延源漏的锗硅体层的原理进行描述。
请参考图1至图3，环栅器件(即GAAFET器件)上SiGe源漏(即源漏的锗硅体层302)外延起始于多个孤立表面(孤立表面指的沟道层漏出于源漏的部分)，在孤立表面外延一定锗硅材料的结构可例如图1所示，此时外延生长的部分锗硅由多个孤立表面301向外延伸，进一步外延后的结构可例如图2所示，源漏的锗硅体层302成型后的结构可例如图3所示，其中，相邻栅极之间外延的SiGe晶面交叠，容易形成层错从而造成应力弛豫。
具体来说，在外延SiGe源漏(即源漏的锗硅体层)之前，结构具有多个相互孤立的SiGe外延起始表面(即孤立表面301)，随着外延厚度增加，由这些外延起始表面生长的SiGe材料相互合并，并可能形成大量的层错，从而造成SiGe源漏(即源漏的锗硅体层)应力弛豫，最严重可导致完全弛豫，从而无法给硅的沟道提供足够的应力。
为解决以上问题，本发明实施例中，请参考图4，环栅器件的源漏制备方法，包括：
S11：在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元。
经步骤S11处理后的结构可例如图8所示，在基底201上，所述鳍片包括交替层叠的预备沟道层203与预备牺牲层202；在图示的举例中，鳍片中仅显示了预备沟道层203与预备牺牲层202，在其他举例中，鳍片的结构可不限于以上预备沟道层203与预备牺牲层202。
一种举例中，所述预备牺牲层的材料为SiGe，所述预备沟道层的材料为Si。各预备沟道层的厚度可以是相同的，也可以是不同的，各预备牺牲层 的厚度可以是相同的，也可以是不同的。其他举例中，预备牺牲层、预备沟道层的材料也可根据需求任意变化，同时，预备牺牲层、预备沟道层的厚度也可根据需求任意变化。
所述伪栅极单元206的数量为多个，多个所述伪栅极单元206沿所述预备沟道层的沟道方向依次分布，该沟道方向可例如图8所示的左右方向。伪栅极单元可采用金属栅材料，具体的，可以根据对应区参杂的离子的类型，采用不同的金属栅材料。伪栅极单元206可基于后文所提及的(即图7所示的)伪栅极堆叠件205制作而成。
步骤S11之后，可包括：
S12：刻蚀掉相邻两个伪栅极单元之间的预备牺牲层部分。
S13：对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层，所述种子层分别连接相邻两个伪栅极单元下同层级的沟道层。
经步骤S12刻蚀后的结构可例如图10所示，此时，沿沟道方向，预备牺牲层202之间相间隔。
经步骤S13刻蚀后的结构可例如图12所示，此时，沿沟道方向，种子层209的两端分别连接同层级的预备沟道层203。
其中的种子层209，可理解为是对部分预备沟道层203进行刻蚀减薄之后剩余的部分，单个种子层209中，其厚度可以是均匀不变的，也可以是非均匀的，在种子层209与预备沟道层203之间可形成有厚度渐变的渐变部分，不同种子层209的厚度可以是相同的，也可以是不相同的，只要通过种子层209实现了同层级预备沟道层203之间的连接，就不脱离本发明实施例的范围。
其中一种实施方式中，所述种子层的厚度处于2-10纳米的区间范围内。
步骤S13之后，可包括：
S14：基于所述种子层，外延源漏的锗硅体层，并在所述锗硅体层形成源极与漏极。
步骤S14中形成锗硅体层210之后的结构可例如图13所示。在锗硅体层210的基础上，任意形成源极与漏极的方式，均不脱离本发明实施例的范 围。
可见，以上方案中，通过对预备沟道层进行刻蚀并保留部分沟道层材料作为种子层，保障了种子层分别连接两个伪栅极单元下同层级的预备沟道层，有效减少了源漏的锗硅体层外延的起始孤立表面数目，并且，不存在两个伪栅极之间外延锗硅材料的合并，减少甚至消除了竖直方向上的层错，而该层错恰是影响源漏施加给沟道应力最为主要的位错。进而，本发明能够有效解决由于源漏的锗硅体层外延在伪栅极之间合并所造成的应力弛豫问题。
其中一种实施方式中，请参考图5，步骤S12之前，还可包括；
S15:在所述伪栅极单元的指定侧面形成第一侧壁。
步骤S15之后的结构可例如图9所示，其中的第一侧壁207可覆盖伪栅极单元206左右两侧的侧面(即对应的指定侧面)，所述伪栅极单元的指定侧面的朝向匹配于所述沟道方向。该沟道方向可理解为图9所示的左右方向。
其中一种实施方式中，请参考图5，步骤S13之前，还可包括：
S16：在所述预备牺牲层的指定侧面形成第二侧壁。
步骤S16之后的结构可例如图11所示，其中的第二侧壁208可覆盖预备牺牲层202左右两侧的侧面(即对应的指定侧面)，所述预备牺牲层的指定侧面的朝向匹配于所述沟道方向。该沟道方向可理解为图11所示的左右方向。
以上所涉及的侧壁(包括以上第一侧壁207与第二侧壁208)可表征为Spacer，通过侧壁，可以为后续的刻蚀步骤提供保护，避免刻蚀过程对相应的预备沟道层、预备牺牲层产生影响，此外还可以保证器件的栅极与源漏之间的电学隔离。
其中一种实施方式中，请参考图6，步骤S11具体可以包括：
S111：在所述基底上形成所述外延层；
所述外延层包括交替层叠的外延牺牲层与外延沟道层；
S112：对所述外延层与所述基底进行刻蚀，形成所述鳍片；
S114：在所述基底与所述鳍片上形成横跨所述外延层的伪栅极堆叠件。
经步骤S114处理之后的结构，可例如图7所示。
其中的伪栅极堆叠件205，可理解为没有电功能的栅极堆叠件，提供 GAA晶体管结构表面的一致工艺环境(例如一致的形貌)，进一步地，在后续制造工艺中，可以采用有电功能的栅极替代伪栅极堆叠件。
请参考图6，步骤S114之后，还可包括：
S115：图案化所述伪栅极堆叠件，得到所述伪栅极单元。
部分举例中，步骤S112之后，还可包括：
S113：在所述鳍片沿所述沟道方向的至少一侧的剩余基底上制作隔离氧化层。
其中的隔离氧化层204，也可表征为STI氧化层，其中的STI具体为：Shallow Trench Isolation，进而，可理解为浅槽隔离。
可见，在具体方案中，可在伪栅极单元206和第一侧壁207形成之后，选择性刻蚀了SiGe的预备牺牲层(如图10所示)，再形成第二侧壁208(如图11所示)。然后对预备沟道层进行刻蚀，其可理解为刻蚀Si的纳米片刻蚀减薄(如图12所示)，作为SiGe源漏(即源漏的锗硅体层)外延的起始表面。部分举例中，在形成图12的结构之后，还可在基底201上伪栅极单元206之间的部分以及相邻两预备沟道层203与相邻两伪栅极206围成的间隙内填充绝缘层(例如可填充SiO 2)，并对绝缘层进行刻蚀减薄至指定厚度(例如小于5nm的厚度)，从而可抑制底部寄生晶体管的导通。
在这一方案中，SiGe源漏(即源漏的锗硅体层)外延的起始表面的个数减少，并且不存在两个栅极之间外延SiGe的合并，减少了竖直方向上的层错(这是影响源漏施加给沟道应力最为主要的位错)。而起始于不同Si沟道的SiGe源漏之间的合并外延，可能会在它们交叠位置水平方向上产生层错，但对SiGe源漏给沟道施加的应力不会造成严重影响。因此，本发明实施例的具体方案能够有效解决由于SiGe源漏(即源漏的锗硅体层)外延合并所造成的应力弛豫问题。
本发明实施例还提供了一种环栅器件的器件制备方法，包括：以上可选方案涉及的源漏制备方法。
本发明实施例还提供了一种环栅器件，采用以上可选方案涉及的器件制备方法制备而成。
本发明实施例还提供了一种电子设备，包括以上可选方案涉及的环栅器件。
在本说明书的描述中，参考术语“一种实施方式”、“一种实施例”、“具体实施过程”、“一种举例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

  1. 一种环栅器件的源漏制备方法，其特征在于，包括：
    在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元，所述鳍片包括交替层叠的预备沟道层与预备牺牲层；所述伪栅极单元的数量为多个，多个所述伪栅极单元沿所述预备沟道层的沟道方向依次分布；
    刻蚀掉相邻两个伪栅极单元之间的预备牺牲层部分；
    对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层；
    基于所述种子层，外延源漏的锗硅体层，并在所述锗硅体层形成源极与漏极。
  2. 根据权利要求1所述的环栅器件的源漏制备方法，其特征在于，所述种子层的厚度处于2-10纳米的区间范围内。
  3. 根据权利要求1所述的环栅器件的源漏制备方法，其特征在于，刻蚀掉相邻两个伪栅极堆叠件之间的预备牺牲层部分之前，还包括：
    在所述伪栅极单元的指定侧面形成第一侧壁；所述伪栅极单元的指定侧面的朝向匹配于所述沟道方向。
  4. 根据权利要求1所述的环栅器件的源漏制备方法，其特征在于，
    对相邻两个伪栅极单元之间的预备沟道层部分进行刻蚀减薄，并保留部分沟道层材料作为种子层之前，还包括：
    在所述预备牺牲层的指定侧面形成第二侧壁，所述预备牺牲层的指定侧面的朝向匹配于所述沟道方向。
  5. 根据权利要求1至4任一项所述的环栅器件的源漏制备方法，其特征在于，
    在基底上形成鳍片，以及横跨所述鳍片的伪栅极单元，包括：
    在所述基底上形成所述外延层；所述外延层包括交替层叠的外延牺牲层与外延沟道层；
    对所述外延层与所述基底进行刻蚀，形成所述鳍片；
    在所述基底与所述鳍片上形成横跨所述外延层的伪栅极堆叠件；
    图案化所述伪栅极堆叠件，得到所述伪栅极单元。
  6. 根据权利要求5所述的环栅器件的源漏制备方法，其特征在于，
    对所述外延层进行刻蚀，形成所述鳍片之后，还包括：
    在所述鳍片沿所述沟道方向的至少一侧的剩余基底上制作隔离氧化层。
  7. 根据权利要求1至4任一项所述的环栅器件的源漏制备方法，其特征在于，所述预备牺牲层的材料为SiGe，所述预备沟道层的材料为Si。
  8. 一种环栅器件的器件制备方法，其特征在于，包括：权利要求1至6任一项所述的源漏制备方法。
  9. 一种环栅器件，其特征在于，采用权利要求7所述的器件制备方法制备而成。
  10. 一种电子设备，其特征在于，包括权利要求9所述的环栅器件。
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