WO2022236680A1 - 显示面板及其制备方法、显示触控装置 - Google Patents

显示面板及其制备方法、显示触控装置 Download PDF

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Publication number
WO2022236680A1
WO2022236680A1 PCT/CN2021/093055 CN2021093055W WO2022236680A1 WO 2022236680 A1 WO2022236680 A1 WO 2022236680A1 CN 2021093055 W CN2021093055 W CN 2021093055W WO 2022236680 A1 WO2022236680 A1 WO 2022236680A1
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Prior art keywords
line
display
sub
area
layer
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PCT/CN2021/093055
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English (en)
French (fr)
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WO2022236680A9 (zh
Inventor
高文辉
徐鹏
张顺
张跳梅
张锴
蒋志亮
王领然
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001110.8A priority Critical patent/CN115605832A/zh
Priority to US17/762,093 priority patent/US20240111376A1/en
Priority to DE112021004795.7T priority patent/DE112021004795T5/de
Priority to PCT/CN2021/093055 priority patent/WO2022236680A1/zh
Publication of WO2022236680A1 publication Critical patent/WO2022236680A1/zh
Publication of WO2022236680A9 publication Critical patent/WO2022236680A9/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0444—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single conductive element covering the whole sensing surface, e.g. by sensing the electrical current flowing at the corners
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds

Definitions

  • This article relates to but not limited to the field of display technology, especially a display panel, a manufacturing method thereof, and a display touch device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display touch device.
  • an embodiment of the present disclosure provides a display panel, including: a base substrate, a display structure layer, a touch control structure layer, at least one first power line, at least one first display signal line, and at least one first touch signal line Wire.
  • the base substrate includes a display area, a wire lead-out area located on one side of the display area, and a signal access area, and the wire lead-out area is located between the display area and the signal access area.
  • the display structure layer and the touch structure layer are located in the display area, and the touch structure layer is arranged on a side of the display structure layer away from the base substrate.
  • At least one first power line, at least one first touch signal line, and at least one first display signal line are located in the wiring lead-out area.
  • the first power line is connected to the display structure layer, the first display signal line is connected to the display structure layer, and the first touch signal line is connected to the touch structure layer.
  • the first touch signal line is located on a side of the first power line away from the base substrate, and the first display signal line is located on a side of the first power line close to the base substrate.
  • the orthographic projection of the first touch signal line on the base substrate at least partially overlaps the orthographic projection of the first power supply line on the base substrate.
  • the orthographic projection of the first touch signal line on the base substrate does not overlap with the orthographic projection of the first display signal line on the base substrate.
  • the orthographic projection of the first touch signal line on the base substrate is located within the orthographic projection of the first power supply line on the base substrate.
  • the base substrate further includes: a bending region.
  • the wire lead-out area includes: a first wire lead-out area and a second wire lead-out area arranged in sequence along a direction away from the display area; the bending area is located between the first wire lead-out area and the second wire lead-out area Between the two routing lead-out areas.
  • the bending area includes: at least one first power connection line, at least one touch signal connection line, and at least one display signal connection line arranged on the base substrate.
  • the first power connection line, the touch signal connection line and the display signal connection line have the same layer structure, and the first power connection line is located between the touch signal connection line and the display signal connection line.
  • the first touch signal line in the wire lead-out area includes: a first sub-touch signal line located in the first wire lead-out area, a sub-touch signal line located in the second wire lead-out area The second sub-touch signal line.
  • the first display signal line in the routing lead-out area includes: a first sub-display signal line located in the first routing-out area, and a second sub-display signal line in the second routing-out area.
  • the touch signal connection line is connected to the first sub-touch signal line and the second sub-touch signal line;
  • the display signal connection line is connected to the first sub-display signal line and the second sub-display signal line ;
  • the first sub-touch signal line and the second sub-touch signal line are located on the side of the touch signal connection line away from the base substrate, and the first sub-display signal line and the second sub-display signal line
  • the wire is located on a side of the display signal connection wire close to the base substrate.
  • the first power supply line in the routing area includes: a first sub-power line located in the first routing area, a second sub-power line located in the second routing area A power line; the first power connection line is connected to the first sub-power line and the second sub-power line; the first sub-power line, the first power connection line and the second sub-power line are integrated.
  • the first power connection lines, the touch signal connection lines and the display signal connection lines in the bending area all extend along the first direction.
  • at least one display signal connection line, at least one first power supply connection line, at least one touch signal connection line, at least one first power supply connection line and at least one display signal connection line are sequentially arranged in the bending area. connection line.
  • the first direction and the second direction are located in the same plane, and the first direction is perpendicular to the second direction.
  • the display structure layer at least includes: a driving circuit layer disposed on the base substrate; the driving circuit layer at least includes: an active layer disposed on the base substrate, The first gate metal layer, the second gate metal layer and the source-drain metal layer.
  • the first power connection line, the touch signal connection line and the display signal connection line in the bending area are in the same layer structure as the source-drain metal layer in the display area.
  • the at least one first display signal line in the wiring lead-out area and the first gate metal layer or the second gate metal layer in the display area are in the same layer structure.
  • the touch structure layer at least includes a touch electrode layer.
  • the at least one first touch signal line in the wiring lead-out area and the touch electrode layer in the display area are of the same layer structure.
  • the first power line in the wiring lead-out area and the source-drain metal layer in the display area are in the same layer structure.
  • the wiring lead-out area further includes: at least one second power supply line.
  • the bending area further includes: at least one second power connection line provided on the base substrate.
  • the second power supply line in the wiring lead-out area includes: a third sub-power supply line located in the first wiring lead-out area and a fourth sub-power supply line located in the second wiring lead-out area.
  • the second power connection line is connected to the third sub-power line and the fourth sub-power line.
  • the second power connection line is located on a side of the display signal connection line away from the first power connection line.
  • the wiring lead-out area includes: a plurality of first display signal lines.
  • the multiple first display signal lines are divided into a first group of first display signal lines and a second group of first display signal lines; the orthographic projection of at least one first touch signal line on the base substrate is located at the first Between the orthographic projections of the first group of display signal lines and the second group of first display signal lines on the base substrate.
  • the plurality of first display signal lines in the wiring lead-out area include: at least one first data lead-out line, and at least one first drive control signal line; the first drive control signal line is The orthographic projection on the base substrate is adjacent to the orthographic projection of the first touch signal line on the base substrate.
  • the display structure layer includes at least one light-emitting element
  • the light-emitting element includes: a first electrode, a second electrode, and an organic light-emitting layer between the first electrode and the second electrode;
  • the first electrode is located on a side of the second electrode close to the base substrate.
  • the base substrate also includes: a first frame area located between the display area and the wiring lead-out area; the first frame area is provided with a display control circuit and at least one second touch signal line;
  • the second touch signal line is connected to the first touch signal line in the wiring lead-out area.
  • the orthographic projection of the second touch signal line on the base substrate is located within the orthographic projection of the second electrode on the base substrate.
  • the first power line is a high voltage power line.
  • the signal access area is provided with a touch and display driver integration (TDDI) circuit; line connection.
  • TDDI touch and display driver integration
  • an embodiment of the present disclosure provides a display touch device, including the above-mentioned display panel.
  • an embodiment of the present disclosure provides a method for manufacturing a display panel, including: sequentially forming a display structure layer and a touch structure layer in the display area of the base substrate, The wire lead-out area between the wire lead-out areas forms the first power line, at least one first touch signal line and at least one first display signal line.
  • the first power line and the first display signal line are connected to the display structure layer, and the first touch signal line is connected to the touch structure layer.
  • the first touch signal line is located on the side of the first power line away from the base substrate, and the first display signal line is located on the side of the first power line close to the base substrate;
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • FIG. 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an arrangement of touch electrodes of a display panel according to at least one embodiment of the present disclosure
  • Fig. 3 is a partial cross-sectional schematic diagram along the R-R direction in Fig. 1;
  • Fig. 4 is a partial schematic diagram of area S1 in Fig. 1;
  • FIG. 5 is a schematic diagram of a second wiring layer formed in the wiring lead-out area of at least one embodiment of the present disclosure
  • 6A is a schematic diagram of a third wiring layer formed in the wiring lead-out area and the bending area of at least one embodiment of the present disclosure
  • 6B is a schematic diagram of a third wiring layer formed by a wiring lead-out area and a bending area according to at least one embodiment of the present disclosure
  • FIG. 7A is a schematic diagram of touch signal lines formed in the wiring lead-out area of at least one embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of touch signal lines formed in the wiring lead-out area of at least one embodiment of the present disclosure.
  • Fig. 8 is a partial cross-sectional schematic diagram along the P-P direction in Fig. 4;
  • FIG. 9 is a schematic diagram of second electrodes shielding touch signal lines according to at least one embodiment of the present disclosure.
  • Fig. 10 is another partial cross-sectional schematic diagram along the P-P direction in Fig. 4;
  • FIG. 11 is another structural schematic diagram of a display area of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 12 is a partial plan view of a touch structure layer of a display panel according to at least one embodiment of the present disclosure
  • FIG. 13 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 14 is another schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • Fig. 15 is a partial schematic diagram of area S2 in Fig. 14;
  • FIG. 16 is a schematic diagram of a display touch device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the means and contents can be changed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • connection includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected constituent elements.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • the display panel provided by the embodiments of the present disclosure can integrate a touch structure.
  • the display panel may include a liquid crystal display (LCD) substrate, or may be an organic light emitting diode (OLED) display substrate, or may be a plasma display device (PDP) display substrate, or may be an electrophoretic display (EPD) display substrate.
  • the display panel may include an OLED display substrate, and the OLED display substrate may include: a base substrate, a driving circuit layer disposed on the base substrate, a light emitting element layer disposed on the driving circuit layer, and a light emitting element layer disposed on the on the encapsulation layer.
  • the touch structure is set on the packaging layer of the display substrate to form a structure of the touch structure on the thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE).
  • Touch on TFE a structure of the touch structure on the thin film encapsulation
  • the Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure.
  • the FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode.
  • the integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode.
  • the FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode, and the integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.
  • At least one embodiment of the present disclosure provides a display panel, including: a base substrate, a display structure layer, a touch structure layer, at least one first power line, at least one first display signal line, and at least one first touch signal line .
  • the base substrate includes: a display area, a wire lead-out area and a signal access area located on one side of the display area.
  • the wire lead-out area is located between the display area and the signal access area.
  • the display structure layer and the touch structure layer are located in the display area, and the touch structure layer is arranged on the side of the display structure layer away from the base substrate.
  • At least one first power supply line, at least one first touch signal line and at least one first display signal line are located in the wiring lead-out area.
  • the first power line is connected to the display structure layer, the first display signal line is connected to the display structure layer, and the first touch signal line is connected to the touch structure layer.
  • the first touch signal line is located on a side of the first power line away from the base substrate, and the first display signal line is located on a side of the first power line close to the base substrate.
  • the orthographic projection of the first touch signal line on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the first touch signal line and the first display signal line are isolated by the first power line in the lead-out region. Since the first power line transmits a DC signal, and the DC signal cannot pass through the plate capacitance structure formed between the film layers, the use of the first power line can reduce the signal interference between the first touch signal line and the first display signal line , thereby improving display and touch effects.
  • the orthographic projection of the first touch signal line on the base substrate does not overlap with the orthographic projection of the first display signal line on the base substrate.
  • the overlapping of the first touch signal line and the first display signal line in a direction perpendicular to the base substrate to form a capacitive structure can be avoided, and the influence of signal crosstalk can be reduced, thereby improving display and touch effects.
  • the orthographic projection of the first touch signal line on the base substrate is located within the orthographic projection of the first power supply line on the base substrate. In this exemplary embodiment, the orthographic projection of the first touch signal line on the base substrate is covered by the orthographic projection of the first power line on the base substrate, so that the first touch signal line and the The signal crosstalk generated between the first display signal lines improves display and touch effects.
  • the base substrate may further include: a bending region.
  • the wire lead-out area includes: a first wire lead-out area and a second wire lead-out area arranged in sequence along a direction away from the display area.
  • the bending area is located between the first routing area and the second routing area.
  • the bending area includes: at least one first power connection line, at least one touch signal connection line and at least one display signal connection line arranged on the base substrate.
  • the first power connection line, the touch signal connection line and the display signal connection line have the same layer structure, and the first power connection line is located between the touch signal connection line and the display signal connection line.
  • the first power connection line is used in the bending area to separate the touch signal connection line from the display signal connection line, which can reduce the signal interference between the display signal connection line and the touch signal connection line , thereby improving display and touch effects.
  • the first touch signal line in the wire lead-out area includes: a first sub-touch signal line located in the first wire lead-out area, a second sub-touch signal line located in the second wire lead-out area signal line.
  • the first display signal line in the routing lead-out area includes: a first sub-display signal line located in the first routing-out area, and a second sub-display signal line located in the second routing-out area.
  • the touch signal connection line is connected with the first sub-touch signal line and the second sub-touch signal line.
  • the display signal connection line is connected to the first sub-display signal line and the second sub-display signal line.
  • the first sub-touch signal line and the second sub-touch signal line are located on the side of the touch signal connection line away from the substrate substrate, and the first sub-display signal line and the second sub-display signal line are located on the display signal connection line close to the substrate. side of the substrate.
  • the display signal connection line in the bending area is used to connect the corresponding sub-display signal lines in the first wiring lead-out area and the second wiring lead-out area
  • the touch signal connection line in the bending area is used to connect the second
  • the sub-touch signal lines corresponding to the first wire lead-out area and the second wire lead-out area can realize the transmission of display signals and touch signals.
  • the first power supply line in the wire lead-out area includes: a first sub-power supply line located in the first wire lead-out area, and a second sub-power supply line located in the second wire lead-out area.
  • the first power connection line is connected to the first sub-power line and the second sub-power line.
  • the first sub-power line, the first power connection line and the second sub-power line may have an integral structure.
  • this embodiment does not limit it.
  • the first sub-power line and the second sub-power line may have the same layer structure, and may have a different-layer structure from the first power connection line.
  • the first power connection line in the bending area is used to connect the sub-power lines in the first line lead-out area and the second line lead-out area to realize the transmission of the first power supply signal.
  • the first power connection lines, the touch signal connection lines and the display signal connection lines in the bending area all extend along the first direction.
  • at least one display signal connection line, at least one first power supply connection line, at least one touch signal connection line, at least one first power supply connection line and at least one display signal connection line are sequentially arranged in the bending area .
  • the first direction and the second direction are located in the same plane, and the first direction is perpendicular to the second direction.
  • the first power connection line separates the display signal connection line from the touch signal connection line, which can reduce signal interference between the display signal connection line and the touch signal connection line, thereby improving display and touch control. control effect.
  • the display structure layer at least includes: a driving circuit layer disposed on the base substrate.
  • the driving circuit layer at least includes: an active layer disposed on the base substrate, a first gate metal layer, a second gate metal layer and a source-drain metal layer.
  • the first power connection line, the touch signal connection line and the display signal connection line in the bending area are in the same layer structure as the source-drain metal layer in the display area.
  • the at least one first display signal line in the wire lead-out area and the first gate metal layer or the second gate metal layer in the display area have the same layer structure.
  • the touch structure layer at least includes a touch electrode layer.
  • the at least one first touch signal line in the wiring lead-out area and the touch electrode layer in the display area have the same layer structure.
  • the first power line in the wiring lead-out area and the source-drain metal layer in the display area are of the same layer structure. However, this embodiment does not limit it.
  • the wiring lead-out area further includes: at least one second power supply line provided on the base substrate
  • the bending area further includes: at least one second power supply connection line provided on the base substrate.
  • the second power supply line in the wiring lead-out area includes: a third sub-power supply line located in the first wiring lead-out area and a fourth sub-power supply line located in the second wiring lead-out area.
  • the second power connection line is connected to the third sub-power line and the fourth sub-power line.
  • the second power connection line is located on the side of the display signal connection line away from the first power connection line.
  • the second power line may be a low voltage power line VSS. However, this embodiment does not limit it.
  • the first power line may be a high voltage power line VDD. However, this embodiment does not limit it.
  • the first power line may be a low-voltage power line VSS.
  • the wiring lead-out area includes: a plurality of first display signal lines.
  • the plurality of first display signal lines are divided into a first group of first display signal lines and a second group of first display signal lines; the orthographic projection of at least one first touch signal line on the base substrate is located in the first group of first display signal lines Between the signal line and the orthographic projection of the second group of first display signal lines on the base substrate.
  • this embodiment does not limit it.
  • the plurality of first display signal lines in the wiring lead-out area include: at least one first data lead-out line, and at least one first driving control signal line.
  • the orthographic projection of the first driving control signal line on the base substrate is adjacent to the orthographic projection of the first touch signal line on the base substrate.
  • this embodiment does not limit it.
  • the display structure layer includes at least one light emitting element.
  • the light emitting element includes: a first electrode, a second electrode and an organic light emitting layer between the first electrode and the second electrode.
  • the first electrode is located on a side of the second electrode close to the base substrate.
  • the base substrate also includes: a first frame area located between the display area and the lead-out area.
  • the first frame area is provided with a display control circuit and at least one second touch signal line.
  • the second touch signal line is connected to the first touch signal line in the wiring lead-out area.
  • the orthographic projection of the second touch signal line on the base substrate is located within the orthographic projection of the second electrode on the base substrate.
  • the second electrode of the light-emitting element is used to shield the second touch signal line, which can reduce the signal interference between the display signal and the touch signal, thereby improving the display and touch control. control effect.
  • the signal access area is provided with a Touch and Display Driver Integration (TDDI, Touch and Display Driver Integration) circuit.
  • the TDDI circuit is connected to the first display signal line and the first touch signal line in the wiring lead-out area.
  • the TDDI circuit is used for display and touch driving control, which is beneficial to realize thinner and lighter display panels, can simplify the manufacturing process of the display panel, reduce costs, and improve the performance of the display panel.
  • this embodiment does not limit it.
  • FIG. 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • an FSLOC structure formed by integrating a display panel with a self-capacitive touch structure is taken as an example for illustration.
  • the display panel includes: a display area 10 , a first frame area 22 surrounding the display area 10 , and a second frame area located on one side of the display area 10 .
  • the second frame area includes a first wire lead-out area 201 , a bent area 202 , a second wire lead-out area 203 and a signal access area 23 arranged in sequence along a direction away from the display area 10 (namely the first direction D1).
  • the first wiring lead-out area 201 is located on a side of the first frame area 22 away from the display area 10 .
  • the first wiring lead-out area 201 communicates with the first frame area 22 .
  • the signal access area 23 is located on a side of the second wire lead-out area 203 away from the display area 10 .
  • the signal access area 23 communicates with the second routing area 203 .
  • the signal access area 23 includes: a circuit area 204 and a binding pin area 205 arranged in sequence along a direction away from the display area 10 (ie, the first direction D1 ).
  • the bending area 202 is configured such that the second wiring lead-out area 203 and the signal access area 23 are bent to the back of the display area 10 .
  • the circuit area 204 is configured to provide corresponding integrated circuits.
  • the binding pin area 205 is configured to set multiple binding pins, and multiple binding pins can be bound to a flexible circuit board (FPC, Flexible Printed Circuit), so that multiple signal leads (for example, drive control lines, power lines etc.) to interface with external control devices through multiple bonded pins.
  • the integrated circuit disposed in the circuit area 204 may be a touch and display driver integrated circuit (TDDI, Touch and Display Driver Integration). However, this embodiment does not limit it.
  • the display area 10 may be circular. However, this embodiment does not limit it.
  • the display area 10 may be in other shapes such as a rectangle or an ellipse.
  • the display area 10 includes: a display structure layer and a touch control structure layer sequentially disposed on the base substrate.
  • the display structure layer includes a plurality of display units (ie sub-pixels), a plurality of gate lines and a plurality of data lines. Orthographic projections of the plurality of gate lines and the plurality of data lines on the substrate intersect to form a plurality of sub-pixel regions.
  • One sub-pixel is arranged in one sub-pixel area.
  • the multiple data lines are electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the sub-pixels.
  • the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines are configured to provide gate driving signals to the plurality of sub-pixels.
  • one pixel unit may include three sub-pixels, and the three sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels respectively. However, this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels
  • the four sub-pixels can be arranged horizontally, vertically or squarely. The embodiment does not limit this.
  • the touch structure layer includes a plurality of touch units. At least one touch unit may include at least one touch electrode.
  • the orthographic projection of at least one touch electrode on the base substrate may include the orthographic projection of a plurality of sub-pixels on the base substrate.
  • the touch control unit includes a plurality of touch electrodes, the plurality of touch electrodes can be arranged at intervals, and adjacent touch electrodes can be connected to each other through a connecting portion.
  • the touch electrodes and the connection part may be of the same layer structure.
  • the touch electrodes may have a rhombus shape, such as a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus. However, this embodiment does not limit it.
  • the touch electrodes may have any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons and other polygons.
  • FIG. 2 is a schematic diagram of an arrangement of touch electrodes of a display panel according to at least one embodiment of the present disclosure.
  • the display area 10 including 24 self-capacitive touch electrodes as an example.
  • the display area 10 may include 24 regularly arranged touch electrodes 100 .
  • the rectangular first electrode area 101 may include 4 rows*4 columns of touch electrodes 100 arranged in a matrix, each touch electrode 100 may be rectangular in shape, and the area of 16 touch electrodes 100 may be same.
  • the crown-shaped second electrode area 102 and the third electrode area 103 may both include two touch electrodes 100, and the two touch electrodes 100 may be arranged in sequence along the second direction D2, and the two touch electrodes in each electrode area
  • the areas of the electrodes 100 may be the same, and the areas of the touch electrodes 100 in the second electrode region 102 and the areas of the touch electrodes 100 in the third electrode region 103 may be the same.
  • the fourth electrode area 104 and the fifth electrode area 105 in the shape of a crown may both include two touch electrodes 100, the two touch electrodes 100 are arranged in sequence along the first direction D1, and the two touch electrodes 100 in each electrode area
  • the areas of the electrodes 100 may be the same, and the areas of the touch electrodes 100 in the fourth electrode region 104 and the areas of the touch electrodes 100 in the fifth electrode region 105 may be the same.
  • the plurality of touch electrodes 100 in the display area 10 may be arranged symmetrically with respect to the central line O, which may be a central line extending along the first direction D1 and equally dividing the display area 10 .
  • the touch electrodes in the display panel may be in the form of a metal grid, the metal grid is formed by interweaving a plurality of metal wires, the metal grid includes a plurality of grid patterns, and the grid pattern is surrounded by a plurality of metal wires.
  • the polygonal metal grid-shaped touch electrodes have the advantages of small resistance, small thickness and fast response speed. However, this embodiment does not limit it.
  • FIG. 3 is a schematic partial cross-sectional view along the R-R direction in FIG. 1 .
  • the display area 10 in a plane perpendicular to the display panel, the display area 10 includes: a base substrate 41 , a driving circuit layer 42 sequentially disposed on the base substrate 41 , and a light emitting element 43 , encapsulation layer 44 and touch structure layer 45 .
  • the structure of only one sub-pixel is taken as an example for illustration.
  • the base substrate 41 may be a flexible substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer.
  • the material of the first flexible material layer and the second flexible material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or the polymer soft film through surface treatment, the first
  • the material of the inorganic material layer and the second inorganic material layer can adopt silicon nitride (SiNx) or silicon oxide (SiOx) etc., is used to improve the anti-water and oxygen ability of base substrate, and the material of semiconductor layer can adopt amorphous silicon (a -si).
  • this embodiment does not limit it.
  • the driving circuit layer 42 includes a plurality of transistors forming a pixel driving circuit and at least one storage capacitor, and the pixel driving circuit may be 2T1C (that is, two thin film transistors and a capacitor), 3T1C (that is, three thin film transistors and a capacitor) or 7T1C (that is, seven thin film transistors and a capacitor) design.
  • a first transistor and a first storage capacitor are taken as examples for illustration.
  • the driving circuit layer 42 of the display area 10 may include: a first insulating layer 51 disposed on the base substrate 41, an active layer disposed on the first insulating layer 51, a second insulating layer 52 covering the active layer, a disposed The first gate metal layer on the second insulating layer 52, the third insulating layer 53 covering the first gate metal layer, the second gate metal layer disposed on the third insulating layer 53, the first gate metal layer covering the second gate metal layer Four insulating layers 54 , source and drain metal layers disposed on the fourth insulating layer 54 .
  • the active layer may include at least a first active layer
  • the first gate metal layer may include at least a first gate electrode and a first capacitor electrode
  • the second gate metal layer may include at least a second capacitor electrode
  • the source-drain metal layer may include at least a first source electrode and a first drain electrode.
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode form the first transistor 401
  • the first capacitor electrode and the second capacitor electrode form the first storage capacitor 402 .
  • the light emitting element 43 may include a first electrode 431 , a pixel definition layer 434 , an organic light emitting layer 432 and a second electrode 433 .
  • the first electrode 431 is disposed on the first planar layer 56 and connected to the first drain electrode of the first transistor 401 through the first via hole opened on the first planar layer 56 and the fifth insulating layer 55 .
  • the pixel definition layer 434 is disposed on the first electrode 431 and the first planar layer 56 , a pixel opening is disposed on the pixel definition layer 434 , and the pixel opening exposes the first electrode 431 .
  • the organic light emitting layer 432 is at least partially disposed in the pixel opening, and the organic light emitting layer 432 is connected to the first electrode 431 .
  • the second electrode 433 is disposed on the organic light emitting layer 432 , and the second electrode 433 is connected to the organic light emitting layer 432 .
  • the organic light-emitting layer 432 of the light-emitting element 43 may include an light-emitting layer (EML, Emitting Layer), and include a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport One of Layer), hole blocking layer (HBL, Hole Block Layer), electron blocking layer (EBL, Electron Block Layer), electron injection layer (EIL, Electron Injection Layer), electron transport layer (ETL, Electron Transport Layer) or multiple layers.
  • EML Light-emitting layer
  • EML Electron Transport Layer
  • the light emitting characteristics of the organic material are used to emit light according to the required grayscale.
  • light emitting elements of different colors have different light emitting layers.
  • a red light emitting element includes a red light emitting layer
  • a green light emitting element includes a green light emitting layer
  • a blue light emitting element includes a blue light emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer can use a common layer
  • the electron injection layer and electron transport layer on the other side of the light-emitting layer can use a common layer.
  • any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and the The surface of the formed film layer is separated or separated by means of surface treatment.
  • any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, Fine Metal Mask) or an open mask (Open Mask), or by an inkjet process.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation layer 44 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer can be made of inorganic materials
  • the second encapsulation layer can be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter and emit light.
  • Element 43 does not limit it.
  • the encapsulation layer may adopt a five-layer stacked structure of inorganic/organic/inorganic/organic/inorganic.
  • the touch structure layer 45 may include: a first touch insulation layer 451 disposed on the side of the encapsulation layer 44 away from the base substrate 41 , a first touch insulation layer 451 disposed on the side away from the base substrate The touch electrode layer 452 on the side of the touch electrode layer 41 and the touch protection layer 455 disposed on the side of the touch electrode layer 452 away from the base substrate 41 .
  • this embodiment does not limit it.
  • FIG. 4 is a partial schematic diagram of area S1 in FIG. 1 .
  • FIG. 5 is a schematic diagram of a second wiring layer formed in the wiring lead-out area of at least one embodiment of the present disclosure.
  • the wire lead-out area includes: a first wire lead-out area 201 and a second wire lead-out area 203 .
  • the second wiring layer in the wiring lead-out area and the second gate metal layer in the display area 10 may have the same layer structure, and the first wiring layer in the wiring lead-out area and the first gate metal layer in the display area 10 may be in the same layer structure.
  • FIG. 6A is a schematic diagram of a third wiring layer formed in the wiring lead-out area and the bending area according to at least one embodiment of the present disclosure.
  • FIG. 6B is a schematic diagram of a third wiring layer formed by the wiring lead-out area and the bending area according to at least one embodiment of the present disclosure.
  • the third wiring layer in the wiring lead-out area and the bending area and the source-drain metal layer in the display area 10 may have the same layer structure.
  • Fig. 7A is a schematic diagram of the trace signal line formed in the lead-out area of at least one embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of touch signal lines formed in the lead-out area of at least one embodiment of the present disclosure.
  • the touch signal line and the touch electrode layer of the display area 10 may have the same layer structure.
  • FIG. 8 is a schematic partial cross-sectional view along the P-P direction in FIG. 4 .
  • the routing in the routing area may be symmetrical with respect to the central line O
  • the routing in the bending area may be symmetrical with respect to the central line O.
  • this embodiment does not limit it.
  • the wire lead-out area includes: a first wire lead-out area 201 and a second wire lead-out area 203 , and the bending area 202 is located between the first wire lead-out area 201 and the second wire lead-out area 203 . Between the two wiring lead-out areas 203 .
  • the first wiring lead-out area 201 is located on a side of the first frame area 22 away from the display area 10 .
  • the plurality of first display signal lines in the routing lead-out area include: a plurality of first data leads and a plurality of first driving control signal lines.
  • the multiple display signal connection lines in the bending area 202 include: multiple data connection lines and multiple drive control connection lines.
  • multiple first data leads, multiple first drive control signal lines, multiple first touch signal lines, multiple data connection lines, multiple drive control connection lines, and multiple touch control lines The signal connection lines are shown as a whole.
  • the numbers of the first data leads, the first drive control signal lines, the first touch signal lines, the data connection lines, the drive control connection lines and the touch signal connection lines are not limited. .
  • At least one first data lead in the lead-out area includes: a first sub-data lead located in the first lead-out area 201 , a second lead in the second The second sub-data wires of the region 203 are led out.
  • the first sub-data lead and the second sub-data lead are connected through the data connection line in the bending area 202 .
  • the first data wire 35a includes: a first sub-data wire 351a and a corresponding second sub-data wire 353a
  • the first data wire 35b includes: a first sub-data wire 351b and a corresponding second sub-data wire 353b.
  • the data connection line 352a in the bending area 202 is connected to the first sub-data lead 351a and the corresponding second sub-data lead 353a, and the data connection line 352b is connected to the first sub-data lead 351b and the corresponding second sub-data lead 353b.
  • the first sub-data lead 351a can extend to the first frame area 22, and the second data lead 350a of the first frame area 22; the first sub-data lead 351b can extend to the first frame area 22, and the first frame area 22
  • the second data lead 350b is connected.
  • first sub-data wires 351a and the correspondingly connected second data wires 350a may have an integral structure
  • first sub-data wires 351b and the correspondingly connected second data wires 350b may have an integral structure
  • the second sub-data wires 353a and 353b may extend to the circuit area 204 along the first direction D1, for example, be connected to the TDDI circuit of the circuit area 204 .
  • At least one first drive control signal line in the wire lead-out area at least includes: a first sub-drive control signal line located in the first wire lead-out area 201 The signal line, the second sub-drive control signal line, the third sub-drive control signal line, the fourth sub-drive control signal line and the fifth sub-drive control signal line located in the second wiring lead-out area 203 .
  • the first sub-drive control signal line and the second sub-drive control signal line are connected through the drive control connection line in the bending area 202 .
  • the first drive control signal line 36a includes: a first sub-drive signal line 361a, a second sub-drive signal line 363a, a third sub-drive signal line 364a, a fourth sub-drive signal line 365a, a fifth sub-drive signal line connected in sequence.
  • the signal line 366a is driven.
  • the second drive control signal line 36b includes: a first sub-drive signal line 361b, a second sub-drive signal line 363b, a third sub-drive signal line 364b, a fourth sub-drive signal line 365b, and a fifth sub-drive signal line connected in sequence. Line 366b.
  • the driving control connection line 362a of the bending area 202 is connected to the first sub-driving signal line 361a and the second sub-driving signal line 363a.
  • the driving control connection line 362b of the bending area 202 is connected to the first sub-driving signal line 361b and the second sub-driving signal line 363b.
  • the first sub-driving signal lines 361 a and 361 b may be respectively connected to the second driving control signal lines 360 a and 360 b of the first frame area 22 , and connected to the ESD circuit 32 in the first frame area 22 . Both the second sub driving signal lines 363a and 363b extend along the first direction D1.
  • the third sub-drive signal line 364a is located on the right side of the second sub-data lead 353a, toward the side close to the second sub-data lead 353a, and sequentially extends along the first direction D1 and the second direction D2, so as to be consistent with the fourth sub-driver signal line 364a.
  • the signal line 365a is connected to the fifth sub-drive signal line 366a.
  • the third sub-drive signal line 364b is located on the left side of the second sub-data lead 353b, toward the side close to the second sub-data lead 353b, and extends along the first direction D1 and the second direction D2 in sequence, so as to be consistent with the fourth sub-driver signal line 364b.
  • the signal line 365b is connected to the fifth sub-drive signal line 366b.
  • the fourth sub-driving signal line 365a is located on the left side of the second sub-data wiring 353a, and extends along the second direction D2 and the third direction D3 in sequence toward a side away from the second sub-data wiring 353a.
  • the fourth sub-driving signal line 365b is located on the right side of the second sub-data wiring 353b, and extends along the second direction D2 and the third direction D3 in sequence toward a side away from the second sub-data wiring 353b.
  • the third direction D3 intersects both the first direction D1 and the second direction D2.
  • the fourth sub-driving signal lines 365a and 365b may extend to the binding pin area, and be connected to the binding pins of the binding pin area.
  • the fifth sub-driving signal lines 366a and 366b may extend to the circuit area along the first direction D1, for example, be connected to the TDDI circuit of the circuit area.
  • this embodiment does not limit it.
  • the at least one first touch signal line in the wire lead-out area includes: a first sub-touch signal line located in the first wire lead-out area 201 ,
  • the second wiring leads out the second sub-touch signal line of the region 203 .
  • the first sub-touch signal line and the second sub-touch signal line are connected through the touch signal connection line in the bending area 202 .
  • the at least one first touch signal line 37 includes: a first sub-touch signal line 371 located in the first routing area 201 , and a second sub-touch signal line 373 located in the second routing area 203 .
  • the first sub-touch signal line 371 and the second sub-touch signal line 373 are connected through the touch signal connection line 372 in the bending area 202 .
  • the first sub-touch signal line 371 can be connected to the second touch signal line 370 of the first frame area 22 .
  • the second sub-touch signal line 373 may extend to the circuit area along the first direction D1, for example, be connected to the TDDI circuit in the circuit area.
  • the first touch signal line 37 and the second touch signal line 370 may be integrated. However, this embodiment does not limit it.
  • the first power supply line 33 in the wiring lead-out area may include: a first sub-power supply line 331 located in the first wiring lead-out area 201 , The second sub-power line 333 of the line lead-out area 203 .
  • the first sub power line 331 may be connected to the third power line 330 in the first frame area 22 .
  • the first sub power line 331 and the second sub power line 333 are connected through the first power connection lines 332 a and 332 b of the bending area 202 .
  • the first sub-power line 331 has a first notch M1 at an end close to the bending area 202 .
  • the second sub power line 333 has a first extension part 333a, a second extension part 333b and a third extension part 333c.
  • the third extension portion 333c extends along the first direction D1.
  • the third extension portion 333c has a second notch M2 at an end close to the bending area 202 .
  • One end of the third extension portion 333c having the second notch M2 is connected to the first power connection lines 332a and 332b.
  • the first extension portion 333a is located on the left side of the third extension portion 333c, toward the side away from the third extension portion 333c, and extends in sequence along the second direction D2, the first direction D1, the second direction D2 and the third direction D3, Or extend along the second direction D2, the first direction D1, the third direction D3, the second direction D2 and the third direction D3 in sequence.
  • the second extension portion 333b is located on the right side of the third extension portion 333c, toward the side away from the third extension portion 333c, and extends in sequence along the second direction D2, the first direction D1, the second direction D2 and the third direction D3, Or extend along the second direction D2, the first direction D1, the third direction D3, the second direction D2 and the third direction D3 in sequence.
  • the first extension part 333a and the second extension part 333b may extend to the binding pin area, and be connected with the binding pins of the binding pin area.
  • the first sub-power line 331 , the second sub-power line 333 , and the first power connection lines 332 a and 332 b of the first power line 33 may have an integral structure.
  • this embodiment does not limit it.
  • the first power connection lines 332a and 332b may be in a heterogeneous structure with the first sub-power line 331 and the second sub-power line 333 .
  • the second power supply line in the wiring lead-out area includes: a third sub-power supply line located in the first wiring lead-out area 201, a third sub-power supply line located in the second wiring lead-out area 203 for the fourth sub power line.
  • the third sub-power line and the fourth sub-power line may be connected through the second power connection line in the bending area.
  • the second power line 34a includes: a third sub-power line 341a located in the first routing area 201, a fourth sub-power line 343a located in the second area 203;
  • the second power line 34b includes: The third sub-power line 341b in the first routing area 201, the fourth sub-power line 343b located in the second routing area 203;
  • the second power connection line 342a connects the third sub-power line 341a and the fourth sub-power line 343a
  • the second power connection line 342b connects the third sub-power line 341b and the fourth sub-power line 343b.
  • the third sub power lines 341a and 341b are connected to the fourth power lines 340a and 340b of the first bezel area 22, respectively.
  • the fourth sub-power line 343a is located on the left side of the second sub-power line 333, facing away from the second sub-power line 333, and sequentially along the first direction D1, the third direction D3, the second direction D2 and the third direction D3 Extend; the fourth sub-power line 343b is located on the right side of the second sub-power line 333, facing away from the second sub-power line 333, along the first direction D1, the third direction D3, the second direction D2 and the third direction in sequence.
  • the direction D3 extends.
  • the fourth sub-power lines 343a and 343b may extend to the binding pin area, and be connected to the binding pins of the binding pin area.
  • the third sub-power line 341a, the second power connection line 342a and the fourth sub-power line 343a may have an integral structure
  • the wire 342b and the fourth sub-power wire 343b may have an integral structure.
  • this embodiment does not limit it.
  • the second power connection line, the third sub-power line and the fourth sub-power line may have a heterogeneous structure.
  • the first panel crack detection (PCD, Panel Crack Detect) signal line in the wiring lead-out area includes: The PCD signal line, the second sub-PCD signal line located in the second routing area 203 .
  • the first sub-PCD signal line and the second sub-PCD signal line are connected through the PCD connection signal line in the bending area 202 .
  • the first PCD signal line 38a includes: a first sub-PCD signal line 381a located in the first routing area 201, a second sub-PCD signal line 383a located in the second routing area 203; the first PCD signal line 38b It includes: a first sub-PCD signal line 381b located in the first routing area 201 , and a second sub-PCD signal line 383b located in the second routing area 203 .
  • the PCD connection signal line 382a in the bending area 202 is connected to the first sub-PCD signal line 381a and the second sub-PCD signal line 383a
  • the PCD connection signal line 382b is connected to the first sub-PCD signal line 381b and the second sub-PCD signal line 383b.
  • the first sub-PCD signal lines 381a and 381b are connected to the second PCD signal lines 380a and 380b of the first bezel area 22, respectively.
  • the second sub-PCD signal lines 383a and 383b may extend to the binding pin area, and be connected to the binding pins of the binding pin area.
  • the first sub-PCD signal line 381a and the second PCD signal line 380a may have an integral structure
  • the first sub-PCD signal line 381b and the second PCD signal line 380b may have an integral structure.
  • this embodiment does not limit it.
  • the shape of the first frame area 22 may be a ring surrounding the display area 10 .
  • the first frame area 22 is provided with a plurality of second touch signal lines 370 .
  • the first end of at least one second touch signal line 370 is connected to a touch unit in the display area 10, the second end of the second touch signal line 370 extends along the frame shape of the display area 10, and is connected to the wiring
  • the first touch signal line 37 in the lead-out area is connected, for example, the second touch signal line 370 is extended to connect with the first sub-touch signal line 371 in the first trace lead-out area 201 .
  • the second touch signal line 370 and the first sub-touch signal line 371 may be integrated. However, this embodiment does not limit it.
  • the first frame area 22 is also provided with a display control circuit, for example including: a gate drive circuit (GOA) 30, a multiplexing circuit (MUX) 31, a test circuit (CT) (not shown) and electrostatic discharge (ESD) circuit 32 .
  • the gate drive circuit 30 may include a plurality of cascaded shift register units, and each shift register unit may be connected to at least one scanning signal line of the display area 10 and configured to scan at least one of the display area 10 The signal lines provide gate driving signals.
  • the test circuit may include a plurality of test units, each test unit may be connected to a plurality of data signal lines in the display area, and configured to provide test data signals to the plurality of data signal lines in the display area 10 .
  • the multiplexing circuit 31 may include multiple multiplexing units, and each multiplexing unit may be connected to multiple data signal lines of the display area 10, and is configured such that one signal source provides data signals for multiple data signal lines.
  • shift register units may be spaced apart from multiplexing units. However, this embodiment does not limit it.
  • the ESD circuit 32 may include a plurality of electrostatic discharge units, for example, each electrostatic discharge unit may be connected to at least one second driving control signal line of the first frame area 22 to eliminate static electricity on the signal line.
  • the frame area 22 is provided with a plurality of second display signal lines, for example including a plurality of second data leads and a plurality of second driving control signal lines.
  • the second data lead may be connected to the multiplexing circuit 31 .
  • the plurality of second data wires includes a first group of second data wires 350a and a second group of second data wires 350b.
  • the first group of second data wires 350a extend from the first frame area 22 on the left side of the display area 10 to the first frame area 22 on the lower side, and are connected with the first data wires 35a in the routing area, for example, extend to the first
  • the wire lead-out area 201 is connected to the first sub-data lead 351a.
  • the second group of second data wires 350b extends from the first frame area 22 on the right side of the display area 10 to the first frame area 22 on the lower side, and is connected with the first data wires 35b in the wiring lead-out area, for example, extends to the first frame area 22 on the lower side.
  • the wiring lead-out area 201 is connected to the first sub-data lead 351b.
  • the second data lead and the correspondingly connected first data lead may be of an integral structure. However, this embodiment does not limit it.
  • the plurality of second drive control signal lines in the first frame region 22 include a first group of second drive control signal lines 360 a and a second group of second drive control signal lines 360 a. 360b.
  • the first group of second drive control signal lines 360a extends from the first frame area 22 on the left side of the display area 10 to the first frame area 22 on the lower side, and is connected to the ESD circuit 32 at the first frame area 22 on the lower side, and is connected to the first frame area 22 on the lower side.
  • the first drive control signal line in the wire lead-out area is connected, for example, connected to the first sub-drive control signal line 361a in the first wire lead-out area 201 .
  • the second group of second driving control signal lines 360b extends from the first frame area 22 on the right side of the display area 10 to the first frame area 22 on the lower side, and is connected to the ESD circuit 32 at the first frame area 22 on the lower side, and is connected to the first frame area 22 on the lower side.
  • the first drive control signal line in the wire lead-out area is connected, for example, connected to the first sub-drive control signal line 361b in the first wire lead-out area 201 .
  • the first driving control signal line and the second driving control signal line may have a heterogeneous structure. However, this embodiment does not limit it.
  • the first frame area 22 is further provided with a third power line 330 and fourth power lines 340a and 340b.
  • the third power line 330 in the first frame area 22 on the left side and the right side of the display area 10 extends along the frame shape of the display area 10 to the first frame area 22 on the lower side of the display area 10, and gathers together and extends to the walkway.
  • the line lead-out area is connected to the first power line 33 in the line lead-out area, for example, the third power line 330 is connected to the first sub-power line 331 in the first line lead-out area 201 .
  • the third power line 330 and the first power line 33 may have an integral structure.
  • the fourth power lines 340a and 340b are located on the side of the third power line 330 away from the display area 10, and extend to the lead-out area, and are respectively connected to the second power lines 34a and 34b in the lead-out area, such as the fourth power line 340a is connected to the fourth sub-power line 341a of the first routing area 201 , and the fourth power line 340b is connected to the fourth sub-power line 341b of the first routing area 201 .
  • the fourth power line 340a and the second power line 34a may have an integral structure
  • the fourth power line 340b and the second power line 34b may have an integral structure.
  • this embodiment does not limit it.
  • the first power line 33 and the third power line 330 may be a high voltage power line VDD
  • the second power lines 34a and 34b and the fourth power lines 340a and 340b may be a low voltage power line VSS.
  • the DC stable signal can be provided through the first power line, the second power line, the third power line and the fourth power line.
  • this embodiment does not limit it.
  • the first frame area 22 is further provided with second PCD signal lines 380a and 380b.
  • the second PCD signal line 380a is located on the side of the fourth power line 340a away from the display area 10
  • the second PCD signal line 380b is located on the side of the fourth power line 340a away from the display area 10 .
  • the second PCD signal lines 380a and 380b extend to the wiring lead-out area and are respectively connected to the first PCD signal lines 38a and 38b in the wiring lead-out area.
  • One sub-PCD signal line 381a is connected, and the second PCD signal line 380b is connected to the first sub-PCD signal line 381b of the first routing area 201 .
  • the second PCD signal line 380a and the first sub-PCD signal line 381a may have an integral structure
  • the second PCD signal line 380b and the first sub-PCD signal line 381b may have an integral structure.
  • this embodiment does not limit it.
  • the first wiring lead-out area 201 is provided with a plurality of first sub-data leads 351a and 351b, a plurality of first sub-drive signal lines 361a and 361b, a plurality of first sub-drive signal lines 361a and 361b, a plurality of first A sub-power line 331, third sub-power lines 341a and 341b, a plurality of first sub-touch signal lines 371, and first sub-PCD signal lines 381a and 381b.
  • the orthographic projections of the plurality of first sub-driving signal lines 361a and 361b on the substrate are located in the middle of the orthographic projections of the plurality of first sub-data leads 351a and the plurality of first sub-data leads 351b on the substrate.
  • the orthographic projections of the multiple first sub-touch signal lines 371 on the base substrate are located in the middle of the orthographic projections of the multiple first sub-driving signal lines 361 a and 361 b on the base substrate.
  • the orthographic projection of the plurality of first sub-touch signal lines 371 on the substrate is different from the orthographic projection of the plurality of first sub-data leads 351a and 351b and the plurality of first sub-driving signal lines 361a and 361b on the substrate. overlap.
  • the orthographic projection of the first sub-power supply line 331 on the base substrate is located in the middle of the orthographic projections of the first sub-data leads 351a and the plurality of first sub-data leads 351b on the base substrate, and is aligned with the plurality of first sub-data leads 351b.
  • the orthographic projections of the driving signal lines 361a and 361b on the base substrate overlap.
  • the first sub-touch signal line can be isolated from the first sub-drive signal line and the first sub-data lead line through the first sub-power supply line 331, so as to avoid the gap between the touch signal and the display signal. Interference between each other, shielding signal jumps, thereby improving display and touch effects.
  • the orthographic projection of the third sub-power supply line 341 a on the base substrate is located at the position where the first sub-driving signal line 361 a is located.
  • the orthographic projection on the base substrate is away from the side of the orthographic projection of the first sub-power line 331 on the base substrate, and the orthographic projection of the third sub-power line 341b on the base substrate is located on the side of the first sub-drive signal line 361b on the base substrate.
  • the orthographic projection on the base substrate is away from the side of the orthographic projection of the first sub-power line 331 on the base substrate.
  • the first sub-PCD signal line 381a is located on a side of the third sub-power line 341a away from the first sub-power line 331
  • the first sub-PCD signal line 381b is located on a side of the third sub-power line 341b away from the first sub-power line 331 .
  • a plurality of first sub-touch signal lines 371 are located on a side of the first sub-power supply line 331 away from the base substrate.
  • the plurality of first sub-data leads 351a and 351b, and the plurality of first sub-drive signal lines 361a and 361b are located on the side of the first sub-power supply line 331 close to the base substrate.
  • the first sub-power line 331 , the third sub-power line 341 a and 341 b have the same layer structure, for example, the same layer structure as the source-drain metal layer of the display region 10 .
  • the multiple first sub-touch signal lines 371 have the same layer structure, for example, the same layer structure as the touch electrode layer of the display area 10 .
  • the plurality of first sub-driving signal lines 361 a and 361 b may be of the same layer structure, for example, located on the first gate metal layer or the second gate metal layer of the display region 10 .
  • the first sub-PCD signal lines 381 a and 381 b may be connected to the first gate metal layer or the second gate metal layer of the display area 10 .
  • the plurality of first sub-data wires 351a and 351b may be in a hetero-layer structure.
  • the plurality of first sub-data leads 351a and 351b are numbered sequentially, the odd-numbered first sub-data leads and the first gate metal layer of the display area 10 have the same layer structure, the even-numbered first sub-data leads and the display area 10
  • the second gate metal layer of the display area 10 has the same layer structure, or the odd-numbered first sub-data leads and the second gate metal layer of the display area 10 have the same layer structure, and the even-numbered first sub-data leads and the second gate metal layer of the display area 10 have the same layer structure.
  • a gate metal layer has the same layer structure.
  • the orthographic projections of the plurality of first sub-data leads on the base substrate do not overlap.
  • first sub-data leads can be arranged on the same layer.
  • at least one first sub-driving signal line may include a first sub-wiring and a second sub-wiring in parallel, the first sub-wiring may have the same layer structure as the first gate metal layer of the display area, and the second The second sub-wire may have the same layer structure as the second gate metal layer in the display area.
  • the bending region 202 is provided with a plurality of data connection lines 352a and 352b, a plurality of drive control connection lines 362a and 362b, and a plurality of touch signal connection lines 372 , first power connection lines 332a and 332b, second power connection lines 342a and 342b, and PCD signal connection lines 382a and 382b.
  • Multiple data connection lines are connected to multiple first sub-data leads in one-to-one correspondence
  • multiple drive control connection lines are connected to multiple first sub-drive signal lines in one-to-one correspondence
  • multiple touch signal connection lines are connected to multiple first sub-drive signal lines.
  • the sub-touch signal lines are connected in one-to-one correspondence.
  • the first power connection lines 332 a and 332 b are connected to the first sub power line 331 .
  • the second power connection line is connected to the corresponding third sub-power line.
  • the traces in the bending region 202 all extend along the first direction D1 and are arranged side by side in sequence, and there is no electrical connection between adjacent traces.
  • the traces in the bending region 202 have the same layer structure, for example, the same layer structure as the source-drain metal layer of the display region 10 .
  • a plurality of drive control connection lines 362a, a first power supply connection line 332a, a touch signal connection line 372, a first power supply connection line 332b, a plurality of drive control connection lines 362b, a plurality of data connection lines 352b, and a second power supply connection line 342b and the PCD signal connection line 382b are arranged side by side in sequence.
  • the first power supply connection lines 332a and 332b are located between the drive control connection line and the touch signal connection line, which can realize the isolation of the display signal and the touch signal, and avoid the gap between the touch signal and the display signal. Mutual interference, shielding signal jumps, thereby improving display and touch effects.
  • the orthographic projection of the touch signal connection line 372 on the base substrate is the same as that of the first sub-power supply line 331 and the second sub-power supply line 333 on the base substrate.
  • the orthographic projections of do not overlap.
  • the overlapping area of the orthographic projection of the first sub-touch signal line 371 and the touch signal connection line 372 on the base substrate is located within the orthographic projection of the first notch M1 of the first sub-power supply line 331 on the base substrate.
  • the first sub-touch signal line 371 is connected to the touch signal connection line 372 through a via hole.
  • the overlapping area of the orthographic projection of the touch signal connection line 372 and the second sub-touch signal line 373 on the base substrate is located in the second gap M2 of the third extension portion 333c of the second sub-power line 333 on the base substrate in the orthographic projection of .
  • the second sub-touch signal line 372 is connected to the touch signal connection line 372 through a via hole.
  • this embodiment does not limit it.
  • the second wiring lead-out area 203 is provided with a plurality of second sub-data leads 353a and 353b, a plurality of second sub-drive signal lines 363a and 363b, a plurality of second sub-drive signal lines 363a and 363b, a plurality of A third sub-drive signal line 364a and 364b, a plurality of fourth sub-drive signal lines 365a and 365b, a plurality of fifth sub-drive signal lines 366a and 366b, a plurality of second sub-touch signal lines 373, a second sub-power supply line 333, fourth sub power supply lines 343a and 343b, and second sub PCD signal lines 383a and 383b.
  • the orthographic projections of the plurality of second sub-touch signal lines 373 on the base substrate are located in the middle of the orthographic projections of the plurality of second sub-drive signal lines 363a and 363b on the base substrate, and are located in the middle of the plurality of third sub-drive signal lines.
  • the orthographic projections of the plurality of third sub-touch signal lines 373 on the substrate are the same as the orthographic projections of the second sub-data leads 353a and 353b and the second to fifth sub-driving signal lines on the substrate. There is no overlap.
  • the orthographic projections of the plurality of second sub-touch signal lines 373 on the base substrate overlap with the orthographic projections of the second sub-power supply lines 333 on the base substrate, wherein each second sub-touch signal line 373 is Both the orthographic projection on the base substrate and the orthographic projection of the second sub-power line 333 on the base substrate overlap.
  • the orthographic projections of the plurality of second sub-touch signal lines 373 on the base substrate overlap with the orthographic projections of the third extension portion 333c of the second sub-power line 333 on the base substrate.
  • the second sub-touch signal line 373, the second sub-data lead wire and the second The sub-drive signal line is isolated from the fifth sub-drive signal line to avoid mutual interference between the touch signal and the display signal, shield signal jumps, and improve display and touch effects.
  • the second sub-drive signal lines 363a and 363b, the fourth sub-drive signal lines 365a and 365b, and the fifth sub-drive signal lines 366a and 366b may be It is the same layer structure, for example, it is the same layer structure as the first gate metal layer or the second gate metal layer of the display region 10 .
  • the third sub-driving signal lines 364 a and 364 b are, for example, in the same layer structure as the source-drain metal layer of the display region 10 .
  • the second sub-touch signal line 373 may have the same layer structure as the touch electrode layer of the display area 10 .
  • the second sub power line 333 , the fourth sub power line 343 a and 343 b may have the same layer structure as the source and drain metal layers of the display area 10 .
  • the second sub-PCD signal lines 383 a and 383 b may have the same layer structure as the first gate metal layer or the second gate metal layer of the display area 10 . However, this embodiment does not limit it.
  • the orthographic projection of the third sub-drive signal line 364a on the base substrate is the same as the orthographic projection of the second sub-data lead wire 353a on the base substrate.
  • the orthographic projection of the third sub-drive signal line 364b on the base substrate overlaps with the orthographic projection of the second sub-data lead wire 353b on the base substrate.
  • the orthographic projection of the fourth sub-drive signal line 365a on the base substrate overlaps with the orthographic projection of the first extension portion 333a of the second sub-power supply line 333 on the base substrate, and the fourth sub-drive signal line 365b is on the substrate.
  • the orthographic projection on the substrate overlaps with the orthographic projection of the second extension portion 333b of the second sub-power line 333 on the base substrate.
  • the orthographic projection of the first extension part 333a of the second sub-power supply line 333 on the base substrate overlaps with the orthographic projection of the second sub-data lead wire 353a on the base substrate, and the second extension of the second sub-power supply connection line 333
  • the orthographic projection of the portion 333b on the base substrate overlaps with the orthographic projection of the second sub-data lead 353b on the base substrate.
  • the orthographic projection of the third extension portion 333c of the second sub-power supply connection line 333 on the substrate is located between the orthographic projections of the third sub-driving signal lines 364a and 364b on the substrate.
  • an electrostatic discharge area may be provided between the second wiring lead-out area 203 and the circuit area.
  • An electrostatic discharge circuit may be provided in the electrostatic discharge area, and the electrostatic discharge circuit may prevent electrostatic damage to the display panel by eliminating static electricity.
  • an electrostatic discharge circuit may be connected to a plurality of second sub-data leads. However, this embodiment does not limit it.
  • the first wire lead-out region 201 in a plane perpendicular to the display panel, includes: a base substrate 41 , a first insulating layer sequentially disposed on the base substrate 41 51, the second insulating layer 52, the first wiring layer, the third insulating layer 53, the second wiring layer, the fourth insulating layer 54, the third wiring layer, the first flat layer 56, the pixel definition layer 434, the contact The control signal line layer and the touch protection layer 455.
  • the first wiring layer includes at least: a plurality of first sub-data wires 351a and 351b;
  • the second wiring layer includes at least: a plurality of first sub-data wires 351a and 351b, a plurality of first sub-drive signal lines 361a and 361b, first sub-PCD signal lines 381a and 381b;
  • the third wiring layer at least includes: first sub-power supply lines 331, second sub-power supply lines 341a and 341b; touch
  • touch The signal line layer at least includes: a plurality of first sub-touch signal lines 371 .
  • this embodiment does not limit it.
  • the bending region 202 in a plane perpendicular to the display panel, includes: a base substrate 41 , a third wiring layer sequentially arranged on the base substrate 41 , a A flat layer 56 , a pixel definition layer 434 , and a touch protection layer 455 .
  • a base substrate 41 in a plane perpendicular to the display panel, includes: a base substrate 41 , a third wiring layer sequentially arranged on the base substrate 41 , a A flat layer 56 , a pixel definition layer 434 , and a touch protection layer 455 .
  • the third wiring layer at least includes: a plurality of data connection lines 352a and 352b, a plurality of drive control connection lines 361a and 361b, a plurality of touch signal connection lines 372, The first power connection lines 332a and 332b, the second power connection lines 342a and 342b, and the PCD signal connection lines 382a and 382b.
  • this embodiment does not limit it.
  • the second lead region 203 in a plane perpendicular to the display panel, includes: a base substrate 41 , a first insulating layer 51 sequentially disposed on the base substrate 41 , The second insulating layer 52, the first wiring layer, the third insulating layer 53, the second wiring layer, the fourth insulating layer 54, the third wiring layer, the first flat layer 56, the pixel definition layer 434, the touch signal Wire layer and touch protection layer 455 .
  • the first wiring layer includes at least: a plurality of second sub-data wires 353a and 353b;
  • the second wiring layer includes at least: a plurality of second sub-data wires 353a and 353b, multiple second sub-drive signal lines 363a and 363b, multiple fourth sub-drive signal lines 365a and 365b, multiple fifth sub-drive signal lines 366a and 366b, second sub-PCD signal lines 383a and 383b;
  • the wiring layer includes at least: the second sub-power supply line 333, the fourth sub-power supply line 343a and 343b, and a plurality of third sub-driving signal lines 364a and 364b;
  • the touch signal line layer includes at least: a plurality of second sub-touch signal lines Line 373.
  • this embodiment does not limit it.
  • FIG. 9 is a schematic diagram of second electrodes shielding touch signal lines according to at least one embodiment of the present disclosure.
  • the second electrodes 433 of the plurality of sub-pixels in the display area 10 may have an integral structure.
  • the second electrode 433 is connected to a low voltage power line.
  • the second electrode 433 may extend from the display area 10 to the first frame area 22 .
  • the orthographic projections of the plurality of second touch signal lines 370 on the base substrate in the first frame area 22 are located within the orthographic projections of the second electrodes 433 on the base substrate.
  • the second touch signal line 370 is connected to the first sub-touch signal line 371 of the first wiring lead-out area 201 , for example, may have an integral structure.
  • the second electrode shields the second touch signal line in the first frame area, which can avoid mutual interference between the touch signal in the first frame area and the display signal, thereby improving display and touch control. Effect.
  • the second touch signal line in the first frame area, is shielded by the second electrode transmitting a low-voltage power signal, and in the wiring lead-out area, the first power supply line transmitting a high-voltage power signal is used to shield the second touch signal line. Shielding the first touch signal line by the line can reduce display and touch noise generated by mutual interference between the touch signal and the display signal, thereby improving display and touch effects.
  • the "patterning process" mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, coating can use any one or more of spray coating, spin coating and inkjet printing, etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process includes at least one "pattern”.
  • a and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display panel.
  • the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the range of the orthographic projection of A within the boundary range, or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the manufacturing process of the display panel may include the following operations.
  • the base substrate 41 may be a flexible substrate, for example, including a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second Inorganic material layer.
  • Materials such as the first flexible material layer and the second flexible material layer are polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the materials of the first inorganic material layer and the second inorganic material layer are silicon nitride (SiNx) or silicon oxide (SiOx), etc., which are used to improve the water and oxygen resistance of the base substrate.
  • the first inorganic material layer, the second inorganic material layer The layer is also called the barrier (Barrier) layer.
  • the material of the semiconductor layer is amorphous silicon (a-si).
  • the preparation process includes: Coating a layer of polyimide, forming a first flexible material layer after curing into a film; then depositing a layer of barrier film on the first flexible material layer to form a first barrier layer covering the first flexible layer; A layer of amorphous silicon film is deposited on the barrier layer to form a semiconductor layer covering the first barrier layer; then a layer of polyimide is coated on the semiconductor layer, and the second flexible material layer is formed after curing into a film; then A barrier thin film is deposited on the second flexible material layer to form a second barrier layer covering the second flexible material layer, and the preparation of the flexible substrate 41 is completed, as shown in FIGS. 3 and 8 . After this process, the display area 10 , the first wire lead-out area 201 , the bent area 202 and the second wire lead-out area 203 all include the base substrate 41 .
  • the first insulating film and the active layer film are sequentially deposited on the base substrate 41, and the active layer film is patterned through a patterning process to form the first insulating film covering the entire base substrate 41.
  • an insulating layer 51 , and an active layer pattern disposed on the first insulating layer 51 As shown in FIG. 3 , an active layer pattern is formed in the display area 10 , including at least a first active layer.
  • the first wire lead-out region 201 , the bent region 202 and the second wire lead-out region 203 include the first insulating layer 51 disposed on the base substrate 41 .
  • a second insulating film and a first conductive film are sequentially deposited on the base substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a second insulating film covering the active layer.
  • the insulating layer 52 , and the first gate metal layer and the first wiring layer pattern disposed on the second insulating layer 52 As shown in FIG. 3 and FIG.
  • the first gate metal layer is formed in the display area 10, at least including: a first wiring layer, a first gate electrode, a first capacitor electrode and a plurality of gate lines (not shown in the figure), the first The wiring layer at least includes: a plurality of first sub-data leads 351a and 351b and a plurality of second sub-data leads 353a and 353b formed in the wiring lead-out area.
  • a third insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned by a patterning process to form a third insulating layer 53 and The second gate metal layer and the second wiring layer.
  • the second gate metal layer at least includes: the second capacitor electrode formed in the display area 10
  • the second wiring layer at least includes: a plurality of first sub-data leads formed in the wiring lead-out area 351a and 352a, multiple second sub-data leads 353a and 353b, multiple first sub-drive signal lines 361a and 361b, multiple second sub-drive signal lines 363a and 363b, multiple fourth sub-drive signal lines 365a and 365b , a plurality of fifth sub-drive signal lines 366a and 366b, first sub-PCD signal lines 381a and 381b, and second sub-PCD signal lines 383a and 383b.
  • multiple first sub-data wires are alternately arranged on the first wiring layer and the second wiring layer, and multiple second sub-data wires are arranged on the first wiring layer and the second wiring layer Arranged alternately.
  • the bending region 202 includes the first insulating layer 51 , the second insulating layer 52 and the third insulating layer 53 stacked on the base substrate 41 .
  • a fourth insulating film is deposited on the base substrate forming the above structure, and the fourth insulating film is patterned by a patterning process to form the fourth insulating layer 54 .
  • the fourth insulating film is patterned by a patterning process to form the fourth insulating layer 54 .
  • FIG. 3 at least two first via holes are opened on the fourth insulating layer 54 of the display area 10, and the fourth insulating layer 54, the third insulating layer 53 and the second insulating layer in the two first via holes 53 is etched away, exposing both ends of the first active layer.
  • a plurality of second via holes and a plurality of third via holes are opened on the fourth insulating layer 54 of the first wiring lead-out area 201, and the fourth insulating layer 54 in the plurality of second via holes is etched away, exposing the The surface of the second wiring layer, the fourth insulating layer 54 and the third insulating layer 53 in the plurality of third via holes are etched away, exposing the surface of the first wiring layer.
  • the bending region 202 includes: a first insulating layer 51 , a second insulating layer 52 , a third insulating layer 53 and a fourth insulating layer 54 stacked on the base substrate.
  • the first groove and the second groove can be formed in the bending region 202 by two etching processes.
  • the fourth insulating layer 54 in the bending region 202 is etched through the first mask (EBA MASK, Etch Bending A MASK) to form a first groove and expose the surface of the third insulating layer 53.
  • the third insulating layer 53, the second insulating layer 52 and the first insulating layer 51 in the first groove in the bending region 202 are etched through the second mask (EBB MASK, Etch Bending B MASK), exposing the lining surface of the base substrate 41 .
  • the bending area 202 is dug with EBA MASK and EBB MASK, which can reduce the thickness of the bending area 202 and improve the bending effect.
  • the film layer structure of the display region 10 remains unchanged.
  • a third conductive film is deposited on the base substrate forming the above structure, and the third conductive film is patterned by a patterning process to form a source-drain metal layer and a third wiring layer. As shown in FIG. 3, FIG. 6A and FIG.
  • the source-drain metal layer at least includes: a first source electrode, a first drain electrode, and a plurality of data lines formed in the display area 10;
  • the third wiring layer at least includes: The first sub-power line 331, the third sub-power line 341a and 341b of the first wiring lead-out area 201, the first power connection line 332a and 332b, the second power connection line 342a and 342b, the contacts formed in the bending area 202 Control signal connection line 372, data connection line 352a and 352b, drive control connection line 362a and 362b, PCD signal connection line 382a and 382b, the second sub-power supply line 333 formed in the second routing lead-out area 203, the fourth sub-power supply line Lines 343a and 343b.
  • the first source electrode and the first drain electrode in the display area 10 are respectively connected to the first active layer through the first via hole.
  • Two ends of at least one data connection line are respectively connected to the first sub-data lead in the first lead-out area 201 and the second data sub-lead in the second lead-out area through the second via hole.
  • Two ends of at least one data connection line are respectively connected to the first sub-data lead in the first lead-out area 201 and the second sub-data lead in the second lead-out area through the third via hole.
  • At least one driving control connection line is connected to the first sub-driving signal line in the first routing area and the second sub-driving signal line in the second routing area through the second via hole.
  • the PCD signal connection line is connected to the first sub-PCD signal line in the first wiring lead-out area and the second sub-PCD signal line in the second wiring lead-out area through the second via hole.
  • the first sub-power line 331 , the first power connection lines 332 a and 332 b , and the second sub-power line 333 may have an integral structure.
  • the third sub-power line 341a, the second power connection line 342a and the fourth sub-power line 343a can be integrated, and the third sub-power line 341b, the second power connection line 342b and the fourth sub-power line 343b can be integrated.
  • the driving circuit layer of the display area is prepared on the base substrate.
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode form the first transistor 401, the first capacitor electrode and the second capacitor electrode
  • the electrodes form the first storage capacitor 402 .
  • the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may use silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride Any one or more of (SiON), which can be single-layer, multi-layer or composite layer.
  • the first insulating layer 51 can be used to improve the water and oxygen resistance of the base substrate 41 .
  • the first metal film, the second metal film and the third metal film can adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) any one or More, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • the first metal film and the second metal film can be made of metal Mo
  • the third metal film can be made of Ti/Al/Ti.
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si)
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • One or more materials such as hexathiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology and organic technology.
  • a fifth insulating film is deposited on the base substrate forming the aforementioned structure, and a fifth insulating layer 55 is formed through a patterning process, as shown in FIG. 3 .
  • a first planar thin film is coated on the base substrate 10 with the above structure to form a first planar layer 56 covering the entire base substrate 10 .
  • the bending region 202 includes: the base substrate 41 , and the third wiring layer and the first planar layer 56 sequentially disposed on the base substrate 41 .
  • a transparent conductive film is deposited, and the transparent conductive film is patterned by a patterning process to form the pattern of the first electrode 431 .
  • a pixel definition film is coated, and a pixel definition layer (PDL, Pixel Definition Layer) 434 pattern is formed through masking, exposure, and development processes. As shown in FIG. 3 and FIG. 8 , the pixel definition layer 434 is formed in the display area 10 , the first routing area 201 , the bending area 202 and the second routing area 203 .
  • a pixel opening is opened on the pixel definition layer 434 of the display area 10 , and the pixel definition film in the pixel opening is developed to expose the surface of the first electrode 431 .
  • the pixel definition layer 434 of the first routing area 201 , the bending area 202 and the second routing area 203 covers the first flat layer 56 .
  • the organic light-emitting layer 432 and the second electrode 433 are sequentially formed on the base substrate 41 formed with the aforementioned pattern.
  • the organic light-emitting layer 432 may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed in the pixel opening of the display area 10 to realize an organic light-emitting layer.
  • 432 is connected to the first electrode 431 . Since the first electrode 431 is connected to the first drain electrode of the first transistor 401 , light emission control of the organic light emitting layer 432 is realized.
  • a part of the second electrode 433 is formed on the organic light emitting layer 432 . After this patterning process, the film layer structures of the first wire lead-out region 201 , the bent region 202 and the second wire lead-out region 203 remain unchanged.
  • an encapsulation layer 44 is formed on the aforementioned patterned base substrate 10 .
  • the encapsulation layer 44 is formed in the display area 10 , and may adopt a laminated structure of inorganic material/organic material/inorganic material.
  • An organic material layer is disposed between two inorganic material layers. After this patterning process, the film layer structures of the first wire lead-out region 201 , the bent region 202 and the second wire lead-out region 203 remain unchanged.
  • a first touch insulation material is deposited, and the first touch insulation film is patterned by a patterning process to form a first touch insulation (TLD) Layer 451.
  • the first touch insulation layer 451 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer. , multi-layer or composite layer.
  • the touch metal film is deposited, and the touch metal film is patterned by a patterning process, and the touch electrode layer 452 pattern is formed on the first touch insulating layer 451.
  • 202 and the second wiring lead-out area 203 form a touch signal line layer.
  • the pattern of the touch electrode layer 452 includes at least the touch electrodes located in the display area 10 and the connection part.
  • the touch electrodes and connections can be in the form of a metal mesh.
  • the touch signal line layer includes: the second touch signal line located in the frame area 22, the first sub-touch signal line located in the first wiring lead-out area 201, the second sub-touch signal line located in the second wiring lead-out area Wire. As shown in FIG.
  • the touch metal film can adopt a single-layer structure, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • a single-layer structure such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • Various, or a stacked structure can be used, such as Ti/Al/Ti, etc.
  • a protective film is coated to form a touch protective layer 455 covering the pattern of the touch electrode layer and the touch signal line layer.
  • the touch protection layer 455 may use polyimide (PI) or the like.
  • the touch structure layer pattern is prepared.
  • organic materials such as polyimide, acrylic or polyethylene terephthalate may be used for the first flat layer and the pixel definition layer.
  • the display panel can be peeled off from the glass carrier through a peeling process.
  • the preparation process of this exemplary embodiment can be realized by using existing mature preparation equipment, the improvement to the existing process is small, and it can be well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, high in production efficiency, and Low cost and high yield.
  • the structure of the display panel of this exemplary embodiment and the manufacturing process thereof are merely exemplary illustrations.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the display area may be provided with a first source-drain metal layer and a second source-drain metal layer
  • the first source-drain metal layer may include the first source electrode and the first drain electrode of the first transistor
  • the second source-drain metal layer may include
  • the connecting electrode is configured to be connected to the first drain electrode and the first electrode of the light emitting element.
  • the wiring in the bending area may be in the same layer structure as the first source-drain metal layer or the second source-drain metal layer in the display area.
  • the first driving control signal line and the first gate metal layer in the display area may have the same layer structure. However, this embodiment does not limit it.
  • FIG. 10 is another partial cross-sectional schematic view along the P-P direction in FIG. 4 .
  • the first groove and the second groove are formed in the bending region 202 through two etching processes, and in the bending region 202
  • An organic filling layer 61 is formed.
  • the organic filling layer 61 is located in the first groove and the second groove.
  • a source-drain metal layer and a third wiring layer are prepared on the base substrate 41 .
  • the source-drain metal layer is located in the display area 10, and the third wiring layer at least includes: the first sub-power supply line 331 formed in the first wiring lead-out area 201, the third sub-power supply line 341a and 341b formed in the bending area 202
  • the first power connection lines 332a and 332b, the second power supply connection lines 342a and 342b, the touch signal connection lines 372, the data connection lines 352a and 352b, the drive control connection lines 362a and 362b, and the PCD signal connection lines 382a and 382b are formed on The second sub-power supply line 333 and the fourth sub-power supply lines 343 a and 343 b of the second routing lead-out area 203 .
  • FIG. 11 is another schematic structural diagram of a display area of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic partial cross-sectional view along the R-R direction in FIG. 1 .
  • FIG. 12 is a partial plan view of a touch structure layer of a display panel according to at least one embodiment of the present disclosure.
  • an FMLOC structure formed by integrating a mutual capacitive touch structure into a display panel is taken as an example for illustration.
  • the touch structure layer of the display area may include a plurality of first touch units 210 and a plurality of second touch units 220 .
  • the first touch unit 210 has a line shape extending along the second direction D2, a plurality of first touch units 210 are arranged in sequence along the first direction D1, the second touch unit 220 has a line shape extending along the first direction D1, The plurality of second touch units 220 are arranged in sequence along the second direction D2.
  • Each first touch unit 210 includes a plurality of first touch electrodes 211 and first connecting portions 212 sequentially arranged along the second direction D2, and the first touch electrodes 211 and the first connecting portions 212 are arranged alternately and connected in sequence.
  • Each second touch unit 220 includes a plurality of second touch electrodes 221 arranged in sequence along the first direction D1, the plurality of second touch electrodes 221 are arranged at intervals, and adjacent second touch electrodes 221 are connected through the second The parts 222 are connected to each other.
  • the film layer where the second connecting portion 222 is located is different from the film layer where the first touch electrode 211 and the second touch electrode 221 are located.
  • the first touch electrodes 211 and the second touch electrodes 221 are alternately arranged in a third direction D3, and the third direction D3 intersects the first direction D1 and the second direction D2.
  • a plurality of first touch electrodes 211, a plurality of second touch electrodes 221, and a plurality of first connecting parts 212 can be arranged on the touch layer in the same layer, and can be patterned through the same patterning process.
  • the first touch electrode 211 and the first connecting portion 212 may be an integral structure connected to each other.
  • the second connecting portion 222 may be disposed on the bridging layer to connect adjacent second touch electrodes 221 to each other through via holes, and a second touch insulating layer is disposed between the touch electrode layer and the bridging layer.
  • first touch electrodes 211, multiple second touch electrodes 221 and multiple second connecting parts 222 can be arranged on the touch electrode layer in the same layer, and the second touch electrodes 221 and The second connecting portion 222 may be an integral structure connected to each other, and the first connecting portion 212 may be disposed on a bridging layer to connect adjacent first touch electrodes 211 to each other through via holes.
  • the first touch electrodes may be driving (Tx) electrodes
  • the second touch electrodes may be sensing (Rx) electrodes.
  • the first touch electrodes may be sensing (Rx) electrodes
  • the second touch electrodes may be driving (Tx) electrodes.
  • the first touch electrode 211 and the second touch electrode 221 may have a rhombus shape, for example, may be a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus.
  • the first touch electrodes 211 and the second touch electrodes 221 may have any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons and other polygons. , the present disclosure is not limited here.
  • the first touch electrodes 211 and the second touch electrodes 221 may be in the form of transparent conductive electrodes.
  • the first touch electrode 211 and the second touch electrode 221 may be in the form of a metal grid, the metal grid is formed by interweaving a plurality of metal wires, the metal grid includes a plurality of grid patterns, and the grid A pattern is a polygon formed by a plurality of metal lines.
  • the first touch electrodes 211 and the second touch electrodes 221 in metal mesh form have the advantages of low resistance, small thickness and fast response speed.
  • the touch structure layer 45 in the display area may include: a first touch insulation layer 451 sequentially disposed on the encapsulation layer 44 , a bridging layer 454 , a second touch insulation layer 453 , a touch electrode layer 452 and a touch protection layer 455 .
  • the structures of the first frame region, the lead-out region and the bending region may be as described in the foregoing embodiments.
  • the second touch signal line in the first frame area and the first touch signal line in the wiring lead-out area may have the same layer structure as the touch electrode layer or the bridge layer in the display area. However, this embodiment does not limit it.
  • FIG. 13 is another structural schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the driving circuit layer 42 may include: a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, and a fourth insulating layer disposed on the substrate 41 in sequence. layer, a first source-drain metal layer, a fifth insulating layer, a first planar layer, a second source-drain metal layer, and a second planar layer.
  • the first source-drain metal layer may at least include a first source electrode and a first drain electrode of the first transistor 401, and the second source-drain metal layer may include at least a connecting electrode, and the connecting electrode may be connected to the first drain electrode and the first drain electrode of the first transistor 401.
  • the first electrode 431 of the light emitting element 43 may be used to connect the first drain electrode and the first drain electrode of the first transistor 401.
  • the third wiring layer of the first wiring drawing area 201 , the bending area 202 and the second wiring drawing area 203 can be connected with the second source and drain of the display area 10
  • the metal layers are of the same layer structure.
  • the third wiring layer may include: the first sub-power supply line 331 in the first wiring lead-out area 201, the third sub-power supply lines 341a and 341b, all the wiring in the bending area 202, the second wiring The second sub-power supply line 333 and the fourth sub-power supply lines 343 a and 343 b of the line lead-out area 203 .
  • this embodiment does not limit it.
  • the first power line and the second power line in the wiring lead-out area may have the same layer structure as the first source-drain metal layer in the display area 10, and the wiring in the bending area 202 may be the first power line in the display area 10.
  • the two source and drain metal layers are of the same layer structure.
  • the first power line and the second power line in the routing area can be in the same layer structure as the second source and drain metal layer of the display area 10, and the wiring in the bending area 202 can be the first source and drain of the display area 10.
  • the metal layers are of the same layer structure.
  • FIG. 14 is another schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 15 is a partial schematic diagram of area S2 in FIG. 14 .
  • the display panel includes: a display area 10 , a first frame area 22 surrounding the display area 10 , and a second frame area located on one side of the display area 10 .
  • the second frame area includes: a wire lead-out area 21 and a signal access area 23 arranged in sequence along a direction away from the display area 10 (ie, the first direction D1).
  • the signal access area 23 communicates with the wiring lead-out area 21 .
  • the signal access area 23 includes: a circuit area 204 and a binding pin area 205 arranged in sequence along a direction away from the display area 10 (ie, the first direction D1 ).
  • the wiring lead-out area 21 includes: a first power supply line 33 disposed on the base substrate, a plurality of first touch signal lines 37, a plurality of first data lead lines , a plurality of first drive control signal lines.
  • the first power line 33 is connected to the third power line 330 of the first frame area 22 .
  • the first touch signal line 37 is connected to the second touch signal line 370 of the first frame area 22 .
  • the first data lead 35 a is connected to the second data lead 350 a of the first frame region 22
  • the first data lead 35 b is connected to the second data lead 350 b of the first frame region 22 .
  • the first drive control signal line 36 a is connected to the second drive control signal line 360 a of the first frame region 22
  • the first drive control signal line 36 b is connected to the second drive control signal line 360 b of the first frame region 22
  • the first power line 33 is connected to the third power line 330 of the first frame area 22
  • the second power line 34 a is connected to the fourth power line 340 a of the first frame area 22
  • the second power line 34 b is connected to the fourth power line 340 b of the first frame area 22 .
  • the first data lead 35a and the second data lead 350a may have an integral structure, and the first data lead 35b and the second data lead 350b may have an integral structure.
  • the first power line 33 and the third power line 330 may have an integral structure.
  • the first touch signal line 37 and the second touch signal line 370 can be integrated.
  • the second power line 34a and the fourth power line 340a may have an integral structure, and the second power line 34b and the fourth power line 340b may have an integral structure.
  • the first drive control signal line 36a and the second drive control signal line 360a of the first frame region 22 may have a different layer structure, and the first drive control signal line 36b and the second drive control signal line 360b of the first frame region 22 may be heterogeneous structure.
  • the second driving control signal lines 360a and 360b and the source-drain metal layer of the display area 10 may have the same layer structure, and the first driving control signal lines 36a and 36b and the first gate metal layer or the second gate metal layer of the display area 10 Layers can be the same layer structure. However, this embodiment does not limit it.
  • the orthographic projection of the plurality of first touch signal lines 37 on the base substrate is the same as that of the plurality of first data leads and the plurality of first driving control signal lines on the substrate.
  • the orthographic projections on the substrate do not overlap.
  • the orthographic projections of the plurality of first touch signal lines 37 on the base substrate are located within the orthographic projections of the first power supply lines 33 on the base substrate.
  • the first power supply line is used to isolate the first touch signal line from the first data lead and the first drive control signal line, thereby reducing the signal interference between the touch signal and the display signal, thereby improving the display performance. and touch effects.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a display panel, including: forming a first power line and at least one first touch signal in the wiring lead-out area between the display area and the signal access area of the base substrate line and at least one first display signal line.
  • the first touch signal line is located on a side of the first power line away from the base substrate, and the first display signal line is located on a side of the first power line close to the base substrate.
  • the orthographic projection of the first touch signal line on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • FIG. 16 is a schematic diagram of a display touch device according to at least one embodiment of the present disclosure.
  • the present embodiment provides a display touch device 91 including the display panel 910 of the foregoing embodiments.
  • the display panel 910 may be an OLED display panel with an integrated touch control structure.
  • the display and touch device 91 may be any product or component with display and touch functions, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the display touch device 91 may be a wearable display device, for example, it may be worn on a human body in some manner.
  • the display and touch control device 91 may be a smart watch, a smart bracelet, and the like. However, this embodiment does not limit it.

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Abstract

一种显示面板，包括：衬底基板。衬底基板包括显示区域、位于显示区域一侧的走线引出区域和信号接入区域。走线引出区域位于显示区域和信号接入区域之间。走线引出区域包括：设置在衬底基板上的至少一条第一电源线、至少一条第一触控信号线以及至少一条第一显示信号线。第一触控信号线位于第一电源线远离衬底基板的一侧，第一显示信号线位于第一电源线靠近衬底基板的一侧。第一触控信号线在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分交叠。

Description

显示面板及其制备方法、显示触控装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板及其制备方法、显示触控装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及其制备方法、显示触控装置。
一方面，本公开实施例提供一种显示面板，包括：衬底基板、显示结构层、触控结构层、至少一条第一电源线、至少一条第一显示信号线以及至少一条第一触控信号线。衬底基板包括显示区域、位于所述显示区域一侧的走线引出区域和信号接入区域，所述走线引出区域位于所述显示区域和信号接入区域之间。显示结构层和触控结构层位于所述显示区域，触控结构层设置在所述显示结构层远离所述衬底基板的一侧。至少一条第一电源线、至少一条第一触控信号线以及至少一条第一显示信号线位于所述走线引出区域。第一电源线与显示结构层连接，第一显示信号线与显示结构层连接，第一触控信号线与触控结构层连接。所述第一触控信号线位于所述第一电源线远离所述衬底基板的一侧，所述第一显示信号线位于所述第一电源线靠近所述衬底基板的一侧。所述第一触控信号线在所述衬底基板上的正投影与所述第一电 源线在所述衬底基板上的正投影至少部分交叠。
在一些示例性实施方式中，所述第一触控信号线在所述衬底基板上的正投影与所述第一显示信号线在所述衬底基板上的正投影没有交叠。
在一些示例性实施方式中，所述第一触控信号线在所述衬底基板上的正投影位于所述第一电源线在所述衬底基板上的正投影内。
在一些示例性实施方式中，所述衬底基板还包括：弯折区域。所述走线引出区域包括：沿着远离所述显示区域的方向依次设置的第一走线引出区域和第二走线引出区域；所述弯折区域位于所述第一走线引出区域和第二走线引出区域之间。所述弯折区域包括：设置在所述衬底基板上的至少一条第一电源连接线、至少一条触控信号连接线、以及至少一条显示信号连接线。所述第一电源连接线、触控信号连接线和显示信号连接线为同层结构，且所述第一电源连接线位于触控信号连接线和显示信号连接线之间。
在一些示例性实施方式中，所述走线引出区域的第一触控信号线包括：位于所述第一走线引出区域的第一子触控信号线、位于所述第二走线引出区域的第二子触控信号线。所述走线引出区域的第一显示信号线包括：位于所述第一走线引出区域的第一子显示信号线、位于所述第二走线引出区域的第二子显示信号线。所述触控信号连接线与所述第一子触控信号线和第二子触控信号线连接；所述显示信号连接线与所述第一子显示信号线和第二子显示信号线连接；所述第一子触控信号线和第二子触控信号线位于所述触控信号连接线远离所述衬底基板的一侧，所述第一子显示信号线和第二子显示信号线位于所述显示信号连接线靠近所述衬底基板的一侧。
在一些示例性实施方式中，所述走线引出区域的第一电源线包括：位于所述第一走线引出区域的第一子电源线、位于所述第二走线引出区域的第二子电源线；所述第一电源连接线与所述第一子电源线和第二子电源线连接；所述第一子电源线、第一电源连接线和第二子电源线为一体结构。
在一些示例性实施方式中，所述弯折区域内的第一电源连接线、触控信号连接线和显示信号连接线均沿第一方向延伸。在第二方向上，所述弯折区域依次排布有至少一条显示信号连接线、至少一条第一电源连接线、至少一条触控信号连接线、至少一条第一电源连接线以及至少一条显示信号连接线。 所述第一方向和第二方向位于同一平面内，且所述第一方向与第二方向垂直。
在一些示例性实施方式中，所述显示结构层至少包括：设置在所述衬底基板上的驱动电路层；所述驱动电路层至少包括：设置在所述衬底基板上的有源层、第一栅金属层、第二栅金属层和源漏金属层。所述弯折区域的第一电源连接线、触控信号连接线和显示信号连接线与所述显示区域的源漏金属层为同层结构。所述走线引出区域的至少一条第一显示信号线与所述显示区域的第一栅金属层或第二栅金属层为同层结构。所述触控结构层至少包括触控电极层。所述走线引出区域的至少一条第一触控信号线与所述显示区域的触控电极层为同层结构。所述走线引出区域的第一电源线与所述显示区域的源漏金属层为同层结构。
在一些示例性实施方式中，所述走线引出区域还包括：至少一条第二电源线。所述弯折区域还包括：设置在所述衬底基板上的至少一条第二电源连接线。所述走线引出区域的第二电源线包括：位于所述第一走线引出区域的第三子电源线和位于所述第二走线引出区域的第四子电源线。所述第二电源连接线与所述第三子电源线和第四子电源线连接。在所述弯折区域，所述第二电源连接线位于显示信号连接线远离第一电源连接线的一侧。
在一些示例性实施方式中，所述走线引出区域包括：多条第一显示信号线。所述多条第一显示信号线被分成第一组第一显示信号线和第二组第一显示信号线；至少一条第一触控信号线在所述衬底基板上的正投影位于第一组第一显示信号线和第二组第一显示信号线在所述衬底基板上的正投影之间。
在一些示例性实施方式中，所述走线引出区域的多条第一显示信号线包括：至少一条第一数据引线、以及至少一条第一驱动控制信号线；所述第一驱动控制信号线在所述衬底基板上的正投影与所述第一触控信号线在所述衬底基板上的正投影相邻。
在一些示例性实施方式中，所述显示结构层包括至少一个发光元件，所述发光元件包括：第一电极、第二电极以及位于所述第一电极和第二电极之间的有机发光层；所述第一电极位于所述第二电极靠近所述衬底基板的一侧。所述衬底基板还包括：位于所述显示区域和所述走线引出区域之间的第一边框区域；所述第一边框区域设置有显示控制电路、至少一条第二触控信号线； 所述第二触控信号线与所述走线引出区域的第一触控信号线连接。在所述第一边框区域内，所述第二触控信号线在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影内。
在一些示例性实施方式中，所述第一电源线为高电压电源线。
在一些示例性实施方式中，所述信号接入区域设置有触控与显示驱动集成(TDDI)电路；所述TDDI电路与所述走线引出区域的第一显示信号线和第一触控信号线连接。
另一方面，本公开实施例提供一种显示触控装置，包括如上所述的显示面板。
另一方面，本公开实施例提供一种显示面板的制备方法，包括：在衬底基板的显示区域依次形成显示结构层和触控结构层，在衬底基板的显示区域和信号接入区域之间的走线引出走线引出区域形成第一电源线、至少一条第一触控信号线和至少一条第一显示信号线。其中，所述第一电源线和第一显示信号线与显示结构层连接，所述第一触控信号线与触控结构层连接。所述第一触控信号线位于第一电源线远离衬底基板的一侧，所述第一显示信号线位于第一电源线靠近衬底基板的一侧；所述第一触控信号线在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的示意图；
图2为本公开至少一实施例的显示面板的触控电极的排布示意图；
图3为图1中沿R-R方向的局部剖面示意图；
图4为图1中区域S1的局部示意图；
图5为本公开至少一实施例的走线引出区域形成第二走线层后的示意图；
图6A为本公开至少一实施例的走线引出区域和弯折区域形成第三走线层后的示意图；
图6B为本公开至少一实施例的走线引出区域和弯折区域形成的第三走线层的示意图；
图7A为本公开至少一实施例的走线引出区域形成触控信号线后的示意图；
图7B为本公开至少一实施例的走线引出区域形成的触控信号线的示意图；
图8为图4中沿P-P方向的局部剖面示意图；
图9为本公开至少一实施例的第二电极屏蔽触控信号线的示意图；
图10为图4中沿P-P方向的另一局部剖面示意图；
图11为本公开至少一实施例的显示面板的显示区域的另一结构示意图；
图12为本公开至少一实施例的显示面板的触控结构层的局部平面示意图；
图13为本公开至少一实施例的显示面板的另一局部剖面示意图；
图14为本公开至少一实施例的显示面板的另一示意图；
图15为图14中区域S2的局部示意图；
图16为本公开至少一实施例的显示触控装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间 的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开实施例提供的显示面板可以集成触控结构。显示面板可以包括液晶显示(LCD)基板，或者可以是有机发光二极管(OLED)显示基板，或者可以是等离子体显示装置(PDP)显示基板，或者可以是电泳显示(EPD)显示基板。在一些示例中，显示面板可以包括OLED显示基板，OLED显示基板可以包括：衬底基板、设置在衬底基板上的驱动电路层、设置在驱动电路层上的发光元件层以及设置在发光元件层上的封装层。触控结构设置在显示基板的封装层上，形成触控结构在薄膜封装上(Touch on Thin Film Encapsulation，简称Touch on TFE)的结构，显示结构和触控结构集成在一起，具有轻薄、可折叠等优点，可以满足柔性折叠、窄边框等产品需求。
Touch on TFE结构主要包括柔性多层覆盖表面式(Flexible Multi-Layer On Cell，简称FMLOC)结构和柔性单层覆盖表面式(Flexible Single-Layer On Cell，简称FSLOC)结构。FMLOC结构是基于互容检测的工作原理，一般采用两层金属形成驱动(Tx)电极和感应(Rx)电极，集成电路(IC)通过检测驱动电极和感应电极间的互容来实现触控动作。FSLOC结构是基于自容(或电压)检测的工作原理，一般采用单层金属形成触控电极，集成电路通过检测触控电极自容(或电压)来实现触控动作。
本公开至少一实施例提供一种显示面板，包括：衬底基板、显示结构层、触控结构层、至少一条第一电源线、至少一条第一显示信号线以及至少一条第一触控信号线。衬底基板包括：显示区域、位于显示区域一侧的走线引出区域和信号接入区域。走线引出区域位于显示区域和信号接入区域之间。显 示结构层和触控结构层位于显示区域，触控结构层设置在显示结构层远离衬底基板的一侧。至少一条第一电源线、至少一条第一触控信号线和至少一条第一显示信号线位于走线引出区域。第一电源线与显示结构层连接，第一显示信号线与显示结构层连接，第一触控信号线与触控结构层连接。第一触控信号线位于第一电源线远离衬底基板的一侧，第一显示信号线位于第一电源线靠近衬底基板的一侧。第一触控信号线在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分交叠。
本公开实施例提供的显示面板，在走线引出区域，利用第一电源线将第一触控信号线和第一显示信号线隔离。由于第一电源线传输直流信号，且直流信号无法穿过膜层之间形成的平板电容结构，利用第一电源线可以降低第一触控信号线和第一显示信号线之间产生的信号干扰，从而提高显示和触控效果。
在一些示例性实施方式中，在走线引出区域内，第一触控信号线在衬底基板上的正投影与第一显示信号线在衬底基板上的正投影没有交叠。本示例性实施方式中，可以避免第一触控信号线和第一显示信号线在垂直于衬底基板方向存在交叠而形成电容结构，可以降低信号串扰影响，从而提高显示和触控效果。
在一些示例性实施方式中，第一触控信号线在衬底基板上的正投影位于第一电源线在衬底基板上的正投影内。本示例性实施方式中，利用第一电源线在衬底基板上的正投影覆盖第一触控信号线在衬底基板上的正投影，可以降低走线引出区域的第一触控信号线和第一显示信号线之间产生的信号串扰，从而提高显示和触控效果。
在一些示例性实施方式中，衬底基板还可以包括：弯折区域。走线引出区域包括：沿着远离显示区域的方向依次设置的第一走线引出区域和第二走线引出区域。弯折区域位于第一走线引出区域和第二走线引出区域之间。弯折区域包括：设置在衬底基板上的至少一条第一电源连接线、至少一条触控信号连接线以及至少一条显示信号连接线。第一电源连接线、触控信号连接线和显示信号连接线为同层结构，且第一电源连接线位于触控信号连接线和显示信号连接线之间。在本示例性实施方式中，在弯折区域采用第一电源连 接线将触控信号连接线和显示信号连接线分隔开，可以降低显示信号连接线和触控信号连接线之间的信号干扰，从而提高显示和触控效果。
在一些示例性实施方式中，走线引出区域的第一触控信号线包括：位于第一走线引出区域的第一子触控信号线、位于第二走线引出区域的第二子触控信号线。走线引出区域的第一显示信号线包括：位于第一走线引出区域的第一子显示信号线、位于第二走线引出区域的第二子显示信号线。触控信号连接线与第一子触控信号线和第二子触控信号线连接。显示信号连接线与第一子显示信号线和第二子显示信号线连接。第一子触控信号线和第二子触控信号线位于触控信号连接线远离衬底基板的一侧，第一子显示信号线和第二子显示信号线位于显示信号连接线靠近衬底基板的一侧。在本示例性实施方式中，利用弯折区域的显示信号连接线连接第一走线引出区域和第二走线引出区域的对应子显示信号线，利用弯折区域的触控信号连接线连接第一走线引出区域和第二走线引出区域的对应子触控信号线，可以实现显示信号和触控信号的传输。
在一些示例性实施方式中，走线引出区域的第一电源线包括：位于第一走线引出区域的第一子电源线、位于第二走线引出区域的第二子电源线。第一电源连接线与第一子电源线和第二子电源线连接。第一子电源线、第一电源连接线和第二子电源线可以为一体结构。然而，本实施例对此并不限定。例如，第一子电源线和第二子电源线可以为同层结构，且与第一电源连接线为异层结构。在本示例性实施方式中，利用弯折区域的第一电源连接线连接第一走线引出区域和第二走线引出区域内的子电源线，实现第一电源信号的传输。
在一些示例性实施方式中，弯折区域内的第一电源连接线、触控信号连接线和显示信号连接线均沿第一方向延伸。在第二方向上，弯折区域依次排布有至少一条显示信号连接线、至少一条第一电源连接线、至少一条触控信号连接线、至少一条第一电源连接线以及至少一条显示信号连接线。第一方向和第二方向位于同一平面内，且第一方向与第二方向垂直。在本示例性实施方式中，第一电源连接线将显示信号连接线和触控信号连接线隔开，可以降低显示信号连接线和触控信号连接线之间的信号干扰，从而提高显示和触 控效果。
在一些示例性实施方式中，显示结构层至少包括：设置在衬底基板上的驱动电路层。驱动电路层至少包括：设置在衬底基板上的有源层、第一栅金属层、第二栅金属层和源漏金属层。弯折区域的第一电源连接线、触控信号连接线和显示信号连接线与显示区域的源漏金属层为同层结构。走线引出区域的至少一条第一显示信号线与显示区域的第一栅金属层或第二栅金属层为同层结构。触控结构层至少包括触控电极层。走线引出区域的至少一条第一触控信号线与显示区域的触控电极层为同层结构。走线引出区域的第一电源线与显示区域的源漏金属层为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，走线引出区域还包括：设置在衬底基板上的至少一条第二电源线，弯折区域还包括：设置在衬底基板上的至少一条第二电源连接线。走线引出区域的第二电源线包括：位于第一走线引出区域的第三子电源线和位于第二走线引出区域的第四子电源线。第二电源连接线与第三子电源线和第四子电源线连接。在弯折区域，第二电源连接线位于显示信号连接线远离第一电源连接线的一侧。在一些示例中，第二电源线可以为低电压电源线VSS。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一电源线可以为高电压电源线VDD。然而，本实施例对此并不限定。例如，第一电源线可以为低电压电源线VSS。
在一些示例性实施方式中，走线引出区域包括：多条第一显示信号线。多条第一显示信号线被分成第一组第一显示信号线和第二组第一显示信号线；至少一条第一触控信号线在衬底基板上的正投影位于第一组第一显示信号线和第二组第一显示信号线在衬底基板上的正投影之间。然而，本实施例对此并不限定。
在一些示例性实施方式中，走线引出区域的多条第一显示信号线包括：至少一条第一数据引线、以及至少一条第一驱动控制信号线。第一驱动控制信号线在衬底基板上的正投影与第一触控信号线在衬底基板上的正投影相邻。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示结构层包括至少一个发光元件。发光元件包括：第一电极、第二电极以及位于第一电极和第二电极之间的有机发光 层。第一电极位于第二电极靠近衬底基板的一侧。衬底基板还包括：位于显示区域和走线引出区域之间的第一边框区域。第一边框区域设置有显示控制电路、至少一条第二触控信号线。第二触控信号线与走线引出区域的第一触控信号线连接。在第一边框区域内，第二触控信号线在衬底基板上的正投影位于第二电极在衬底基板上的正投影内。在本示例性实施方式中，在第一边框区域，利用发光元件的第二电极对第二触控信号线进行屏蔽，可以降低显示信号和触控信号之间的信号干扰，从而提高显示和触控效果。
在一些示例性实施方式中，信号接入区域设置有触控与显示驱动集成(TDDI，Touch and Display Driver Integration)电路。TDDI电路与走线引出区域的第一显示信号线和第一触控信号线连接。本示例性实施方式中，采用TDDI电路进行显示和触控驱动控制，有利于实现显示面板的轻薄化，可以简化显示面板的制备工艺、降低成本、并提高显示面板的性能。然而，本实施例对此并不限定。
下面通过多个示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示面板的示意图。在本示例性实施方式中，以显示面板集成自容式触控结构，形成FSLOC结构为例进行说明。
在一些示例性实施方式中，如图1所示，显示面板包括：显示区域10、围绕显示区域10的第一边框区域22、位于显示区域10一侧的第二边框区域。第二边框区域包括沿着远离显示区域10的方向(即第一方向D1)依次设置的第一走线引出区域201、弯折区域202、第二走线引出区域203和信号接入区域23。第一走线引出区域201位于第一边框区域22远离显示区域10的一侧。第一走线引出区域201与第一边框区域22连通。信号接入区域23位于第二走线引出区域203远离显示区域10的一侧。信号接入区域23与第二走线引出区域203连通。信号接入区域23包括：沿着远离显示区域10的方向(即第一方向D1)依次设置的电路区204和绑定引脚区205。
在一些示例性实施方式中，弯折区域202配置为使得第二走线引出区域203、信号接入区域23弯折到显示区域10的背面。电路区204配置为设置相应的集成电路。绑定引脚区205配置为设置多个绑定引脚，多个绑定引脚可以绑定柔性电路板(FPC，Flexible Printed Circuit)，使得多条信号引线(例 如，驱动控制线、电源线等)通过多个绑定引脚与外部控制装置连接。在一些示例中，电路区204设置的集成电路可以是触控与显示驱动器集成电路(TDDI，Touch and Display Driver Integration)。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，显示区域10可以为圆形。然而，本实施例对此并不限定。例如，显示区域10可以为矩形、或者椭圆形等其它形状。
在一些示例性实施方式中，显示区域10包括：依次设置在衬底基板上的显示结构层和触控结构层。显示结构层包括多个显示单元(即子像素)、多条栅线以及多条数据线。多条栅线和多条数据线在衬底基板上的正投影交叉形成多个子像素区域。一个子像素设置在一个子像素区域内。多条数据线与多个子像素电连接，多条数据线配置为向子像素提供数据信号。多条栅线与多个子像素电连接，多条栅线配置为向多个子像素提供栅极驱动信号。
在一些示例中，一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列，本实施例对此不做限定。
在一些示例性实施方式中，触控结构层包括多个触控单元。至少一个触控单元可以包括至少一个触控电极。至少一个触控电极在衬底基板上的正投影可以包含多个子像素在衬底基板上的正投影。当触控单元包括多个触控电极，多个触控电极可以间隔设置，且相邻的触控电极之间可以通过连接部彼此连接。触控电极和连接部可以为同层结构。在一些示例中，触控电极可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。然而，本实施例对此并不限定。在一些示例中，触控电极可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种。
图2为本公开至少一实施例的显示面板的触控电极的排布示意图。在一些示例性实施方式中，以显示区域10包括24个自容式触控电极为例进行示意。如图2所示，在平行于显示面板的平面内，显示区域10可以包括24个规则排布的触控电极100。在一些示例中，矩形状的第一电极区101可以包括矩阵排布的4行*4列触控电极100，每个触控电极100的形状可以为矩形，16个触控电极100的面积可以相同。圆冠形状的第二电极区102和第三电极区103可以均包括两个触控电极100，两个触控电极100可以沿第二方向D2依次设置，每个电极区中的两个触控电极100的面积可以相同，第二电极区102中触控电极100的面积和第三电极区103中触控电极100的面积可以相同。圆冠形状的第四电极区104和第五电极区105可以均包括两个触控电极100，两个触控电极100沿着第一方向D1依次设置，每个电极区中的两个触控电极100的面积可以相同，第四电极区104中触控电极100的面积和第五电极区105中触控电极100的面积可以相同。在一些示例中，显示区域10中的多个触控电极100可以相对于中心线O对称设置，中心线O可以为沿着第一方向D1延伸且均分显示区域10的中心线。
在一些示例中，显示面板中的触控电极可以是金属网格形式，金属网格由多条金属线交织形成，金属网格包括多个网格图案，网格图案是由多条金属线围成的多边形，金属网格形式的触控电极具有电阻小、厚度小和反应速度快等优点。然而，本实施例对此并不限定。
图3为图1中沿R-R方向的局部剖面示意图。在一些示例性实施方式中，如图3所示，在垂直于显示面板的平面内，显示区域10包括：衬底基板41、依次设置在衬底基板41上的驱动电路层42、发光元件43、封装层44以及触控结构层45。图3中仅以一个子像素的结构为例进行示意。
在一些示例性实施方式中，衬底基板41可以是柔性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。其中，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可 以采用非晶硅(a-si)。然而，本实施例对此并不限定。
在一些示例性实施方式中，驱动电路层42包括形成像素驱动电路的多个晶体管和至少一个存储电容，像素驱动电路可以为2T1C(即两个薄膜晶体管和一个电容)、3T1C(即三个薄膜晶体管和一个电容)或7T1C(即七个薄膜晶体管和一个电容)设计。图3中以一个第一晶体管和一个第一存储电容为例进行示意。显示区域10的驱动电路层42可以包括：设置在衬底基板41上的第一绝缘层51、设置在第一绝缘层51上的有源层、覆盖有源层的第二绝缘层52、设置在第二绝缘层52上的第一栅金属层、覆盖第一栅金属层的第三绝缘层53、设置在第三绝缘层53上的第二栅金属层、覆盖第二栅金属层的第四绝缘层54、设置在第四绝缘层54上的源漏金属层。有源层可以至少包括第一有源层，第一栅金属层可以至少包括第一栅电极和第一电容电极，第二栅金属层可以至少包括第二电容电极，源漏金属层可以至少包括第一源电极和第一漏电极。第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管401，第一电容电极和第二电容电极组成第一存储电容402。
在一些示例性实施方式中，发光元件43可以包括第一电极431、像素定义层434、有机发光层432和第二电极433。第一电极431设置在第一平坦层56上，通过第一平坦层56和第五绝缘层55上开设的第一过孔与第一晶体管401的第一漏电极连接。像素定义层434设置在第一电极431和第一平坦层56上，像素定义层434上设置有像素开口，像素开口暴露出第一电极431。有机发光层432至少部分设置在像素开口内，有机发光层432与第一电极431连接。第二电极433设置在有机发光层432上，第二电极433与有机发光层432连接。
在一些示例性实施方式中，发光元件43的有机发光层432可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)中的一个或多个膜层。在第一电极431和第二电极433的电压驱动下，利用有机材料的发光特性根据需要的灰度发光。
在一些示例性实施方式中，不同颜色的发光元件的发光层不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例性实施方式中，封装层44可以包括叠设的第一封装层、第二封装层和第三封装层。其中，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件43。然而，本实施例对此并不限定。例如，封装层可以采用无机/有机/无机/有机/无机的五层叠设结构。
在一些示例性实施方式中，触控结构层45可以包括：设置在封装层44远离衬底基板41一侧的第一触控绝缘层451、设置在第一触控绝缘层451远离衬底基板41一侧的触控电极层452以及设置在触控电极层452远离衬底基板41一侧的触控保护层455。然而，本实施例对此并不限定。
图4为图1中区域S1的局部示意图。图5为本公开至少一实施例的走线引出区域形成第二走线层后的示意图。在本示例中，走线引出区域包括：第一走线引出区域201和第二走线引出区域203。走线引出区域的第二走线层与显示区域10的第二栅金属层可以为同层结构，走线引出区域的第一走线层与显示区域10的第一栅金属层可以为同层结构。图6A为本公开至少一实施例的走线引出区域和弯折区域形成第三走线层后的示意图。图6B为本公开至少一实施例的走线引出区域和弯折区域形成的第三走线层的示意图。走线引出区域和弯折区域的第三走线层与显示区域10的源漏金属层可以为同层结构。图7A为本公开至少一实施例的走线引出区域形成触控信号线后的 示意图。图7B为本公开至少一实施例的走线引出区域形成的触控信号线的示意图。本示例中，触控信号线与显示区域10的触控电极层可以为同层结构。图8为图4中沿P-P方向的局部剖面示意图。在一些示例中，走线引出区域的走线可以相对于中心线O对称，弯折区域的走线可以相对于中心线O对称。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，走线引出区域包括：第一走线引出区域201和第二走线引出区域203，弯折区域202位于第一走线引出区域201和第二走线引出区域203之间。第一走线引出区域201位于第一边框区域22远离显示区域10的一侧。走线引出区域内的多条第一显示信号线包括：多条第一数据引线、多条第一驱动控制信号线。弯折区域202的多条显示信号连接线包括：多条数据连接线、多条驱动控制连接线。在图4至图7B中对多条第一数据引线、多条第一驱动控制信号线、多条第一触控信号线、多条数据连接线、多条驱动控制连接线、多条触控信号连接线分别进行整体示意，本实施例对于第一数据引线、第一驱动控制信号线、第一触控信号线、数据连接线、驱动控制连接线和触控信号连接线的数目并不限定。
在一些示例性实施方式中，如图4和图5所示，走线引出区域的至少一条第一数据引线包括：位于第一走线引出区域201的第一子数据引线、位于第二走线引出区域203的第二子数据引线。第一子数据引线和第二子数据引线之间通过弯折区域202的数据连接线连接。例如，第一数据引线35a包括：第一子数据引线351a和对应的第二子数据引线353a，第一数据引线35b包括：第一子数据引线351b和对应的第二子数据引线353b。弯折区域202的数据连接线352a连接第一子数据引线351a和对应的第二子数据引线353a，数据连接线352b连接第一子数据引线351b和对应的第二子数据引线353b。第一子数据引线351a可以延伸到第一边框区域22，与第一边框区域22的第二数据引线350a；第一子数据引线351b可以延伸到第一边框区域22，与第一边框区域22的第二数据引线350b连接。在一些示例中，第一子数据引线351a与对应连接的第二数据引线350a可以为一体结构，第一子数据引线351b与对应连接的第二数据引线350b可以为一体结构。第二子数据引线353a和353b可以沿第一方向D1延伸到电路区204，例如与电路区204的TDDI电 路连接。
在一些示例性实施方式中，如图4、图5和图6B所示，走线引出区域的至少一条第一驱动控制信号线至少包括：位于第一走线引出区域201的第一子驱动控制信号线、位于第二走线引出区域203的第二子驱动控制信号线、第三子驱动控制信号线、第四子驱动控制信号线和第五子驱动控制信号线。第一子驱动控制信号线和第二子驱动控制信号线之间通过弯折区域202的驱动控制连接线连接。例如，第一驱动控制信号线36a包括：第一子驱动信号线361a、以及依次连接的第二子驱动信号线363a、第三子驱动信号线364a、第四子驱动信号线365a、第五子驱动信号线366a。第二驱动控制信号线36b包括：第一子驱动信号线361b、以及依次连接的第二子驱动信号线363b、第三子驱动信号线364b、第四子驱动信号线365b、第五子驱动信号线366b。弯折区域202的驱动控制连接线362a连接第一子驱动信号线361a和第二子驱动信号线363a。弯折区域202的驱动控制连接线362b连接第一子驱动信号线361b和第二子驱动信号线363b。第一子驱动信号线361a和361b可以分别与第一边框区域22的第二驱动控制信号线360a和360b连接，并与第一边框区域22内的ESD电路32连接。第二子驱动信号线363a和363b均沿第一方向D1延伸。第三子驱动信号线364a位于第二子数据引线353a的右侧，朝着靠近第二子数据引线353a的一侧，依次沿第一方向D1和第二方向D2延伸，以与第四子驱动信号线365a和第五子驱动信号线366a连接。第三子驱动信号线364b位于第二子数据引线353b的左侧，朝着靠近第二子数据引线353b的一侧，依次沿第一方向D1和第二方向D2延伸，以与第四子驱动信号线365b和第五子驱动信号线366b连接。第四子驱动信号线365a位于第二子数据引线353a的左侧，朝着远离第二子数据引线353a的一侧，依次沿第二方向D2和第三方向D3延伸。第四子驱动信号线365b位于第二子数据引线353b的右侧，朝着远离第二子数据引线353b的一侧，依次沿第二方向D2和第三方向D3延伸。第三方向D3与第一方向D1和第二方向D2均交叉。第四子驱动信号线365a和365b可以延伸到绑定引脚区，与绑定引脚区的绑定引脚连接。第五子驱动信号线366a和366b可以沿第一方向D1延伸到电路区，例如与电路区的TDDI电路连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4和图7B所示，走线引出区域的至少一条第一触控信号线包括：位于第一走线引出区域201的第一子触控信号线、位于第二走线引出区域203的第二子触控信号线。第一子触控信号线和第二子触控信号线之间通过弯折区域202的触控信号连接线连接。例如，至少一条第一触控信号线37包括：位于第一走线引出区域201的第一子触控信号线371、位于第二走线引出区域203的第二子触控信号线373。第一子触控信号线371和第二子触控信号线373之间通过弯折区域202的触控信号连接线372连接。第一子触控信号线371可以与第一边框区域22的第二触控信号线370连接。第二子触控信号线373可以沿第一方向D1延伸到电路区，例如与电路区的TDDI电路连接。在一些示例中，第一触控信号线37和第二触控信号线370可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4和图6B所示，走线引出区域的第一电源线33可以包括：位于第一走线引出区域201的第一子电源线331、位于第二走线引出区域203的第二子电源线333。第一子电源线331可以与第一边框区域22内的第三电源线330连接。第一子电源线331和第二子电源线333之间通过弯折区域202的第一电源连接线332a和332b连接。第一子电源线331在靠近弯折区域202的一端具有第一缺口M1。第一子电源线331具有第一缺口M1的一端与第一电源连接线332a和332b连接。第二子电源线333具有第一延伸部333a、第二延伸部333b和第三延伸部333c。第三延伸部333c沿第一方向D1延伸。第三延伸部333c在靠近弯折区域202的一端具有第二缺口M2。第三延伸部333c具有第二缺口M2的一端与第一电源连接线332a和332b连接。第一延伸部333a位于第三延伸部333c的左侧，朝着远离第三延伸部333c的一侧，依次沿第二方向D2、第一方向D1、第二方向D2和第三方向D3延伸，或者依次沿第二方向D2、第一方向D1、第三方向D3、第二方向D2和第三方向D3延伸。第二延伸部333b位于第三延伸部333c的右侧，朝着远离第三延伸部333c的一侧，依次沿第二方向D2、第一方向D1、第二方向D2和第三方向D3延伸，或者依次沿第二方向D2、第一方向D1、第三方向D3、第二方向D2和第三方向D3延伸。第一延伸部333a和第二延伸部333b可以延伸到绑定引脚区，与绑定引脚区的绑定引脚连接。
在一些示例性实施方式中，如图6B所示，第一电源线33的第一子电源线331、第二子电源线333以及第一电源连接线332a和332b可以为一体结构。然而，本实施例对此并不限定。例如，第一电源连接线332a和332b可以与第一子电源线331和第二子电源线333为异层结构。
在一些示例性实施方式中，如图4和图6B所示，走线引出区域的第二电源线包括：位于第一走线引出区域201的第三子电源线、位于第二走线引出区域203的第四子电源线。第三子电源线和第四子电源线可以通过弯折区域的第二电源连接线连接。例如，第二电源线34a包括：位于第一走线引出区域201的第三子电源线341a、位于第二走线引出区域203的第四子电源线343a；第二电源线34b包括：位于第一走线引出区域201的第三子电源线341b、位于第二走线引出区域203的第四子电源线343b；第二电源连接线342a连接第三子电源线341a和第四子电源线343a，第二电源连接线342b连接第三子电源线341b和第四子电源线343b。第三子电源线341a和341b分别与第一边框区域22的第四电源线340a和340b连接。第四子电源线343a位于第二子电源线333的左侧，朝着远离第二子电源线333的方向，依次沿第一方向D1、第三方向D3、第二方向D2和第三方向D3延伸；第四子电源线343b位于第二子电源线333的右侧，朝着远离第二子电源线333的方向，依次沿第一方向D1、第三方向D3、第二方向D2和第三方向D3延伸。第四子电源线343a和343b可以延伸到绑定引脚区，与绑定引脚区的绑定引脚连接。
在一些示例性实施方式中，如图6B所示，第三子电源线341a、第二电源连接线342a和第四子电源线343a可以为一体结构，第三子电源线341b、第二电源连接线342b和第四子电源线343b可以为一体结构。然而，本实施例对此并不限定。例如，第二电源连接线与第三子电源线和第四子电源线可以为异层结构。
在一些示例性实施方式中，如图4和图5所示，走线引出区域的第一面板裂纹检测(PCD，Panel Crack Detect)信号线包括：位于第一走线引出区域201的第一子PCD信号线、位于第二走线引出区域203的第二子PCD信号线。第一子PCD信号线和第二子PCD信号线通过弯折区域202的PCD连接信号线连接。例如，第一PCD信号线38a包括：位于第一走线引出区域 201的第一子PCD信号线381a、位于第二走线引出区域203的第二子PCD信号线383a；第一PCD信号线38b包括：位于第一走线引出区域201的第一子PCD信号线381b、位于第二走线引出区域203的第二子PCD信号线383b。弯折区域202的PCD连接信号线382a连接第一子PCD信号线381a和第二子PCD信号线383a，PCD连接信号线382b连接第一子PCD信号线381b和第二子PCD信号线383b。第一子PCD信号线381a和381b分别与第一边框区域22的第二PCD信号线380a和380b连接。第二子PCD信号线383a和383b可以延伸到绑定引脚区，与绑定引脚区的绑定引脚连接。在一些示例中，第一子PCD信号线381a与第二PCD信号线380a可以为一体结构，第一子PCD信号线381b与第二PCD信号线380b可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，第一边框区域22的形状可以为围绕显示区域10的环形。如图4所示，第一边框区域22设置有多条第二触控信号线370。至少一条第二触控信号线370的第一端与显示区域10中的一个触控单元连接，第二触控信号线370的第二端沿着显示区域10的边框形状延伸，并与走线引出区域内的第一触控信号线37连接，例如第二触控信号线370延伸至与第一走线引出区域201内的第一子触控信号线371连接。在一些示例中，第二触控信号线370与第一子触控信号线371可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，第一边框区域22还设置有显示控制电路，例如包括：栅极驱动电路(GOA)30、多路复用电路(MUX)31、测试电路(CT)(图未示)和静电释放(ESD)电路32。在一些示例中，栅极驱动电路30可以包括多个级联的移位寄存器单元，每个移位寄存器单元可以连接显示区域10的至少一个扫描信号线，配置为向显示区域10的至少一个扫描信号线提供栅极驱动信号。测试电路可以包括多个测试单元，每个测试单元可以连接显示区域的多个数据信号线，配置为向显示区域10的多个数据信号线提供测试数据信号。多路复用电路31可以包括多个复用单元，每个复用单元可以连接显示区域10的多个数据信号线，配置为使一个信号源为多个数据信号线提供数据信号。在一些示例中，移位寄存器单元可以与复用单 元间隔设置。然而，本实施例对此并不限定。ESD电路32可以包括多个静电释放单元，例如，每个静电释放单元可以连接第一边框区域22的至少一个第二驱动控制信号线，以消除信号线上的静电。
在一些示例性实施方式中，如图4所示，边框区域22设置有多条第二显示信号线，例如包括多条第二数据引线以及多条第二驱动控制信号线。第二数据引线可以与多路复用电路31连接。多条第二数据引线包括第一组第二数据引线350a和第二组第二数据引线350b。第一组第二数据引线350a从显示区域10左侧的第一边框区域22延伸到下侧的第一边框区域22，并与走线引出区域的第一数据引线35a连接，例如延伸到第一走线引出区域201与第一子数据引线351a连接。第二组第二数据引线350b从显示区域10右侧的第一边框区域22延伸到下侧的第一边框区域22，并与走线引出区域的第一数据引线35b连接，例如延伸到第一走线引出区域201与第一子数据引线351b连接。在本示例中，第二数据引线和对应连接的第一数据引线可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，第一边框区域22内的多条第二驱动控制信号线包括第一组第二驱动控制信号线360a和第二组第二驱动控制信号线360b。第一组第二驱动控制信号线360a从显示区域10左侧的第一边框区域22延伸到下侧的第一边框区域22，并在下侧的第一边框区域22与ESD电路32连接，并与走线引出区域的第一驱动控制信号线连接，例如与第一走线引出区域201的第一子驱动控制信号线361a连接。第二组第二驱动控制信号线360b从显示区域10右侧的第一边框区域22延伸到下侧的第一边框区域22，并在下侧的第一边框区域22与ESD电路32连接，并与走线引出区域的第一驱动控制信号线连接，例如与第一走线引出区域201的第一子驱动控制信号线361b连接。在本示例中，第一驱动控制信号线和第二驱动控制信号线可以为异层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，第一边框区域22还设置第三电源线330、第四电源线340a和340b。显示区域10左侧和右侧的第一边框区域22内的第三电源线330沿着显示区域10的边框形状延伸到显示区域10下侧的第一边框区域22，并汇聚在一起延伸到走线引出区域，与走线引出区 域的第一电源线33连接，例如第三电源线330与第一走线引出区域201的第一子电源线331连接。在本示例中，第三电源线330与第一电源线33可以为一体结构。第四电源线340a和340b位于第三电源线330远离显示区域10的一侧，并延伸到走线引出区域，分别与走线引出区域的第二电源线34a和34b连接，例如第四电源线340a与第一走线引出区域201的第四子电源线341a连接，第四电源线340b与第一走线引出区域201的第四子电源线341b连接。在本示例中，第四电源线340a与第二电源线34a可以为一体结构，第四电源线340b与第二电源线34b可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一电源线33和第三电源线330可以为高电压电源线VDD，第二电源线34a和34b、第四电源线340a和340b可以为低电压电源线VSS。通过第一电源线、第二电源线、第三电源线和第四电源线可以提供直流稳定信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4所示，第一边框区域22还设置有第二PCD信号线380a和380b。第二PCD信号线380a位于第四电源线340a远离显示区域10的一侧，第二PCD信号线380b位于第四电源线340a远离显示区域10的一侧。第二PCD信号线380a和380b延伸到走线引出区域，分别与走线引出区域的第一PCD信号线38a和38b连接，例如，第二PCD信号线380a与第一走线引出区域201的第一子PCD信号线381a连接，第二PCD信号线380b与第一走线引出区域201的第一子PCD信号线381b连接。在本示例中，第二PCD信号线380a与第一子PCD信号线381a可以为一体结构，第二PCD信号线380b与第一子PCD信号线381b可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4至图7B所示，第一走线引出区域201设置有多条第一子数据引线351a和351b、多条第一子驱动信号线361a和361b、第一子电源线331、第三子电源线341a和341b、多条第一子触控信号线371以及第一子PCD信号线381a和381b。多条第一子驱动信号线361a和361b在衬底基板上的正投影位于多条第一子数据引线351a和多条第一子数据引线351b在衬底基板上的正投影的中间。多条第一子触控信号线371 在衬底基板上的正投影位于多条第一子驱动信号线361a和361b在衬底基板上的正投影的中间。多条第一子触控信号线371在衬底基板上的正投影与多条第一子数据引线351a和351b以及多条第一子驱动信号线361a和361b在衬底基板上的正投影没有交叠。第一子电源线331在衬底基板上的正投影位于多条第一子数据引线351a和多条第一子数据引线351b在衬底基板上的正投影的中间，且与多条第一子驱动信号线361a和361b在衬底基板上的正投影存在交叠。多条第一子触控信号线371在衬底基板上的正投影与第一子电源线331在衬底基板上的正投影存在交叠，其中，每条第一子触控信号线371在衬底基板上的正投影与第一子电源线331在衬底基板上的正投影均存在交叠。在第一走线引出区域201内，通过第一子电源线331可以将第一子触控信号线与第一子驱动信号线和第一子数据引线隔离开，避免触控信号和显示信号之间相互干扰，屏蔽信号跳变，从而提高显示和触控效果。
在一些示例性实施方式中，如图4和图6A所示，在第一走线引出区域201内，第三子电源线341a在衬底基板上的正投影位于第一子驱动信号线361a在衬底基板上的正投影远离第一子电源线331在衬底基板上的正投影的一侧，第三子电源线341b在衬底基板上的正投影位于第一子驱动信号线361b在衬底基板上的正投影远离第一子电源线331在衬底基板上的正投影的一侧。第一子PCD信号线381a位于第三子电源线341a远离第一子电源线331的一侧，第一子PCD信号线381b位于第三子电源线341b远离第一子电源线331的一侧。
在一些示例性实施方式中，如图4至图7B所示，在第一走线引出区域201内，多条第一子触控信号线371位于第一子电源线331远离衬底基板的一侧，多条第一子数据引线351a和351b、多条第一子驱动信号线361a和361b位于第一子电源线331靠近衬底基板的一侧。在一些示例中，第一子电源线331、第三子电源线341a和341b为同层结构，例如与显示区域10的源漏金属层为同层结构。多条第一子触控信号线371为同层结构，例如与显示区域10的触控电极层为同层结构。多条第一子驱动信号线361a和361b可以为同层结构，例如位于显示区域10的第一栅金属层或第二栅金属层。第一子PCD信号线381a和381b可以与显示区域10的第一栅金属层或第二栅金属层。多 条第一子数据引线351a和351b可以为异层结构。例如，多条第一子数据引线351a和351b依次编号，奇数编号的第一子数据引线与显示区域10的第一栅金属层为同层结构，偶数编号的第一子数据引线与显示区域10的第二栅金属层为同层结构，或者，奇数编号的第一子数据引线与显示区域10的第二栅金属层为同层结构，偶数编号的第一子数据引线与显示区域10的第一栅金属层为同层结构。多条第一子数据引线在衬底基板上的正投影没有交叠。通过将多条第一子数据引出线异层设置，可以减小相邻数据引出线之间的间距，并减小相邻数据引出线的传输干扰，提高信号传输性能。然而，本实施例对此并不限定。在一些示例中，多条第一子数据引线可以同层设置。在一些示例中，至少一条第一子驱动信号线可以包括并联的第一子走线和第二子走线，第一子走线可以与显示区域的第一栅金属层为同层结构，第二子走线可以与显示区域的第二栅金属层为同层结构。
在一些示例性实施方式中，如图4至图7B所示，弯折区域202设置有多条数据连接线352a和352b、多条驱动控制连接线362a和362b、多条触控信号连接线372、第一电源连接线332a和332b、第二电源连接线342a和342b、以及PCD信号连接线382a和382b。多条数据连接线与多条第一子数据引线一一对应连接，多条驱动控制连接线与多条第一子驱动信号线一一对应连接，多条触控信号连接线与多条第一子触控信号线一一对应连接。第一电源连接线332a和332b与第一子电源线331连接。第二电源连接线与对应的第三子电源线连接。
在一些示例性实施方式中，如图6B所示，弯折区域202内的走线均沿第一方向D1延伸，且依次并排设置，相邻走线之间没有电连接。弯折区域202内的走线为同层结构，例如与显示区域10的源漏金属层为同层结构。
在一些示例性实施方式中，如图6A和图6B所示，在弯折区域202内，沿着第二方向D2，PCD信号连接线382a、第二电源连接线342a、多条数据连接线352a、多条驱动控制连接线362a、第一电源连接线332a、触控信号连接线372、第一电源连接线332b、多条驱动控制连接线362b、多条数据连接线352b、第二电源连接线342b以及PCD信号连接线382b依次并排排布。在本示例性实施方式中，第一电源连接线332a和332b位于驱动控制连接线 和触控信号连接线之间，可以实现显示信号和触控信号的隔离，避免触控信号和显示信号之间相互干扰，屏蔽信号跳变，从而提高显示和触控效果。
在一些示例性实施方式中，如图4至图6B所示，触控信号连接线372在衬底基板上的正投影与第一子电源线331和第二子电源线333在衬底基板上的正投影没有交叠。第一子触控信号线371和触控信号连接线372在衬底基板上的正投影的交叠区域位于第一子电源线331的第一缺口M1在衬底基板上的正投影内。第一子触控信号线371与触控信号连接线372通过过孔连接。触控信号连接线372和第二子触控信号线373在衬底基板上的正投影的交叠区域位于第二子电源线333的第三延伸部333c的第二缺口M2在衬底基板上的正投影内。第二子触控信号线372与触控信号连接线372通过过孔连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4至图7B所示，第二走线引出区域203设置有多条第二子数据引线353a和353b、多条第二子驱动信号线363a和363b、多条第三子驱动信号线364a和364b、多条第四子驱动信号线365a和365b、多条第五子驱动信号线366a和366b、多条第二子触控信号线373、第二子电源线333、第四子电源线343a和343b、以及第二子PCD信号线383a和383b。多条第二子触控信号线373在衬底基板上的正投影位于多条第二子驱动信号线363a和363b在衬底基板上的正投影的中间，位于多条第三子驱动信号线364a和364b在衬底基板上的正投影的中间。多条第三子触控信号线373在衬底基板上的正投影与第二子数据引线353a和353b以及第二子驱动信号线至第五子驱动信号线在衬底基板上的正投影均没有交叠。多条第二子触控信号线373在衬底基板上的正投影与第二子电源线333在衬底基板上的正投影存在交叠，其中，每条第二子触控信号线373在衬底基板上的正投影与第二子电源线333在衬底基板上的正投影均存在交叠。例如，多条第二子触控信号线373在衬底基板上的正投影与第二子电源线333的第三延伸部333c在衬底基板上的正投影存在交叠。在本示例性实施方式中，在第二走线引出区域203内，通过第二子电源线333的第三延伸部333c可以将第二子触控信号线373和第二子数据引线以及第二子驱动信号线至第五子驱动信号线隔离，避免触控信号和显示信号之间相互干扰，屏蔽信号跳变，以提高显示 和触控效果。
在一些示例性实施方式中，如图5、图6B和图7B所示，第二子驱动信号线363a和363b、第四子驱动信号线365a和365b、第五子驱动信号线366a和366b可以为同层结构，例如与显示区域10的第一栅金属层或第二栅金属层为同层结构。第三子驱动信号线364a和364b例如与显示区域10的源漏金属层为同层结构。第二子触控信号线373可以与显示区域10的触控电极层为同层结构。第二子电源线333、第四子电源线343a和343b可以与显示区域10的源漏金属层为同层结构。第二子PCD信号线383a和383b可以与显示区域10的第一栅金属层或第二栅金属层为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4、图5和图6B所示，第三子驱动信号线364a在衬底基板上的正投影与第二子数据引线353a在衬底基板上的正投影存在交叠，第三子驱动信号线364b在衬底基板上的正投影与第二子数据引线353b在衬底基板上的正投影存在交叠。第四子驱动信号线365a在衬底基板上的正投影与第二子电源线333的第一延伸部333a在衬底基板上的正投影存在交叠，第四子驱动信号线365b在衬底基板上的正投影与第二子电源线333的第二延伸部333b在衬底基板上的正投影存在交叠。第二子电源线333的第一延伸部333a在衬底基板上的正投影与第二子数据引线353a在衬底基板上的正投影存在交叠，第二子电源连接线333的第二延伸部333b在衬底基板上的正投影与第二子数据引线353b在衬底基板上的正投影存在交叠。第二子电源连接线333的第三延伸部333c在衬底基板上的正投影位于第三子驱动信号线364a和364b在衬底基板上的正投影之间。
在一些示例性实施方式中，在第二走线引出区域203和电路区之间可以设置静电释放区域。静电释放区域可以设置静电释放电路，静电释放电路可以通过消除静电防止显示面板的静电损伤。例如，静电释放电路可以与多个第二子数据引线连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8所示，在垂直于显示面板的平面内，第一走线引出区域201包括：衬底基板41、依次设置在衬底基板41上的第一绝缘层51、第二绝缘层52、第一走线层、第三绝缘层53、第二走线层、 第四绝缘层54、第三走线层、第一平坦层56、像素定义层434、触控信号线层和触控保护层455。在一些示例中，如图4至图7B所示，第一走线层至少包括：多条第一子数据引线351a和351b；第二走线层至少包括：多条第一子数据引线351a和351b、多条第一子驱动信号线361a和361b、第一子PCD信号线381a和381b；第三走线层至少包括：第一子电源线331、第二子电源线341a和341b；触控信号线层至少包括：多条第一子触控信号线371。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8所示，在垂直于显示面板的平面内，弯折区域202包括：衬底基板41、依次设置在衬底基板41上的第三走线层、第一平坦层56、像素定义层434、以及触控保护层455。在一些示例中，如图4至图7B所示，第三走线层至少包括：多条数据连接线352a和352b、多条驱动控制连接线361a和361b、多条触控信号连接线372、第一电源连接线332a和332b、第二电源连接线342a和342b、PCD信号连接线382a和382b。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8所示，在垂直于显示面板的平面内，第二引线区域203包括：衬底基板41、依次设置在衬底基板41上的第一绝缘层51、第二绝缘层52、第一走线层、第三绝缘层53、第二走线层、第四绝缘层54、第三走线层、第一平坦层56、像素定义层434、触控信号线层和触控保护层455。在一些示例中，如图4至图7B所示，第一走线层至少包括：多条第二子数据引线353a和353b；第二走线层至少包括：多条第二子数据引线353a和353b、多条第二子驱动信号线363a和363b、多条第四子驱动信号线365a和365b、多条第五子驱动信号线366a和366b、第二子PCD信号线383a和383b；第三走线层至少包括：第二子电源线333、第四子电源线343a和343b、多条第三子驱动信号线364a和364b；触控信号线层至少包括：多条第二子触控信号线373。然而，本实施例对此并不限定。
图9为本公开至少一实施例的第二电极屏蔽触控信号线的示意图。如图9所示，在一些示例性实施方式中，显示区域10的多个子像素的第二电极433可以为一体结构。在一些示例中，第二电极433与低电压电源线连接。第二电极433可以从显示区域10延伸至第一边框区域22。第一边框区域22内的 多条第二触控信号线370在衬底基板上的正投影位于第二电极433在衬底基板上的正投影内。第二触控信号线370与第一走线引出区域201的第一子触控信号线371连接，例如，可以为一体结构。本示例性实施方式中，通过第二电极对第一边框区域的第二触控信号线进行屏蔽，可以避免第一边框区域的触控信号和显示信号之间相互干扰，从而提高显示和触控效果。
在一些示例性实施方式中，在第一边框区域，通过传输低电压电源信号的第二电极对第二触控信号线进行屏蔽，在走线引出区域，通过传输高电压电源信号的第一电源线对第一触控信号线进行屏蔽，可以降低触控信号和显示信号之间相互干扰产生的显示和触控噪音，从而提高显示和触控效果。
下面参照图3至图8通过显示面板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示面板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于A的正投影范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，显示面板的制备过程可以包括如下操作。
(1)在玻璃载板上制备衬底基板。
在一示例性实施例中，衬底基板41可以为柔性基底，例如包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层 和第二无机材料层。第一柔性材料层、第二柔性材料层的材料采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。第一无机材料层、第二无机材料层的材料采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，第一无机材料层、第二无机材料层也称之为阻挡(Barrier)层。半导体层的材料采用非晶硅(a-si)。
在一些示例性实施方式中，以叠层结构第一柔性材料层/第一阻挡层/半导体层/第二阻挡层/第二柔性材料层为例，其制备过程包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性材料层；随后在第一柔性材料层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的半导体层；然后在半导体层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性材料层；然后在第二柔性材料层上沉积一层阻挡薄膜，形成覆盖第二柔性材料层的第二阻挡层，完成柔性衬底基板41的制备，如图3和图8所示。本次工艺后，显示区域10、第一走线引出区域201、弯折区域202和第二走线引出区域203均包括衬底基板41。
(2)、在衬底基板上制备有源层图案。
在一些示例性实施方式中，在衬底基板41上依次沉积第一绝缘薄膜和有源层薄膜，通过图案化工艺对有源层薄膜进行图案化处理，形成覆盖整个衬底基板41的第一绝缘层51，以及设置在第一绝缘层51上的有源层图案。如图3所示，有源层图案形成在显示区域10，至少包括第一有源层。在本次工艺后，第一走线引出区域201、弯折区域202和第二走线引出区域203包括设置在衬底基板41上的第一绝缘层51。
(3)、在衬底基板上制备第一栅金属层和第一走线层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行构图，形成覆盖有源层的第二绝缘层52，以及设置在第二绝缘层52上的第一栅金属层和第一走线层图案。如图3和图5所示，第一栅金属层形成在显示区域10，至少包括：第一走线层第一栅电极、第一电容电极和多条栅线(图未示)，第一走线层至少包括：形成在走线引出区域的多条第一子数据引线351a和 351b、多条第二子数据引线353a和353b。
(4)、在衬底基板上制备第二栅金属层和第二走线层。
在一些示例性实施方式中，在形成前述结构的衬底基板41上，依次沉积第三绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行构图，形成第三绝缘层53以及第二栅金属层和第二走线层。如图3和图5所示，第二栅金属层至少包括：形成在显示区域10的第二电容电极，第二走线层至少包括：形成在走线引出区域的多条第一子数据引线351a和352a、多条第二子数据引线353a和353b、多条第一子驱动信号线361a和361b、多条第二子驱动信号线363a和363b、多条第四子驱动信号线365a和365b、多条第五子驱动信号线366a和366b、第一子PCD信号线381a和381b、第二子PCD信号线383a和383b。
在本示例性实施方式中，多条第一子数据引线在第一走线层和第二走线层交替排布，多条第二子数据引线在第一走线层和第二走线层交替排布。通过多条第一子数据引线和多条第二子数据引线异层设置，可以减小相邻数据引线之间的间距，并减小相邻数据引线的传输干扰，从而提高信号传输性能。
在本次工艺之后，弯折区域202包括在衬底基板41上叠设的第一绝缘层51、第二绝缘层52和第三绝缘层53。
(5)、在衬底基板上制备第四绝缘层。
在一些示例性实施方式中，在形成上述结构的衬底基板上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行构图，形成第四绝缘层54。如图3所示，显示区域10的第四绝缘层54上开设有至少两个第一过孔，两个第一过孔内的第四绝缘层54、第三绝缘层53和第二绝缘层53被刻蚀掉，暴露出第一有源层的两端表面。第一走线引出区域201的第四绝缘层54上开设有多个第二过孔和多个第三过孔，多个第二过孔内的第四绝缘层54被刻蚀掉，暴露出第二走线层的表面，多个第三过孔内的第四绝缘层54和第三绝缘层53被刻蚀掉，暴露出第一走线层的表面。
在本次工艺后，弯折区域202包括：在衬底基板上叠设的第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54。
在一些示例中，可以通过两次刻蚀工艺在弯折区域202形成第一凹槽和第二凹槽。通过第一次掩模(EBA MASK，Etch Bending A MASK)刻蚀弯折区域202的第四绝缘层54，形成第一凹槽，暴露出第三绝缘层53的表面。通过第二次掩模(EBB MASK，Etch Bending B MASK)刻蚀弯折区域202中的第一凹槽内的第三绝缘层53、第二绝缘层52和第一绝缘层51，暴露出衬底基板41的表面。在本示例中，通过EBA MASK和EBB MASK对弯折区域202进行挖槽，可以减少弯折区域202的厚度，提高弯折效果。
在本次工艺之后，显示区域10的膜层结构没有变化。
(6)、在衬底基板上制备源漏金属层和第三走线层。
在一些示例性实施方式中，在形成上述结构的衬底基板上，沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行构图，形成源漏金属层和第三走线层。如图3、图6A和图6B所示，源漏金属层至少包括：形成在显示区域10的第一源电极、第一漏电极、多条数据线；第三走线层至少包括：形成在第一走线引出区域201的第一子电源线331、第三子电源线341a和341b，形成在弯折区域202的第一电源连接线332a和332b、第二电源连接线342a和342b、触控信号连接线372、数据连接线352a和352b、驱动控制连接线362a和362b、PCD信号连接线382a和382b，形成在第二走线引出区域203的第二子电源线333、第四子电源线343a和343b。显示区域10内的第一源电极和第一漏电极分别通过第一过孔与第一有源层连接。至少一条数据连接线的两端分别通过第二过孔与第一走线引出区域201的第一子数据引线和第二走线引出区域的第二子数据引线连接。至少一条数据连接线的两端分别通过第三过孔与第一走线引出区域201的第一子数据引线和第二走线引出区域的第二子数据引线连接。至少一条驱动控制连接线通过第二过孔与第一走线引出区域的第一子驱动信号线和第二走线引出区域的第二子驱动信号线连接。PCD信号连接线通过第二过孔与第一走线引出区域的第一子PCD信号线和第二走线引出区域的第二子PCD信号线连接。
在一些示例中，第一子电源线331、第一电源连接线332a和332b、第二子电源线333可以为一体结构。第三子电源线341a、第二电源连接线342a和第四子电源线343a可以为一体结构，第三子电源线341b、第二电源连接 线342b和第四子电源线343b可以为一体结构。
至此，在衬底基板上制备完成显示区域的驱动电路层。如图3所示，在显示区域10的驱动电路层中，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管401，第一电容电极和第二电容电极组成第一存储电容402。
在一些示例性实施方式中，第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层51可以用于提高衬底基板41的抗水氧能力。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。例如，第一金属薄膜和第二金属薄膜可以采用金属Mo，第三金属薄膜可以采用Ti/Al/Ti。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。
(7)、在衬底基板上制备第五绝缘层和第一平坦层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，沉积第五绝缘薄膜，通过图案化工艺形成第五绝缘层55，如图3所示。
在一些示例性实施方式中，在形成上述结构的衬底基板10上涂覆第一平坦薄膜，形成覆盖整个衬底基板10的第一平坦层56。
在本次工艺之后，弯折区域202包括：衬底基板41、以及依次设置在衬底基板41上的第三走线层和第一平坦层56。
(8)、在衬底基板上制备发光元件。
在一些示例性实施方式中，在形成前述结构的衬底基板上，在形成前述结构的衬底基板41上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成第一电极431图案。在形成前述结构的衬底基板41上，涂覆像 素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层(PDL，Pixel Definition Layer)434图案。如图3和图8所示，像素定义层434形成在显示区域10、第一走线引出区域201、弯折区域202和第二走线引出区域203。显示区域10的像素定义层434上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出第一电极431的表面。第一走线引出区域201、弯折区域202和第二走线引出区域203的像素定义层434覆盖第一平坦层56。
随后，在形成前述图案的衬底基板41上依次形成有机发光层432和第二电极433。如图3所示，有机发光层432可以包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域10的像素开口内，实现有机发光层432与第一电极431连接。由于第一电极431与第一晶体管401的第一漏电极连接，因而实现了有机发光层432的发光控制。第二电极433的一部分形成在有机发光层432上。本次构图工艺之后，第一走线引出区域201、弯折区域202和第二走线引出区域203的膜层结构没有变化。
(9)、制备封装层。
在一些示例性实施方式中，在形成前述图案的衬底基板10上，形成封装层44。如图3所示，封装层44形成在显示区域10，可以采用无机材料/有机材料/无机材料的叠层结构。有机材料层设置在两个无机材料层之间。本次构图工艺之后，第一走线引出区域201、弯折区域202和第二走线引出区域203的膜层结构没有变化。
(10)、制备触控结构层。
在一些示例性实施方式中，在形成前述结构的衬底基板上，沉积第一触控绝材料，通过图案化工艺对第一触控绝缘薄膜进行图案化，形成第一触控绝缘(TLD)层451。在一些示例性实施方式中，第一触控绝缘层451可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
随后，沉积触控金属薄膜，通过图案化工艺对触控金属薄膜进行图案化，在第一触控绝缘层451上形成触控电极层452图案，在第一走线引出区域201、弯折区域202和第二走线引出区域203形成触控信号线层。触控电极层452图案至少包括位于显示区域10的触控电极和连接部。在一些示例中，触控电 极和连接部可以为金属网络(metal mesh)形式。触控信号线层包括：位于边框区域22的第二触控信号线、位于第一走线引出区域201的第一子触控信号线、位于第二走线引出区域的第二子触控信号线。如图8所示，第一子触控信号线371和第二子触控信号线373通过像素定义层上434上开设的第四过孔分别与触控信号连接线372连接。第四过孔内的像素定义层434和第一平坦层56被去除，暴露出第三走线层的表面。在一些示例性实施方式中，触控金属薄膜可以采用单层结构，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或者可以采用叠层结构，如Ti/Al/Ti等。
随后，涂覆保护薄膜，形成覆盖触控电极层和触控信号线层图案的触控保护层455。在示例性实施方式中，触控保护层455可以采用聚酰亚胺(PI)等。
至此，制备完成触控结构层图案。
在一些示例性实施方式中，第一平坦层和像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在制备完成上述膜层结构后，可以通过剥离工艺将显示面板从玻璃载板上剥离。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本示例性实施例的显示面板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示区域可以设置第一源漏金属层和第二源漏金属层，第一源漏金属层可以包括第一晶体管的第一源电极和第一漏电极，第二源漏金属层可以包括连接电极，配置为与第一漏电极和发光元件的第一电极连接。弯折区域的走线可以与显示区域的第一源漏金属层或第二源漏金属层为同层结构。又如，第一驱动控制信号线可以与显示区域的第一栅金属层为同层结构。然而，本实施例对此并不限定。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图10为图4中沿P-P方向的另一局部剖面示意图。在一些示例性实施方式中，在衬底基板41上形成第四绝缘层54后，通过两次刻蚀工艺在弯折区域202形成第一凹槽和第二凹槽内，在弯折区域202形成有机填充层61。有机填充层61位于第一凹槽和第二凹槽内。随后，在衬底基板41上制备源漏金属层和第三走线层。源漏金属层位于显示区域10，第三走线层至少包括：形成在第一走线引出区域201的第一子电源线331、第三子电源线341a和341b，形成在弯折区域202的第一电源连接线332a和332b、第二电源连接线342a和342b、触控信号连接线372、数据连接线352a和352b、驱动控制连接线362a和362b、PCD信号连接线382a和382b，形成在第二走线引出区域203的第二子电源线333、第四子电源线343a和343b。
关于本实施例的显示面板的其余结构和制备过程可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图11为本公开至少一实施例的显示面板的显示区域的另一结构示意图。图11为图1中沿R-R方向的局部剖面示意图。图12为本公开至少一实施例的显示面板的触控结构层的局部平面示意图。本示例性实施方式中，以显示面板集成互容式触控结构，形成FMLOC结构为例进行说明。
在一些示例性实施方式中，如图12所示，显示区域的触控结构层可以包括多个第一触控单元210和多个第二触控单元220。第一触控单元210具有沿第二方向D2延伸的线形状，多个第一触控单元210沿第一方向D1依次排列，第二触控单元220具有沿第一方向D1延伸的线形状，多个第二触控单元220沿第二方向D2依次排。每个第一触控单元210包括沿第二方向D2依次排列的多个第一触控电极211和第一连接部212，第一触控电极211和第一连接部212交替设置且依次连接。每个第二触控单元220包括沿第一方向D1依次排列的多个第二触控电极221，多个第二触控电极221间隔设置，相邻的第二触控电极221通过第二连接部222彼此连接。在示例性实施方式中，第二连接部222所在的膜层不同于第一触控电极211和第二触控电极221所在的膜层。第一触控电极211和第二触控电极221在第三方向D3上交替布置，第三方向D3与第一方向D1和第二方向D2交叉。
在一些示例性实施方式中，多个第一触控电极211、多个第二触控电极221和多个第一连接部212可以同层设置在触控层，并且可以通过同一次图案化工艺形成，第一触控电极211和第一连接部212可以为相互连接的一体结构。第二连接部222可以设置在桥接层，通过过孔使相邻的第二触控电极221相互连接，触控电极层与桥接层之间设置有第二触控绝缘层。在一些可能的实现方式中，多个第一触控电极211、多个第二触控电极221和多个第二连接部222可以同层设置在触控电极层，第二触控电极221和第二连接部222可以为相互连接的一体结构，第一连接部212可以设置在桥接层，通过过孔使相邻的第一触控电极211相互连接。在示例性实施方式中，第一触控电极可以是驱动(Tx)电极，第二触控电极可以是感应(Rx)电极。或者，第一触控电极可以是感应(Rx)电极，第二触控电极可以是驱动(Tx)电极。
在一些示例性实施方式中，第一触控电极211和第二触控电极221可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。在一些可能的实现方式中，第一触控电极211和第二触控电极221可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，本公开在此不做限定。
在一些示例性实施方式中，第一触控电极211和第二触控电极221可以是透明导电电极形式。在示例性实施方式中，第一触控电极211和第二触控电极221可以是金属网格形式，金属网格由多条金属线交织形成，金属网格包括多个网格图案，网格图案是由多条金属线构成的多边形。金属网格式的第一触控电极211和第二触控电极221具有电阻小、厚度小和反应速度快等优点。
在一些示例性实施方式中，如图11所示，在垂直于衬底基板的平面内，显示区域的触控结构层45可以包括：依次设置在封装层44上的第一触控绝缘层451、桥接层454、第二触控绝缘层453、触控电极层452以及触控保护层455。在本示例性实施方式中，第一边框区域、走线引出区域以及弯折区域的结构可以如前述实施例的说明。其中，第一边框区域的第二触控信号线和走线引出区域的第一触控信号线可以与显示区域的触控电极层或者桥接层为同层结构。然而，本实施例对此并不限定。
本示例性实施例中的显示面板的其余结构与前述实施例中描述的相应结构类似，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图13为本公开至少一实施例的显示面板的另一结构示意图。在一些示例性实施方式中，在垂直于衬底基板的平面内，如图13所示，显示区域10包括：衬底基板41、以及依次设置在衬底基板41上的驱动电路层42、发光元件43、封装层44以及触控结构层45。驱动电路层42可以包括：依次设置在衬底基板41上的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层、第一源漏金属层、第五绝缘层、第一平坦层、第二源漏金属层以及第二平坦层。第一源漏金属层可以至少包括第一晶体管401的第一源电极和第一漏电极，第二源漏金属层可以至少包括连接电极，连接电极可以连接第一晶体管401的第一漏电极和发光元件43的第一电极431。
在一些示例性实施方式中，如图13所示，第一走线引出区域201、弯折区域202和第二走线引出区域203的第三走线层可以与显示区域10的第二源漏金属层为同层结构。在一些示例中，第三走线层可以包括：第一走线引出区域201的第一子电源线331、第三子电源线341a和341b，弯折区域202内的全部走线、第二走线引出区域203的第二子电源线333、第四子电源线343a和343b。然而，本实施例对此并不限定。在一些示例中，走线引出区域的第一电源线和第二电源线可以与显示区域10的第一源漏金属层为同层结构，弯折区域202的走线可以为显示区域10的第二源漏金属层为同层结构。或者，走线引出区域的第一电源线和第二电源线可以与显示区域10的第二源漏金属层为同层结构，弯折区域202的走线可以为显示区域10的第一源漏金属层为同层结构。
本示例性实施例中的显示面板的其余结构与前述实施例中描述的相应结构类似，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图14为本公开至少一实施例的显示面板的另一示意图。图15为图14中区域S2的局部示意图。在一些示例性实施方式中，如图14和图15所示， 显示面板包括：显示区域10、围绕显示区域10的第一边框区域22、位于显示区域10一侧的第二边框区域。第二边框区域包括：沿着远离显示区域10的方向(即第一方向D1)依次设置的走线引出区域21和信号接入区域23。信号接入区域23与走线引出区域21连通。信号接入区域23包括：沿着远离显示区域10的方向(即第一方向D1)依次设置的电路区204和绑定引脚区205。
在一些示例性实施方式中，如图15所示，走线引出区域21包括：设置在衬底基板上的第一电源线33、多条第一触控信号线37、多条第一数据引线、多条第一驱动控制信号线。第一电源线33与第一边框区域22的第三电源线330连接。第一触控信号线37与第一边框区域22的第二触控信号线370连接。第一数据引线35a与第一边框区域22的第二数据引线350a连接，第一数据引线35b与第一边框区域22的第二数据引线350b连接。第一驱动控制信号线36a与第一边框区域22的第二驱动控制信号线360a连接，第一驱动控制信号线36b与第一边框区域22的第二驱动控制信号线360b连接。第一电源线33与第一边框区域22的第三电源线330连接。第二电源线34a与第一边框区域22的第四电源线340a连接，第二电源线34b与第一边框区域22的第四电源线340b连接。
在一些示例性实施方式中，如图15所示，第一数据引线35a与第二数据引线350a可以为一体结构，第一数据引线35b与第二数据引线350b可以为一体结构。第一电源线33与第三电源线330可以为一体结构。第一触控信号线37与第二触控信号线370可以为一体结构。第二电源线34a与第四电源线340a可以为一体结构，第二电源线34b与第四电源线340b可以为一体结构。第一驱动控制信号线36a与第一边框区域22的第二驱动控制信号线360a可以为异层结构，第一驱动控制信号线36b与第一边框区域22的第二驱动控制信号线360b可以为异层结构。例如，第二驱动控制信号线360a和360b与显示区域10的源漏金属层可以为同层结构，第一驱动控制信号线36a和36b与显示区域10的第一栅金属层或第二栅金属层可以为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图15所示，多条第一触控信号线37在衬 底基板上的正投影与多条第一数据引线和多条第一驱动控制信号线在衬底基板上的正投影没有交叠。多条第一触控信号线37在衬底基板上的正投影位于第一电源线33在衬底基板上的正投影内。本示例性实施方式中，利用第一电源线将第一触控信号线与第一数据引线和第一驱动控制信号线隔离，降低触控信号和显示信号之间产生的信号干扰，从而提高显示和触控效果。
本示例性实施例中的显示面板的其余结构与前述实施例中描述的相应结构类似，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
本公开至少一实施例还提供一种显示面板的制备方法，包括：在衬底基板的显示区域和信号接入区域之间的走线引出区域形成第一电源线、至少一条第一触控信号线和至少一条第一显示信号线。第一触控信号线位于第一电源线远离衬底基板的一侧，第一显示信号线位于第一电源线靠近衬底基板的一侧。第一触控信号线在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分交叠。
关于本实施例的显示面板的制备方法可以参照前述实施例的说明，故于此不再赘述。
图16为本公开至少一实施例的显示触控装置的示意图。如图16所示，本实施例提供一种显示触控装置91，包括前述实施例的显示面板910。在一些示例中，显示面板910可以为集成触控结构的OLED显示面板。显示触控装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示和触控功能的产品或部件。在一些示例性实施方式中，显示触控装置91可以为穿戴式显示装置，例如可以通过某些方式佩戴在人体上。比如，显示触控装置91可以为智能手表、智能手环等。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (16)

  1. 一种显示面板，包括：
    衬底基板，包括显示区域、位于所述显示区域一侧的走线引出区域和信号接入区域，所述走线引出区域位于所述显示区域和信号接入区域之间；
    显示结构层，位于所述显示区域；
    触控结构层，位于所述显示区域，且设置在所述显示结构层远离所述衬底基板的一侧；
    至少一条第一电源线，位于所述走线引出区域，并与所述显示结构层连接；
    至少一条第一显示信号线，位于所述走线引出区域，与所述显示结构层连接，且位于所述第一电源线靠近所述衬底基板的一侧；
    至少一条第一触控信号线，位于所述走线引出区域，与所述触控结构层连接，且位于所述第一电源线远离所述衬底基板的一侧；
    所述第一触控信号线在所述衬底基板上的正投影与所述第一电源线在所述衬底基板上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述第一触控信号线在所述衬底基板上的正投影与所述第一显示信号线在所述衬底基板上的正投影没有交叠。
  3. 根据权利要求1所述的显示面板，其中，所述第一触控信号线在所述衬底基板上的正投影位于所述第一电源线在所述衬底基板上的正投影内。
  4. 根据权利要求1至3中任一项所述的显示面板，其中，所述衬底基板还包括：弯折区域；
    所述走线引出区域包括：沿着远离所述显示区域的方向依次设置的第一走线引出区域和第二走线引出区域；所述弯折区域位于所述第一走线引出区域和第二走线引出区域之间；
    所述弯折区域包括：设置在所述衬底基板上的至少一条第一电源连接线、至少一条触控信号连接线、以及至少一条显示信号连接线；
    所述第一电源连接线、触控信号连接线和显示信号连接线为同层结构，且所述第一电源连接线位于触控信号连接线和显示信号连接线之间。
  5. 根据权利要求4所述的显示面板，其中，所述走线引出区域的第一触控信号线包括：位于所述第一走线引出区域的第一子触控信号线、位于所述第二走线引出区域的第二子触控信号线；
    所述走线引出区域的第一显示信号线包括：位于所述第一走线引出区域的第一子显示信号线、位于所述第二走线引出区域的第二子显示信号线；
    所述触控信号连接线与所述第一子触控信号线和第二子触控信号线连接；
    所述显示信号连接线与所述第一子显示信号线和第二子显示信号线连接；
    所述第一子触控信号线和第二子触控信号线位于所述触控信号连接线远离所述衬底基板的一侧，所述第一子显示信号线和第二子显示信号线位于所述显示信号连接线靠近所述衬底基板的一侧。
  6. 根据权利要求4或5所述的显示面板，其中，所述走线引出区域的第一电源线包括：位于所述第一走线引出区域的第一子电源线、位于所述第二走线引出区域的第二子电源线；
    所述第一电源连接线与所述第一子电源线和第二子电源线连接；
    所述第一子电源线、第一电源连接线和第二子电源线为一体结构。
  7. 根据权利要求4至6中任一项所述的显示面板，其中，所述弯折区域内的第一电源连接线、触控信号连接线和显示信号连接线均沿第一方向延伸；
    在第二方向上，所述弯折区域依次排布有至少一条显示信号连接线、至少一条第一电源连接线、至少一条触控信号连接线、至少一条第一电源连接线以及至少一条显示信号连接线；
    所述第一方向和第二方向位于同一平面内，且所述第一方向与第二方向垂直。
  8. 根据权利要求4至7中任一项所述的显示面板，其中，所述显示结构层至少包括：设置在所述衬底基板上的驱动电路层；所述驱动电路层至少包括：设置在所述衬底基板上的有源层、第一栅金属层、第二栅金属层和源漏金属层；
    所述弯折区域的第一电源连接线、触控信号连接线和显示信号连接线与所述显示区域的源漏金属层为同层结构；
    所述走线引出区域的至少一条第一显示信号线与所述显示区域的第一栅金属层或第二栅金属层为同层结构；
    所述触控结构层至少包括触控电极层；
    所述走线引出区域的至少一条第一触控信号线与所述显示区域的触控电极层为同层结构；
    所述走线引出区域的第一电源线与所述显示区域的源漏金属层为同层结构。
  9. 根据权利要求4至8中任一项所述的显示面板，其中，所述走线引出区域还包括：至少一条第二电源线；所述弯折区域还包括：设置在所述衬底基板上的至少一条第二电源连接线；
    所述走线引出区域的第二电源线包括：位于所述第一走线引出区域的第三子电源线和位于所述第二走线引出区域的第四子电源线；
    所述第二电源连接线与所述第三子电源线和第四子电源线连接；
    在所述弯折区域，所述第二电源连接线位于显示信号连接线远离第一电源连接线的一侧。
  10. 根据权利要求1所述的显示面板，其中，所述走线引出区域包括：多条第一显示信号线；
    所述多条第一显示信号线被分成第一组第一显示信号线和第二组第一显示信号线；至少一条第一触控信号线在所述衬底基板上的正投影位于第一组第一显示信号线和第二组第一显示信号线在所述衬底基板上的正投影之间。
  11. 根据权利要求10所述的显示面板，其中，所述走线引出区域的多条第一显示信号线包括：至少一条第一数据引线、以及至少一条第一驱动控制信号线；所述第一驱动控制信号线在所述衬底基板上的正投影与所述第一触控信号线在所述衬底基板上的正投影相邻。
  12. 根据权利要求1至11中任一项所述的显示面板，其中，所述显示结构层包括至少一个发光元件，所述发光元件包括：第一电极、第二电极以及 位于所述第一电极和第二电极之间的有机发光层；所述第一电极位于所述第二电极靠近所述衬底基板的一侧；
    所述衬底基板还包括：位于所述显示区域和所述走线引出区域之间的第一边框区域；所述第一边框区域设置有显示控制电路、至少一条第二触控信号线；所述第二触控信号线与所述走线引出区域的第一触控信号线连接；
    在所述第一边框区域内，所述第二触控信号线在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影内。
  13. 根据权利要求1至12中任一项所述的显示面板，其中，所述第一电源线为高电压电源线。
  14. 根据权利要求1至13中任一项所述的显示面板，其中，所述信号接入区域设置有触控与显示驱动集成TDDI电路；所述TDDI电路与所述走线引出区域的第一显示信号线和第一触控信号线连接。
  15. 一种显示触控装置，包括如权利要求1至14中任一项所述的显示面板。
  16. 一种显示面板的制备方法，包括：
    在衬底基板的显示区域依次形成显示结构层和触控结构层，在所述衬底基板的显示区域和信号接入区域之间的走线引出区域形成至少一条第一电源线、至少一条第一触控信号线和至少一条第一显示信号线；
    其中，所述第一电源线和第一显示信号线与显示结构层连接，所述第一触控信号线与触控结构层连接；所述第一触控信号线位于所述第一电源线远离衬底基板的一侧，所述第一显示信号线位于所述第一电源线靠近衬底基板的一侧；所述第一触控信号线在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分交叠。
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