WO2022230498A1 - 受光素子およびx線撮像素子ならびに電子機器 - Google Patents
受光素子およびx線撮像素子ならびに電子機器 Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/24—Measuring radiation intensity with semiconductor detectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/1446—Devices controlled by radiation in a repetitive configuration
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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- H—ELECTRICITY
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
Definitions
- the present disclosure relates to, for example, a light-receiving element suitable for X-ray imaging for medical use and non-destructive inspection, an X-ray imaging element including the same, and an electronic device.
- Solid-state imaging devices are used in a variety of applications, such as imaging devices such as digital still cameras and video cameras, electronic devices such as mobile terminal devices having an imaging function, and electromagnetic wave sensors that detect various wavelengths other than visible light.
- a solid-state imaging device has an APS (Active Pixel Sensor) equipped with an amplifying element for each pixel.
- complementary MOS) image sensors (CIS) are widely used.
- a light-receiving element PIN photodiode
- FD floating diffusion
- Such a light receiving element has a simple structure and is easy to manufacture. Also, any potential difference can be applied to the pn junction forming the photoelectric conversion region. Therefore, it is easy to increase the thickness of the photoelectric conversion region.
- a light receiving element includes a semiconductor substrate including a photoelectric conversion region, and a first first conductivity type region provided at an interface on one surface of the semiconductor substrate and connected to a first electrode. a second first-conductivity-type region provided around the first first-conductivity-type region and connected to the second electrode at the interface of the one surface; and a third electrically floating first-conductivity-type region provided around the first-conductivity-type region.
- An X-ray imaging element includes a plurality of light receiving elements according to the embodiment of the present disclosure, which generate signal charges based on X-rays.
- An electronic device includes the X-ray imaging device according to the embodiment of the present disclosure.
- the A second first-conductivity-type region connected to the second electrode and an electrically floating third first-conductivity-type region are arranged in this order around the first first-conductivity-type region connected to the second electrode. made it As a result, the dark current generated at the interface on the one surface of the semiconductor substrate is discharged from the second first-conductivity-type region and is prevented from reaching the first first-conductivity-type region. Moreover, the moving speed of the signal charges generated in the semiconductor substrate 11 in the horizontal direction is improved.
- FIG. 4 is a schematic cross-sectional view showing another example of the configuration of the light receiving element according to the first embodiment of the present disclosure
- 3 is a schematic diagram showing an example of a planar configuration of a p-type conductivity type region of the light receiving element shown in FIG. 2
- FIG. 3 is a schematic diagram showing another example of the planar configuration of the p-type conductivity type region of the light receiving element shown in FIG. 2
- FIG. 3 is a schematic diagram showing another example of the planar configuration of the p-type conductivity type region of the light receiving element shown in FIG.
- FIG. 3 is a schematic diagram showing an example of power supply connection to the n-type conductivity type region of the light receiving element shown in FIG. 2.
- FIG. 3 is a schematic diagram showing another example of power supply connection to the n-type conductivity region of the light receiving element shown in FIG. 2.
- FIG. 11 is a schematic cross-sectional view showing the configuration of a light receiving element according to a third embodiment of the present disclosure.
- 11 is a schematic cross-sectional view showing the configuration of a light receiving element according to a fourth embodiment of the present disclosure
- 11 is a schematic diagram showing an example of a planar configuration of a p-type conductivity type region of the light receiving element shown in FIG. 10
- FIG. FIG. 11 is a schematic cross-sectional view showing the configuration of a light receiving element according to a fifth embodiment of the present disclosure
- 13 is a schematic diagram showing an example of the planar configuration of the n-well of the light receiving element shown in FIG. 12;
- FIG. 10 is a schematic diagram showing an example of a planar configuration of a p-type conductivity region of a light receiving element according to a modified example of the present disclosure; It is a block diagram showing the structure of an X-ray imaging element. 16 is a block diagram showing a detailed configuration example of a column selection unit shown in FIG. 15; FIG.
- Third Embodiment Example in which an Anode Protruding Portion is Provided Between an N-type Conductive Layer and a Buried Layer
- Fourth embodiment an example of a light-receiving element in which the line width and spacing of a plurality of guard rings are varied
- Fifth Embodiment Example of Providing a Buried Layer Having an Impurity Concentration Distribution
- Modification 7 Application example
- FIG. 1 illustrates a cross-sectional configuration of a light receiving element (light receiving element 10) according to the first embodiment of the present disclosure.
- the light receiving element 10 is composed of, for example, a PIN (Positive Intrinsic Negative) type photodiode that applies a reverse bias between the front surface and the rear surface of the semiconductor substrate 11. and X-rays, etc.), constitutes one pixel (pixel P) in a radiation imaging device (for example, an X-ray imaging device 1; see FIG. 15) for reading subject information (imaging a subject) or an electromagnetic wave detection device. It is.
- a radiation imaging device for example, an X-ray imaging device 1; see FIG. 15
- the light receiving element 10 has, for example, a p-type conductivity region (first conductivity type region) 13 partially formed at the interface of one surface (surface S1; one surface) of an n-type semiconductor substrate 11, and the surface S1 is different from the surface S1.
- An n-type conductive layer (second conductive type layer) 12 is formed at the interface of the opposite surface (back surface S2; other surface).
- the p-type conductivity type region 13 is composed of a plurality of regions, and in the light receiving element 10 of the present embodiment, for example, a region (first first conductivity type region) forming the anode 13A and a drain 13B. and a region (third first conductivity type region) forming the guard ring 13C.
- an n-type conductivity region (second conductivity type region) is formed as the embedded layer 14 inside the semiconductor substrate 11 .
- An insulating layer 15 is formed on the surface S ⁇ b>1 of the semiconductor substrate 11 .
- the semiconductor substrate 11 is composed of, for example, an n-type, p-type, or i-type (intrinsic semiconductor) semiconductor. As described above, the semiconductor substrate 11 has the p-type conductivity region (first conductivity type region) 13 formed at the interface on the surface S1 side, and has a pn junction or a pin junction serving as a photoelectric conversion region. In addition, in the present embodiment, an example in which the semiconductor substrate 11 uses an n-type semiconductor substrate is shown.
- the film thickness (hereinafter simply referred to as thickness) of the semiconductor substrate 11 in the lamination direction (Y-axis direction) is, for example, 10 ⁇ m or more and 700 ⁇ m or less.
- the p-type conductivity type regions 13 are regions containing p-type impurities (p-type impurity regions), and are formed in plurality at the interface on the surface S1 side of the semiconductor substrate 11 .
- p-type conductivity type region 13 has three regions: a region forming anode 13A, a region forming drain 13B, and a region forming guard ring 13C. Each region is provided separately, the drain 13B is formed in a ring shape around the anode 13A, and the guard ring 13C is formed in a ring shape around the drain 13B.
- the thickness of the p-type conductivity region 13 depends on the configuration of the pixels P, for example, when the pitch of the pixels P is 10 ⁇ m or more and 100 ⁇ m or less, the thickness of the p-type conductivity region 13 is, for example, 2 ⁇ m to 2 ⁇ m from the interface of the surface S1 of the semiconductor substrate 11. It is formed with a thickness of 3 ⁇ m.
- the anode 13A is an electrode to which a voltage is applied to read out, for example, hole carriers (h+) as signal charges among charge carriers generated by photoelectric conversion.
- the anode 13A is individually formed in the center of the pixel P, for example.
- the planar shape of the anode 13A is not particularly limited, and may be circular (eg, see FIG. 3) or polygonal.
- the size of the anode 13A depends on the size of the pixel P, but is, for example, 0.100 ⁇ m or more and 10 ⁇ m or less when the pitch of the pixels P is 10 ⁇ m or more and 100 ⁇ m or less.
- the drain 13B is an electrode to which a voltage is applied for discharging dark current generated at the interface of the surface S1 when the semiconductor substrate 11 is irradiated with light, and is connected to the electrode 17 (second electrode), for example.
- the drain 13B is formed in a ring shape around the anode 13A, so that the dark current generated at the interface of the surface S1 when the semiconductor substrate 11 is irradiated with light is always discharged from the drain 13B and flows into the anode 13A. can be prevented.
- the planar shape of the drain 13B is not particularly limited, and may be an annular shape or a polygonal shape (see FIG. 3, for example).
- the guard ring 13C is for alleviating electric field concentration on the drain 13B and at the same time generating a horizontal electric field for assisting horizontal signal carrier transport.
- Guard ring 13C is formed in a ring shape around drain 13B so as to surround anode 13A and drain 13B.
- the guard ring 13C is electrically floating unlike the anode 13A and the drain 13B.
- one guard ring 13C (single layer) may be formed around the drain 13B, but a plurality of guard rings 13C may also be formed.
- FIG. 2 schematically shows another example of the cross-sectional configuration of the light receiving element 10 of the present embodiment
- FIG. 3 schematically shows the planar configuration of the guard ring 13C of the light receiving element 10 shown in FIG.
- the guard ring 13C has three p-type conductivity regions and is formed in triplicate (guard rings 13C1, 13C2, 13C3) around the drain 13B.
- guard rings 13C1, 13C2, 13C3 triplicate
- FIG. 3 shows an example in which the drain 13B and the guard ring 13C are provided continuously around the anode 13A, but the present invention is not limited to this.
- the drain 13B and guard ring 13C may be partially cut off as shown in FIG. 4, or may be intermittently formed.
- the line width of the rings forming the drain 13B and the guard ring 13C is preferably, for example, 0.100 ⁇ m or more and 10 ⁇ m or less.
- the distance between the drain 13B and the guard ring 13C is preferably 0.100 ⁇ m or more and 10 ⁇ m or less.
- the distance between the drain 13B and the guard ring 13C and the line width of the drain 13B and the guard ring 13C are not necessarily constant.
- the drain 13B and the plurality of guard rings 13C are each formed in a polygonal shape (for example, a rectangular shape), as shown in FIG. is preferably formed such that the corner portion (Wb) is wider than the straight portion (Wa). This further reduces the concentration of the electric field at the corners.
- the n-type conductive layer 12 is a region (n-type impurity region) containing n-type impurities at a higher concentration than the n-type semiconductor substrate 11, and is formed at the interface of the semiconductor substrate 11 on the back surface S2 side.
- the n-type conductive layer 12 is connected to, for example, a power supply VDD, and when hole carriers, for example, among charge carriers generated by photoelectric conversion are read out as signal charges through the anode 13A, this n-type conductive layer Electron carriers (e ⁇ ) can be ejected through 12 .
- the thickness of the n-type conductive layer 12 depends on the configuration of the pixels P, for example, when the pitch of the pixels P is 10 ⁇ m or more and 100 ⁇ m or less, the thickness of the n-type conductive layer 12 is, for example, 1 ⁇ m from the interface of the back surface S2 of the semiconductor substrate 11. is formed by
- FIG. 6 and 7 each show an example of a method of connecting a power supply to the n-type conductive layer 12.
- a transparent electrode 18 is formed on the n-type conductive layer 12, a power supply VDD is connected to this, and a voltage is applied from the back surface S2 side of the semiconductor substrate 11.
- FIG. 7 a neutral region 11N is formed outside a depletion region 11D formed in a semiconductor substrate 11 in a peripheral region 110B around a pixel region 110A in which a plurality of pixels P are arranged.
- a voltage is applied through the n-type conductivity region 19 provided at the interface of the surface S1 of the substrate 11.
- FIG. In this case, as shown in FIG.
- the high breakdown voltage guard ring closest to the pixel region 110A is preferably connected to the ground GND.
- the embedded layer 14 is for preventing charge carriers (here, hole carriers) generated in the semiconductor substrate 11 by photoelectric conversion from being transferred to the drain 13B and the guard ring 13C.
- the embedded layer 14 is buried inside the semiconductor substrate 11 , specifically near the p-type conductivity region 13 , and is an n-type layer containing n-type impurities at a higher concentration than the n-type semiconductor substrate 11 . It is a conductivity type region. More specifically, embedded layer 14 is provided in a region of p-type conductivity region 13 corresponding to drain 13B and guard ring 13C, and has an opening in a region facing anode 13A. As a result, signal charges (hole carriers) generated in the semiconductor substrate 11 are efficiently read out from the anode 13A.
- the embedded layer 14 is preferably arranged so as not to be in direct contact with the drain 13B and the guard ring 13C.
- the thickness of the embedded layer 14 varies depending on the magnitude of the reverse bias voltage applied between the front surface S1 and the back surface S2 of the semiconductor substrate 11, and is, for example, 0.100 ⁇ m or more and 10 ⁇ m or less.
- the insulating layer 15 is formed on the surface S1 of the semiconductor substrate 11, and is formed using an inorganic insulating material, for example.
- Inorganic insulating materials include silicon nitride (SiN), aluminum oxide ( Al2O3 ) , silicon oxide ( SiO2 ) and hafnium oxide ( HfO2).
- the insulating layer 15 contains at least one of these.
- a logic circuit or the like is formed on the insulating layer 15 .
- the light receiving element 10 can be manufactured, for example, as follows. First, the n-type conductive layer 12 is formed on the back surface S2 of the semiconductor substrate 11 using the ion implantation technique. Subsequently, after forming a mask on a predetermined region of the surface S1 of the semiconductor substrate 11, an n-type impurity (for example, phosphorus (P)) is doped using an ion implantation technique to form an n-type conductive region (buried layer). 14).
- n-type impurity for example, phosphorus (P)
- ion implantation technology is used to dope p-type impurities (for example, boron (B)) to form p-type conductive regions (anode 13A, A drain 13B and a guard ring 13C) are formed.
- p-type impurities for example, boron (B)
- p-type conductive regions anode 13A, A drain 13B and a guard ring 13C
- the insulating layer 15 is formed on the surface S1 of the semiconductor substrate 11 using, for example, a CVD (Chemical Vapor Deposition) method. Thereby, the light receiving element 10 shown in FIG. 1 is completed.
- the solid-state imaging device is, for example, an imaging device such as a digital still camera or a video camera, an electronic device such as a mobile terminal device having an imaging function, or an electromagnetic wave sensor that detects various wavelengths other than visible light. etc., are used for various purposes.
- These solid-state imaging devices widely use CMOS image sensors that read out signal charges accumulated in photodiodes, which are photoelectric conversion elements, via MOS transistors.
- a unit pixel of a CMOS image sensor includes, for example, a photodiode (PD) having a HAD (Hole Accumulated Diode) structure in a semiconductor substrate, and a floating diffusion region (FD) arranged at a position across a transfer gate from the photodiode. and
- the unit pixel has, for example, a reset transistor, a select transistor and an amplifier transistor.
- the unit pixel of the CMOS image sensor there is a structure in which the photoelectric conversion region and the FD are integrated in the semiconductor substrate without having the HAD.
- This structure is simple and easy to manufacture, and any potential difference can be applied to the pn junction forming the photoelectric conversion region. Therefore, it is easy to increase the thickness of the photoelectric conversion region, and taking advantage of this advantage, it is often used in sensors for scientific applications that require high-sensitivity measurement.
- CMOS image sensor since the surface of the semiconductor substrate is in contact with the depletion layer, for example, when a fixed charge is generated in the insulating film provided on the semiconductor substrate or its interface due to the incidence of strong radiation, There was a problem that the capacity and electric field of the capacitor fluctuated greatly, and the resistance to high energy input was low.
- the p-type conductivity region is formed at the interface of the surface S1 of the n-type semiconductor substrate 11 forming the photoelectric conversion region, and is connected to the electrode 16.
- An anode 13A is provided, and around it is provided a drain 13B, which is also composed of a p-type conductivity type region and is connected to an electrode (electrode 17) different from the anode 13A.
- an electrically floating guard ring 13C which is also composed of a p-type conductivity type region, is provided. This makes it possible to improve the speed of movement of signal charges (here, hole carriers) generated in the semiconductor substrate 11 in the planar direction.
- the drain 13B connected to the electrode 17 different from the electrode 16 connected to the anode 13A is provided around the anode 13A provided at the interface of the surface S1 of the semiconductor substrate 11. Further, a floating guard ring 13C is provided around the drain 13B.
- the moving speed of the signal charges (here, hole carriers) generated in the semiconductor substrate 11 in the planar direction is improved, and the transfer speed of the signal charges is improved without increasing the size of the anode 13A. becomes possible.
- the dark current can be discharged by the drain 13B, and the resistance to high energy input can be improved. Become. Therefore, it is possible to realize a reduction in dark current, a reduction in capacity, and an improvement in readout speed.
- the buried layer 14 having a high n-type impurity concentration is formed inside the semiconductor substrate 11, specifically, in the vicinity of the drain 13B and the guard ring 13C. .
- FIG. 8 illustrates a cross-sectional configuration of a light receiving element (light receiving element 20) according to the second embodiment of the present disclosure.
- the light-receiving element 20 is, for example, a PIN-type photodiode that applies a reverse bias between the front surface and the back surface of the semiconductor substrate 11, as in the first embodiment. , ⁇ -rays, ⁇ -rays, X-rays, etc.), a single pixel ( It constitutes the pixel P).
- the light receiving element 20 has, for example, a p-type conductivity region 23 having an anode 23A, a drain 13B, and a guard ring 13C formed at the interface of the surface S1 of the n-type semiconductor substrate 11 .
- An n-type conductive layer 12 is formed at the interface of the back surface S2 of the semiconductor substrate 11 .
- the anode 23A has the extending portion 23X1 that extends toward the back surface S2, so that the lower end of the anode 13A is formed at a position deeper than the drain 13B and the guard ring 13C.
- the extending portion 23X1 preferably protrudes toward the rear surface S2 from the bottom surface of the embedded layer 14 formed below the drain 13B and the guard ring 13C, for example.
- the anode 23A formed at the interface of the surface S1 of the n-type semiconductor substrate 11 is provided with the extended portion 23X1, and the tip of the extended portion 23X1 extends inside the semiconductor substrate 11, specifically, the drain. 13B and guard ring 13C.
- signal charges for example, hole carriers
- FIG. 9 illustrates a cross-sectional configuration of a light receiving element (light receiving element 30) according to the third embodiment of the present disclosure.
- the light-receiving element 30 is, for example, a PIN-type photodiode that applies a reverse bias between the front surface and the rear surface of the semiconductor substrate 11, as in the first embodiment. , ⁇ -rays, ⁇ -rays, X-rays, etc.), a single pixel ( It constitutes the pixel P).
- the light receiving element 30 has, for example, a p-type conductivity region 33 having an anode 33A, a drain 13B, and a guard ring 13C formed at the interface of the surface S1 of the n-type semiconductor substrate 11 .
- An n-type conductive layer 12 is formed at the interface of the back surface S2 of the semiconductor substrate 11 .
- the anode 33A has an extended portion 33X1 extending toward the rear surface S2 and an extended portion 33X2 extending in the planar direction of the semiconductor substrate 11 (for example, the XZ plane direction) at the tip thereof. is doing.
- the projecting portion 33X2 is provided in a layer below the embedded layer 14 formed below the drain 13B and the guard ring 13C. It is preferable that the tip of the projecting portion 33X2 extends to the edge of the pixel P. As shown in FIG. Alternatively, it may be formed continuously with the projecting portion 33X2 of another pixel P that is arranged adjacently.
- the anode 33A formed at the interface of the surface S1 of the n-type semiconductor substrate 11 is provided with the extending portion 33X1, and the extension projecting in the planar direction of the semiconductor substrate 11 is provided at the tip of the extending portion 33X1.
- a portion 33X2 is provided.
- FIG. 10 illustrates a cross-sectional configuration of a light receiving element (light receiving element 40) according to the fourth embodiment of the present disclosure.
- FIG. 11 schematically shows a planar configuration of the p-type conductivity type region 43 of the light receiving element 40 shown in FIG.
- the light-receiving element 40 is, for example, a PIN-type photodiode that applies a reverse bias between the front surface and the rear surface of the semiconductor substrate 11, as in the first embodiment. , ⁇ -rays, ⁇ -rays, X-rays, etc.), a single pixel ( It constitutes the pixel P).
- the light receiving element 40 has, for example, a p-type conductivity region 33 having an anode 43A, a drain 43B, and a guard ring 43C formed at the interface of the surface S1 of the n-type semiconductor substrate 11 .
- An n-type conductive layer 12 is formed at the interface of the back surface S2 of the semiconductor substrate 11 .
- the line widths of the guard rings 43C1, 43C2, 43C3 and the line widths of the guard rings 43C1, 43C2, 43C3 and the guard rings 43C1, 43C1, 43C3 increase as the guard rings 43C1, 43C2, 43C3 formed in plurality (in this case, three folds) are closer to the outer periphery. It has a configuration in which the interval between 43C2 and 43C3 is wide.
- the line widths of the guard rings 43C1, 43C2 and 43C3 and the intervals between the guard rings 43C1, 43C2 and 43C3 are formed so as to widen toward the outer periphery.
- the guard rings 13C1, 13C2, and 13C3 are arranged at equal intervals as in the first embodiment, the potential difference between the guard rings becomes smaller toward the outer circumference, and the transfer electric field (horizontal electric field) weakens. There is fear.
- the potential difference between the guard rings 43C1, 43C2, 43C3 is equalized, and the potential difference between the guard rings 43C1, 43C2, 43C3 is increased to the anode 43A. It is possible to equalize the direction of the horizontal electric field within the pixel P.
- FIG. 12 illustrates a cross-sectional configuration of a light receiving element (light receiving element 50) according to the fifth embodiment of the present disclosure.
- FIG. 13 schematically shows a planar configuration of the p-type conductivity type region 13 and the buried layer 54 of the light receiving element 50 shown in FIG.
- the light-receiving element 50 is, for example, a PIN-type photodiode that applies a reverse bias between the front surface and the rear surface of the semiconductor substrate 11, as in the first embodiment. , ⁇ -rays, ⁇ -rays, X-rays, etc.), a single pixel ( It constitutes the pixel P).
- the light receiving element 50 has, for example, a p-type conductivity region 33 having an anode 33A, a drain 13B, and a guard ring 13C formed at the interface of the surface S1 of the n-type semiconductor substrate 11 .
- An n-type conductive layer 12 is formed at the interface of the back surface S2 of the semiconductor substrate 11 .
- the buried layer 54 provided under the drain 13B and the guard ring 13C has a locally high impurity concentration region, which is different from the first embodiment. different.
- the buried layer 54 includes, for example, an impurity region 54a having the same n-type impurity concentration as that of the buried layer 14 in the first embodiment, and a high impurity region 54a having a higher impurity concentration than the impurity region 54a. and an impurity region 54b.
- the high impurity region 54b is preferably formed in a region where signal charges (here, hole carriers) generated in the semiconductor substrate 11 are likely to leak into the drain 13B and the guard ring 13C.
- the buried layer 54 is formed with a locally high impurity concentration region (high impurity region 54b). This makes it possible to reinforce regions where signal charges generated in the semiconductor substrate 11 tend to leak into the drain 13B and the guard ring 13C. It is possible to further improve the transfer efficiency of signal charges (for example, hole carriers) generated inside.
- FIG. 14 schematically shows the planar configuration of the p-type conductivity region 63 in the light-receiving element (light-receiving element 60) according to the modified example of the first embodiment of the present disclosure together with other adjacent pixels P. be.
- the light-receiving element 60 is, for example, a PIN-type photodiode that applies a reverse bias between the front surface and the back surface of the semiconductor substrate 11, as in the first embodiment. , ⁇ -rays, ⁇ -rays, X-rays, etc.), a single pixel ( It constitutes the pixel P).
- the anode 13A is arranged at the center of the pixel P, and the drain 13B and the guard ring 13C are arranged in this order around it.
- an anode 63A may be formed at one corner of a rectangular pixel P, for example.
- four pixels P adjacent to each other may be set as one set, and the anode 63A may be formed in the center of each set.
- the drain 63B is preferably formed so as to surround each anode 63A.
- Guard rings 63C1, 63C2, and 63C3 are provided so as to surround anodes 63A and drains 63B provided in four pixels P, respectively.
- FIG. 15 shows the functional configuration of an X-ray imaging element 1 using the element structure of the light receiving element (for example, light receiving element 10) described in the first to fifth embodiments and modifications.
- the X-ray imaging device 1 reads information about a subject (pictures an image of the subject) based on, for example, incident radiation Rrad (eg, ⁇ -rays, ⁇ -rays, ⁇ -rays, X-rays, etc.).
- the X-ray imaging device 1 includes a pixel section (pixel region 110A), and a row scanning section 121, an A/D conversion section 122, a column scanning section 123 and a driving circuit (peripheral circuit section) for the pixel region 110A.
- a system control unit 124 is provided.
- the pixel region 110A includes a plurality of pixels (imaging pixels) P that generate signal charges based on radiation.
- a plurality of pixels P are two-dimensionally arranged in a matrix. As shown in FIG. 1, the horizontal direction (row direction) in the pixel region 110A is the "H" direction, and the vertical direction (column direction) is the "V" direction.
- the row scanning unit 121 includes a shift register circuit, a predetermined logic circuit, etc., which will be described later. scanning). Specifically, an imaging operation such as a readout operation and a reset operation for each pixel P is performed by, for example, line sequential scanning. This line-sequential scanning is performed by supplying the above-described row scanning signal to each pixel P via the readout control line Lread.
- the A/D conversion unit 122 has a plurality of column selection units 125 provided for each of the plurality (here, four) of signal lines Lsig, and selects the signal voltage ( A/D conversion (analog/digital conversion) is performed based on the voltage corresponding to the signal charge). As a result, output data Dout (imaging signal) composed of digital signals is generated and output to the outside.
- Each column selector 125 includes, for example, as shown in FIG. 16, a charge amplifier 172, a capacitive element (capacitor or feedback capacitive element) C1, a switch SW1, a sample hold (S/H) circuit 173, and four switches SW2. It has a multiplexer circuit (selection circuit) 174 and an A/D converter 175 . Among these, the charge amplifier 172, the capacitive element C1, the switch SW1, the S/H circuit 173 and the switch SW2 are provided for each signal line Lsig. A multiplexer circuit 174 and an A/D converter 175 are provided for each column selection section 125 . The charge amplifier 172, the capacitive element C1 and the switch SW1 constitute a charge amplifier circuit.
- the charge amplifier 172 is an amplifier (amplifier) for converting the signal charge read from the signal line Lsig into a voltage (QV conversion).
- this charge amplifier 172 one end of the signal line Lsig is connected to a negative (-) input terminal, and a predetermined reset voltage Vrst is inputted to a positive (+) input terminal. .
- a feedback connection is established between the output terminal of the charge amplifier 172 and the negative input terminal via a parallel connection circuit of the capacitive element C1 and the switch SW1. That is, one terminal of the capacitive element C ⁇ b>1 is connected to the negative input terminal of the charge amplifier 172 , and the other terminal is connected to the output terminal of the charge amplifier 172 .
- one terminal of the switch SW1 is connected to the negative input terminal of the charge amplifier 172 and the other terminal is connected to the output terminal of the charge amplifier 172 .
- the ON/OFF state of the switch SW1 is controlled by a control signal (amplifier reset control signal) supplied from the system control section 124 via the amplifier reset control line Lcarst.
- the S/H circuit 173 is arranged between the charge amplifier 172 and the multiplexer circuit 174 (switch SW2), and is a circuit for temporarily holding the output voltage Vca from the charge amplifier 172.
- the multiplexer circuit 174 selectively connects each S/H circuit 173 and the A/D converter 175 by sequentially turning on one of the four switches SW2 according to the scanning drive by the column scanning section 123. Or it is a circuit to cut off.
- the A/D converter 175 is a circuit that performs A/D conversion on the output voltage from the S/H circuit 173 input via the switch SW2 to generate and output the output data Dout described above. .
- the column scanning section 123 includes, for example, a shift register and an address decoder (not shown), and sequentially drives the switches SW2 in the column selecting section 125 while scanning them. By such selective scanning by the column scanning unit 123, the signal of each pixel P (the output data Dout) read out via each of the signal lines Lsig is sequentially output to the outside.
- the system control section 124 controls each operation of the row scanning section 121 , the A/D conversion section 122 and the column scanning section 123 .
- the system control unit 124 has a timing generator that generates the various timing signals (control signals) described above. 121 , A/D conversion unit 122 and column scanning unit 123 are controlled. Based on the control of the system control unit 124, the row scanning unit 121, the A/D conversion unit 122, and the column scanning unit 123 each perform imaging driving (line sequential imaging driving) for the plurality of pixels P in the pixel area 110A. , the output data Dout is obtained from the pixel area 110A.
- the layer structure of the light receiving element 10 described in the above embodiment and the like is an example, and may further include other layers. Furthermore, the material and thickness of each layer are also examples, and are not limited to those described above.
- the X-ray imaging device 1 is mentioned in the above application example, the light receiving device (for example, the light receiving device 10) described in the above embodiments and the like can also be applied to radiation imaging devices and electromagnetic wave detection devices, not limited to X-rays. can be applied.
- the present disclosure can also be configured as follows. According to the present technology having the following configuration, a first first-conductivity-type region connected to a first electrode, which is provided at an interface on one surface of a semiconductor substrate, and an electrically floating third conductive region. Since the second first-conductivity-type region connected to the second electrode is arranged between the semiconductor substrate and the semiconductor-type region, the dark current generated at the interface on one surface of the semiconductor substrate is reduced to the first conductivity-type region. Reaching the mold area is reduced. In addition, the moving speed of the signal charges generated in the semiconductor substrate 11 in the planar direction is improved.
- the first first conductivity type region can be made smaller with respect to the pixel area, and it is possible to realize a reduction in dark current, a reduction in capacitance, and an improvement in readout speed.
- a semiconductor substrate including a photoelectric conversion region; a first first conductivity type region provided at an interface on one surface of the semiconductor substrate and connected to a first electrode; a second first-conductivity-type region provided around the first first-conductivity-type region at the interface of the one surface and connected to a second electrode; and a third electrically floating first-conductivity-type region provided around the second first-conductivity-type region at the interface of the one surface.
- the second first-conductivity-type region and the third first-conductivity-type region are arranged in this order around the first first-conductivity-type region, and have curved corners.
- the light receiving element according to any one of (1) to (6), wherein the semiconductor substrate further has a second conductivity type region embedded in the substrate.
- the light receiving element according to (7), wherein the second conductivity type region has an opening at a position facing the first first conductivity type region.
- the light receiving element according to (7) or (8), wherein the second conductivity type region has regions with different impurity concentrations.
- the first first-conductivity-type region extends in the other plane direction than the second first-conductivity-type region and the third first-conductivity-type region, the above (2) to ( 9)
- the light receiving element according to any one of the items.
- the first first-conductivity-type region extends in the direction of the other surface facing the one surface, and further extends in the horizontal direction toward the other surface than the second-conductivity-type region.
- the light receiving element according to any one of (7) to (10) above, which has an overhanging region.
- the light receiving element according to any one of (1) to (15), wherein the semiconductor substrate is made of an intrinsic semiconductor.
- the light receiving element is a semiconductor substrate including a photoelectric conversion region; a first first conductivity type region provided at an interface on one surface of the semiconductor substrate and connected to a first electrode; a second first-conductivity-type region provided around the first first-conductivity-type region at the interface of the one surface and connected to a second electrode; and an electrically floating third first-conductivity-type region provided around the second first-conductivity-type region at the interface of the one surface.
- the X-ray imaging element has a plurality of light receiving elements that generate signal charges based on X-rays
- the light receiving element is a semiconductor substrate including a photoelectric conversion region; a first first conductivity type region provided at an interface on one surface of the semiconductor substrate and connected to a first electrode; a second first-conductivity-type region provided around the first first-conductivity-type region at the interface of the one surface and connected to a second electrode; and an electrically floating third first-conductivity-type region provided around the second first-conductivity-type region at the interface of the one surface.
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Abstract
Description
1.第1の実施の形態(アノードとガードリングとの間にドレインを設けた受光素子の例)
1-1.受光素子の構成
1-2.受光素子の製造方法
1-3.作用・効果
2.第2の実施の形態(アノードをn型導電層方向へ延伸させた例)
3.第3の実施の形態(n型導電層と埋込層との間にアノードの張り出し部を設けた例)
4.第4の実施の形態(複数設けられたガードリングの線幅および間隔を変化させた受光素子の例)
5.第5の実施の形態(不純物の濃度分布を有する埋込層を設けた例)
6.変形例
7.適用例
図1は、本開示の第1の実施形態に係る受光素子(受光素子10)の断面構成を表したものである。受光素子10は、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN(Positive Intrinsic Negative)型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
受光素子10は、例えば、n型の半導体基板11の一面(表面S1;一の面)の界面にp型導電型領域(第1導電型領域)13が部分的に形成され、表面S1とは反対側の面(裏面S2;他の面)の界面にn型導電層(第2導電型層)12が形成されている。p型導電型領域13は複数の領域から構成されており、本実施の形態の受光素子10では、例えば、アノード13Aを構成する領域(第1の第1導電型領域)と、ドレイン13Bを構成する領域(第2の第1導電型領域)と、ガードリング13Cを構成する領域(第3の第1導電型領域)とを有する。更に、本実施の形態では、半導体基板11の内部に埋込層14としてn型導電型領域(第2導電型領域)が形成されている。また、半導体基板11の表面S1上には、絶縁層15が形成されている。
受光素子10は、例えば次のようにして製造することができる。まず、半導体基板11の裏面S2にイオンインプラント技術を用いてn型導電層12を形成する。続いて、半導体基板11の表面S1の所定の領域にマスクを形成したのち、イオンインプラント技術を用いてn型の不純物(例えばリン(P))をドーピングしてn型導電型領域(埋込層14)を形成する。次に、半導体基板11の表面S1の所定の領域にマスクを形成したのち、イオンインプラント技術を用いてp型の不純物(例えばホウ素(B))をドーピングしてp型導電型領域(アノード13A、ドレイン13Bおよびガードリング13C)を形成する。最後に、半導体基板11の表面S1上に、例えばCVD(Chemical Vapor Deposition)法を用いて絶縁層15を形成する。これにより、図1に示した受光素子10が完成する。
前述したように、固体撮像装置は、例えば、デジタルスチルカメラやビデオカメラ等の撮像装置や、撮像機能を有する携帯端末装置等の電子機器、あるいは、可視光以外の様々な波長を検知する電磁波センサ等、様々な用途に用いられている。これら固体撮像装置では、光電変換素子であるフォトダイオードに蓄積された信号電荷を、MOSトランジスタを介して読み出すCMOSイメージセンサが広く利用されている。
図8は、本開示の第2の実施形態に係る受光素子(受光素子20)の断面構成を表したものである。受光素子20は、上記第1の実施の形態と同様に、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
図9は、本開示の第3の実施形態に係る受光素子(受光素子30)の断面構成を表したものである。受光素子30は、上記第1の実施の形態と同様に、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
図10は、本開示の第4の実施形態に係る受光素子(受光素子40)の断面構成を表したものである。図11は、図10に示した受光素子40のp型導電型領域43の平面構成を模式的に表したものである。受光素子40は、上記第1の実施の形態と同様に、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
図12は、本開示の第5の実施形態に係る受光素子(受光素子50)の断面構成を表したものである。図13は、図12に示した受光素子50のp型導電型領域13および埋込層54の平面構成を模式的に表したものである。受光素子50は、上記第1の実施の形態と同様に、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
図14は、本開示の第1の実施形態等の変形例に係る受光素子(受光素子60)におけるp型導電型領域63の平面構成を隣接する他の画素Pと共に模式的に表したものである。受光素子60は、上記第1の実施の形態と同様に、例えば、半導体基板11の表面と裏面との間に逆バイアスを印加するPIN型のフォトダイオードからなり、例えば、放射線(例えば、α線、β線、γ線およびX線等)に基づいて被写体の情報を読み取る(被写体を撮像する)放射線撮像素子(例えば、X線撮像素子1;図15参照)や電磁波検出装置において1つの画素(画素P)を構成するものである。
図15は、上記第1~第5実施の形態および変形例において説明した受光素子(例えば、受光素子10)の素子構造を用いたX線撮像素子1の機能構成を表したものである。X線撮像素子1は、例えば入射する放射線Rrad(例えばα線,β線,γ線,X線等)に基づいて被写体の情報を読み取る(被写体を撮像する)ものである。このX線撮像素子1は、画素部(画素領域110A)を備えると共に、この画素領域110Aの駆動回路(周辺回路部)として、行走査部121、A/D変換部122、列走査部123およびシステム制御部124を備えている。
画素領域110Aは、放射線に基づいて信号電荷を発生させる複数の画素(撮像画素)Pを備えたものである。複数の画素Pは、行列状(マトリクス状)に2次元配置されている。尚、図1に示したように、画素領域110A内における水平方向(行方向)を「H」方向とし、垂直方向(列方向)を「V」方向とする。
行走査部121は、後述のシフトレジスタ回路や所定の論理回路等を含んで構成されており、画素領域110A内の複数の画素Pに対して行単位(水平ライン単位)での駆動(線順次走査)を行う画素駆動部(行走査回路)である。具体的には、各画素Pの読み出し動作やリセット動作等の撮像動作を例えば線順次走査により行う。尚、この線順次走査は、読み出し制御線Lreadを介して前述した行走査信号を各画素Pへ供給することによって行われる。
A/D変換部122は、複数(ここでは4つ)の信号線Lsigごとに1つ設けられた複数の列選択部125を有しており、信号線Lsigを介して入力された信号電圧(信号電荷に応じた電圧)に基づいてA/D変換(アナログ/デジタル変換)を行うものである。これにより、デジタル信号からなる出力データDout(撮像信号)が生成され、外部へ出力される。
列走査部123は、例えば図示しないシフトレジスタやアドレスデコーダ等を含んで構成されており、上記した列選択部125内の各スイッチSW2を走査しつつ順番に駆動するものである。このような列走査部123による選択走査によって、信号線Lsigの各々を介して読み出された各画素Pの信号(上記出力データDout)が、順番に外部へ出力されるようになっている。
システム制御部124は、行走査部121、A/D変換部122および列走査部123の各動作を制御するものである。具体的には、システム制御部124は、前述した各種のタイミング信号(制御信号)を生成するタイミングジェネレータを有しており、このタイミングジェネレータにおいて生成される各種のタイミング信号を基に、行走査部121、A/D変換部122および列走査部123の駆動制御を行う。このシステム制御部124の制御に基づいて、行走査部121、A/D変換部122および列走査部123がそれぞれ画素領域110A内の複数の画素Pに対する撮像駆動(線順次撮像駆動)を行うことにより、画素領域110Aから出力データDoutが取得されるようになっている。
(1)
光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を備えた受光素子。
(2)
前記半導体基板は、さらに、前記一の面と対向する他の面の界面に第2導電型層を有する、前記(1)に記載の受光素子。
(3)
前記第3の第1導電型領域は、前記第2の第1導電型領域の周囲に複数形成されている、前記(1)または(2)のうちのいずれかに記載の受光素子。
(4)
前記第2の第1導電型領域は、前記第1の第1導電型領域の周囲に連続して設けられている、前記(1)乃至(3)のうちのいずれかに記載の受光素子。
(5)
前記第3の第1導電型領域は、前記第2の第1導電型領域の周囲に連続して設けられている、前記(1)乃至(4)のうちのいずれかに記載の受光素子。
(6)
前記第2の第1導電型領域および前記第3の第1導電型領域は、前記第1の第1導電型領域を中心に、この順に配置されると共に、角部が曲線状に形成された多角形の平面形状を有する、前記(1)乃至(5)のうちのいずれかに記載の受光素子。
(7)
前記半導体基板は、さらに、基板内に埋め込み形成された第2導電型領域を有する、前記(1)乃至(6)のうちのいずれかに記載の受光素子。
(8)
前記第2導電型領域は、前記第1の第1導電型領域との対向する位置に開口を有する、前記(7)に記載の受光素子。
(9)
前記第2導電型領域は、不純物濃度の異なる領域を有する、前記(7)または(8)に記載の受光素子。
(10)
前記第1の第1導電型領域は、前記第2の第1導電型領域および前記第3の第1導電型領域よりも前記他の面方向に延在している、前記(2)乃至(9)のうちのいずれかに記載の受光素子。
(11)
前記第1の第1導電型領域は、前記一の面と対向する他の面方向に延在すると共に、前記第2導電型領域よりも前記他の面側に、水平方向にさらに延在する張り出し領域を有する、前記(7)乃至(10)のうちのいずれかに記載の受光素子。
(12)
前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域は、互いに異なる線幅を有する、前記(3)乃至(11)のうちのいずれかに記載の受光素子。
(13)
前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域の線幅は、前記第1の第1導電型領域から離れるに従って段階的に広くなっている、前記(3)乃至(12)のうちのいずれかに記載の受光素子。
(14)
前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域の間隔は、外側に向かって段階的に広くなっている、前記(3)乃至(13)のうちのいずれかに記載の受光素子。
(15)
前記半導体基板は第2導電型を有し、前記第2導電型層および前記第2導電型領域は、前記半導体基板よりも不純物濃度が高い、前記(1)乃至(14)のうちのいずれか1に記載の受光素子。
(16)
前記半導体基板は真性半導体によって構成されている、前記(1)乃至(15)のうちのいずれか1に記載の受光素子。
(17)
X線に基づく信号電荷を発生する複数の受光素子を備え、
前記受光素子は、
光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を有するX線撮像素子。
(18)
複数の画素が配列された画素領域と、
前記画素領域の周囲に設けられた周辺領域とを有し、
前記半導体基板は、前記画素領域に空乏領域を、前記周辺領域に中性領域を有する、前記(17)に記載のX線撮像素子。
(19)
前記受光素子は前記複数の画素毎に設けられ、前記半導体基板の前記一の面と前記一の面と対向する他の面との間に逆バイアスを印加するpn接合型受光素子である、前記(17)または(18)に記載のX線撮像素子。
(20)
X線撮像素子を備え、
前記X線撮像素子は、X線に基づく信号電荷を発生する複数の受光素子を有し、
前記受光素子は、
光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を備える電子機器。
Claims (20)
- 光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を備えた受光素子。 - 前記半導体基板は、さらに、前記一の面と対向する他の面の界面に第2導電型層を有する、請求項1に記載の受光素子。
- 前記第3の第1導電型領域は、前記第2の第1導電型領域の周囲に複数形成されている、請求項1に記載の受光素子。
- 前記第2の第1導電型領域は、前記第1の第1導電型領域の周囲に連続して設けられている、請求項1に記載の受光素子。
- 前記第3の第1導電型領域は、前記第2の第1導電型領域の周囲に連続して設けられている、請求項1に記載の受光素子。
- 前記第2の第1導電型領域および前記第3の第1導電型領域は、前記第1の第1導電型領域を中心に、この順に配置されると共に、角部が曲線状に形成された多角形の平面形状を有する、請求項1に記載の受光素子。
- 前記半導体基板は、さらに、基板内に埋め込み形成された第2導電型領域を有する、請求項1に記載の受光素子。
- 前記第2導電型領域は、前記第1の第1導電型領域との対向する位置に開口を有する、請求項7に記載の受光素子。
- 前記第2導電型領域は、不純物濃度の異なる領域を有する、請求項7に記載の受光素子。
- 前記第1の第1導電型領域は、前記第2の第1導電型領域および前記第3の第1導電型領域よりも前記他の面方向に延在している、請求項2に記載の受光素子。
- 前記第1の第1導電型領域は、前記一の面と対向する他の面方向に延在すると共に、前記第2導電型領域よりも前記他の面側に、水平方向にさらに延在する張り出し領域を有する、請求項7に記載の受光素子。
- 前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域は、互いに異なる線幅を有する、請求項3に記載の受光素子。
- 前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域の線幅は、前記第1の第1導電型領域から離れるに従って段階的に広くなっている、請求項3に記載の受光素子。
- 前記第2の第1導電型領域の周囲に複数形成されている前記第3の第1導電型領域の間隔は、外側に向かって段階的に広くなっている、請求項3に記載の受光素子。
- 前記半導体基板は第2導電型領域をさらに有し、前記第2導電型層および前記第2導電型領域は、前記半導体基板よりも不純物濃度が高い、請求項2に記載の受光素子。
- 前記半導体基板は真性半導体によって構成されている、請求項1に記載の受光素子。
- X線に基づく信号電荷を発生する複数の受光素子を備え、
前記受光素子は、
光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を有するX線撮像素子。 - 複数の画素が配列された画素領域と、
前記画素領域の周囲に設けられた周辺領域とを有し、
前記半導体基板は、前記画素領域に空乏領域を、前記周辺領域に中性領域を有する、請求項17に記載のX線撮像素子。 - 前記受光素子は前記複数の画素毎に設けられ、前記半導体基板の前記一の面と前記一の面と対向する他の面との間に逆バイアスを印加するpn接合型受光素子である、請求項17に記載のX線撮像素子。
- X線撮像素子を備え、
前記X線撮像素子は、X線に基づく信号電荷を発生する複数の受光素子を有し、
前記受光素子は、
光電変換領域を含む半導体基板と、
前記半導体基板の一の面の界面に設けられると共に、第1の電極に接続された第1の第1導電型領域と、
前記一の面の界面において、前記第1の第1導電型領域の周囲に設けられると共に、第2の電極に接続された第2の第1導電型領域と、
前記一の面の界面において、前記第2の第1導電型領域の周囲に設けられると共に、電気的に浮遊状態な第3の第1導電型領域と
を備える電子機器。
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