WO2022228200A1 - 镀膜件及其制备方法、壳体及电子产品 - Google Patents

镀膜件及其制备方法、壳体及电子产品 Download PDF

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WO2022228200A1
WO2022228200A1 PCT/CN2022/087627 CN2022087627W WO2022228200A1 WO 2022228200 A1 WO2022228200 A1 WO 2022228200A1 CN 2022087627 W CN2022087627 W CN 2022087627W WO 2022228200 A1 WO2022228200 A1 WO 2022228200A1
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base layer
layer
metal
base
anodized
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PCT/CN2022/087627
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English (en)
French (fr)
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禹跃斌
许金宝
王想威
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比亚迪股份有限公司
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Priority to EP22794671.2A priority Critical patent/EP4299798A1/en
Priority to KR1020237033653A priority patent/KR20230151545A/ko
Priority to JP2023560322A priority patent/JP2024518253A/ja
Publication of WO2022228200A1 publication Critical patent/WO2022228200A1/zh
Priority to US18/373,842 priority patent/US20240018644A1/en

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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/06—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used
    • C25D11/10—Anodisation of aluminium or alloys based thereon characterised by the electrolytes used containing organic acids
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/16—Pretreatment, e.g. desmutting
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • C25D11/18—After-treatment, e.g. pore-sealing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00—Casings, cabinets or drawers for electric apparatus
    • H05K5/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00—Casings, cabinets or drawers for electric apparatus
    • H05K5/04—Metal casings

Definitions

  • PVD Physical Vapor Deposition, Physical Vapor Deposition
  • the aluminum alloy itself does not have good bonding strength with the PVD coating, and the surface of the aluminum alloy will produce a layer of naturally oxidized aluminum oxide, which affects the combination of the aluminum alloy and the PVD coating.
  • the surface of the aluminum material presents a porous honeycomb structure, and the traditional PVD coating is difficult to combine with the anodic oxide layer, showing the problem of poor surface wear resistance and corrosion resistance.
  • the present application provides a coated part, a preparation method thereof, a casing and an electronic product.
  • the present application provides a coated part, comprising a substrate, an anodized layer and a base layer, the anodized layer is formed on the surface of the substrate, and the base layer is located on the surface of the anodized layer,
  • the base layer includes a first base layer and a second base layer that are stacked in sequence along a direction away from the anodized layer, the first base layer and the second base layer are selected from the deposition layers of metal A, and the first base layer and the second base layer are selected from the deposited layers of metal A.
  • the average grain size of the base layer is smaller than the average grain size of the second base layer, the anodized layer has a microporous structure, and the crystal grains of the first base layer are partially embedded in the micropores of the anodized layer .
  • the average grain size of the crystal grains in the first base layer is 3 nm-30 nm, and the nanohardness of the first base layer is 10 GPa-16 GPa.
  • the thickness of the third base layer is 30 nm-100 nm.
  • the functional layer further includes a transition layer, the transition layer is located between the color layer and the base layer, and the transition layer includes metal A and metal M.
  • the base material is not connected to a bias voltage, and the second base layer is formed by sputtering on the surface of the first base layer by means of vacuum coating.
  • the method before the anodizing treatment, further includes: performing glue dispensing treatment on the electrical contact sites on the surface of the substrate; after the anodizing, removing glue on the surface of the substrate to expose the electrical contact sites point, in a subsequent operation, the substrate is negatively biased with the electrical contact sites.
  • the conditions for controlling the vacuum coating are: applying a negative bias voltage to the substrate, the voltage value is 30V-120V, and the target current is 15A-25A.
  • the present application also provides an electronic product including the above-mentioned housing.
  • an anodized layer is formed on the surface of the base material, and a base layer is provided outside the anodized layer, and the base layer includes a first base layer with a smaller average grain size and an average grain size.
  • the second base layer with larger grain size can be better embedded in the micropores of the anodized layer due to the smaller average grain size of the first base layer, thereby increasing the contact area, thereby increasing the The bonding force between the base layer and the anodized layer, and at the same time, the average grain size of the second base layer is larger than that of the first base layer, which can reduce the base layer to a certain extent. to avoid the problem of the film layer falling off due to the excessive stress of the base layer.
  • the average grain size of the first base layer 31 is small, it can be better embedded in the micropores of the anodized layer 2 , increasing the contact area, thereby improving the connection between the base layer 3 and the anode.
  • the bonding force between the oxide layers 2, at the same time, the average grain size of the second base layer 32 is larger than that of the first base layer 31, which can reduce the internal stress of the base layer 3 to a certain extent, The problem of film peeling due to excessive stress of the base layer 3 is avoided.
  • the substrate 1 can be selected from an integral piece of aluminum or an aluminum alloy, or a laminated structure or a mosaic structure that is partially made of aluminum or an aluminum alloy.
  • the average grain size of the crystal grains in the second base layer 32 is 50nm-100nm, and the nanohardness of the second base layer 32 is 6GPa-9GPa.
  • the third base layer 33 is arranged on the outside of the cladding, which can transform the columnar crystal structure to the fine-grained structure and form a relatively dense surface layer, which is beneficial to improve its wear resistance and provide a good adhesion basis for the subsequent coating layers.
  • the average grain size of the crystal grains in the third base layer 33 is 30nm-60nm, and the nanohardness of the third base layer 33 is 8GPa-10GPa.
  • the average grain size and nanohardness of the third base layer 33 are between the first base layer 31 and the second base layer 32 , so as to further improve the overall strength and wear resistance of the base layer 3 performance.
  • the thickness of the third base layer 33 is 30 nm-100 nm.
  • the thickness of the third base layer 33 is within the above range, it has better coverage and avoids problems of insufficient coverage or excessive internal stress.
  • the pore size of the micropores of the anodized layer 2 is 10 nm-100 nm, and the number of micropores of the anodized layer satisfies 100/ ⁇ m 2 -3000/ ⁇ m 2 .
  • the pore size and the number of pores of the anodized layer 2 are within the above ranges, sufficient micropores can be provided to combine with the first base layer 31 , and the pore size is also beneficial to the crystallinity of the first base layer 31 .
  • the particles are embedded in the pores of the anodized layer 2 to improve the bonding strength.
  • the coating member further includes a functional layer 4 , and the functional layer 4 is located on the side of the base layer 3 away from the anodized layer 2 .
  • the functional layer 4 can be a coating layer that realizes different functions, such as an anti-fingerprint layer, a high hardness layer, etc., or a decorative layer, such as a color layer or a glare layer.
  • the functional layer 4 includes a color layer 42, and the color layer 42 includes oxides of metal M, nitrides of metal M, carbides of metal M, and combinations thereof, and the metal M is selected from Cr , one or more of Ti and W.
  • the color layer 42 can be a single layer or a multi-layer, when the color layer 42 is a multi-layer, different metal M oxides, metal M nitrides or metal M carbides can be provided in different layers, so as to To achieve the purpose of adjusting the color.
  • the thickness of the functional layer 4 is 0.3 ⁇ m ⁇ 3.7 ⁇ m.
  • the color layer 42 is directly disposed on the surface of the base layer 3 .
  • the functional layer 4 further includes a transition layer 41 located between the color layer 42 and the base layer 3 , and the transition layer 41 includes metal A and metal M.
  • Another embodiment of the present application provides a method for preparing the above-mentioned coated part, comprising the following operation steps:
  • the metal A is used as the target material, and the substrate 1 is not connected to a bias voltage, and the second base layer 32 is formed by sputtering on the surface of the first base layer 31 by means of vacuum coating.
  • the metal A ions formed tend to deposit on the first base layer 31 to form a coarse columnar crystal structure in a non-biased manner, and the hardness is low, which is conducive to reducing the The internal stress of the first base layer 31 is described.
  • the method before the anodizing treatment, further includes: performing glue dispensing treatment on the electrical contact sites on the surface of the substrate 1; after the anodizing, removing glue on the surface of the substrate 1 to expose the electrical contacts site, in a subsequent operation, a negative bias is applied to the substrate 1 with the electrical contact site.
  • a negative bias voltage needs to be applied to the substrate 1, and the anodic oxide layer 2 produced by anodization is a non-conductive structure, which is not conducive to the electrical contact between the substrate 1 and the applied power supply.
  • the negative bias applied by the substrate 1, the inventors performed glue dispensing treatment on the electrical contact sites of the substrate 1 before the anodization treatment, so as to form protection for the substrate 1, and then remove the glue after anodization, which can effectively The subsequent application of negative bias voltage on the substrate 1 is ensured, and the film formation quality is improved.
  • the substrate 1 prior to the dispensing process, the substrate 1 is subjected to polishing treatment, and the polishing treatment is chemical polishing or mechanical polishing or a combination thereof, and the natural surface of the substrate 1 is removed by polishing treatment.
  • the oxide layer and surface defects can improve the smoothness of the surface of the substrate 1, which is conducive to the direct contact between the plastic and the surface of the substrate 1 during the dispensing process, and is also conducive to the formation of a denser anodic oxidation process.
  • Anodized layer 2 is anodized layer 2.
  • one or more operations of degreasing, hot water washing, alkaline water washing, cold water washing, and acid washing are performed on the surface of the substrate 1, so that the substrate 1 is 1 Form a smooth surface, remove surface oil and defects, and improve the consistency of film formation.
  • the anodizing treatment conditions are: the tank liquid of the anodizing tank is selected from at least one of sulfuric acid solution, phosphoric acid solution and oxalic acid solution, and the molar concentration of acid in the tank liquid is 0.3mol/L-0.8mol /L, the bath temperature is 15°C-25°C.
  • an anodized layer 2 with uniform pores and a pore size of 10 nm-100 nm is formed on the surface of the substrate 1 , which is beneficial for the embedding of crystal grains in the first base layer 31 .
  • a pre-vacuum operation is performed on the substrate 1 on which the anodized layer 2 is formed.
  • the anodized layer 2 of the substrate 1 has a large number of micropores, which is easy to adsorb dust in the air, and at the same time, there are also debris remaining in the processing process in the micropores, and dust remaining in the micropores. and debris will become the surface impurities of the subsequent vacuum coating, which will further affect the performance of the coating layer.
  • the pre-evacuation method is adopted in this preparation method, and the dust and debris in the micropores of the anodized layer 2 are promoted by the change of air pressure. Chips are discharged to ensure the quality of subsequent coating.
  • ion bombardment is performed on the anodized layer 2 to improve the cleanliness of the anodized layer 2 and increase the surface energy of the anodized layer 2 .
  • the bias voltage used for preparing the first base layer 31 is a further improvement of this preparation method.
  • the inventors adopted a voltage that exceeds the normal range.
  • This bias voltage range can promote the metal A ions to enter the microporous structure of the anodized layer 2, increase the contact area, and thus improve the adhesion.
  • too high negative bias will increase the reverse sputtering, decrease the deposition rate, and cause a large number of defects (vacancies, point defects, line defects), damage the integrity of the film, thereby reducing the quality of the film and affecting the surface properties.
  • the method further includes: performing ion bombardment on the first base layer 31 for 5 min to 10 min, so as to improve the first base layer 31 .
  • the surface energy of a base layer 31 is a base layer 31 .
  • the conditions for controlling the vacuum coating are: DC mode, no bias voltage, and target current of 5A-10A.
  • a negative bias is applied to the base material 1 , and the third base layer 33 is formed by sputtering on the surface of the second base layer 32 by means of vacuum coating.
  • the second base layer 32 prepared without bias voltage has a coarse columnar crystal structure. Therefore, after the second base layer 32 is deposited to a certain thickness, the third base layer 33 is added to make the film layer change from a columnar structure to a fine crystal structure, and the final completion Base layer 3 plated.
  • the preparation method further comprises the following operations:
  • a transition layer 41 is formed on the surface of the base layer 3 by vacuum coating by sputtering, the metal A includes Cr and/or Ti, and the metal M includes Cr, Ti and W one or more of.
  • the preparation method further comprises the following operations:
  • the oxygen source can be selected from O 2
  • the nitrogen source can be selected from N 2
  • the carbon source can be selected from C 2 H 2 .
  • the reactive gas may not be introduced, so as to obtain a coating of the metal M, and the coating has metallic luster.
  • Another embodiment of the present application provides an electronic product casing, including the above-mentioned coating member.
  • the electronic product casing Due to the use of the above-mentioned coated parts, the electronic product casing has better surface wear resistance and also has better aesthetic effects.
  • This embodiment is used to illustrate the coated parts disclosed in the present application and the preparation method thereof, including the following operation steps:
  • Anodizing pretreatment the aluminum alloy substrate is subjected to mechanical polishing-dispensing-oil removal-hot water washing-alkali washing-cold washing-pickling-cold washing in sequence.
  • Anodizing treatment the pretreated aluminum alloy substrate is placed in an anodizing tank for anodizing operation.
  • the solution used for anodizing is a sulfuric acid solution with a concentration of 0.5 mol/L and a tank temperature of 18°C.
  • An anodized layer with a film thickness of 8 mm, a pore size of 20-40 nm, and a pore number of 2000/ ⁇ m 2 was formed.
  • PVD coating pretreatment includes degumming-cleaning-drying-pre-pumping high vacuum. Wherein, the glue removal is to remove the plastic in step (1).
  • PVD coating place the aluminum alloy substrate treated above in a vacuum coating machine, and conduct coating treatment after vacuuming, heating, and ion cleaning. details as follows:
  • Preparation of the first base layer a Cr target is used, the bias voltage is set to -300V, the Cr target current is 25A, the thickness of the coating film is 50nm, the average grain size of the first base layer is 8nm, and the first base layer The nanohardness of 14GPa; ion bombardment for 10min after coating;
  • Preparation of the second base layer use a Cr target, set the DC mode (no bias), the Cr target current is 8A, the thickness of the coating layer is 80nm, the average grain size of the second base layer is 60nm, and the first The nanohardness of the second base layer is 8GPa;
  • Preparation of the third base layer use a Cr target, set a bias voltage of -80V, a Cr target current of 20A, the thickness of the coating layer is 60nm, the average grain size of the third base layer is 40nm, and the third base layer
  • the nano-hardness is 9GPa, that is, the base layer plating is completed.
  • Ti target and Cr target are used for co-plating, DC mode (no bias voltage) is set, target current is 20A, and the thickness of the coating film is 500nm.
  • Preparation of color layer Ti target was used, reactant gas was introduced during magnetron sputtering, the reactant gas was nitrogen, DC mode (no bias) was set, target current was 20A, and the thickness of the coating film was 800nm.
  • the present embodiment is used to illustrate the coated parts disclosed in the application and the preparation method thereof, including most of the operation steps in the embodiment 1, and the difference is:
  • Preparation of the first base layer use a Cr target, set a bias voltage of -200V, a Cr target current of 20A, a thickness of the plated film layer of 100nm, the average grain size of the first base layer is 25nm, and the first base layer The nanohardness of 11GPa; ion bombardment for 10min after coating;
  • Preparation of the second base layer use a Cr target, set the DC mode (no bias), the Cr target current is 10A, the thickness of the coating layer is 50nm, the average grain size of the second base layer is 50nm, and the first The nanohardness of the second base layer is 9GPa;
  • Preparation of the third base layer use a Cr target, set a bias voltage of -120V, a Cr target current of 25A, the thickness of the coating film layer is 30nm, the average grain size of the third base layer is 30nm, and the third base layer
  • the nano-hardness is 10GPa, that is, the base layer plating is completed.
  • Preparation of the second base layer use a Cr target, set the DC mode (no bias), the Cr target current is 5A, the thickness of the coating layer is 120nm, the average grain size of the second base layer is 100nm, and the first The nanohardness of the second base layer is 6GPa;
  • Preparation of the third base layer use a Cr target, set a bias voltage of -30V, a Cr target current of 15A, the thickness of the coating film layer is 100nm, the average grain size of the third base layer is 60nm, and the third base layer
  • the nano-hardness is 8GPa, that is, the base layer plating is completed.
  • the thickness of the plated film layer is 20 nm.
  • the thickness of the plated film layer is 40 nm.
  • the thickness of the plated film layer is 150 nm.
  • step (4) after the second base layer is prepared, the transition layer is directly plated without the preparation of the third base layer.
  • step (3) no pre-pumping high vacuum treatment is performed.
  • This comparative example is used to compare and illustrate the coated parts disclosed in the present application and the preparation method thereof, including most of the operation steps in Example 1, and the differences are:
  • This comparative example is used to compare and illustrate the coated parts disclosed in the present application and the preparation method thereof, including most of the operation steps in Example 1, and the differences are:
  • step (4) during the preparation of the base layer, the preparation of the second base layer is not carried out, and the preparation of the first base layer and the third base layer is directly carried out.
  • the film layer is partially or completely peeled off in large fragments along the cutting edge, and/or partially or completely peeled off on different parts of the lattice, and the affected cross-cut area is greater than 15%, but not greater than 35%;
  • the coating is peeled off in large fragments along the cutting edge, and/or some squares are partially or completely peeled off, and the affected cross-cut area is greater than 35%, but not greater than 65%;
  • the surface of the coated part was sprayed with salt water continuously with a NaCl solution with a pH value of 6.8 and 5% by weight; after every 12h of the test, the appearance of the sample was checked; Rinse gently with warm water and wipe clean with a dust-free cloth. Check the sample after placing it at room temperature for 2 hours, and record the longest time when there is no abnormality in the appearance of the film layer and no obvious change in appearance (such as rust, discoloration and peeling of the surface treatment layer, etc.).

Abstract

提供了一种镀膜件及其制备方法、壳体及电子产品，镀膜件包括基材、阳极氧化层和基础层，所述阳极氧化层形成于所述基材的表面，所述基础层位于所述阳极氧化层的表面，所述基础层包括沿远离所述阳极氧化层的方向依次层叠的第一基础层和第二基础层，所述第一基础层和第二基础层选自金属A的沉积层，所述第一基础层的平均晶粒粒径小于所述第二基础层的平均晶粒粒径，所述阳极氧化层具有微孔结构，所述第一基础层的晶粒部分嵌入所述阳极氧化层的微孔中。

Description

镀膜件及其制备方法、壳体及电子产品
优先权信息
本申请请求于2021年04月30日向中国国家知识产权局提交的、专利申请号为202110484484.1、申请名称为“镀膜件及其制备方法、壳体及电子产品”的中国专利申请的优先权，并且其全部内容通过引用结合在本申请中。
技术领域
本申请属于金属表面处理技术领域，具体涉及一种镀膜件及其制备方法、壳体及电子产品。
背景技术
由于电子产品的轻量化要求，主流机型多数采用铝合金作为中框选材。目前，铝合金表面通常采用阳极氧化技术来提高表面耐腐蚀、耐磨擦磨损等性能。PVD(Physical Vapor Deposition，物理气相沉积)技术不仅可以显著提高基材表面耐磨、耐腐蚀性、硬度，还能获得色彩、光泽度优于阳极氧化技术的外观面。该技术在不锈钢材料上已获得广泛应用，但在铝合金基材上却很少用PVD镀层进行表面保护，其原因主要在于：
铝合金本身与PVD镀层没有较好的结合强度，而且铝合金的表面会产生一层自然氧化的氧化铝，影响铝合金与PVD镀层的结合，尤其是，现有的铝合金在阳极氧化后铝材表面呈现多孔蜂窝结构，传统的PVD镀层难以与阳极氧化层较好的结合，表现出表面耐磨性能和耐腐蚀性能差的问题，最终铝材外观面不具有明显的金属质感，失去了与阳极染色封孔的成熟工艺方案的竞争优势。
公开内容
针对现有阳极氧化后的铝合金进行PVD镀层存在耐磨性和耐腐蚀性差的问题，本申请提供了一种镀膜件及其制备方法、壳体及电子产品。
本申请解决上述技术问题所采用的技术方案如下：
一方面，本申请提供了一种镀膜件，包括基材、阳极氧化层和基础层，所述阳极氧化层形成于所述基材的表面，所述基础层位于所述阳极氧化层的表面，所述基础层包括沿远离所述阳极氧化层的方向依次层叠的第一基础层和第二基础层，所述第一基础层和第二基础层选自金属A的沉积层，所述第一基础层的平均晶粒粒径小于所述第二基础层的平均晶粒粒径，所述阳极氧化层具有微孔结构，第一基础层的晶粒部分嵌入所述阳极氧化层的微 孔中。
根据本申请的实施例，所述基材包括铝或铝合金。
根据本申请的实施例，所述金属A包括Cr和/或Ti。
根据本申请的实施例，所述第一基础层的厚度为30nm-100nm，所述第二基础层的厚度为50nm-120nm。
根据本申请的实施例，所述第一基础层中晶粒的平均粒径为3nm-30nm，所述第一基础层的纳米硬度为10GPa-16GPa。
根据本申请的实施例，所述第二基础层中晶粒的平均粒径为50nm-100nm，所述第二基础层的纳米硬度为6GPa-9GPa。
根据本申请的实施例，所述基础层还包括第三基础层，所述第一基础层、所述第二基础层和所述第三基础层沿远离所述阳极氧化层的方向依次层叠，所述第三基础层选自金属A的沉积层，所述第三基础层的平均晶粒粒径小于所述第二基础层的平均晶粒粒径。
根据本申请的实施例，所述第三基础层中晶粒的平均粒径为30nm-60nm，所述第三基础层的纳米硬度为8GPa-10GPa。
根据本申请的实施例，所述第三基础层的厚度为30nm-100nm。
根据本申请的实施例，所述阳极氧化层的厚度4μm-16μm。
根据本申请的实施例，所述阳极氧化层的微孔的孔径为10nm-100nm，所述阳极氧化层的微孔数量满足100个/μm 2-3000个/μm 2。
根据本申请的实施例，所述镀膜件还包括有功能层，所述功能层位于所述基础层上背离所述阳极氧化层的一侧，所述功能层包括颜色层，所述颜色层包括金属M的氧化物、金属M的氮化物或金属M的碳化物及其组合，所述金属M选自Cr、Ti和W中的一种或多种。
根据本申请的实施例，所述颜色层的厚度为0.3μm-3μm。
根据本申请的实施例，所述功能层还包括过渡层，所述过渡层位于所述颜色层与所述基础层之间，所述过渡层包括金属A和金属M。
根据本申请的实施例，所述过渡层的厚度为0.3μm-1μm。
另一方面，本申请提供了制备如上所述的镀膜件的方法，包括以下操作步骤：
提供基材，对基材的表面进行阳极氧化处理，以形成阳极氧化层；
以金属A为靶材，对基材施加负偏压，通过真空镀膜的方式在阳极氧化层的表面溅射形成第一基础层；
以金属A为靶材，基材不接入偏压，通过真空镀膜的方式在第一基础层的表面溅射形成第二基础层。
根据本申请的实施例，在所述阳极氧化处理之前，还包括：对基材表面的电接触位点进行点胶处理；在阳极氧化后，对基材表面进行除胶，以露出电接触位点，在后续操作中，以所述电接触位点对所述基材施加负偏压。
根据本申请的实施例，所述阳极氧化处理条件为：阳极氧化槽的槽液选自硫酸溶液、磷酸溶液和草酸溶液中的至少一种，槽液中酸的摩尔浓度为0.3mol/L-0.8mol/L，槽液温度为15℃-25℃。
根据本申请的实施例，制备所述第一基础层时，控制真空镀膜的条件为：对基材施加负偏压，电压值为200V～400V，靶电流为20A-30A。
根据本申请的实施例，制备所述第一基础层后，制备所述第二基础层之前，还包括：对第一基础层进行离子轰击，时间为5min-10min。
根据本申请的实施例，制备所述第二基础层时，控制真空镀膜的条件为：直流模式，无偏压，靶电流为5A-10A。
根据本申请的实施例，还包括以下操作：
以金属A为靶材，对基材施加负偏压，通过真空镀膜的方式在所述第二基础层的表面溅射形成第三基础层。
根据本申请的实施例，制备所述第三基础层时，控制真空镀膜的条件为：对基材施加负偏压，电压值为30V～120V，靶电流为15A-25A。
根据本申请的实施例，上述方法还包括以下操作：
以金属A和金属M为靶材，通过真空镀膜的方式在基础层的表面溅射形成过渡层，所述金属A包括Cr和/或Ti，所述金属M包括Cr、Ti和W中的一种或多种。
根据本申请的实施例，上述方法还包括以下操作：
以金属M为靶材，通入氧源、氮源或碳源的一种或多种作为反应性气体，通过真空镀膜的方式在过渡层的表面溅射形成颜色层。
另一方面，本申请提供了一种壳体，包括如上所述的镀膜件。
另一方面，本申请还提供了一种电子产品，包括如上所述的壳体。
根据本申请提供的镀膜件，在基材的表面形成阳极氧化层，在阳极氧化层的外部设置有基础层，所述基础层包括有平均晶粒粒径较小的第一基础层和平均晶粒粒径较大的第二基础层，由于所述第一基础层的平均晶粒粒径较小，因此能够更好地嵌入于所述阳极氧化层的微孔中，增加接触面积，进而提高所述基础层与所述阳极氧化层之间的结合力，同时，所述第二基础层的平均晶粒粒径相比于第一基础层较大，能够在一定程度上降低所述基础层的内应力，避免由于基础层的应力过大造成膜层脱落的问题。由所述第一基础层和所述第二基础层结合形成的基础层，一方面对所述阳极氧化层具有封孔的作用，避免后续灰尘 等进入阳极氧化层中；另一方面也可作为后续真空镀膜的基础，能够有效提高基材与后续真空镀膜的结合强度，达到耐磨损和耐腐蚀的作用。
本公开的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1是本申请提供的镀膜件的结构示意图。
说明书附图中的附图标记如下：
1、基材；2、阳极氧化层；3、基础层；31、第一基础层；32、第二基础层；33、第三基础层；4、功能层；41、过渡层；42、颜色层。
具体实施方式
为了使本申请所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
参见图1所示，本申请实施例提供了一种镀膜件，包括基材1、阳极氧化层2和基础层3，所述阳极氧化层2形成于所述基材1的表面，所述基础层3位于所述阳极氧化层2的表面，所述基础层3包括沿远离所述阳极氧化层2的方向依次层叠的第一基础层31和第二基础层32，所述第一基础层31和第二基础层32选自金属A的沉积层，所述第一基础层31的平均晶粒粒径小于所述第二基础层32的平均晶粒粒径，所述阳极氧化层2具有微孔结构，所述第一基础层31的晶粒部分嵌入所述阳极氧化层2的微孔中。
由于所述第一基础层31的平均晶粒粒径较小，因此能够更好地嵌入于所述阳极氧化层2的微孔中，增加接触面积，进而提高所述基础层3与所述阳极氧化层2之间的结合力，同时，所述第二基础层32的平均晶粒粒径相比于第一基础层31较大，能够在一定程度上降低所述基础层3的内应力，避免由于基础层3的应力过大造成膜层脱落的问题。由所述第一基础层31和所述第二基础层32结合形成的基础层3，一方面对所述阳极氧化层2具有封孔的作用，避免后续灰尘等进入阳极氧化层2中；另一方面也可作为后续真空镀膜的基础，能够有效提高基材1与后续真空镀膜的结合强度，达到耐磨损和耐腐蚀的作用。
在一些实施例中，所述基材1包括铝或铝合金。
在不同的实施例中，所述基材1可选自铝或铝合金的整体件，或是部分为铝或铝合金的层叠结构或镶嵌结构。
在一些实施例中，所述金属A包括Cr和/或Ti。
在一些实施例中，所述第一基础层31的厚度为30nm-100nm，所述第二基础层32的厚度为50nm-120nm。
当所述第一基础层31的厚度处于上述范围内时，所述第一基础层31具有与所述阳极氧化层2较强的结合力，同时，当所述第二基础层32的厚度处于上述范围内时，所述第一基础层31的内应力能够被所述第二基础层32较好的减弱，形成过渡缓冲作用。
在一些实施例中，所述第一基础层31中晶粒的平均粒径为3nm-30nm，所述第一基础层31的纳米硬度为10GPa-16GPa。
在一些实施例中，所述第二基础层32中晶粒的平均粒径为50nm-100nm，所述第二基础层32的纳米硬度为6GPa-9GPa。
所述第一基础层31为细晶结构，结构稳定致密，附着性能好，但硬度较高，成型后内应力较高，存在一定的缺陷(空位、点缺陷、线缺陷)。所述第二基础层32为粗大的柱状晶结构，其相对硬度较低，将所述第二基础层32与所述第一基础层31结合，利于降低内应力，减少缺陷数量。
在一些实施例中，所述基础层3还包括第三基础层33，所述第一基础层31、所述第二基础层32和所述第三基础层33沿远离所述阳极氧化层2的方向依次层叠，所述第三基础层33选自金属A的沉积层，所述第三基础层33的平均晶粒粒径小于所述第二基础层32的平均晶粒粒径。
由于所述第二基础层32为粗大的柱状晶结构，性质不够致密，直接在第二基础层32上进行后续其他物质的镀膜，存在结合力不足的问题，通过在所述第二基础层32的外部设置所述第三基础层33，能够使柱状晶结构向细晶结构转变，形成较为致密的表层，利于提高其耐磨性能，以及为后续镀层提供良好的附着基础。
在一些实施例中，所述第三基础层33中晶粒的平均粒径为30nm-60nm，所述第三基础层33的纳米硬度为8GPa-10GPa。
所述第三基础层33的平均晶粒粒径和纳米硬度处于所述第一基础层31和所述第二基础层32之间，用于进一步提高所述基础层3的整体强度和耐磨性能。
在一些实施例中，所述第三基础层33的厚度为30nm-100nm。
所述第三基础层33的厚度处于上述范围内时，具有较好的覆盖性，避免覆盖不到位或内应力过大的问题。
在一些实施例中，所述阳极氧化层2的厚度4μm-16μm。
在一些实施例中，所述阳极氧化层2的微孔的孔径大小为10nm-100nm，所述阳极氧化层的微孔数量满足100个/μm 2-3000个/μm 2。
当所述阳极氧化层2的孔径和孔数处于上述范围中时，能够提供足够的微孔与所述第 一基础层31进行结合，同时该孔径大小也利于所述第一基础层31的晶粒嵌入到所述阳极氧化层2的微孔中，以提高结合强度。
在一些实施例中，所述镀膜件还包括有功能层4，所述功能层4位于所述基础层3上背离所述阳极氧化层2的一侧。
在不同的实施例中，所述功能层4可以是实现不同功能的镀膜层，如抗指纹层、高硬度层等，也可以是装饰层，如颜色层或炫光层等。
在一些实施例中，所述功能层4包括颜色层42，所述颜色层42包括金属M的氧化物、金属M的氮化物或金属M的碳化物及其组合，所述金属M选自Cr、Ti、W中的一种或多种。
所述颜色层42可为单层或多层，当所述颜色层42为多层时，可在不同层中设置不同金属M的氧化物、金属M的氮化物或金属M的碳化物，以达到调整颜色的目的。
在一些实施例中，所述功能层4的厚度为0.3μm～3.7μm。
在一些实施例中，所述颜色层42的厚度为0.3μm-3μm。
在一些实施例中，所述颜色层42直接设置于所述基础层3的表面。
在另一实施例中，所述功能层4还包括过渡层41，所述过渡层41位于所述颜色层42与所述基础层3之间，所述过渡层41包括金属A和金属M。
所述过渡层41用于作为所述基础层3和所述颜色层42之间的过渡，所述基础层3中含有金属A，所述颜色层42由金属M的氧化物、金属M的氮化物或金属M的碳化物组成，所述过渡层41中同时含有金属A和金属M，所述过渡层41与所述基础层3和所述颜色层42的亲和性均较高，能够保证其同时与所述基础层3和所述颜色层42具有较好的结合强度，避免由于物质差异过大导致的分层现象。
在一些实施例中，所述过渡层41的厚度为0.3μm-1μm。
本申请的另一实施例提供了制备如上所述的镀膜件的方法，包括以下操作步骤：
提供基材1，对基材1的表面进行阳极氧化处理，以形成阳极氧化层2；
以金属A为靶材，对基材1施加负偏压，通过真空镀膜的方式在阳极氧化层2的表面溅射形成第一基础层31；
以金属A为靶材，基材1不接入偏压，通过真空镀膜的方式在第一基础层31的表面溅射形成第二基础层32。
上述提供的制备方法中，在第一基础层31的真空镀膜过程中，金属A的靶材受到高能粒子冲击电离出的金属A离子，通过对基材1施加负偏压，能够提高基材1对于金属A离子的吸引力并加速金属A离子，赋予金属A离子在沉积的同时还具有轰击基材1的能量，通过提供负偏压，成型的第一基础层31由粗大的柱状晶结构向细晶结构转化，细晶结构稳 定、致密，是理想的膜层结构，附着性能好。而在第二基础层32的真空镀膜过程中，采用无偏压的方式，形成的金属A离子则偏向于在第一基础层31上沉积形成粗大的柱状晶结构，硬度较低，利于降低所述第一基础层31的内应力。
在一些实施例中，在所述阳极氧化处理之前，还包括：对基材1表面的电接触位点进行点胶处理；在阳极氧化后，对基材1表面进行除胶，以露出电接触位点，在后续操作中，以所述电接触位点对所述基材1施加负偏压。
由于在本制备方法中，需要对所述基材1施加负偏压，而由于阳极氧化产生的阳极氧化层2为非导电结构，不利于基材1与施加电源的电接触，为保证对所述基材1施加的负偏压，发明人通过在阳极氧化处理之前对基材1的电接触位点进行点胶处理，从而对基材1形成保护，在阳极氧化后再除胶，能够有效保证基材1后续负偏压的施加，提升了成膜质量。
点胶处理所用的材料无特别选择，可以为现有的塑胶材料。
在一些实施例中，在进行点胶处理之前，对所述基材1进行抛光处理，所述抛光处理为化学抛光或机械抛光或其结合，通过抛光处理以去除所述基材1表面的自然氧化层以及表面缺陷(如划痕等)，能够提高基材1表面的光滑度，有利于点胶处理时，塑胶与基材1表面的直接接触，也利于阳极氧化处理过程中形成更加致密的阳极氧化层2。
在一些实施例中，在进行点胶处理后，对所述基材1表面进行除油、热水洗、碱水洗、冷水洗、酸洗操作中的一种或多种，以使所述基材1形成光洁表面，去除表面油污和缺陷，提高成膜的一致性。
在一些实施例中，所述阳极氧化处理条件为：阳极氧化槽的槽液选自硫酸溶液、磷酸溶液和草酸溶液的至少一种，槽液中酸的摩尔浓度为0.3mol/L-0.8mol/L，槽液温度为15℃-25℃。
通过上述阳极氧化处理，在所述基材1的表面形成一层孔隙均匀的，孔径大小为10nm-100nm的阳极氧化层2，利于所述第一基础层31的晶粒嵌入。
在一些实施例中，制备所述第一基础层31之前，对形成有阳极氧化层2的基材1进行预抽真空操作。
所述基材1的阳极氧化层2上具有大量的微孔，极易对空气中的灰尘进行吸附，同时在微孔中也留有加工过程中残留的碎屑，而微孔中残留的灰尘和碎屑会成为后续真空镀膜的表面杂质，进一步影响膜层性能，为解决该问题，本制备方法中采用了预抽真空的方式，通过气压变化促使阳极氧化层2微孔中的灰尘和碎屑排出，保证后续镀膜质量。
在一些实施例中，制备所述第一基础层31之前，对阳极氧化层2进行离子轰击，以提高所述阳极氧化层2的清洁度，提高阳极氧化层2的表面能。
在一些实施例中，制备所述第一基础层31时，控制真空镀膜的条件为：对基材施加负偏压，电压值为200V～400V，靶电流为20A-30A。
需要说明的是，制备所述第一基础层31所采用的偏压是本制备方法进一步的改进，为了进一步增加第一基础层31与阳极氧化层2的结合力，发明人采用了超出正常范围的高偏压工艺参数，该偏压范围可以促使金属A离子进入阳极氧化层2微孔结构中，增加接触面积，从而提升附着力。然而过高的负偏压会使得反溅射增大，沉积速率下降，并造成大量缺陷(空位、点缺陷、线缺陷)，损伤膜层完整性，从而降低了膜层质量，影响表面性能。
在一些实施例中，制备所述第一基础层31后，制备所述第二基础层32之前，还包括：对第一基础层31进行离子轰击，时间为5min-10min，以提高所述第一基础层31的表面能。
在一些实施例中，制备所述第二基础层32时，控制真空镀膜的条件为：直流模式，无偏压，靶电流为5A-10A。
为使得受损的第一基础层31得到一定程度的修复，需要在此基础之上沉积一层相对质软的第二基础层32以形成过渡，降低第一基础层31内应力，减少缺陷数量。
在一些实施例中，所述制备方法还包括以下操作：
以金属A为靶材，对基材1施加负偏压，通过真空镀膜的方式在所述第二基础层32的表面溅射形成第三基础层33。
无偏压制备得到的第二基础层32是粗大的柱状晶结构，因此在第二基础层32沉积一定厚度后，增加第三基础层33使得膜层由柱状结构向细晶结构转变，最终完成基础层3镀制。
在一些实施例中，制备所述第三基础层33时，控制真空镀膜的条件为：对基材施加负偏压，电压值为30V～120V，靶电流为15A-25A。
在一些实施例中，所述制备方法还包括以下操作：
以金属A和金属M为靶材，通过真空镀膜的方式在基础层3的表面溅射形成过渡层41，所述金属A包括Cr和/或Ti，所述金属M包括Cr、Ti和W中的一种或多种。
在一些实施例中，所述制备方法还包括以下操作：
以金属M为靶材，通入氧源、氮源或碳源的一种或多种作为反应性气体，通过真空镀膜的方式在过渡层41的表面溅射形成颜色层42。
所述氧源可选自O 2，所述氮源可选自N 2，所述碳源可选自C 2H 2。
需要说明的是，当采用氧源、氮源或碳源中的多种作为反应性气体时，为避免反应性气体之间的相互反应，需要将氧源、氮源或碳源分别通入与靶材溅射出的金属M离子反应，以形成金属M的氧化物、金属M的氮化物或金属M的碳化物混合层。
在一些实施例中，制备所述颜色层42时，也可不通入所述反应性气体，以得到金属M 的镀层，镀层呈金属光泽。
本申请的另一实施例提供了一种电子产品壳体，包括如上所述的镀膜件。
由于采用了如上所述的镀膜件，所述电子产品壳体具有较好的表面耐磨性能，同时也具有较好的美观效果。
以下通过实施例对本申请进行进一步的说明。
实施例1
本实施例用于说明本申请公开的镀膜件及其制备方法，包括以下操作步骤：
(1)阳极氧化预处理：将铝合金基材依次进行机械抛光—点胶—除油—热水洗—碱洗—冷水洗—酸洗—冷水洗处理。
(2)阳极氧化处理：将预处理后的铝合金基材置于阳极氧化槽中进行阳极氧化操作，阳极氧化使用的溶液为硫酸溶液，浓度为0.5mol/L，槽液温度为18℃，形成膜层厚度8mm，孔径大小为20-40nm，孔数2000个/μm 2的阳极氧化层。
(3)PVD镀膜预处理：PVD镀膜预处理包括除胶—清洗—烘干—预抽高真空。其中，除胶是将步骤(1)中的塑胶去除。
(4)PVD镀膜：将经过上述处理的铝合金基材置于真空镀膜机中，经过抽真空、加热、离子清洗后进行镀膜处理。具体如下：
第一基础层的制备：采用Cr靶，设置偏压-300V，Cr靶电流25A，镀制膜层厚度50nm，所述第一基础层的平均晶粒粒径为8nm，所述第一基础层的纳米硬度为14GPa；镀膜后离子轰击10min；
第二基础层的制备：采用Cr靶，设置直流模式(无偏压)，Cr靶电流8A，镀制膜层厚度80nm，所述第二基础层的平均晶粒粒径为60nm，所述第二基础层的纳米硬度为8GPa；
第三基础层的制备：采用Cr靶，设置偏压-80V，Cr靶电流20A，镀制膜层厚度60nm，所述第三基础层的平均晶粒粒径为40nm，所述第三基础层的纳米硬度为9GPa，即完成基础层镀制。
过渡层的制备：采用Ti靶和Cr靶共同镀制，设置直流模式(无偏压)，靶电流20A，镀制膜层厚度500nm。
颜色层的制备：采用Ti靶，磁控溅射时通入反应气体，所述反应气体为氮气，设置直流模式(无偏压)，靶电流20A，镀制膜层厚度800nm。
实施例2
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作 步骤，其不同之处在于：
第一基础层的制备：采用Cr靶，设置偏压-200V，Cr靶电流20A，镀制膜层厚度100nm，所述第一基础层的平均晶粒粒径为25nm，所述第一基础层的纳米硬度为11GPa；镀膜后离子轰击10min；
第二基础层的制备：采用Cr靶，设置直流模式(无偏压)，Cr靶电流10A，镀制膜层厚度50nm，所述第二基础层的平均晶粒粒径为50nm，所述第二基础层的纳米硬度为9GPa；
第三基础层的制备：采用Cr靶，设置偏压-120V，Cr靶电流25A，镀制膜层厚度30nm，所述第三基础层的平均晶粒粒径为30nm，所述第三基础层的纳米硬度为10GPa，即完成基础层镀制。
实施例3
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第一基础层的制备：采用Cr靶，设置偏压-400V，Cr靶电流30A，镀制膜层厚度30nm，所述第一基础层的平均晶粒粒径为3nm，所述第一基础层的纳米硬度为16GPa；镀膜后离子轰击10min；
第二基础层的制备：采用Cr靶，设置直流模式(无偏压)，Cr靶电流5A，镀制膜层厚度120nm，所述第二基础层的平均晶粒粒径为100nm，所述第二基础层的纳米硬度为6GPa；
第三基础层的制备：采用Cr靶，设置偏压-30V，Cr靶电流15A，镀制膜层厚度100nm，所述第三基础层的平均晶粒粒径为60nm，所述第三基础层的纳米硬度为8GPa，即完成基础层镀制。
实施例4
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第一基础层的制备中：镀制膜层厚度20nm。
实施例5
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第一基础层的制备中：镀制膜层厚度150nm。
实施例6
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第二基础层的制备中：镀制膜层厚度40nm。
实施例7
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第二基础层的制备中：镀制膜层厚度150nm。
实施例8
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
第一基础层的制备中：设置偏压-500V。
实施例9
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
步骤(4)中，制备完第二基础层后，不进行第三基础层的制备，直接镀制过渡层。
实施例10
本实施例用于说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
步骤(3)中，不进行预抽高真空处理。
对比例1
本对比例用于对比说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
步骤(4)中，进行基础层的制备时，不进行第一基础层的制备，直接进行第二基础层和第三基础层的制备。
对比例2
本对比例用于对比说明本申请公开的镀膜件及其制备方法，包括实施例1中大部分的操作步骤，其不同之处在于：
步骤(4)中，进行基础层的制备时，不进行第二基础层的制备，直接进行第一基础层和第三基础层的制备。
性能测试
对上述实施例1～10和对比例1～2制备得到的镀膜件进行如下性能测试：
1、百格附着力测试：
1)测试前检查外观无异常，无变色、气泡、裂口、脱落等，并用无尘布将基材表面擦拭干净；
2)握住切割刀具，划格时刀面与测试面垂直防止刀口将膜层翘起，划格方向与样品成45度角，对切割刀具均匀施力(力度以使刀刃刚好透过膜层到达底材为准)形成10×10个连续的1mm×1mm的正方形小格；
3)用无尘布将测试区域的碎片刷干净，均匀拉出一段NICHIBAN CT405AP-24胶带，除去最前面的一段，然后剪下约55mm的胶带，把该胶带的中心点放在网格上方，方向与一组切割线平行，然后用指甲把胶带在网格区上方的部位压平，确保胶带与膜层接触良好(注意指甲不允许刮伤胶带及膜层)，胶带长度至少超过网格20mm；
4)贴上胶带静置90s，拿住胶带悬空的一端，并在尽可能接近60度的角度，在0.5-1.0s内迅速拉下胶带；
5)检查膜层脱落状况，其中，达到或者超过4B时为合格，具体的评定标准如下：
5B：切割边缘完全平滑，无一脱落；
4B：在切口交叉处有少许涂层脱落，受影响的交叉切割面积不大于5％；
3B：在切口交叉处和/或沿切口边缘有涂层脱落，受影响的交叉切割面积大于5％，但不大于15％；
2B：膜层沿切割边缘部分或全部以大碎片脱落，和/或在格子不同部分上部分或全部脱落，受影响的交叉切割面积大于15％，但不大于35％；
1B：涂层沿切割边缘大碎片剥落，和/或一些方格部分或者全部出现脱落，受影响的交叉切割面积大于35％，但不大于65％；
0B：剥落的程度超过1B。
2.、耐磨性能：
1)准备3份RKF 10K(黄色圆锥体)和1份RKK15P(绿色棱锥体)，共15L，加入到 振动摩擦设备(ROSLER，型号为R180/530TE-30，频率为50±0.5Hz，振幅为1.65±0.1mm)研磨槽内；
2)用移液管吸取FC120 10ml至研磨槽内，并加入0.5L水；
3)加入0.5L水到研磨槽内；测试过程中每隔30min加入0.5L水和10ml FC120；
4)准备测试用整机或配重的整机，将各样品安装在整机上，放入振动摩擦测试设备进行测试，各样品每0.5小时检查一次，记录符合标准(连续锯齿磨损不超过10mm(锯齿定义：线性磨损区域有两个以上位置宽度在1-1.5mm之间，宽度超过1.5mm不接受)；点磨损不超过1.5mm*1.5mm；1mm*1mm～1.5mm*1.5mm不超过2个；1mm*1mm以下不计)的最长时间。
3、盐水喷雾试验：
在温度为35℃、湿度为90％的密闭环境中，用pH值为6.8、5重量％的NaCl溶液连续对镀膜件表面进行盐水喷雾；每试验12h时间后，检查样品外观；然后使用38℃的温水进行轻柔的冲洗，并用无尘布擦拭干净，常温放置2小时后检查样品，记录膜层外观无异常、外观无明显变化(如锈蚀、变色及表面处理层剥落等)的最长时间。
得到的测试结果填入表1。
表1
Figure PCTCN2022087627-appb-000001
从表1的测试结果可以看出，相比于对比例，本申请提供的镀膜件具有更为优异的膜层附着力、耐磨性能和耐腐蚀性，说明通过基础层中不同膜层的平均晶粒粒径控制，能够 有效提高其与阳极氧化层和外部的功能层之间的结合强度。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (27)

  1. 一种镀膜件，其中，包括基材、阳极氧化层和基础层，所述阳极氧化层形成于所述基材的表面，所述基础层位于所述阳极氧化层的表面，所述基础层包括沿远离所述阳极氧化层的方向依次层叠的第一基础层和第二基础层，所述第一基础层和第二基础层选自金属A的沉积层，所述第一基础层的平均晶粒粒径小于所述第二基础层的平均晶粒粒径，所述阳极氧化层具有微孔结构，所述第一基础层的晶粒部分嵌入所述阳极氧化层的微孔中。
  2. 根据权利要求1所述的镀膜件，其中，所述基材包括铝或铝合金。
  3. 根据权利要求1或2所述的镀膜件，其中，所述金属A包括Cr和/或Ti。
  4. 根据权利要求1-3中任一项所述的镀膜件，其中，所述第一基础层的厚度为30nm-100nm，所述第二基础层的厚度为50nm-120nm。
  5. 根据权利要求1-4中任一项所述的镀膜件，其中，所述第一基础层中晶粒的平均粒径为3nm-30nm，所述第一基础层的纳米硬度为10GPa-16GPa。
  6. 根据权利要求1-5中任一项所述的镀膜件，其中，所述第二基础层中晶粒的平均粒径为50nm-100nm，所述第二基础层的纳米硬度为6GPa-9GPa。
  7. 根据权利要求1-6中任一项所述的镀膜件，其中，所述基础层还包括第三基础层，所述第一基础层、所述第二基础层和所述第三基础层沿远离所述阳极氧化层的方向依次层叠，所述第三基础层选自金属A的沉积层，所述第三基础层的平均晶粒粒径小于所述第二基础层的平均晶粒粒径。
  8. 根据权利要求1-7中任一项所述的镀膜件，其中，所述第三基础层中晶粒的平均粒径为30nm-60nm，所述第三基础层的纳米硬度为8GPa-10GPa。
  9. 根据权利要求1-8中任一项所述的镀膜件，其中，所述第三基础层的厚度为30nm-100nm。
  10. 根据权利要求1-9中任一项所述的镀膜件，其中，所述阳极氧化层的厚度4μm-16μm。
  11. 根据权利要求1-10中任一项所述的镀膜件，其中，所述阳极氧化层的微孔的孔径为10nm-100nm，所述阳极氧化层的微孔数量满足100个/μm 2-3000个/μm 2。
  12. 根据权利要求1-11中任一项所述的镀膜件，其中，所述镀膜件还包括功能层，所述功能层位于所述基础层上背离所述阳极氧化层的一侧，所述功能层包括颜色层，所述颜色层包括金属M的氧化物、金属M的氮化物或金属M的碳化物及其组合，所述金属M选自Cr、Ti和W中的一种或多种。
  13. 根据权利要求1-12中任一项所述的镀膜件，其中，所述颜色层的厚度为0.3μm-3μm。
  14. 根据权利要求1-13中任一项所述的镀膜件，其中，所述功能层还包括过渡层，所述过渡层位于所述颜色层与所述基础层之间，所述过渡层包括金属A和金属M。
  15. 根据权利要求1-14中任一项所述的镀膜件，其中，所述过渡层的厚度为0.3μm-1μm。
  16. 一种制备如权利要求1～15中任一项所述的镀膜件的方法，其中，包括以下操作步骤：
    提供基材，对基材的表面进行阳极氧化处理，以形成阳极氧化层；
    以金属A为靶材，对基材施加负偏压，通过真空镀膜的方式在阳极氧化层的表面溅射形成第一基础层；
    以金属A为靶材，基材不接入偏压，通过真空镀膜的方式在第一基础层的表面溅射形成第二基础层。
  17. 根据权利要求16所述的方法，其中，在所述阳极氧化处理之前，还包括：对基材表面的电接触位点进行点胶处理；在阳极氧化后，对基材表面进行除胶，以露出电接触位点。
  18. 根据权利要求16或17所述的方法，其中，所述阳极氧化处理条件为：阳极氧化槽的槽液选自硫酸溶液、磷酸溶液和草酸溶液中的至少一种，槽液中酸的摩尔浓度为0.3mol/L-0.8mol/L，槽液温度为15℃-25℃。
  19. 根据权利要求16-18中任一项所述的方法，其中，制备所述第一基础层时，控制真空镀膜的条件为：对基材施加负偏压，电压值为200V～400V，靶电流为20A-30A。
  20. 根据权利要求16-19中任一项所述的方法，其中，制备所述第一基础层后，制备所述第二基础层之前，还包括：对第一基础层进行离子轰击，时间为5min-10min。
  21. 根据权利要求16-20中任一项所述的方法，其中，制备所述第二基础层时，控制真空镀膜的条件为：直流模式，无偏压，靶电流为5A-10A。
  22. 根据权利要求16-21中任一项所述的方法，其中，还包括以下操作：
    以金属A为靶材，对基材施加负偏压，通过真空镀膜的方式在所述第二基础层的表面溅射形成第三基础层。
  23. 根据权利要求16-22中任一项所述的方法，其中，制备所述第三基础层时，控制真空镀膜的条件为：对基材施加负偏压，电压值为30V～120V，靶电流为15A-25A。
  24. 根据权利要求16-23中任一项所述的方法，其中，还包括以下操作：
    以金属A和金属M为靶材，通过真空镀膜的方式在基础层的表面溅射形成过渡层，所述金属A包括Cr和/或Ti，所述金属M包括Cr、Ti和W中的一种或多种。
  25. 根据权利要求16-24中任一项所述的方法，其中，还包括以下操作：
    以金属M为靶材，通入氧源、氮源或碳源的一种或多种作为反应性气体，通过真空镀膜的方式在过渡层的表面溅射形成颜色层。
  26. 一种壳体，其中，包括如权利要求1～15中任一项所述的镀膜件。
  27. 一种电子产品，其中，包括权利要求26所述的壳体。
PCT/CN2022/087627 2021-04-30 2022-04-19 镀膜件及其制备方法、壳体及电子产品 WO2022228200A1 (zh)

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