WO2022226985A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022226985A1
WO2022226985A1 PCT/CN2021/091429 CN2021091429W WO2022226985A1 WO 2022226985 A1 WO2022226985 A1 WO 2022226985A1 CN 2021091429 W CN2021091429 W CN 2021091429W WO 2022226985 A1 WO2022226985 A1 WO 2022226985A1
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WIPO (PCT)
Prior art keywords
conductive
layer
display substrate
signal line
base substrate
Prior art date
Application number
PCT/CN2021/091429
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English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
徐攀
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/754,369 priority Critical patent/US20240057407A1/en
Priority to EP21938459.1A priority patent/EP4220727A4/en
Priority to PCT/CN2021/091429 priority patent/WO2022226985A1/zh
Priority to CN202180001006.9A priority patent/CN116058106A/zh
Publication of WO2022226985A1 publication Critical patent/WO2022226985A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • the uniformity of light emission is one of the important indicators to measure the quality of the display panel.
  • the existing display panel there is a phenomenon that the display panel emits light unevenly, that is, the light emission uniformity is poor.
  • uncontrollable factors such as process instability, parameter drift, and device aging of TFT and OLED light-emitting devices lead to changes in OLED current, which in turn lead to uneven light emission of the display panel.
  • a display substrate comprising:
  • each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element;
  • the pixel driving circuit includes at least a driving transistor, a switching transistor and a sensing transistor;
  • the switching transistor includes a first gate and a first active layer, the first active layer is located in the semiconductor layer, and the first gate is located in the first conductive layer;
  • the driving transistor includes a second gate and a second active layer, the second active layer is located in the semiconductor layer, and the second gate is located in the second conductive layer;
  • the sensing transistor includes a third gate and a third active layer, the third active layer is located in the semiconductor layer, and the third gate is located in the second conductive layer;
  • the display substrate further includes a channel defining portion for defining a channel region of the switching transistor, the channel defining portion is located in the second conductive layer, and the channel defining portion is located in the second conductive layer.
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the first active layer on the base substrate.
  • the orthographic projection of the channel defining portion on the base substrate falls within the orthographic projection of the first gate on the base substrate.
  • the first active layer extends in a first direction
  • the second active layer and the third active layer extend in a second direction, the first direction and the The second direction intersects.
  • the display substrate further includes a first power supply signal line for transmitting a first power supply signal, and it is characterized in that the display substrate further includes a third conductive layer, and the third conductive layer On the side of the first conductive layer close to the base substrate, the first power signal line is located in the third conductive layer.
  • the display substrate further includes a sensing signal line for transmitting a sensing signal
  • the sensing transistor includes a source electrode and a drain electrode, the sensing signal line and the sensing transistor The source or drain is electrically connected, and the sensing signal line is located in the third conductive layer.
  • the pixel driving circuit further includes a storage capacitor, and the storage capacitor includes a first capacitor;
  • the display substrate includes a first conductive portion located in the first conductive layer and a first conductive portion located in the first conductive layer.
  • the orthographic projections of at least a portion of the first conductive portion and at least a portion of the second conductive portion on the base substrate overlap with each other, and the first conductive portion and the The overlapping portion of the second conductive portion forms the first capacitor.
  • the storage capacitor further includes a second capacitor, the second capacitor is connected in parallel with the first capacitor;
  • the display substrate further includes a fourth conductive layer, and the fourth conductive layer is located on the the second conductive layer is away from the side of the base substrate;
  • the display substrate further includes a third conductive part and a fourth conductive part, the third conductive part is located in the fourth conductive layer, and the fourth conductive part is located in the fourth conductive layer.
  • the conductive portion is located in the semiconductor layer, and the fourth conductive portion includes a conductorized portion of the semiconductor layer; at least a portion of the third conductive portion and at least a portion of the fourth conductive portion are located in the lining
  • the orthographic projections on the base substrate overlap with each other, and the overlapping portion of the third conductive portion and the fourth conductive portion forms the second capacitor.
  • the fourth conductive part is electrically connected to the first conductive part through a first via hole
  • the third conductive part is electrically connected to the second conductive part through a second via hole.
  • the display substrate further includes a first scan signal line in the first conductive layer, the first scan signal line and the first conductive portion are spaced apart; and the first scan signal line A portion of a scan signal line overlapping the semiconductor layer forms the first gate electrode.
  • both the first scanning signal line and the sensing signal line extend along a first direction; and/or, the first power signal line and the first conductive portion both extend along a first direction Extend in two directions.
  • the display substrate further includes a fifth conductive part in the semiconductor layer; the second active layer, the third active layer, the fourth conductive part and the The fifth conductive part is an integral part located in the semiconductor layer and extending continuously; and the first active layer is spaced from the integral part.
  • a portion of the third active layer is electrically connected to the sensing signal line through a third via hole, and a portion of the fifth conductive portion is electrically connected to the first via a fourth via hole
  • the power signal lines are electrically connected.
  • the display substrate further includes a second scan signal line in the second conductive layer, the second scan signal line being parallel to the first scan signal line; the second scan signal line
  • the scanning signal line, the second conductive part and the channel defining part are arranged at intervals from each other; and a portion of the second conductive part overlapping with the second active layer forms the second gate, and the second gate is formed.
  • the portion of the two scan signal lines overlapping the third active layer forms the third gate.
  • the display substrate further includes a data line in the fourth conductive layer; the data line is spaced apart from the third conductive part; a part of the third conductive part passes through the fourth conductive layer.
  • the five via holes are electrically connected to one end of the first active layer, and a part of the data line is electrically connected to the other end of the first active layer through the sixth via hole.
  • the orthographic projection of the second conductive portion on the base substrate falls within the orthographic projection of the first conductive portion on the base substrate; and/or the A portion of the third conductive portion straddles the fifth conductive portion.
  • the fifth conductive portion extends in a first direction
  • a portion of the third conductive portion across the fifth conductive portion extends in a second direction
  • the second via hole and the The fifth via holes are located on opposite sides of the fifth conductive portion.
  • the light emitting element includes a first electrode, and the first electrode is directly electrically connected to the fourth conductive part through a seventh via hole.
  • the orthographic projection of the seventh via on the base substrate at least partially overlaps the orthographic projection of the second via on the base substrate.
  • the channel defining portion is in a suspended state.
  • a display device comprising the display substrate as described above.
  • FIG. 1A is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1B is a partial plan view of a display substrate according to an embodiment of the present disclosure, which schematically illustrates a more specific structure of the display substrate;
  • FIG. 2A is an equivalent circuit diagram of a pixel driving circuit of a plurality of sub-pixels of the display substrate in FIG. 1B;
  • FIG. 2B is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG. 1B;
  • FIG. 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, which schematically illustrates a plan view of a pixel driving circuit and a first electrode of a light emitting element included in the display substrate;
  • FIG. 4 to 13 are plan views of the plurality of film layers shown in FIG. 3, respectively.
  • Fig. 14 is a cross-sectional view taken along line AA' in Fig. 3 .
  • first direction the directional expressions "first direction”, "second direction” are used to describe different directions along the pixel area, eg, the longitudinal direction and the transverse direction of the pixel area. It should be understood that such representations are exemplary descriptions only, and not limitations of the present disclosure.
  • the expression “on the same layer” generally means that the first part and the second part may use the same material and may be formed by the same patterning process.
  • the expression “A and B are joined in one piece” means that part A and part B are integrally formed, ie they generally comprise the same material and are formed as one structurally continuous unitary part.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source electrode and the drain electrode of the thin film transistor used here are symmetrical, the source electrode and the drain electrode can be interchanged. In the following examples, the description is mainly given of the case of a P-type thin film transistor used as a driving transistor, and other transistors are of the same or different type as the driving transistor according to circuit design. Similarly, in other embodiments, the drive transistors may also be shown as N-type thin film transistors.
  • a display substrate comprising: the display substrate comprising: a base substrate; a plurality of pixel units disposed on the base substrate, each pixel unit comprising a plurality of sub-bases a pixel, each sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element; a semiconductor layer disposed on the base substrate; a first pixel disposed on the side of the semiconductor layer close to the base substrate a conductive layer; and a second conductive layer disposed on the side of the semiconductor layer away from the base substrate, wherein the pixel driving circuit at least includes a driving transistor, a switching transistor and a sensing transistor; the switching transistor includes a first a gate electrode and a first active layer, the first active layer is located in the semiconductor layer, the first gate electrode is located in the first conductive layer; the driving transistor includes a second gate electrode and a second active layer layer, the second active layer is located in the semiconductor layer, the second gate is
  • a display substrate according to an embodiment of the present disclosure may include a base substrate 100 , a pixel unit PX disposed on the base substrate 100 , a driving unit DRU disposed on the base substrate 100 , and a pixel unit PX disposed on the base substrate 100 .
  • the unit PX is electrically connected to the wiring PL of the driving unit DRU, and the driving unit DRU is used for driving the pixel unit PX.
  • the display substrate may include a display area AA and a non-display area NA.
  • the display area AA may be an area in which pixel units PX displaying images are provided. Each pixel unit PX will be described later.
  • the non-display area NA is an area where no pixel unit PX is provided, that is, an area where no image is displayed.
  • the driving unit DRU for driving the pixel unit PX and some wiring lines PL connecting the pixel unit PX and the driving unit DRU may be disposed in the non-display area NA.
  • the non-display area NA corresponds to the frame in the final display device, and the width of the frame can be determined according to the width of the non-display area NA.
  • the display area AA may have various shapes.
  • the display area AA may have various shapes such as a closed-shaped polygon including straight sides (eg, a rectangle), a circle including curved sides, an ellipse, and the like, and a semicircle, semi-ellipse, and the like including straight and curved sides. shape set.
  • the display area AA is set as an area having a quadrangular shape including straight sides, and it should be understood that this is only an exemplary embodiment of the present disclosure, and not a limitation of the present disclosure.
  • the non-display area NA may be disposed at at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the outer circumference of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a lateral portion extending in the first direction X and a longitudinal portion extending in the second direction Y.
  • the pixel unit PX is arranged in the display area AA.
  • the pixel unit PX is the smallest unit for displaying an image, and can be provided in plural.
  • the pixel unit PX may include a light emitting device that emits white light and/or color light.
  • the pixel units PX may be provided in plural, arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y.
  • the embodiment of the present disclosure does not specifically limit the arrangement form of the pixel cells PX, and the pixel cells PX may be arranged in various forms.
  • the pixel cells PX may be arranged such that a direction inclined with respect to the first direction X and the first direction Y becomes a column direction, and a direction crossing the column direction becomes a row direction.
  • One pixel unit PX may include a plurality of sub-pixels.
  • one pixel unit PX may include 3 sub-pixels, ie, a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3.
  • one pixel unit PX may include 4 sub-pixels, that is, a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3 and a fourth sub-pixel.
  • the first subpixel SP1 may be a red subpixel
  • the second subpixel SP2 may be a green subpixel
  • the third subpixel SP3 may be a blue subpixel
  • the fourth subpixel may be a white subpixel.
  • Each subpixel may include a light emitting element and a pixel driving circuit for driving the light emitting element.
  • the first sub-pixel SP1 may include a first light-emitting element located in the first light-emitting area SPA1, and a first pixel driving circuit SPC1 for driving the first light-emitting element, the first light-emitting element may emit red light;
  • the second The sub-pixel SP2 may include a second light-emitting element located in the second light-emitting area SPA2 and a second pixel driving circuit SPC2 for driving the second light-emitting element, and the second light-emitting element may emit green light;
  • the third sub-pixel SP3 may include a second light-emitting element located in the second light-emitting area SPA2.
  • the third light emitting element in the third light emitting area SPA3 and the third pixel driving circuit SPC3 for driving the third light emitting element can emit blue light.
  • the light-emitting region of the sub-pixel may be the region where the light-emitting element of the sub-pixel is located.
  • a light-emitting element of a sub-pixel may include a first electrode (eg, an anode), a layer of a light-emitting material, and a second electrode (eg, a cathode) arranged in layers.
  • the light-emitting region of the sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and the cathode.
  • the sub-pixel also includes a non-light-emitting area, for example, a pixel driving circuit of the sub-pixel is located in the non-light-emitting area of the sub-pixel.
  • a pixel driving circuit of the sub-pixel is located in the non-light-emitting area of the sub-pixel.
  • the OLED light-emitting device may not have good consistency during fabrication.
  • the EL layer is fabricated by an evaporation process, each sub-pixel produced due to the limitations of the evaporation process
  • the EL layers are inconsistent, resulting in non-uniform luminous brightness or chromaticity between different sub-pixels.
  • the EL layer will age to different degrees, and the EL layer of each sub-pixel will also be inconsistent, resulting in non-uniform luminous brightness or chromaticity between different sub-pixels.
  • the display substrate may further include a photosensitive circuit OSC, and the photosensitive circuit OSC can sense the light actually emitted by the pixel unit.
  • the display substrate can perform optical compensation on the sub-pixels in each pixel unit based on the light actually emitted by the pixel unit sensed by the photosensitive circuit OSC, so as to improve the uniformity of light emission of the display substrate .
  • each pixel unit PX is provided with one photometric circuit OSC.
  • Each photometric circuit OSC senses the light actually emitted by the pixel unit PX in which it is located.
  • At least two pixel units PX may share one photosensitive circuit OSC.
  • two pixel units PX located in two adjacent rows may share one photosensitive circuit OSC. In this way, it is not necessary to provide a photosensitive circuit for each pixel unit PX, the number of photosensitive circuits can be reduced, and the aperture ratio can be increased.
  • the photosensitive circuit OSC can sense the light actually emitted by the two adjacent pixel units.
  • the photosensitive circuit OSC may include at least a photoelectric conversion element (which will be described further below). In this way, the photosensitive circuit OSC can be configured to: sense the light actually emitted by the two pixel units adjacent to it; and send a sensed electrical signal according to the sensed light.
  • the photosensitive circuit OSC may send the sensing electrical signal to an external circuit, such as a control IC of a display device.
  • the control IC can control the control signal sent to the pixel unit PX according to the sensing electrical signal, for example, can control the data signal (ie, the data signal) sent to the pixel driving circuit of each sub-pixel. Under the control of the data signal, each sub-pixel emits light accordingly.
  • the sub-pixels SP1 , SP2 and SP3 are arranged side by side, and each of the sub-pixels SP1 , SP2 and SP3 has its own data line DL.
  • FIG. 2A is an equivalent circuit diagram of a pixel driving circuit of a plurality of sub-pixels of the display substrate in FIG. 1B
  • FIG. 2B is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG. 1B
  • the pixel driving circuit shown in FIG. 2B may be any one of the pixel driving circuits SPC1 , SPC2 , and SPC3 described above.
  • the pixel driving circuit may include multiple elements such as a switching transistor T1 , a driving transistor T2 , a sensing transistor T3 , and a storage capacitor Cst1 .
  • the pixel driving circuit can be called a 3T1C structure.
  • the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here by taking the 3T1C structure as an example, but the pixel driving circuit included in the display substrate in the embodiment of the present disclosure is not limited to the 3T1C structure.
  • the gate of the switching transistor T1 is connected to the first scan signal line GL1, the first electrode of the switching transistor T1 is connected to the data line DL, and the second electrode of the switching transistor T1 is connected to the gate of the driving transistor T2, for example , the second electrode of the switching transistor T1 and the gate of the driving transistor T2 may both be electrically connected to the node GN.
  • the switching transistor T1 is used to control the writing of the voltage signal from the data line DL to the pixel driving circuit.
  • each transistor may include an active layer, a gate electrode, a first electrode (eg, a source electrode) and a second electrode (eg, a drain electrode).
  • the switching transistor T1 includes a first gate G1 and a first active layer ACT1;
  • the driving transistor T2 includes a second gate G2 and a second active layer ACT2;
  • the sensing transistor T3 includes a third gate The pole G3 and the third active layer ACT3.
  • the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in a different conductive layer.
  • the first electrode of the transistor may refer to one of the source electrode and the drain electrode of the transistor
  • the second electrode of the transistor may refer to the other one of the source electrode and the drain electrode of the transistor
  • the gate of the driving transistor T2 is electrically connected to the node GN, the first electrode of the driving transistor T2 is connected to a first power supply signal (eg, a high voltage level signal VDD), and the second electrode of the driving transistor T2 may be connected to the anode of the light-emitting element D1 , so that the driving current can be generated according to the voltage signal to drive the light-emitting element D1 to emit light.
  • the light emitting element D1 may be an organic light emitting diode (OLED).
  • Two ends of the storage capacitor Cst1 are respectively connected to the gate and source of the driving transistor T2 for storing the voltage signal input from the data line.
  • one end of the storage capacitor Cst1 is electrically connected to the node GN
  • the other end of the storage capacitor Cst1 is electrically connected to the node SN. That is, one end of the storage capacitor Cst1, the second electrode of the switching transistor T1 and the gate of the driving transistor T2 are all electrically connected to the node GN, and the other end of the storage capacitor Cst1, the second electrode of the driving transistor T2 and the anode of the light-emitting element D1 are all electrically connected to the node GN. Electrically connected to node SN.
  • the gate of the sensing transistor T3 is connected to the second scan signal line GL2, the first electrode of the sensing transistor T3 is connected to the sensing signal line SL, and the second electrode of the sensing transistor T3 is electrically connected to the node SN.
  • the anode of the light-emitting element D1 is electrically connected to the node SN, and the cathode of the light-emitting element D1 is electrically connected to the low voltage level signal VSS.
  • the level signals VDD and VSS are both DC voltage signals, which are used to provide necessary voltages for driving the light-emitting element D1 to emit light.
  • FIG. 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, which schematically illustrates a plan view of a pixel driving circuit and a first electrode of a light emitting element included in the display substrate.
  • 4 to 13 are plan views of the plurality of film layers shown in FIG. 3, respectively.
  • the display substrate may include a plurality of conductive layers, a semiconductor layer and a plurality of insulating layers.
  • the plurality of conductive layers are described as a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, respectively.
  • FIG. 4 shows a portion of the third conductive layer 30 .
  • FIG. 5 shows a part of the first conductive layer 10 and a part of the third conductive layer 30.
  • the first conductive layer 10 may be the gates of some transistors of the first scan signal line GL1 and the film layer where the first conductive parts are located, for example , which can be a conductive layer composed of gate material.
  • FIG. 6 schematically illustrates a plurality of via holes exposing a portion of the third conductive layer 30 and the first conductive layer 10 .
  • FIG. 7 also shows a semiconductor layer ACT, in which the active layers of the respective transistors may be located. It should be noted that a part of the semiconductor layer ACT may have semiconductor properties to form the channel regions of the respective transistors, and other parts of the semiconductor layer ACT may be conductive to have conductor properties to form the source regions, Drain region and other conductive parts.
  • FIG. 4-FIG. 7, FIG. 8 also shows a part of the second conductive layer 20, the gates of some transistors, the second scan signal line GL2, etc.
  • FIG. 9 schematically illustrates a plurality of vias exposing a portion of the second conductive layer 20 .
  • FIG. 10 also shows a part of the fourth conductive layer 40, the fourth conductive layer 40 may be the film layer where the data line DL, the conductive part, etc. are located, that is, it may be formed by the source The conductive layer composed of the drain material.
  • FIG. 11 schematically illustrates a plurality of vias exposing a portion of the fourth conductive layer 40 .
  • FIG. 12 schematically shows a via hole exposing a part of the semiconductor layer ACT to electrically connect the first electrode of the light emitting element.
  • FIG. 13 also shows a part of the layer where the first electrode of the light-emitting element is located, for example, it may be a conductive layer composed of a transparent conductive material such as ITO.
  • the third conductive layer 30, the first conductive layer 10, the semiconductor layer ACT, the second conductive layer 20, the fourth conductive layer 40 and the first electrode may be sequentially stacked on the base substrate of the display substrate.
  • the third conductive layer 30 may be disposed on the base substrate, the first conductive layer 10 is disposed on the side of the third conductive layer 30 away from the base substrate, and the semiconductor layer ACT is disposed on the first conductive layer 10 away from all
  • the second conductive layer 20 is disposed on the side of the semiconductor layer ACT away from the base substrate, and the fourth conductive layer 40 is disposed on the side of the second conductive layer 20 away from the base substrate,
  • the first electrode is disposed on the side of the fourth conductive layer 40 away from the base substrate.
  • the display substrate may further include two adjacent ones of the base substrate 100 , the third conductive layer 30 , the first conductive layer 10 , the semiconductor layer ACT, the second conductive layer 20 and the fourth conductive layer 40 .
  • a plurality of insulating layers in between, hereinafter, these insulating layers will be described with reference to cross-sectional views.
  • via holes or recesses exposing at least a part of one of the third conductive layer 30 , the first conductive layer 10 , the semiconductor layer ACT, the second conductive layer 20 , and the fourth conductive layer 40 may be formed Slots to allow electrical connection of components located between different film layers.
  • the display substrate may include a plurality of signal lines.
  • the plurality of signal lines may include a first scan signal line GL1, a second scan signal line GL2, a data line DL, and a first power supply signal line.
  • VDD and the sense signal line SL may be located in the third conductive layer 30
  • the first scan signal line GL1 may be located in the first conductive layer 10
  • the second scan signal line GL2 may be located in the second conductive layer 10.
  • the data line DL may be located in the fourth conductive layer 40 .
  • the first scan signal line GL1, the second scan signal line GL2, and a part of the sensing signal line SL may extend substantially along the first direction X, the data line DL, the first power signal line VDD .
  • Another portion of the sensing signal line SL may extend substantially along the second direction Y.
  • the second scan signal line GL2 may be located between the first scan signal line GL1 and a portion of the sensing signal line SL.
  • the first power supply signal line VDD and the sensing signal line SL are both located in the third conductive layer 30 .
  • the first power supply signal line VDD and the sensing signal line SL are arranged spaced apart from each other.
  • the sensing signal line SL may be located between two adjacent first power supply signal lines VDD.
  • the first power supply signal line VDD extends along the second direction Y.
  • the sensing signal line SL may include a first portion and a second portion, the first portion of the sensing signal line SL extends substantially along the first direction X, and the second portion of the sensing signal line SL extends substantially along the second direction Y.
  • the display substrate may include a first conductive part 101 , and the first scan signal line GL1 and the first conductive part 101 are located in the first conductive layer 10 .
  • the first scan signal line GL1 and the first conductive portion 101 are spaced apart from each other.
  • the first scan signal line GL1 may extend substantially along the first direction X
  • the first conductive portion 101 may extend substantially along the second direction Y.
  • at least three first conductive parts 101 may be provided, and the three first conductive parts 101 are spaced apart from each other.
  • a portion of the first scan signal line GL1 may form a first gate of the switching transistor T1, and a portion of the first conductive portion 101 may form a plate of the storage capacitor Cst1.
  • the display substrate may include a plurality of via holes exposing a portion of the third conductive layer 30 and the first conductive layer 10 .
  • the plurality of via holes include a via hole VH1 exposing the first power supply signal line VDD, a via hole VH2 exposing the sensing signal line SL, and a via hole VH3 exposing the first conductive portion 101 to facilitate subsequent formation of conductive parts They are electrically connected to the exposed portions of these via holes, respectively.
  • the display substrate further includes a first active layer ACT1 , a second active layer ACT2 , a third active layer ACT3 , a fourth conductive part ACT4 and a first active layer ACT1 in the semiconductor layer ACT Five conductive parts ACT5.
  • the second active layer ACT2, the third active layer ACT3, the fourth conductive part ACT4 and the fifth conductive part ACT5 may be integral parts located in the semiconductor layer ACT and extending continuously.
  • the first active layer ACT1 is spaced apart from the integral part.
  • the first active layer ACT1 extends along the first direction X, and the orthographic projection of the first active layer ACT1 on the base substrate may fall within the orthographic projection of the first scan signal line GL1 on the base substrate.
  • the plurality of first active layers ACT1 may be disposed along the first direction X at intervals.
  • the fifth conductive portion ACT5 may extend substantially along the first direction X.
  • a part of the fifth conductive part ACT5 can be electrically connected to the first power supply signal line VDD on one side through a via hole VH1, and another part of the fifth conductive part ACT5 can be connected to the first power supply signal line VDD on the other side through another via hole VH1.
  • the power signal line VDD is electrically connected.
  • the fifth conductive portion ACT5 may be located on a side of the second active layer ACT2 away from the fourth conductive portion ACT4.
  • a part of the fourth conductive part ACT4 may be electrically connected to the first conductive part 101 through the via hole VH3.
  • the orthographic projection of the fourth conductive portion ACT4 on the base substrate may at least partially overlap with the orthographic projection of the first conductive portion 101 on the base substrate, for example, the orthographic projection of the fourth conductive portion ACT4 on the base substrate may fall within The first conductive portion 101 is in the orthographic projection on the base substrate.
  • the fourth conductive part ACT4 may be located between the second active layer ACT2 and the third active layer ACT3.
  • a portion of the third active layer ACT3 may be electrically connected to the sensing signal line SL through the via hole VH2.
  • a portion of the first scan signal line GL1 overlapping with the first active layer ACT1 may form the first gate G1 of the switching transistor T1.
  • the display substrate includes a second scan signal line GL2 in the second conductive layer 20 , a second conductive part 202 and a channel defining part 200 .
  • the second scan signal line GL2, the second conductive portion 202 and the channel defining portion 200 are spaced apart from each other.
  • the second scan signal lines GL2 are parallel to the first scan signal lines GL1, that is, they both extend in the first direction X.
  • the overlapping portion of the second conductive portion 202 and the second active layer ACT2 forms the second gate G2 of the driving transistor T2.
  • the overlapping portion of the second scan signal line GL2 and the third active layer ACT3 forms the third gate G3 of the sensing transistor.
  • the channel defining portion 200 is used to define the channel region of the switching transistor T1 , and the channel defining portion 200 is located in the second conductive layer 20 . 8 , the orthographic projection of the channel defining portion 200 on the base substrate at least partially overlaps with the orthographic projection of the first active layer ACT1 on the base substrate. The orthographic projection of the channel defining portion 200 on the base substrate falls within the orthographic projection of the first gate G1 or the first scanning signal line GL1 on the base substrate.
  • the expression "the channel defining part 200 is used to define the channel region of the switching transistor T1" means: the orthographic projection of the channel defining part 200 on the base substrate is the same as the switching transistor The orthographic projections of the channel region of T1 on the base substrate are substantially coincident.
  • the display substrate may include via holes VH4 exposing the second conductive part 202 , via holes VH5 , VH6 exposing the source and drain regions of the first active layer ACT1 , respectively, so as to facilitate The conductive parts formed subsequently are electrically connected to the exposed portions of the via holes, respectively.
  • the display substrate includes a data line DL and a third conductive portion 401 located in the fourth conductive layer 40 .
  • the data line DL is spaced apart from the third conductive portion 403 .
  • the data lines DL may extend along the second direction Y, and between the adjacent first power supply signal lines VDD and the sensing signal lines SL, at least three data lines DL may be provided.
  • a part of the third conductive part 403 is electrically connected to one end of the first active layer ACT1 through a via hole VH5, and a part of the data line DL is electrically connected to the first active layer ACT1 through a via hole VH6 The other end is electrically connected.
  • a part of the third conductive portion 403 is electrically connected to the second conductive portion 202 through the via hole VH4.
  • the orthographic projection of the third conductive portion 403 on the base substrate at least partially overlaps the orthographic projection of the first conductive portion 101 on the base substrate.
  • a portion of the third conductive portion 403 crosses the fifth conductive portion ACT5.
  • the fifth conductive portion ACT5 extends in the first direction X
  • the portion of the third conductive portion 403 that crosses the fifth conductive portion ACT5 extends in the second direction Y
  • the via hole VH4 and the via hole VH5 is located on opposite sides of the fifth conductive portion ACT5.
  • the via hole VH4 and the via hole VH5 may be substantially aligned in the second direction Y.
  • the display substrate may include via holes VH7 , for example, the via holes VH7 may penetrate the passivation layer and the planarization layer to expose a part of the fourth conductive portion ACT4 , so as to facilitate the subsequent formation of the first light emitting element.
  • An electrode is electrically connected to the fourth conductive portion.
  • a first electrode 300 of a light-emitting element such as an anode
  • the first electrode 300 may be electrically connected to the fourth conductive portion ACT4 through the via hole VH7.
  • the pixel opening 400 is schematically shown.
  • the pixel opening 400 may be defined by a pixel defining layer on the side of the first electrode 300 away from the base substrate.
  • the display substrate may include a base substrate 100 , a third conductive layer 30 disposed on the base substrate 100 , and a buffer layer disposed on the side of the third conductive layer 30 away from the base substrate 100 12.
  • the first conductive layer 10 disposed on the side of the buffer layer 12 away from the base substrate 100, and the first gate insulating layer 22 disposed on the side of the first conductive layer 10 away from the base substrate 100, disposed on the first gate insulating layer 22.
  • the second electrode 600 is provided on the side of the light-emitting material layer EL away from the base substrate 100 .
  • each of the above-mentioned insulating layers may include a single-layer structure or a stacked-layer structure composed of multiple insulating layers.
  • the first insulating layer 42 may include two passivation layers
  • the second insulating layer 52 may include one passivation layer and one planarization layer.
  • the switch transistor T1 included in the display substrate has a bottom gate structure, that is, the first gate G1 of the switch transistor T1 is located in the first active layer ACT1 close to the substrate One side of the base substrate 100; both the driving transistor T2 and the sensing transistor T3 have a top gate structure, that is, the second gate G2 of the driving transistor T2 is located on the side of the second active layer ACT2 away from the base substrate 100, and the sensing The third gate G3 of the transistor T3 is located on the side of the third active layer ACT3 away from the base substrate 100 .
  • a channel defining portion 200 is further provided for the switching transistor T1 having a bottom gate structure.
  • the channel defining part 200 is located on the same layer as the gates G2 and G3 of the driving transistor T2 and the sensing transistor T3 having a top gate structure. In this way, when the semiconductor layer is subjected to the conducting process, the channel defining portion 200 can be used as a mask to conduct the conducting process, so that the portion of the first active layer ACT1 not covered by the channel defining portion 200 is conductive, and the first active layer ACT1 is conductive. A portion of the source layer ACT1 covered by the channel defining portion 200 forms a channel region of the switching transistor T1. That is, through the self-alignment of the channel defining portion 200, the channel region of the switching transistor T1 can be formed.
  • the switching transistor T1 with the bottom gate structure, the driving transistor T2 and the sensing transistor T3 with the top gate structure can form the channel region through the same conductorization process, which is beneficial to save process steps; and, in this way, It can be ensured that the formed switching transistor T1 has better characteristics.
  • the driving transistor and the sensing transistor adopt the top gate structure, which can save the distance arrangement in the second direction Y, which is beneficial to increase the width of the first scanning signal line, thereby reducing the first scanning load on the signal line, which in turn can match the higher refresh rate.
  • the channel defining portion 200 is in a suspended state. That is, the channel defining portion 200 may not receive electrical signals.
  • the storage capacitor includes a first capacitor C1 and a second capacitor C2, and the first capacitor and the second capacitor may be connected in parallel to increase the capacitance value of the storage capacitor.
  • the display substrate includes a first conductive part 101 in the first conductive layer and a second conductive part 202 in the second conductive layer, the first conductive part 101
  • the orthographic projections of at least a part of the second conductive part 202 and at least a part of the second conductive part 202 on the base substrate overlap each other, and the overlapping part of the first conductive part 101 and the second conductive part 202 forms the first conductive part 101 Capacitor C1.
  • the display substrate further includes a third conductive part 403 and a fourth conductive part ACT4, the third conductive part 403 is located in the fourth conductive layer 40, the fourth conductive part ACT4 is located in the semiconductor layer ACT,
  • the fourth conductive portion ACT4 includes a conductive portion of the semiconductor layer ACT. Orthographic projections of at least a part of the third conductive part 403 and at least a part of the fourth conductive part ACT4 on the base substrate overlap with each other, and the third conductive part 403 and the fourth conductive part ACT4 overlap each other part forms the second capacitor C2.
  • the fourth conductive portion ACT4 is electrically connected to the first conductive portion through a via hole VH3
  • the third conductive portion 403 is electrically connected to the second conductive portion 202 via a via hole VH4 .
  • a part of the third active layer ACT3 is electrically connected to the sensing signal line SL through a via hole VH2, and a part of the fifth conductive part ACT5 is electrically connected to the first power supply signal line VDD through a via hole VH1 connect.
  • the first electrode 300 is directly electrically connected to the fourth conductive portion ACT4 through a via hole VH7.
  • the orthographic projection of the via hole VH7 on the base substrate at least partially overlaps the orthographic projection of the via hole VH3 on the base substrate.
  • the first electrode 300 is formed of a material with strong climbing ability, such as ITO, the first electrode 300 can be directly electrically connected to the conductive parts located in the semiconductor layer through the via hole VH7, which can save wiring space, saving a higher space for the storage capacitor, thereby helping to increase the capacitance value of the storage capacitor.
  • an embodiment of the present disclosure further provides a display device, and the display device may include the above-mentioned display substrate.
  • the display device may include but is not limited to: electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, and any other product or component with display function. It should be understood that the display device has the same beneficial effects as the display substrate provided by the foregoing embodiments.

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Abstract

提供一种显示基板和显示装置。所述显示基板包括：设置于衬底基板的多个像素单元，每一个像素单元包括多个子像素，每一个子像素包括发光元件和用于驱动发光元件的像素驱动电路；设置于衬底基板的半导体层；设置于半导体层靠近衬底基板一侧的第一导电层；和设置在半导体层远离衬底基板一侧的第二导电层。像素驱动电路至少包括驱动晶体管、开关晶体管和感测晶体管；开关晶体管包括第一栅极和第一有源层，第一有源层位于半导体层，第一栅极位于第一导电层；显示基板还包括沟道限定部，沟道限定部用于限定开关晶体管的沟道区，沟道限定部位于所述第二导电层，沟道限定部在衬底基板上的正投影与第一有源层在衬底基板上的正投影至少部分重叠。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示基板和显示装置。
背景技术
发光均一性是衡量显示面板质量的重要指标之一。在现有的显示面板中，存在显示面板发光不均匀的现象，即，发光均一性较差。例如，在OLED显示面板中，因TFT和OLED发光器件等工艺不稳定、参数漂移和器件老化等不可控因素存在，导致OLED电流发生变化，进而导致显示面板发光不均匀。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域技术人员已知的现有技术的信息。
发明内容
在一个方面，提供一种显示基板，所述显示基板包括：
衬底基板；
设置于所述衬底基板的多个像素单元，每一个像素单元包括多个子像素，每一个子像素包括发光元件和用于驱动所述发光元件的像素驱动电路；
设置于所述衬底基板的半导体层；
设置于所述半导体层靠近所述衬底基板一侧的第一导电层；和
设置在所述半导体层远离所述衬底基板一侧的第二导电层，
其中，所述像素驱动电路至少包括驱动晶体管、开关晶体管和感测晶体管；
所述开关晶体管包括第一栅极和第一有源层，所述第一有源层位于所述半导体层，所述第一栅极位于所述第一导电层；
所述驱动晶体管包括第二栅极和第二有源层，所述第二有源层位于所述半导体层，所述第二栅极位于所述第二导电层；
所述感测晶体管包括第三栅极和第三有源层，所述第三有源层位于所述半导体层，所述第三栅极位于所述第二导电层；
所述显示基板还包括沟道限定部，所述沟道限定部用于限定所述开关晶体管的沟道区，所述沟道限定部位于所述第二导电层，所述沟道限定部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影至少部分重叠。
根据一些示例性的实施例，所述沟道限定部在所述衬底基板上的正投影落入所述第一栅极在所述衬底基板上的正投影内。
根据一些示例性的实施例，所述第一有源层沿第一方向延伸，所述第二有源层和所述第三有源层沿第二方向延伸，所述第一方向和所述第二方向相交。
根据一些示例性的实施例，所述的显示基板还包括用于传输第一电源信号的第一电源信号线，其特征在于，所述显示基板还包括第三导电层，所述第三导电层位于所述第一导电层靠近所述衬底基板的一侧，所述第一电源信号线位于所述第三导电层中。
根据一些示例性的实施例，所述显示基板还包括用于传输感测信号的感测信号线，所述感测晶体管包括源极和漏极，所述感测信号线与所述感测晶体管的源极或漏极电连接，所述感测信号线位于所述第三导电层中。
根据一些示例性的实施例，所述像素驱动电路还包括存储电容，所述存储电容包括第一电容；所述显示基板包括位于所述第一导电层中的第一导电部和位于所述第二导电层中的第二导电部，所述第一导电部的至少一部分与所述第二导电部的至少一部分在所述衬底基板上的正投影彼此重叠，所述第一导电部和所述第二导电部重叠的部分形成所述第一电容。
根据一些示例性的实施例，所述存储电容还包括第二电容，所述第二电容与所述第一电容并联；所述显示基板还包括第四导电层，所述第四导电层位于所述第二导电层远离所述衬底基板的一侧；所述显示基板还包括第三导电部和第四导电部，所述第三导电部位于所述第四导电层中，所述第四导电部位于所述半导体层中，所述第四导电部包括所述半导体层中被导体化的部分；所述第三导电部的至少一部分与所述第四导电部的至少一部分在所述衬底基板上的正投影彼此重叠，所述第三导电部和所述第四导电部重叠的部分形成所述第二电容。
根据一些示例性的实施例，所述第四导电部通过第一过孔与所述第一导电部电连接，所述第三导电部通过第二过孔与所述第二导电部电连接。
根据一些示例性的实施例，所述显示基板还包括位于所述第一导电层中的第一扫描信号线，所述第一扫描信号线和所述第一导电部间隔设置；以及所述第一扫描信号线与所述半导体层重叠的部分形成所述第一栅极。
根据一些示例性的实施例，所述第一扫描信号线和所述感测信号线均沿第一方向延伸；和/或，所述第一电源信号线和所述第一导电部均沿第二方向延伸。
根据一些示例性的实施例，所述显示基板还包括位于所述半导体层中的第五导电部；所述第二有源层、所述第三有源层、所述第四导电部和所述第五导电部为位于所述半导体层中连续延伸的一体部分；以及所述第一有源层与所述一体部分间隔设置。
根据一些示例性的实施例，所述第三有源层的一部分通过第三过孔与所述感测信号线电连接，所述第五导电部的一部分通过第四过孔与所述第一电源信号线电连接。
根据一些示例性的实施例，所述显示基板还包括位于所述第二导电层中的第二扫描信号线，所述第二扫描信号线平行于所述第一扫描信号线；所述第二扫描信号线、所述第二导电部和所述沟道限定部彼此间隔设置；以及所述第二导电部与所述第二有源层重叠的部分形成所述第二栅极，所述第二扫描信号线与所述第三有源层重叠的部分形成所述第三栅极。
根据一些示例性的实施例，所述显示基板还包括位于所述第四导电层中的数据线；所述数据线与所述第三导电部间隔设置；所述第三导电部的一部分通过第五过孔与所述第一有源层的一端电连接，所述数据线的一部分通过第六过孔与所述第一有源层的另一端电连接。
根据一些示例性的实施例，所述第二导电部在所述衬底基板上的正投影落入所述第一导电部在所述衬底基板上的正投影内；和/或，所述第三导电部的一部分跨过所述第五导电部。
根据一些示例性的实施例，所述第五导电部沿第一方向延伸，跨过所述第五导电部的第三导电部的部分沿第二方向延伸，所述第二过孔和所述第五过孔位于所述第五导电部的相对两侧。
根据一些示例性的实施例，所述发光元件包括第一电极，所述第一电极通过第七过孔与所述第四导电部直接电连接。
根据一些示例性的实施例，所述第七过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影至少部分重叠。
根据一些示例性的实施例，所述沟道限定部处于悬置状态。
在另一方面，提供一种显示装置，所述显示装置包括如上所述的显示基板。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显而易见，并可帮助对本公开有全面的理解。
图1A是根据本公开的实施例的显示基板的平面示意图；
图1B是根据本公开的实施例的显示基板的局部平面图，其示意性示出了所述显示基板的更多具体结构；
图2A是图1B中的显示基板的多个子像素的像素驱动电路的等效电路图；
图2B是图1B中的显示基板的单个子像素的像素电路的等效电路图；
图3是根据本公开的实施例的一些实施例的显示基板的局部平面图，其示意性示出了显示基板包括的像素驱动电路和发光元件的第一电极的平面图；
图4至图13分别是图3中所示的多个膜层的平面图；以及
图14是沿图3中的线AA’截取的截面图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为第二元件，类似 地，第二元件可以被命名为第一元件。如在这里使用的术语“和/或”包括一个或多个相关所列的项目的任意组合和所有组合。
应该理解的是，当元件或层被称作“形成在”另一元件或层“上”时，该元件或层可以直接地或间接地形成在另一元件或层上。也就是，例如，可以存在中间元件或中间层。相反，当元件或层被称作“直接形成在”另一元件或层“上”时，不存在中间元件或中间层。应当以类似的方式来解释其它用于描述元件或层之间的关系的词语(例如，“在...之间”与“直接在…之间”、“相邻的”与“直接相邻的”等)。
在本文中，使用方向性表述“第一方向”、“第二方向”来描述沿像素区的不同方向，例如，像素区的纵向方向和横向方向。应该理解，这样的表示仅为示例性的描述，而不是对本公开的限制。
在本文中，如无特别说明，表述“位于同一层”一般表示的是：第一部件和第二部件可以使用相同的材料并且可以通过同一构图工艺形成。表述“A与B连接成一体”表示部件A与部件B是一体形成的，即，它们通常包括相同的材料，并且形成为一个结构上连续的整体部件。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在以下示例中主要以用作驱动晶体管的P型薄膜晶体管的情况进行描述，其他晶体管根据电路设计与驱动晶体管具有相同或不同的类型。类似地，在其他实施例中，驱动晶体管也可以被示为N型薄膜晶体管。
本公开的一些示例性实施例提供一种显示基板，所述显示基板包括：所述显示基板包括：衬底基板；设置于所述衬底基板的多个像素单元，每一个像素单元包括多个子像素，每一个子像素包括发光元件和用于驱动所述发光元件的像素驱动电路；设置于所述衬底基板的半导体层；设置于所述半导体层靠近所述衬底基板一侧的第一导电层；和设置在所述半导体层远离所述衬底基板一侧的第二导电层，其中，所述像素驱动电路至少包括驱动晶体管、开关晶体管和感测晶体管；所述开关晶体管包括第一栅极和第一有源层，所述第一有源层位于所述半导体层，所述第一栅极位于所述第一导电层；所述驱动晶体管包括第二栅极和第二有源层，所述第二有源层位于所述半导体层，所述第二栅极位于所述第二导电层；所述感测晶体管包括第三栅极和第三有源层，所述第三有源层位于所述半导体层，所述第三栅极位于所述第二导电层；所述显示基板还包括沟道限定部，所述沟道限定部用于限定所述开关晶体管的沟道区，所述沟道 限定部位于所述第二导电层，所述沟道限定部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影至少部分重叠。通过这样的方式，可以保证形成的开关晶体管具有较好的特性。
图1A是根据本公开的实施例的显示基板的平面示意图，图1B是根据本公开的实施例的显示基板的局部平面图，其示意性示出了所述显示基板的更多具体结构。结合参照图1A和图1B，根据本公开的实施例的显示基板可以包括衬底基板100、设置在衬底基板100上的像素单元PX、设置在衬底基板100上的驱动单元DRU以及将像素单元PX与驱动单元DRU电连接的走线PL，所述驱动单元DRU用于驱动像素单元PX。
所述显示基板可以包括显示区域AA和非显示区域NA。显示区域AA可以是设置有显示图像的像素单元PX的区域。稍后将描述每个像素单元PX。非显示区域NA是不设置像素单元PX的区域，即可以是不显示图像的区域。用于驱动像素单元PX的驱动单元DRU以及将像素单元PX与驱动单元DRU连接的一些走线PL可以设置在非显示区域NA中。非显示区域NA与最终显示装置中的边框对应，并且边框的宽度可以根据非显示区域NA的宽度来确定。
显示区域AA可以具有各种形状。例如，显示区域AA可以以诸如包括直边的闭合形状的多边形(例如矩形)、包括曲边的圆形、椭圆形等以及包括直边和曲边的半圆形、半椭圆形等的各种形状设置。在本公开的实施例中，将显示区域AA设置为具有包括直边的四边形形状的一个区域，应该理解，这仅是本公开的示例性实施例，而不是对本公开的限制。
非显示区域NA可以设置在显示区域AA的至少一侧处。在本公开的实施例中，非显示区域NA可以围绕显示区域AA的外周。在本公开的实施例中，非显示区域NA可以包括在第一方向X上延伸的横向部分和在第二方向Y上延伸的纵向部分。
像素单元PX设置在显示区域AA中。像素单元PX是用于显示图像的最小单元，并且可以设置为多个。例如，像素单元PX可以包括发射白色光和/或彩色光的发光器件。
像素单元PX可以设置成多个，以沿着在第一方向X上延伸的行和在第一方向Y上延伸的列呈矩阵形式布置。然而，本公开的实施例不具体限制像素单元PX的布置形式，并且可以以各种形式布置像素单元PX。例如，像素单元PX可以布置为使得相对于第一方向X和第一方向Y倾斜的方向成为列方向，并且使得与列方向交叉的方向 成为行方向。
一个像素单元PX可以包括多个子像素。例如，一个像素单元PX可以包括3个子像素，即第一子像素SP1、第二子像素SP2和第三子像素SP3。再例如，一个像素单元PX可以包括4个子像素，即第一子像素SP1、第二子像素SP2、第三子像素SP3和第四子像素。例如，第一子像素SP1可以为红色子像素，第二子像素SP2可以为绿色子像素，第三子像素SP3可以为蓝色子像素，第四子像素可以为白色子像素。
每一个子像素可以包括发光元件和用于驱动发光元件的像素驱动电路。例如，第一子像素SP1可以包括位于第一发光区域SPA1中的第一发光元件和用于驱动第一发光元件的第一像素驱动电路SPC1，所述第一发光元件可以发射红色光；第二子像素SP2可以包括位于第二发光区域SPA2中的第二发光元件和用于驱动第二发光元件的第二像素驱动电路SPC2，第二发光元件可以发射绿色光；第三子像素SP3可以包括位于第三发光区域SPA3中的第三发光元件和用于驱动第三发光元件的第三像素驱动电路SPC3，第三发光元件可以发射蓝色光。
子像素的发光区域可以是子像素的发光元件所在的区域。例如，在OLED显示面板中，子像素的发光元件可以包括叠层设置的第一电极(例如阳极)、发光材料层和第二电极(例如阴极)。这样，子像素的发光区域可以是被夹在阳极和阴极的发光材料层的部分所对应的区域。
子像素还包括非发光区域，例如，子像素的像素驱动电路位于子像素的非发光区域中。每一个子像素的发光区域的面积与该子像素的整体面积(发光区域和非发光区域的面积之和)的比率，决定了该子像素的开口率。
OLED的发光器件(例如发光层，简称为EL层)可能在制作时的一致性不够好，例如，在用蒸镀工艺制作EL层时，由于蒸镀工艺的局限性导致制作出的各个子像素的EL层不一致，从而导致不同子像素之间的发光亮度或色度不均一。而且，随着使用时间的增长，EL层会出现不同程度的老化，也会导致各个子像素的EL层不一致，从而导致不同子像素之间的发光亮度或色度不均一。在本公开的实施例中，所述显示基板还可以包括感光电路OSC，所述感光电路OSC可以感测像素单元实际发出的光。这样，在本公开的实施例中，所述显示基板可以基于感光电路OSC感测出的像素单元实际发出的光，对各个像素单元内的子像素进行光学补偿，以提高显示基板的发光均一性。
例如，在本公开的一些示例性实施例中，每一个像素单元PX中都设置有一个测 光电路OSC。每一个测光电路OSC对其位于的像素单元PX实际发出的光进行感测。
例如，在本公开的实施例中，至少两个像素单元PX可以共用一个感光电路OSC。参照图1A和图1B，在同一列的像素单元中，位于相邻两行的两个像素单元PX可以共用一个感光电路OSC。这样，不需要对每一个像素单元PX都设置一个感光电路，可以减少感光电路的数量，从而可以提高开口率。
在所述显示基板处于显示状态时，感光电路OSC可以感测出与它相邻的2个像素单元实际发出的光。例如，所述感光电路OSC可以至少包括光电转换元件(将在下文中进一步说明)。这样，所述感光电路OSC可以被配置为：感测与它相邻的2个像素单元实际发出的光；以及根据感测出的光，发送感测电信号。
再例如，参照图1A，所述感光电路OSC可以将所述感测电信号发送至外部电路，例如显示装置的控制IC。控制IC可以根据所述感测电信号控制发送给像素单元PX的控制信号，例如，可以控制发送给各个子像素的像素驱动电路的数据信号(即data信号)。在所述数据信号的控制下，各个子像素相应地进行发光。
在图1A和图1B所示的实施例中，子像素SP1、SP2、SP3并排设置，各个子像素SP1、SP2、SP3具有各自的数据线DL。
图2A是图1B中的显示基板的多个子像素的像素驱动电路的等效电路图，图2B是图1B中的显示基板的单个子像素的像素电路的等效电路图。图2B中所示的像素驱动电路可以是上述像素驱动电路SPC1、SPC2、SPC3中的任一个。参照图2A和图2B，所述像素驱动电路可以包括开关晶体管T1、驱动晶体管T2、感测晶体管T3和存储电容Cst1等多个元件。该像素驱动电路可称为3T1C结构。
需要说明的是，此处以3T1C结构为例对根据本公开实施例的显示基板包括的像素驱动电路进行说明，但是，本公开实施例的显示基板包括的像素驱动电路不局限于3T1C结构。
继续参照图2B，开关晶体管T1的栅极与第一扫描信号线GL1连接，开关晶体管T1的第一电极连接至数据线DL，开关晶体管T1的第二电极连接至驱动晶体管T2的栅极，例如，开关晶体管T1的第二电极和驱动晶体管T2的栅极可以均电连接至节点GN。开关晶体管T1用于控制来自数据线DL的电压信号向像素驱动电路的写入。
需要说明的是，每个晶体管可以包括有源层、栅极、第一电极(例如源极)和第二电极(例如漏极)。例如，所述开关晶体管T1包括第一栅极G1和第一有源层ACT1； 所述驱动晶体管T2包括第二栅极G2和第二有源层ACT2；所述感测晶体管T3包括第三栅极G3和第三有源层ACT3。在本公开的实施例中，所述晶体管的有源层可以位于半导体层中，栅极可以位于不同的导电层中。
需要说明的是，在本文中，晶体管的第一电极可以指晶体管的源极和漏极中的一个，晶体管的第二电极可以指晶体管的源极和漏极中的另一个。
驱动晶体管T2的栅极电连接至节点GN，驱动晶体管T2的第一电极与第一电源信号(例如高电压电平信号VDD)连接，驱动晶体管T2的第二电极可连接至发光元件D1的阳极，从而可以根据电压信号来产生驱动电流以驱动发光元件D1发光。例如，所述发光元件D1可以是有机发光二极管(OLED)。
存储电容Cst1的两端分别连接至驱动晶体管T2的栅极和源极，用于存储从数据线输入的所述电压信号。例如，存储电容Cst1的一端电连接至节点GN，存储电容Cst1的另一端电连接至节点SN。即，存储电容Cst1的一端、开关晶体管T1的第二电极和驱动晶体管T2的栅极均电连接至节点GN，存储电容Cst1的另一端、驱动晶体管T2的第二电极和发光元件D1的阳极均电连接至节点SN。
感测晶体管T3的栅极连接至第二扫描信号线GL2，感测晶体管T3的第一电极与感测信号线SL连接，感测晶体管T3的第二电极电连接至节点SN。
发光元件D1的阳极电连接至节点SN，发光元件D1的阴极电连接至低电压电平信号VSS。电平信号VDD和VSS均为直流电压信号，用于为驱动发光元件D1发光提供必要的电压。
图3是根据本公开的实施例的一些实施例的显示基板的局部平面图，其示意性示出了显示基板包括的像素驱动电路和发光元件的第一电极的平面图。图4至图13分别是图3中所示的多个膜层的平面图。
结合参照图3至图13，所述显示基板可以包括多个导电层、一个半导体层和多个绝缘层。为了描述方便，将多个导电层分别描述为第一导电层、第二导电层、第三导电层和第四导电层。例如，图4示出了第三导电层30的一部分。图5示出了第一导电层10的一部分和第三导电层30的一部分，第一导电层10可以是第一扫描信号线GL1一些晶体管的栅极以及第一导电部所在的膜层，例如，它可以是由栅极材料构成的导电层。图6示意性示出了暴露第三导电层30和第一导电层10的一部分的多个过孔。在图4-图6的基础上，图7还示出了半导体层ACT，各个晶体管的有源层可以位于该 半导体层ACT中。需要说明的是，半导体层ACT的一部分可以具有半导体特性，以形成各个晶体管的沟道区，半导体层ACT的其他部分可以被导体化，以具有导体特性，以分别形成各个晶体管的源极区、漏极区以及其他的导电部。在图4-图7的基础上，图8还示出了第二导电层20的一部分，一些晶体管的栅极、第二扫描信号线GL2等可以位于第二导电层20中，例如，第二导电层20可以是由栅极材料构成的导电层。图9示意性示出了暴露第二导电层20的一部分的多个过孔。在图4-图9的基础上，图10还示出了第四导电层40的一部分，第四导电层40可以是数据线DL、导电部等所在的膜层，即，它可以是由源漏极材料构成的导电层。图11示意性示出了暴露第四导电层40的一部分的多个过孔。图12示意性示出了暴露半导体层ACT的一部分以电连接发光元件的第一电极的过孔。在图4-图12的基础上，图13还示出了发光元件的第一电极所在的层的一部分，例如，它可以是由例如ITO的透明导电材料构成的导电层。
例如，第三导电层30、第一导电层10、半导体层ACT、第二导电层20、第四导电层40和第一电极可以依次叠置在显示基板的衬底基板上。具体地，第三导电层30可以设置在衬底基板上，第一导电层10设置在第三导电层30远离所述衬底基板的一侧，半导体层ACT设置在第一导电层10远离所述衬底基板的一侧，第二导电层20设置在半导体层ACT远离所述衬底基板的一侧，第四导电层40设置在第二导电层20远离所述衬底基板的一侧，第一电极设置在第四导电层40远离所述衬底基板的一侧。关于各个膜层的层叠关系，下文将结合截面图更详细地描述。
应该理解，所述显示基板还可以包括位于衬底基板100、第三导电层30、第一导电层10、半导体层ACT、第二导电层20和第四导电层40中任意相邻的两者之间的多个绝缘层，在下文中，将结合截面图描述这些绝缘层。在所述绝缘层中，可以形成暴露第三导电层30、第一导电层10、半导体层ACT、第二导电层20、第四导电层40中的一个膜层的至少一部分的过孔或凹槽，以便实现位于不同膜层之间的部件的电连接。
所述显示基板可以包括多条信号线，结合参照图2B和图3，所述多条信号线可以包括第一扫描信号线GL1、第二扫描信号线GL2、数据线DL、第一电源信号线VDD和感测信号线SL。第一电源信号线VDD和感测信号线SL可以位于第三导电层30中，第一扫描信号线GL1可以位于所述第一导电层10中，第二扫描信号线GL2可以位于所述第二导电层20中，数据线DL可以位于所述第四导电层40中。
在图3所示的实施例中，第一扫描信号线GL1、第二扫描信号线GL2、感测信号线SL的一部分可以基本沿第一方向X延伸，数据线DL、第一电源信号线VDD、感 测信号线SL的另一部分可以基本沿第二方向Y延伸。例如，在第二方向Y上，第二扫描信号线GL2可以位于第一扫描信号线GL1和感测信号线SL的一部分之间。
结合参照图2B至图4，在根据本公开的实施例的显示基板中，第一电源信号线VDD和感测信号线SL均位于第三导电层30中。第一电源信号线VDD和感测信号线SL彼此间隔设置。感测信号线SL可以位于相邻的2个第一电源信号线VDD之间。例如，第一电源信号线VDD沿第二方向Y延伸。感测信号线SL可以包括第一部分和第二部分，感测信号线SL的第一部分基本沿第一方向X延伸，感测信号线SL的第二部分基本沿第二方向Y延伸。
结合参照图2B至图5，所述显示基板可以包括第一导电部101，第一扫描信号线GL1和第一导电部101位于第一导电层10中。第一扫描信号线GL1和第一导电部101彼此间隔设置。例如，第一扫描信号线GL1可以基本沿第一方向X延伸，第一导电部101可以基本沿第二方向Y延伸。例如，在相邻的第一电源信号线VDD和感测信号线SL之间，可以设置至少3个第一导电部101，3个第一导电部101彼此间隔设置。第一扫描信号线GL1的一部分可以形成开关晶体管T1的第一栅极，第一导电部101的一部分可以形成存储电容Cst1的一个极板。
结合参照图2B至图6，所述显示基板可以包括暴露第三导电层30和第一导电层10的一部分的多个过孔。例如，所述多个过孔包括暴露第一电源信号线VDD的过孔VH1、暴露感测信号线SL的过孔VH2和暴露第一导电部101的过孔VH3，以便于后续形成的导电部件分别与这些过孔暴露的部分电连接。
结合参照图2B至图7，所述显示基板还包括位于所述半导体层ACT中的第一有源层ACT1、第二有源层ACT2、第三有源层ACT3、第四导电部ACT4和第五导电部ACT5。例如，第二有源层ACT2、第三有源层ACT3、第四导电部ACT4和第五导电部ACT5可以为位于所述半导体层ACT中连续延伸的一体部分。所述第一有源层ACT1与所述一体部分间隔设置。
例如，第一有源层ACT1沿第一方向X延伸，第一有源层ACT1在衬底基板上的正投影可以落入第一扫描信号线GL1在衬底基板上的正投影内。多个第一有源层ACT1可以沿第一方向X间隔设置。
例如，第五导电部ACT5可以基本沿第一方向X延伸。第五导电部ACT5的一部分可以通过一个过孔VH1与位于一侧的第一电源信号线VDD电连接，第五导电部ACT5的另一部分可以通过另一个过孔VH1与位于另一侧的第一电源信号线VDD电 连接。例如，第五导电部ACT5可以位于第二有源层ACT2远离第四导电部ACT4的一侧。
第四导电部ACT4的一部分可以通过过孔VH3与第一导电部101电连接。第四导电部ACT4在衬底基板上的正投影可以与第一导电部101在衬底基板上的正投影至少部分重叠，例如，第四导电部ACT4在衬底基板上的正投影可以落入第一导电部101在衬底基板上的正投影内。
例如，在第二方向Y上，第四导电部ACT4可以位于第二有源层ACT2和第三有源层ACT3之间。第三有源层ACT3的一部分可以通过过孔VH2与感测信号线SL电连接。
在本公开的实施例中，第一扫描信号线GL1与第一有源层ACT1重叠的部分可以形成开关晶体管T1的第一栅极G1。
结合参照图2B至图8，所述显示基板包括位于所述第二导电层20中的第二扫描信号线GL2、第二导电部202和沟道限定部200。所述第二扫描信号线GL2、所述第二导电部202和所述沟道限定部200彼此间隔设置。
例如，第二扫描信号线GL2平行于所述第一扫描信号线GL1，即，它们都沿第一方向X延伸。
所述第二导电部202与所述第二有源层ACT2重叠的部分形成所述驱动晶体管T2的第二栅极G2。所述第二扫描信号线GL2与所述第三有源层ACT3重叠的部分形成所述感测晶体管的第三栅极G3。
在本公开的实施例中，所述沟道限定部200用于限定所述开关晶体管T1的沟道区，所述沟道限定部200位于所述第二导电层20中。参照图8，所述沟道限定部200在所述衬底基板上的正投影与所述第一有源层ACT1在所述衬底基板上的正投影至少部分重叠。所述沟道限定部200在所述衬底基板上的正投影落入所述第一栅极G1或所述第一扫描信号线GL1在所述衬底基板上的正投影内。
在本文中，表述“所述沟道限定部200用于限定所述开关晶体管T1的沟道区”表示：所述沟道限定部200在所述衬底基板上的正投影与所述开关晶体管T1的沟道区在所述衬底基板上的正投影基本重合。
结合参照图2B至图9，所述显示基板可以包括暴露第二导电部202的过孔VH4、分别暴露第一有源层ACT1的源极区和漏极区的过孔VH5、VH6，以便于后续形成的导电部件分别与这些过孔暴露的部分电连接。
结合参照图2B至图10，所述显示基板包括位于所述第四导电层40中的数据线DL和第三导电部401。所述数据线DL与所述第三导电部403间隔设置。
例如，数据线DL可以沿第二方向Y延伸，在相邻的第一电源信号线VDD和感测信号线SL之间，可以设置至少3条数据线DL。
例如，所述第三导电部403的一部分通过过孔VH5与所述第一有源层ACT1的一端电连接，所述数据线DL的一部分通过过孔VH6与所述第一有源层ACT1的另一端电连接。
例如，所述第三导电部403的一部分通过过孔VH4与第二导电部202电连接。
例如，所述第三导电部403在所述衬底基板上的正投影与所述第一导电部101在所述衬底基板上的正投影至少部分重叠。所述第三导电部403的一部分跨过所述第五导电部ACT5。例如，所述第五导电部ACT5沿第一方向X延伸，跨过所述第五导电部ACT5的第三导电部403的部分沿第二方向Y延伸，所述过孔VH4和所述过孔VH5位于所述第五导电部ACT5的相对两侧。例如，所述过孔VH4和所述过孔VH5在第二方向Y上可以基本对齐。
结合参照图2B至图12，所述显示基板可以包括过孔VH7，例如，过孔VH7可以贯穿钝化层和平坦化层以暴露第四导电部ACT4的一部分，以便后续形成的发光元件的第一电极与第四导电部电连接。
结合参照图2B至图13，示意性示出了发光元件的第一电极300，例如阳极。第一电极300可以通过过孔VH7与第四导电部ACT4电连接。
结合参照图2B至图13，示意性示出了像素开口400。例如，该像素开口400可以由位于第一电极300远离衬底基板一侧的像素界定层界定。
图14是沿图3中的线AA’截取的截面图。结合参照图2B至图14，所述显示基板可以包括衬底基板100，设置在衬底基板100上的第三导电层30，设置在第三导电层30远离衬底基板100一侧的缓冲层12，设置在缓冲层12远离衬底基板100一侧的第一导电层10，设置在第一导电层10远离衬底基板100一侧的第一栅绝缘层22，设置在第一栅绝缘层22远离衬底基板100一侧的半导体层ACT，设置在半导体层ACT远离衬底基板100一侧的第二栅绝缘层24，设置在第二栅绝缘层24远离衬底基板100一侧的第二导电层20，设置在第二导电层20远离衬底基板100一侧的层间介电层32，设置在层间介电层32远离衬底基板100一侧的第四导电层40，设置在第四导电层40远离衬底基板100一侧的第一绝缘层42，设置在第一绝缘层42远离衬底基板100一 侧的第二绝缘层52，设置在第二绝缘层52远离衬底基板100一侧的第一电极300，设置在第一电极300远离衬底基板100一侧的像素界定层500，设置在像素界定层500远离衬底基板100一侧的发光材料层EL，和设置在发光材料层EL远离衬底基板100一侧的第二电极600。
需要说明的是，上述各个绝缘层可以包括单层结构或多个绝缘层构成的叠层结构。例如，第一绝缘层42可以包括两个钝化层，第二绝缘层52可以包括一个钝化层和一个平坦化层。
结合参照图2B至图14，在本公开的实施例中，所述显示基板包括的开关晶体管T1具有底栅结构，即，开关晶体管T1的第一栅极G1位于第一有源层ACT1靠近衬底基板100的一侧；驱动晶体管T2和感测晶体管T3均具有顶栅结构，即，驱动晶体管T2的第二栅极G2位于第二有源层ACT2远离衬底基板100的一侧，感测晶体管T3的第三栅极G3位于第三有源层ACT3远离衬底基板100的一侧。并且，针对具有底栅结构的开关晶体管T1，还设置有沟道限定部200。沟道限定部200与具有顶栅结构的驱动晶体管T2和感测晶体管T3的栅极G2、G3位于同一层。这样，在对半导体层实施导体化工艺时，可以沟道限定部200为掩模来实施导体化工艺，使得第一有源层ACT1未被沟道限定部200覆盖的部分导体化，第一有源层ACT1被沟道限定部200覆盖的部分形成开关晶体管T1的沟道区。即，通过沟道限定部200的自对准，可以形成开关晶体管T1的沟道区。也就是说，具有底栅结构的开关晶体管T1以及具有顶栅结构的驱动晶体管T2和感测晶体管T3可以通过同一导体化工艺形成沟道区，有利于节省工艺步骤；而且，通过这样的方式，可以保证形成的开关晶体管T1具有较好的特性。此外，在本公开的实施例中，驱动晶体管和感测晶体管采用顶栅结构，可节省第二方向Y上的距离排布，有利于使第一扫描信号线的宽度增加，从而降低第一扫描信号线上的负载，进而可匹配较高的刷新频率。
例如，所述沟道限定部200处于悬置状态。即，所述沟道限定部200可以不接入电信号。
在本公开的实施例中，所述存储电容包括第一电容C1和第二电容C2，且第一电容和第二电容可以并联，以增大存储电容的电容值。结合参照图2B至图14，所述显示基板包括位于所述第一导电层中的第一导电部101和位于所述第二导电层中的第二导电部202，所述第一导电部101的至少一部分与所述第二导电部202的至少一部分在所述衬底基板上的正投影彼此重叠，所述第一导电部101和所述第二导电部202重 叠的部分形成所述第一电容C1。所述显示基板还包括第三导电部403和第四导电部ACT4，所述第三导电部403位于所述第四导电层40中，所述第四导电部ACT4位于所述半导体层ACT中，所述第四导电部ACT4包括所述半导体层ACT中被导体化的部分。所述第三导电部403的至少一部分与所述第四导电部ACT4的至少一部分在所述衬底基板上的正投影彼此重叠，所述第三导电部403和所述第四导电部ACT4重叠的部分形成所述第二电容C2。例如，所述第四导电部ACT4通过过孔VH3与所述第一导电部电连接，所述第三导电部403通过过孔VH4与所述第二导电部202电连接。
例如，所述第三有源层ACT3的一部分通过过孔VH2与所述感测信号线SL电连接，所述第五导电部ACT5的一部分通过过孔VH1与所述第一电源信号线VDD电连接。
例如，所述第一电极300通过过孔VH7与所述第四导电部ACT4直接电连接。例如，所述过孔VH7在所述衬底基板上的正投影与所述过孔VH3在所述衬底基板上的正投影至少部分重叠。
在本公开的实施例中，由于第一电极300由例如ITO等爬坡能力强的材料形成，所以，第一电极300可以通过过孔VH7直接电连接位于半导体层中的导电部件，可节省布线空间，给存储电容节省较高空间，从而有利于增加存储电容的电容值。
可选地，本公开的实施例还提供一种显示装置，该显示装置可以包括上述显示基板。所述显示装置可以包括但不限于：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。应该理解，该显示装置具有与前述实施例提供的显示基板相同的有益效果。
虽然本公开总体构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不背离本总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种显示基板，其特征在于，所述显示基板包括：
    衬底基板；
    设置于所述衬底基板的多个像素单元，每一个像素单元包括多个子像素，每一个子像素包括发光元件和用于驱动所述发光元件的像素驱动电路；
    设置于所述衬底基板的半导体层；
    设置于所述半导体层靠近所述衬底基板一侧的第一导电层；和
    设置在所述半导体层远离所述衬底基板一侧的第二导电层，
    其中，所述像素驱动电路至少包括驱动晶体管、开关晶体管和感测晶体管；
    所述开关晶体管包括第一栅极和第一有源层，所述第一有源层位于所述半导体层，所述第一栅极位于所述第一导电层；
    所述驱动晶体管包括第二栅极和第二有源层，所述第二有源层位于所述半导体层，所述第二栅极位于所述第二导电层；
    所述感测晶体管包括第三栅极和第三有源层，所述第三有源层位于所述半导体层，所述第三栅极位于所述第二导电层；
    所述显示基板还包括沟道限定部，所述沟道限定部用于限定所述开关晶体管的沟道区，所述沟道限定部位于所述第二导电层，所述沟道限定部在所述衬底基板上的正投影与所述第一有源层在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其特征在于，所述沟道限定部在所述衬底基板上的正投影落入所述第一栅极在所述衬底基板上的正投影内。
  3. 根据权利要求1或2所述的显示基板，其特征在于，所述第一有源层沿第一方向延伸，所述第二有源层和所述第三有源层沿第二方向延伸，所述第一方向和所述第二方向相交。
  4. 根据权利要求3所述的显示基板，还包括用于传输第一电源信号的第一电源信号线，其特征在于，所述显示基板还包括第三导电层，所述第三导电层位于所述第一 导电层靠近所述衬底基板的一侧，所述第一电源信号线位于所述第三导电层中。
  5. 根据权利要求4所述的显示基板，其特征在于，所述显示基板还包括用于传输感测信号的感测信号线，所述感测晶体管包括源极和漏极，所述感测信号线与所述感测晶体管的源极或漏极电连接，所述感测信号线位于所述第三导电层中。
  6. 根据权利要求3至5中任一项所述的显示基板，其特征在于，所述像素驱动电路还包括存储电容，所述存储电容包括第一电容；
    所述显示基板包括位于所述第一导电层中的第一导电部和位于所述第二导电层中的第二导电部，所述第一导电部的至少一部分与所述第二导电部的至少一部分在所述衬底基板上的正投影彼此重叠，所述第一导电部和所述第二导电部重叠的部分形成所述第一电容。
  7. 根据权利要求3至5中任一项所述的显示基板，其特征在于，所述存储电容还包括第二电容，所述第二电容与所述第一电容并联；
    所述显示基板还包括第四导电层，所述第四导电层位于所述第二导电层远离所述衬底基板的一侧；
    所述显示基板还包括第三导电部和第四导电部，所述第三导电部位于所述第四导电层中，所述第四导电部位于所述半导体层中，所述第四导电部包括所述半导体层中被导体化的部分；
    所述第三导电部的至少一部分与所述第四导电部的至少一部分在所述衬底基板上的正投影彼此重叠，所述第三导电部和所述第四导电部重叠的部分形成所述第二电容。
  8. 根据权利要求7所述的显示基板，其特征在于，所述第四导电部通过第一过孔与所述第一导电部电连接，所述第三导电部通过第二过孔与所述第二导电部电连接。
  9. 根据权利要求8所述的显示基板，其特征在于，所述显示基板还包括位于所述第一导电层中的第一扫描信号线，所述第一扫描信号线和所述第一导电部间隔设置； 以及
    所述第一扫描信号线与所述半导体层重叠的部分形成所述第一栅极。
  10. 根据权利要求9所述的显示基板，其特征在于，所述第一扫描信号线和所述感测信号线均沿第一方向延伸；和/或，
    所述第一电源信号线和所述第一导电部均沿第二方向延伸。
  11. 根据权利要求7所述的显示基板，其特征在于，所述显示基板还包括位于所述半导体层中的第五导电部；
    所述第二有源层、所述第三有源层、所述第四导电部和所述第五导电部为位于所述半导体层中连续延伸的一体部分；以及
    所述第一有源层与所述一体部分间隔设置。
  12. 根据权利要求11所述的显示基板，其特征在于，所述第三有源层的一部分通过第三过孔与所述感测信号线电连接，所述第五导电部的一部分通过第四过孔与所述第一电源信号线电连接。
  13. 根据权利要求8所述的显示基板，其特征在于，所述显示基板还包括位于所述第二导电层中的第二扫描信号线，所述第二扫描信号线平行于所述第一扫描信号线；
    所述第二扫描信号线、所述第二导电部和所述沟道限定部彼此间隔设置；以及
    所述第二导电部与所述第二有源层重叠的部分形成所述第二栅极，所述第二扫描信号线与所述第三有源层重叠的部分形成所述第三栅极。
  14. 根据权利要求10所述的显示基板，其特征在于，所述显示基板还包括位于所述第四导电层中的数据线；
    所述数据线与所述第三导电部间隔设置；
    所述第三导电部的一部分通过第五过孔与所述第一有源层的一端电连接，所述数据线的一部分通过第六过孔与所述第一有源层的另一端电连接。
  15. 根据权利要求14所述的显示基板，其特征在于，所述第二导电部在所述衬底基板上的正投影落入所述第一导电部在所述衬底基板上的正投影内；和/或，
    所述第三导电部的一部分跨过所述第五导电部。
  16. 根据权利要求15所述的显示基板，其特征在于，所述第五导电部沿第一方向延伸，跨过所述第五导电部的第三导电部的部分沿第二方向延伸，所述第二过孔和所述第五过孔位于所述第五导电部的相对两侧。
  17. 根据权利要求7所述的显示基板，其特征在于，所述发光元件包括第一电极，所述第一电极通过第七过孔与所述第四导电部直接电连接。
  18. 根据权利要求17所述的显示基板，其特征在于，所述第七过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影至少部分重叠。
  19. 根据权利要求1或2所述的显示基板，其特征在于，所述沟道限定部处于悬置状态。
  20. 一种显示装置，其特征在于，所述显示装置包括根据权利要求1至19中任一项所述的显示基板。
PCT/CN2021/091429 2021-04-30 2021-04-30 显示基板和显示装置 WO2022226985A1 (zh)

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