WO2022224906A1 - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Semiconductor device and manufacturing method for semiconductor device Download PDF

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WO2022224906A1
WO2022224906A1 PCT/JP2022/017898 JP2022017898W WO2022224906A1 WO 2022224906 A1 WO2022224906 A1 WO 2022224906A1 JP 2022017898 W JP2022017898 W JP 2022017898W WO 2022224906 A1 WO2022224906 A1 WO 2022224906A1
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region
type layer
semiconductor device
electric field
impurity element
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PCT/JP2022/017898
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French (fr)
Japanese (ja)
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喜直 三浦
昭 中島
旭強 沈
悠久 平井
信介 原田
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国立研究開発法人産業技術総合研究所
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Priority to JP2023515445A priority Critical patent/JPWO2022224906A1/ja
Priority to DE112022001173.4T priority patent/DE112022001173T5/en
Publication of WO2022224906A1 publication Critical patent/WO2022224906A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

Definitions

  • the present invention relates to a semiconductor device and its manufacturing method, and more particularly to a nitride semiconductor device and its manufacturing method.
  • a technique has been proposed for improving the breakdown voltage of a nitride semiconductor device by forming a termination structure in which a p-type guard ring portion is provided around an active portion and an i-type or n-type ion implantation region is provided therearound. (See Patent Document 1, for example).
  • a recessed groove is formed around the element region to provide an electric field relaxation region with a thin p-layer.
  • Patent Document 1 a depletion layer spreads between the p-type guard ring portion and the adjacent i-type or n-type ion-implanted region along the surface of the nitride semiconductor layer of the termination structure, and an electric field is applied.
  • a guard ring structure has a problem that local electric field concentration tends to occur.
  • the electric field relaxation region is a p-layer, electric field concentration can be avoided, but there is a problem that electric field concentration is likely to occur at the inner and outer ends of the electric field relaxation region.
  • An object of the present invention is to provide a semiconductor device capable of suppressing electric field concentration in a termination region surrounding an element region and improving breakdown voltage, and a method of manufacturing the same.
  • an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer with a higher acceptor concentration on the first p-type layer are the first p-type layer and the second p-type layer within the first p-type layer and the second p-type layer in the electric field relaxation region;
  • a semiconductor device is provided having a region containing an impurity element that deactivates a portion of the acceptors in the mold layer.
  • the region containing the impurity element that inactivates part of the acceptor is formed in the first p-type layer and the second p-type layer. .
  • the region containing the impurity element a part of the acceptor is inactivated and the resistance is increased. Therefore, formation of an electric field concentration point where the electric field is locally concentrated is suppressed, and the withstand voltage of the semiconductor device is improved. be able to.
  • a semiconductor substrate includes an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer with a higher acceptor concentration on the first p-type layer.
  • the acceptor concentration optimum for the device performance for the first p-type layer and the second p-type layer epitaxially grown in the device region and to relax the electric field surrounding the device region.
  • impurity element ions are implanted into the first p-type layer and the second p-type layer to inactivate a part of the acceptor to form a region having a high resistance, so that the electric field is locally concentrated.
  • the breakdown voltage of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to one embodiment;
  • FIG. 1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment; 1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment; 1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment;
  • FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to the embodiment.
  • FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to one embodiment.
  • FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to the embodiment.
  • FIG. 3 is a diagram showing conditions for multistage ion implantation of a semiconductor device according to one embodiment
  • FIG. 3 is a diagram showing the relationship between the breakdown voltage of a semiconductor device and the total dose of implanted boron according to one embodiment; It is the figure which calculated
  • FIG. 3 is a distribution diagram of equipotential planes when avalanche occurs in a semiconductor device having an acceptor surface density of 1.0 ⁇ 10 13 cm ⁇ 2 ;
  • FIG. 4 is a distribution diagram of equipotential planes during avalanche generation in a semiconductor device (no ion implantation) in which boron ions are not implanted into an electric field relaxation region;
  • 1 is a cross-sectional view showing the configuration of a semiconductor device of Example 1;
  • FIG. 1 is a plan view showing the configuration of a semiconductor device of Example 1;
  • FIG. 2 is a diagram showing conditions for multistage ion implantation of the semiconductor device of Example 1;
  • 3 is a cross-sectional view showing the configuration of a semiconductor device of Example 2;
  • FIG. FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 3;
  • FIG. 11 is a graph obtained by simulation of the breakdown voltage of the semiconductor device of Example 3;
  • FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 4;
  • FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 5;
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to one embodiment.
  • a gallium nitride vertical diode in which a pn diode is formed in an element region will be described as an example of a nitride semiconductor device.
  • the element region to the isolation region at the edge of the periphery thereof are shown.
  • the element region, the electric field relaxation region, and the isolation region are divisions of regions in the in-plane direction of the semiconductor, and are bounded by planes (lines in the cross-sectional view shown in FIG. 1) perpendicular to the stacking direction.
  • planes lines in the cross-sectional view shown in FIG. 1
  • an element region is positioned in the central portion
  • an electric field relaxation region surrounding the element region is positioned around the element region
  • an isolation region surrounding the electric field relaxation region is positioned around the electric field relaxation region. do.
  • a semiconductor device 10 has an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 formed on a semiconductor substrate 11 in this order.
  • the n-type layer 12 , the first p-type layer 13 and the second p-type layer 14 in the element region 31 extend horizontally at least up to the electric field relaxation region 32 .
  • a protective film 15 is formed on the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 surrounding it.
  • the protective film 15 is also formed outside the electric field relaxation region 32 , and is formed on the n-type layer 12 in the isolation region 33 surrounding the electric field relaxation region 32 .
  • the anode electrode 16 is formed on the second p-type layer 14 in the opening of the protective film 15 .
  • a cathode electrode 18 is formed on the back side of the gallium nitride semiconductor substrate 11 .
  • the semiconductor substrate 11 is, for example, n+ type with an impurity element concentration of 1 ⁇ 10 18 cm ⁇ 3 , and gallium nitride can be used.
  • the gallium nitride semiconductor substrate 11 has a wurtzite (hexagonal) crystal structure, and the main surface is the (0001) plane.
  • the impurity element is silicon (Si), for example.
  • the n-type layer 12 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the semiconductor substrate 11 by metal organic chemical vapor deposition (MOCVD), and has a thickness of 10 ⁇ m, for example.
  • the n-type layer 12 contains an n-type impurity element, such as silicon (Si), and has an impurity element concentration of, for example, 1.3 ⁇ 10 16 cm ⁇ 3 .
  • the first p-type layer 13 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the n-type layer 12 by MOCVD, and has a thickness of, for example, 1.0 ⁇ m.
  • the first p-type layer 13 contains a p-type impurity element such as magnesium (Mg) and has a concentration of 2 ⁇ 10 18 cm ⁇ 3 or less, for example.
  • the second p-type layer 14 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the first p-type layer 13 by MOCVD, and has a thickness of, for example, 50 nm.
  • the second p-type layer 14 contains a p-type impurity element such as magnesium (Mg) and has a concentration of 1 ⁇ 10 20 cm ⁇ 3 or higher, for example.
  • the element region 31 is located in the center of the pn diode and is a region through which on-current flows.
  • the anode electrode 16 is in ohmic contact with the second p-type layer 14 .
  • the anode electrode 16 may be a single metal film with a large work function such as gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), or an alloy film thereof, and a nickel (Ni) film is formed by sputtering.
  • a layered film of a gold (Au) film as a base is preferable.
  • the impurity element implantation region 20 is formed in the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14.
  • Impurity element-implanted region 20 contains an impurity element that inactivates acceptors in first p-type layer 13 and second p-type layer 14 .
  • Impurity elements preferably include at least one of boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe). Thereby, the active acceptor concentrations of the first p-type layer 13 and the second p-type layer 14 are lowered.
  • the impurity element contains boron (B) in particular from the viewpoint of electrical and thermal stability of withstand voltage characteristics.
  • B boron
  • the impurity element contains boron (B) in particular from the viewpoint of electrical and thermal stability of withstand voltage characteristics.
  • the impurity element In the vicinity of the boundary between the first p-type layer 13 and the n-type layer 12, it is preferable to implant the impurity element so that the acceptor areal density of the first p-type layer 13 and the donor areal density of the n-type layer 12 immediately below are balanced.
  • the electric field relaxation region 32 can be easily depleted when a reverse bias is applied to the pn diode, and electric field concentration on the mesa edge 21 at the boundary between the isolation region 33 and the electric field relaxation region 32 can be suppressed.
  • the breakdown voltage of the entire pn diode can be greatly improved.
  • the impurity element is implanted by an ion implantation method, and is preferably implanted by a multistage implantation method in that the impurity element concentration in the impurity element implantation region 20 can be made uniform.
  • the impurity element-implanted region 20 may be formed to reach the n-type layer 12 below the first p-type layer 13 .
  • the impurity element-implanted region 20 may be formed by forming a plurality of partial regions having different impurity element concentrations in the electric field relaxation region 32 continuously from the side near the element region 31 to the far side (for example, up to the mesa edge 21),
  • the impurity element concentration may be set higher in the partial region on the side farther from the element region 31 than in the partial region on the side closer to the element region 31 .
  • the acceptor concentration on the outer peripheral side of the electric field relaxation region 32 can be made lower than that on the inner peripheral side, so that electric field concentration can be suppressed and the withstand voltage can be further increased.
  • the number of partial regions may be two, or three or more.
  • the impurity element-implanted region 20 may form a plurality of partial regions in the electric field relaxation region 32 so as to surround the device region 31 from the side closer to the device region 31 to the side farther from the device region 31 .
  • the impurity element implanted region in the electric field relaxation region 32 so as to surround the element region 31 in a multiple manner the risk of local electric field concentration occurring due to the shape abnormality of the semiconductor device caused by the manufacturing process can be reduced or avoided.
  • the mesa groove 22 is formed, and the n-type layer 12 is formed by removing the first p-type layer 13 and the second p-type layer 14 .
  • first p-type layer 13 and second p-type layer 14 of semiconductor device 10 are electrically isolated from the surroundings.
  • the angle between the surface 14a of the second p-type layer 14 and the side surface is shown as a right angle (90 degrees) in FIG. This angle may be greater than 90 degrees (ie an obtuse angle) and the cross-sectional shape of the mesa structure may be trapezoidal.
  • the semiconductor layer is the n-type layer 12 on the surface of the mesa groove 22 .
  • An impurity element implanted region 23 may be formed from the surface of the n-type layer 12 to a predetermined depth by implanting an impurity element so as to balance the surface density of the n-type impurity element near the surface of the n-type layer 12 . This reduces the active donor concentration of n-type layer 12 .
  • the impurity element to be implanted may be the same as the impurity element of the impurity element implanted region 20 in the electric field relaxation region 32 .
  • an insulating region may be formed by inactivating the acceptors of the first p-type layer 13 and the second p-type layer 14 without forming the mesa groove 22 in the isolation region. This eliminates the need for dry etching when forming the mesa groove 22, and avoids damage to the crystal layers (the first p-type layer 13 and the second p-type layer 14) that tend to occur around the mesa edge 21. Electric field concentration due to such a manufacturing process can be suppressed.
  • the protective film 15 is formed from the outer periphery of the anode electrode 16 in the element region 31 to the surface of the second p-type layer 14 or the n-type layer 12 in the electric field relaxation region 32 and the isolation region 33 .
  • the protective film 15 is made of an insulating material and has a thickness of 1.0 ⁇ m, for example.
  • a SiO 2 film, a SiN film, or an Al 2 O 3 film can be used for the protective film 15 . It is preferable to form the SiO2 film by the CVD method, the SiN film by the plasma CVD method , and the Al2O3 film by the atomic layer deposition (ALD) method.
  • the cathode electrode 18 is formed on the back surface of the semiconductor substrate 11 .
  • Cathode electrode 18 is preferably a laminated film of an aluminum (Al) film with a titanium (Ti) film as a base because it can form an ohmic contact with semiconductor substrate 11 .
  • the cathode electrode 18 may be a laminated film of three or more layers in which other metals are further laminated.
  • the impurity element implantation region 20 containing the impurity element that deactivates the acceptor is formed in the first p-type layer 13 and the second p-type layer 14. be. Since the impurity element-implanted region 20 has a high resistance by inactivating a part of the acceptor, formation of an electric field concentration point where an electric field is locally concentrated is suppressed, and the withstand voltage of the semiconductor device 10 is improved. can do. Furthermore, in the isolation region 33 surrounding the electric field relaxation region 32, the first p-type layer 13 and the second p-type layer 14 are removed to form the mesa groove 22 exposing the n-type layer 12, thereby reducing electric field concentration. By further suppressing, the withstand voltage of the semiconductor device 10 can be further improved.
  • the p-type layer has a two-layer structure of the first p-type layer 13 and the second p-type layer 14, but a one-layer structure having the same acceptor concentration as the second p-type layer 14 may be used.
  • FIGS. 2A-C and 3A-C are process diagrams (1 and 2) of a semiconductor device according to an embodiment. A method of manufacturing a semiconductor device will be described with reference to FIGS. 2A to 2C and FIGS. 3A to 3C.
  • an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are sequentially formed on a semiconductor substrate 11.
  • an n-type layer 12, a first p-type layer 13 and a second p-type layer 14 are epitaxially grown sequentially by MOCVD on an n+-type gallium nitride semiconductor substrate 11 having an impurity element concentration of 1 ⁇ 10 18 cm ⁇ 3 . .
  • semiconductor substrates laminated in this manner may be used.
  • heat treatment is performed in a nitrogen gas atmosphere to activate the acceptor impurity elements of the first p-type layer 13 and the second p-type layer 14 .
  • the heat treatment conditions are, for example, 800° C. and 30 minutes, but other conditions may be used.
  • the first p-type layer 13 and the second p-type layer 14 in the isolation region 33 are removed to expose the n-type layer 12 and form the mesa groove 22 .
  • a SiO 2 film having a thickness of 1.0 ⁇ m is formed on the entire surface of the second p-type layer 14 by CVD.
  • a resist mask is formed on the SiO2 film by photolithography, the SiO2 film in the isolation region 33 is removed by wet etching to expose the second p-type layer 14, and dry etching such as reactive ion etching is performed.
  • Second p-type layer 14 First p-type layer 13 and n-type layer 12 are removed by a method (RIE method) to expose n-type layer 12. As shown in FIG.
  • the mesa groove 22 is formed, for example, at a depth of 2.5 ⁇ m from the surface of the second p-type layer 14 .
  • the SiO 2 film on the surface of the second p-type layer 14 is removed.
  • an impurity that inactivates a part of the acceptor is added to the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 of the electric field relaxation region 32 and the n-type layer 12 of the isolation region 33.
  • Elemental ions are implanted to form impurity element-implanted regions 20 and impurity element-implanted regions 23 .
  • the surface of the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 and the surface of the n-type layer 12 in the isolation region 33 are formed with a SiO 2 film 24 by a CVD method as a through film for ion implantation.
  • the SiO 2 film 24 has a thickness of 50 nm, for example.
  • a photoresist film 25 is formed on the SiO 2 film 24 in the element region 31 to be used as a mask.
  • impurity element ions are implanted from an impurity element ion source into the electric field relaxation region 32 and the isolation region 33 by a multistage ion implantation method.
  • Impurity element ions preferably include ions of at least one of boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe), particularly Containing boron (B) is preferable in terms of electrical and thermal stability of withstand voltage characteristics.
  • the ion implantation angle is preferably 4° with respect to the c-axis of the crystal axes of the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 (that is, the c-axis of the crystal axis of the semiconductor substrate 11). It is preferably in the range of 7° or more. Thereby, ion channeling along the crystallographic axis can be suppressed.
  • a multistage implantation method in which the implantation energy and dose are changed for each implantation. preferably.
  • the maximum implantation energy is preferably set so that the implanted impurity element reaches the entire p-type layer.
  • the total dose of multistage ion implantation is preferably set so that the surface density of acceptors in the first p-type layer 13 is around 1 ⁇ 10 13 cm ⁇ 2 in terms of electric field concentration suppression in the electric field relaxation region 32 (described later). 6 and 7), for example, in this embodiment, it is set to 1 ⁇ 10 13 cm ⁇ 2 .
  • the second p-type layer 14, the first p-type layer 13, and the n-type layer 12 are formed in the depth direction from the surface of the second p-type layer 14, as shown in FIG. 3A.
  • An impurity element implanted region 20 is formed from the surface of (the interface with the first p-type layer 13) to a predetermined depth.
  • impurity element implantation region 23 is formed from the surface of n-type layer 12 to a predetermined depth.
  • the photoresist film 25 is removed and heat treatment is performed in a nitrogen gas atmosphere to stabilize the characteristics of the impurity element implanted regions 20 and 23 .
  • the heat treatment conditions are, for example, 800° C. and 30 minutes, but other conditions may be used.
  • the SiO2 film 24 is removed by wet etching.
  • the photoresist film 25 is also formed on the surface of the second p-type layer 14 in the electric field relaxation region 32 so as to surround the element region 31 and to form a plurality of photoresist films separated from each other in an annular shape in plan view. may be formed to perform multistage ion implantation.
  • the second p-type layer is implanted in the electric field relaxation region 32 in the depth direction from the surface of the second p-type layer 14 so as to surround the device region 31 from the side closer to the device region 31 to the farther side.
  • a partial region is formed by implanting a plurality of impurity elements to a predetermined depth from the surfaces of the first p-type layer 13 and the n-type layer 12 (the interface with the first p-type layer 13) (Example 1 and See Figure 8).
  • impurity element ions are further implanted into a portion distant from the element region 31 by a multistage ion implantation method, and impurity element implantation close to the element region 31 is performed.
  • a partial region having a surface density of impurity elements higher than that of the region 20 may be formed (see Example 2 and FIG. 10, which will be described later).
  • the protective film 15 is formed to cover the surface of the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 and the surface of the n-type layer 12 in the isolation region 33.
  • An anode electrode 16 is formed by opening the protective film 15 of .
  • a protective film 15 such as a SiO 2 film (1 ⁇ m thick) is formed on the entire surface shown in FIG. 3A by CVD.
  • a resist mask is formed on the protective film 15 by photolithography, and a portion of the protective film 15 where the anode electrode 16 is to be formed is removed by wet etching to expose the second p-type layer 14, for example, an opening having a diameter of 200 ⁇ m.
  • a metal layer such as a nickel (Ni) film, covering the exposed second p-type layer 14 and protective film 15 is formed to a thickness of 100 nm by vapor deposition.
  • a metal layer on the protective film 15 is removed by wet etching after forming a resist mask by photolithography to form the anode electrode 16 .
  • the cathode electrode 18 is formed on the back surface 11a of the semiconductor substrate 11. Then, in the step of FIG. Specifically, the oxide film on the rear surface 11a of the semiconductor substrate 11 is removed and washed, and the entire rear surface 11a is coated with a metal laminate film, for example, a titanium (Ti) film, aluminum (Ti) film, aluminum (Ti) film, etc., from the surface of the rear surface 11a by a sputtering method or a vapor deposition method. Al) film and titanium nitride (TiN) film are sequentially deposited to form the cathode electrode 18 . Next, heat treatment is performed in a nitrogen gas atmosphere to reduce the contact resistance of the anode electrode 16 and the cathode electrode 18 . The heat treatment conditions are, for example, 550° C. and 10 minutes. As described above, the semiconductor device 10 is formed.
  • a metal laminate film for example, a titanium (Ti) film, aluminum (Ti) film, aluminum (Ti) film, etc
  • the acceptor concentration optimum for the device performance can be set in the device region 31 for the epitaxially grown first p-type layer 13 and the second p-type layer 14, and the device region 31
  • impurity element ions are implanted into the first p-type layer 13 and the second p-type layer 14 to inactivate a part of the acceptors to form the impurity element implanted region 20 having a high resistance.
  • the formation of an electric field concentration point where the electric field is locally concentrated can be suppressed, and the withstand voltage of the semiconductor device 10 can be improved.
  • the first p-type layer 13 and the second p-type layer 14 are removed to form the mesa groove 22 exposing the n-type layer 12, thereby reducing electric field concentration.
  • the withstand voltage of the semiconductor device 10 can be further improved.
  • FIG. 4 is a diagram showing conditions for multistage ion implantation of a semiconductor device according to one embodiment, and shows an example of conditions for multistage ion implantation in the process of FIG. 2C.
  • boron ions as an example, the inventors have found conditions under which the surface density of impurity elements in the depth direction of a gallium nitride semiconductor substrate becomes substantially uniform by implanting boron ions in multiple stages while changing the implantation energy and dose.
  • a protective SiO 2 film 50 nm thick
  • a 3 ⁇ m thick resist mask was formed thereon. Referring to FIG. 4, ion implantation was performed in seven stages.
  • FIG. 5 is a diagram showing the relationship between the breakdown voltage of the semiconductor device according to the embodiment and the total dose of implanted boron. Measured.
  • a pn diode with a total boron ion dose of 3 ⁇ 10 12 cm ⁇ 2 to 3 ⁇ 10 13 cm ⁇ 2 has a maximum withstand voltage of 1300 V, and boron ions are implanted as a comparative example. It was found that the breakdown voltage is 100 V to 600 V higher than that in the case without the capacitor. As a result, the effect of improving the breakdown voltage by implanting the impurity element ions into the semiconductor device 10 to form the impurity element implanted region 20 has been confirmed.
  • FIG. 6 is a diagram obtained by simulation of the breakdown voltage of the semiconductor device according to the embodiment.
  • the layer 14 is formed as one p-type layer having a thickness of 1 ⁇ m and an acceptor concentration of 2 ⁇ 10 18 cm ⁇ 3 .
  • a cm ⁇ 2 a simulation was performed to find the withstand voltage in the range of 0.5 ⁇ 10 13 cm ⁇ 2 to 5 ⁇ 10 13 cm ⁇ 2 .
  • the Poisson equation was numerically solved for the two-dimensional model structure corresponding to the above structure, and the literature (IEDM, T. Maeda et. al, Tech. Dig. 2019, 4.2.1 pages to 4.2 .4 page) was applied to calculate the breakdown voltage.
  • the breakdown voltage increases from 900 V, and at 1.0 ⁇ 10 13 cm ⁇ 2 the breakdown voltage shows a maximum value of 1320 V. .
  • the breakdown voltage gradually decreased and remained almost constant.
  • the relationship between this breakdown voltage and the acceptor surface density corresponds to the measurement results shown in FIG.
  • the maximum withstand voltage obtained by the simulation is close to the withstand voltage of 1320 V, which is the measurement result shown in FIG.
  • the acceptor areal density (1.0 ⁇ 10 13 cm ⁇ 2 ) that showed the maximum breakdown voltage is close to the donor areal density of 0.8 ⁇ 10 13 cm ⁇ 2 in the n-type layer, and is the acceptor areal density of the impurity element-implanted region. is the condition under which the areal density of donors in the n-type layer is almost the same.
  • FIG. 7A and 7B are distribution diagrams of equipotential planes when avalanche occurs in a semiconductor device
  • FIG. 7A shows that the semiconductor device shown in FIG.
  • FIG. 7B is a distribution diagram of the equipotential surfaces when showing a breakdown voltage of 750 V as an example in which boron ions are not implanted, that is, an example in which boron is not implanted into the electric field relaxation region 32.
  • It is a distribution map of. 7A and 7B are obtained by simulation. It shows the potential distribution at the moment when the voltage applied to the cathode electrode 18 and the anode electrode 16 reaches the breakdown voltage and the avalanche current starts to flow.
  • the horizontal axis is the distance X ( ⁇ m) from the center of the pn diode, and the vertical axis is the depth from the surface of the second p-type layer 14 .
  • the first p-type layer 13 and the second p-type layer 14 are shown as one layer, and the semiconductor substrate 11 and the n-type layer 12 are shown as one layer.
  • the equipotential surfaces in FIGS. 7A-B are shown every 70V.
  • equipotential planes are equally spaced in the direction of the isolation region 33 on the surface of the p-type layer of the electric field relaxation region 32 . It can be seen that it spreads and electric field concentration is suppressed. The distribution of this equipotential surface is considered to be close to the distribution when the total dose amount is optimized in the electric field relaxation region 32 and the withstand voltage is maximized.
  • the equipotential surface does not appear on the surface of the p-type layer of the electric field relaxation region 32, and the equipotential surface narrows near the mesa edge. Therefore, it is considered that the breakdown voltage is lowered to 750V.
  • the semiconductor device of Example 1 is a vertical pn diode element, and specifically differs from the semiconductor device according to the embodiment shown in FIG. 1 in the structure of the impurity element implantation region in the electric field relaxation region.
  • FIGS. 8A and 8B are diagrams showing the configuration of the semiconductor device of Example 1, where FIG. 8A is a cross-sectional view and FIG. 8B is a plan view. In FIG. 8B, the range of the impurity element implantation region of the gallium nitride semiconductor layer under the protective film is indicated by a dashed line.
  • a pn diode is formed in the element region 31, and the second p-type layer 14 is formed in the central portion of the element region 31 when viewed from above.
  • An anode electrode 16 with a diameter of 200 ⁇ m for ohmic contact is formed.
  • a cathode electrode 18 is formed on the back surface of the semiconductor substrate 11 .
  • the semiconductor substrate 11 is a gallium nitride substrate having a Ga (0001) surface on the surface side, a thickness of 350 ⁇ m, and an n+ crystal doped with Si.
  • the Si concentration is 1 ⁇ 10 18 cm ⁇ 3 but may be higher.
  • n-type layer 12 of gallium nitride epitaxially grown by MOCVD, a first p-type layer 13 and a second p-type layer 14 are formed in this order on a semiconductor substrate 11 .
  • the n-type layer 12 has a thickness of 10 ⁇ m and is doped with Si.
  • the Si concentration is 1.2 ⁇ 10 16 cm -3 . With this Si concentration, a breakdown voltage exceeding 1300 V can be obtained.
  • a higher withstand voltage can be obtained.
  • the first p-type layer 13 has a thickness of 1 ⁇ m and is doped with Mg.
  • the Mg concentration is 1.5 ⁇ 10 18 cm -3 . Although this thickness and Mg concentration are functionally effective, if the Mg concentration is sufficiently controlled and epitaxial growth of the first p-type layer 13 is possible, the Mg concentration should be lower. is preferably set to 1 ⁇ 10 18 cm ⁇ 3 or less, since the electric field relaxation of the electric field relaxation region 32 becomes remarkable.
  • the second p-type layer 14 has a thickness of 50 nm and is doped with Mg.
  • the Mg concentration is 1 ⁇ 10 20 cm -3 . It should be noted that conditions other than this thickness and Mg concentration can be applied as long as the ohmic resistance with the anode electrode 16 is low.
  • the anode electrode 16 is a laminated film obtained by laminating a Ni film and an Au film on the second p-type layer 14 by sputtering. Thereby, the anode electrode 16 can make ohmic contact with the second p-type layer 14 .
  • the cathode electrode 18 is a laminated film in which a Ti film and an Al film are laminated on the rear surface of the semiconductor substrate 11 made of gallium nitride.
  • Boron ions are implanted into the second p-type layer 14 and the first p-type layer 13 in the depth direction from at least the surface of the second p-type layer 14 into the electric field relaxation region 32 surrounding the element region 31 of the first embodiment.
  • An inner injection region 41 close to the element region 31 and an outer injection region 42 far from the element region are formed.
  • the total boron dose is larger in the outer implanted region 42 than in the inner implanted region 41 and is set to 3 ⁇ 10 12 cm ⁇ 2 and 1 ⁇ 10 13 cm ⁇ 2 respectively.
  • the distribution of the boron concentration in the inner implantation region 41 and the outer implantation region 42 in the depth direction varies from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (the first p-type layer 13 and the n-type layer 12). ), and sharply decreases from the interface to the inside of the n-type layer 12 .
  • FIG. 9 is a diagram showing the conditions of multistage ion implantation for the semiconductor device of Example 1.
  • FIG. 9 the multistep implantation of boron ions is performed by the method and conditions described in FIG. 2C.
  • Boron ions are implanted into the impurity element implanted region 43 of the isolation region 33 so that the total dose is 3 ⁇ 10 12 cm ⁇ 2 , and the surfaces of the element region 31 and inner implanted region 41 are newly annealed to a thickness of 3 ⁇ m.
  • boron ions are implanted into the outer implantation region 42 and the impurity element implantation region 43 of the isolation region 33 so that the total dose is 7.times.10.sup.12 cm.sup. -2 . do.
  • the final total dose of the first and second ion implantations in the same region is 1 ⁇ 10 13 cm ⁇ 2 .
  • the in-plane widths of the main surfaces of the inner injection region 41 and the outer injection region 42 are each 10 ⁇ m.
  • the widths of the inner injection region 41 and the outer injection region 42 are preferably longer, and preferably 10 ⁇ m or more and 50 ⁇ m or less in order to more reliably relax the electric field.
  • mesa groove 22 is formed by removing entire first p-type layer 13 and second p-type layer 14 , and n-type layer 12 is exposed on the surface of mesa groove 22 . Boron ions are implanted into the n-type layer 12 to form an impurity element implanted region 43 .
  • the impurity element-implanted region 43 has a boron concentration of 7 ⁇ 10 12 cm ⁇ 2 .
  • the mesa groove 22 has a depth of 2.5 ⁇ m. The depth of the mesa groove 22 is sufficient as long as the first p-type layer 13 and the second p-type layer 14 are completely removed, and a deeper one is preferable from the viewpoint of electric field relaxation.
  • the width of the mesa groove 22 is 20 ⁇ m, but preferably 50 ⁇ m or more from the viewpoint of electric field relaxation.
  • the protective film 15 covers the surface of the gallium nitride crystal layer.
  • Protective film 15 specifically covers the surface of second p-type layer 14 and the surface of n-type layer 12 other than anode electrode 16 .
  • the protective film 15 is a 1 ⁇ m thick SiO 2 film formed by CVD.
  • the shape of the mesa structure in plan view is circular, but it may be oval or hexagonal, and any shape can be applied.
  • the semiconductor device of Example 2 is a vertical pn diode element, and differs from the vertical pn diode element of Example 1 in the termination structure. Other than that, it is the same as the first embodiment.
  • FIG. 10 is a cross-sectional view showing the configuration of the semiconductor device of Example 2.
  • FIG. 10 in a semiconductor device 50 of Example 2, impurity element implantation regions 51 to 53 implanted with boron are formed so as to surround an element region 31 in an electric field relaxation region 32 .
  • the semiconductor device 50 is Impurity element-implanted regions 51 to 53 in a plan view are formed in an annular shape.
  • Boron ions are implanted into the second p-type layer 14 and the first p-type layer 13 in the depth direction from at least the surface of the second p-type layer 14 in the impurity element implantation regions 51 to 53 by multistage ion implantation.
  • the impurity element-implanted regions 51 to 53 are each set to have a total dose of 1 ⁇ 10 13 cm ⁇ 2 . More specifically, the distribution of the boron concentration in the depth direction of the impurity element-implanted regions 51 to 53 is from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (between the first p-type layer 13 and the n-type layer 12). interface), and sharply decreases from the interface to the inside of the n-type layer 12 .
  • the in-plane width of the main surface of the impurity element-implanted regions 51 to 53 is 10 ⁇ m.
  • the width of the impurity element-implanted regions 51 to 53 is preferably 5 ⁇ m or more and 50 ⁇ m or less in order to more reliably relax the electric field.
  • the widths of the impurity element-implanted regions 51 to 53 may differ from each other.
  • the semiconductor device of Example 3 is a vertical pn diode element, and differs from the vertical pn diode elements of Examples 1 and 2 in the termination structure, specifically, in the structure of the impurity element implanted region in the electric field relaxation region. Except for this, it is the same as the embodiment.
  • FIG. 11 is a cross-sectional view showing the configuration of the semiconductor device of Example 3.
  • FIG. 11 Referring to FIG. 11, in a semiconductor device 80 of Example 3, impurity element implantation regions 81 to 85 implanted with boron are formed in an annular manner to surround an element region 31 in an electric field relaxation region 32 .
  • Impurity element-implanted regions 81 to 85 are formed by multistage implantation of boron ions into second p-type layer 14 and first p-type layer 13 at least in the depth direction from the surface of second p-type layer 14 under the same conditions as in the embodiment. It is done.
  • the resist mask used for this ion implantation four rows of parallel mask regions are annularly patterned in the region corresponding to the electric field relaxation region 32, forming impurity element implantation regions 81 to 85 separated from each other. .
  • mask regions with a width of 2 ⁇ m are arranged at positions of 6 ⁇ m, 5 ⁇ m, 4 ⁇ m, and 3 ⁇ m with respect to the mesa edge 21, and the width of each impurity element implanted region decreases in order from the outside to the inside.
  • the dose of boron ions in the impurity element implanted regions 81 to 85 is 1 ⁇ 10 13 cm ⁇ 2 as in the embodiment, and the dose of boron ions in the mask regions sandwiched between the implanted regions is higher than this. small. Therefore, since the mask regions are more sparsely arranged outside the electric field relaxation region 32, the effective boron concentration is high. Become.
  • the present embodiment differs in that the boron concentration changes gradually. Therefore, when a reverse bias is applied, the depletion layer expands in the electric field relaxation region 32, and electric field relaxation becomes more effective. That is, in the semiconductor device of this embodiment, the widths of the plurality of partial regions become wider from the side closer to the element region to the side farther from the device region.
  • the impurity-implanted region 85 (partial region) located farthest from the element region has a width of 1.5 ⁇ m to 8 ⁇ m, preferably 1.5 ⁇ m to 5 ⁇ m.
  • the width of the impurity-implanted region 85 furthest from the element region is 1.5 to 4 times, preferably 1.5 to 3 times, more preferably 1.5 to 2 times, the width of the impurity-implanted region 81 closest to the element region. It can be double.
  • the distances between the impurity-implanted regions 81-85 may be the same or different. Some of the intervals may be the same and others may be different.
  • the n-type layer is formed to a thickness of 10 ⁇ m and a donor concentration of 0.8 ⁇ 10 16 cm ⁇ 3
  • the first p-type layer 13 and the second p-type layer 14 are formed to a thickness of 1 ⁇ m and an acceptor concentration of 2 ⁇ . It was assumed to be formed as one p-type layer of 10 18 cm ⁇ 3 .
  • the acceptor surface density of the impurity element implantation region is swung in the range of 0.3 ⁇ 10 13 cm ⁇ 2 to 1.5 ⁇ 10 13 cm ⁇ 2 , and the impurity element implantation regions are interposed.
  • FIG. 12 shows the result of plotting the breakdown voltage calculated for the above two - dimensional model structure as a function of the average acceptor areal density NA of the electric field relaxation region 32 .
  • the solid line showing the present embodiment has a maximum breakdown voltage of 1360 V and a smaller NA dependence of the breakdown voltage. This means that even if the acceptor concentration and thickness of the first p-type layer 13 and the dose amount of the boron ion implantation fluctuate, the breakdown voltage is less likely to change. It is possible.
  • this embodiment can be realized only by changing the mask layout without changing the processes described in the embodiments, it has a great practical advantage.
  • five impurity element-implanted regions are provided, and numerical examples of the width and spacing are shown. good.
  • the width and spacing are not limited to the examples in FIG. 11 either.
  • the semiconductor device of Example 4 is a vertical pn diode element, and is a modification of the semiconductor device 10 according to the embodiment shown in FIG.
  • mesa groove 22 is formed by removing first p-type layer 13 and second p-type layer 14 in isolation region 33 .
  • the first p-type layer 13 and the second p-type layer 14 are insulated without forming a mesa groove.
  • FIG. 13 is a cross-sectional view showing the configuration of the semiconductor device of Example 4.
  • FIG. 13 in the semiconductor device 60 of Example 4, in the isolation region 33, impurities are deposited from the surface of the second p-type layer 14 of gallium nitride to the depths of the bottoms of the second p-type layer 14 and the first p-type layer 13.
  • An element-implanted region 61 is formed.
  • boron ions are implanted by multistage ion implantation with the maximum implantation energy set to 400 keV so that boron is distributed from the surface of the second p-type layer 14 to the bottom of the first p-type layer 13 .
  • the portions of the second p-type layer 14 and the first p-type layer 13 can be sufficiently insulative, and the impurity element implantation region 61 of the i-type layer can be formed.
  • the impurity element implantation region 20 of the electric field relaxation region 32 has a total dose of 1 ⁇ 10 13 cm ⁇ 2 .
  • the impurity element-implanted region 61 of the isolation region 33 has a total dose of 5 ⁇ 10 14 cm ⁇ 2 , but is set to 3 ⁇ 10 14 cm ⁇ 2 to 3 ⁇ 10 15 cm ⁇ 2 . This is preferable in that electric field concentration can be suppressed.
  • Example 4 the dry etching step for forming the mesa groove 22 of the semiconductor device according to the embodiment shown in FIG. 2B is unnecessary. As a result, damage to the surface portion of the gallium nitride crystal layer that tends to occur around the mesa edge 21 can be avoided, and electric field concentration caused by such a manufacturing process can be suppressed. As a result, the semiconductor device 60 of Example 4 can effectively improve the breakdown voltage in addition to the effect of improving the breakdown voltage of the impurity element implanted region 20 of the electric field relaxation region 32 of the semiconductor device 10 according to the embodiment shown in FIG. can.
  • the semiconductor device of Example 5 is a semiconductor device in which a trench MOS transistor is formed in the element region, and the electric field relaxation region and the isolation region are formed in the same manner as in Example 4 shown in FIG.
  • FIG. 14 is a cross-sectional view showing the configuration of the semiconductor device of Example 5.
  • a semiconductor device 70 is a gallium nitride film epitaxially grown on a semiconductor substrate 11 by MOCVD, similar to the semiconductor device 10 according to the embodiment shown in FIG. 1 and Examples 1 to 3.
  • An n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are formed in this order.
  • an n-channel MOS transistor having a drift region formed in n-type layer 12 and a body region formed in second p-type layer 14 is formed.
  • the impurity concentration of the first p-type layer 13 is designed according to the type and thickness of the gate insulating film and the crystal plane of the gallium nitride in order to perform normally-off operation with the threshold value of the n-channel MOS transistor being +3 V or more. It is preferable to set it to 10 17 cm ⁇ 3 or more and 5 ⁇ 10 18 cm ⁇ 3 .
  • a plurality of striped trenches 71 are formed in parallel to each other, reaching from the surface of the second p-type layer 14 to the n-type layer 12 .
  • the width of each trench 71 is 2 ⁇ m.
  • a gate insulating film 72 of SiO 2 film is formed on the sidewalls and bottom of the trench 71, and a gate electrode 73 is formed inside thereof.
  • a TiN material, for example, can be used for the gate electrode 73 .
  • the gate electrodes 73 are connected to each other at their ends in the longitudinal direction (the direction perpendicular to the plane of the paper in FIG. 14) so that the gate electrodes of the entire element have the same potential.
  • An n+ gallium nitride region 74 is formed in the second p-type layer 14 and the first p-type layer 13 on the surface of the gallium nitride layer on both sides of each trench 71 .
  • the n + gallium nitride region 74 is formed by implanting Si ions and performing activation heat treatment.
  • a source electrode 75 is in ohmic contact with the surface of the n+ gallium nitride region 74 .
  • the source electrode 75 is a film in which a Ti film and an Al film are laminated in this order.
  • the anode electrode 76 is in ohmic contact with the surface of the second p-type layer 14 between each trench 71 .
  • the anode electrode 76 is in contact with the source electrode 75 so as to have the same potential.
  • a Ni film is used for the anode electrode 76 .
  • a cathode electrode 18 formed on the back surface of the semiconductor substrate 11 also serves as the drain electrode.
  • the isolation region 33 and the electric field relaxation region 32 are configured similarly to those of Example 4.
  • the impurity element implanted region 20 of the electric field relaxing region 32 is formed to the same depth as in the fourth embodiment.
  • the total dose of the impurity element-implanted region 20 is set at 1 ⁇ 10 13 cm ⁇ 2 .
  • the impurity element-implanted region 61 of the isolation region 33 has a total dose of 5 ⁇ 10 14 cm ⁇ 2 , but is 3 ⁇ 10 14 cm ⁇ 2 to 3 ⁇ 10 15 cm ⁇ as in the fourth embodiment. Setting to 2 is preferable in that electric field concentration can be suppressed.
  • the trench MOS transistor when a positive bias is applied to the gate electrode 73 , the trench MOS transistor is turned on, and an on-current flows between the drain electrode (cathode electrode 18 ) and the source electrode 75 .
  • the trench MOS transistor When 0 (zero) V or a negative bias is applied to the gate electrode 73, the trench MOS transistor is turned off.
  • a reverse bias is applied between the drain electrode (cathode electrode 18) and the source electrode 75, the n-type layer 12 is depleted. The layer expands and exhibits withstand voltage characteristics.
  • the impurity concentration of the p-type layer required for normally-off design is generally set to approximately 1 ⁇ 10 18 cm ⁇ 3 .
  • the impurity concentration of the p-type layer is approximately 1 ⁇ 10 17 cm ⁇ 3 in the optimum design, which is 1/10 of the impurity concentration of the element region. Therefore, it has been difficult to achieve both impurity concentrations in both regions by epitaxial growth of the p-type layer once.
  • Example 5 by implanting boron into the first p-type layer 13 of the electric field relaxation region 32 to form the impurity element implantation region 20 having an impurity concentration lower than that of the first p-type layer 13 of the element region, the electric field is reduced. Concentration can be suppressed or avoided, and the electric field design can be optimized.
  • the trench MOS transistor is formed in the element region 31 in the fifth embodiment, it is not limited to this.
  • a planar MOS transistor or a high electron mobility transistor (HEMT) may be formed.
  • Examples 1 to 4 a gallium nitride crystal layer epitaxially grown on a gallium nitride substrate was used as the semiconductor epitaxial layer, but a group III nitride in which part of the gallium was replaced with aluminum (Al) or indium (In) It may be a semiconductor epitaxial layer.
  • a crystal layer of a Group III nitride semiconductor epitaxially grown on a substrate such as a silicon carbide (SiC) substrate or a sapphire substrate may be applied.
  • a substrate such as a silicon carbide (SiC) substrate or a sapphire substrate.
  • group III nitride semiconductors it is particularly preferable to use group III nitride semiconductors, but other wide bandgap semiconductors such as SiC and Ga 2 O 3 are also applicable.
  • the embodiment and Examples 1 to 4 may be combined with each other. It may be applied to the impurity element implanted region.
  • the breakdown voltage of semiconductor devices can be improved.

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Abstract

Provided is a semiconductor device comprising: an element region (31) having an n-type layer (12), a first p-type layer (13) on the n-type layer, and a second p-type layer (14) which is on the first p-type layer and which has a higher acceptor concentration than the first p-type layer; and an electric field relaxation region (32) surrounding the element region. The electric field relaxation region includes, in the first p-type layer and the second p-type layer, a region containing an impurity element for inactivating a portion of the acceptors in the first p-type layer and the second p-type layer.

Description

半導体装置および半導体装置の製造方法Semiconductor device and method for manufacturing semiconductor device
　本発明は、半導体装置およびその製造方法に係り、特に窒化物半導体装置およびその製造方法に関する。
　本願は、２０２１年４月２２日に、日本に出願された特願２０２１－０７２５９５号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a nitride semiconductor device and its manufacturing method.
This application claims priority based on Japanese Patent Application No. 2021-072595 filed in Japan on April 22, 2021, the contents of which are incorporated herein.
　活性部の周囲にｐ型のガードリング部と、さらにその周囲にｉ型またはｎ型のイオン注入領域を設けた終端構造を形成して、窒化物半導体装置の耐圧を向上する技術が提案されている（例えば、特許文献１参照）。 A technique has been proposed for improving the breakdown voltage of a nitride semiconductor device by forming a termination structure in which a p-type guard ring portion is provided around an active portion and an i-type or n-type ion implantation region is provided therearound. (See Patent Document 1, for example).
　素子領域の周囲にリセス溝を形成してｐ層を薄くした電界緩和領域を設けて、電圧印加時に電界緩和領域が空乏化し易くすることで、素子領域端の電界を緩和し素子全体を高耐圧化する技術が提案されている（例えば、特許文献２参照）。 A recessed groove is formed around the element region to provide an electric field relaxation region with a thin p-layer. By facilitating depletion of the electric field relaxation region when a voltage is applied, the electric field at the end of the element region is relaxed and the entire device has a high withstand voltage. There has been proposed a technique for converting the
日本国特開２０１９－１８６４２９号公報（Ａ）Japanese Patent Application Laid-Open No. 2019-186429 (A) 日本国特開２０１７－１８３４２８号公報（Ａ）Japanese Patent Application Laid-Open No. 2017-183428 (A)
　しかしながら、特許文献１では、終端構造の窒化物半導体層の表面に沿ってｐ型のガードリング部と隣合うｉ型またはｎ型のイオン注入領域との間に空乏層が拡がり電界がかかる。こうしたガードリング構造では局所的な電界集中が生じ易いという問題がある。特許文献２では、電界緩和領域内はｐ層であるので電界集中は避けられるものの、電界緩和領域の内側および外側の端部に電界集中が生じ易いという問題がある。さらに、ｐ層を薄くするために厚さを精密に制御することは容易ではなく、生産プロセスへの適用が困難であるという問題がある。 However, in Patent Document 1, a depletion layer spreads between the p-type guard ring portion and the adjacent i-type or n-type ion-implanted region along the surface of the nitride semiconductor layer of the termination structure, and an electric field is applied. Such a guard ring structure has a problem that local electric field concentration tends to occur. In Patent Document 2, since the electric field relaxation region is a p-layer, electric field concentration can be avoided, but there is a problem that electric field concentration is likely to occur at the inner and outer ends of the electric field relaxation region. Furthermore, it is not easy to precisely control the thickness of the p-layer to make it thin, and it is difficult to apply it to the production process.
　本発明の目的は、素子領域を囲む終端領域において電界集中を抑制して耐圧を向上可能な半導体装置およびその製造方法を提供することである。 An object of the present invention is to provide a semiconductor device capable of suppressing electric field concentration in a termination region surrounding an element region and improving breakdown voltage, and a method of manufacturing the same.
　本開示の一態様によれば、ｎ型層と、ｎ型層上の第１のｐ型層と、第１のｐ型層上のこれよりもアクセプタ濃度が高い第２のｐ型層とを有する素子領域とその周囲を囲む電界緩和領域と備え、上記電界緩和領域において、上記第１のｐ型層および上記第２のｐ型層内に、その第１のｐ型層および第２のｐ型層内のアクセプタの一部を不活性化させる不純物元素を含む領域を有する、半導体装置が提供される。 According to one aspect of the present disclosure, an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer with a higher acceptor concentration on the first p-type layer are the first p-type layer and the second p-type layer within the first p-type layer and the second p-type layer in the electric field relaxation region; A semiconductor device is provided having a region containing an impurity element that deactivates a portion of the acceptors in the mold layer.
　上記態様によれば、素子領域の周囲を囲む電界緩和領域おいて、第１のｐ型層および第２のｐ型層にアクセプタの一部を不活性化させる不純物元素を含む領域が形成される。不純物元素を含む領域はアクセプタの一部が不活性化して高抵抗化されているので、電界が局所的に集中する電界集中点が形成されることを抑制して、半導体装置の耐圧を向上することができる。 According to the above aspect, in the electric field relaxation region surrounding the element region, the region containing the impurity element that inactivates part of the acceptor is formed in the first p-type layer and the second p-type layer. . In the region containing the impurity element, a part of the acceptor is inactivated and the resistance is increased. Therefore, formation of an electric field concentration point where the electric field is locally concentrated is suppressed, and the withstand voltage of the semiconductor device is improved. be able to.
　本開示の他の態様によれば、半導体基板にｎ型層と、ｎ型層上の第１のｐ型層と、第１のｐ型層上のこれよりもアクセプタ濃度が高い第２のｐ型層とをエピタキシャル成長により形成するステップと、上記第１および第２のｐ型層のアクセプタを活性化するステップと、素子領域の周囲を囲む電界緩和領域において上記第１および第２のｐ型層に多段イオン注入法によりその第１のｐ型層および該第２のｐ型層内の上記アクセプタの一部を不活性化させる不純物元素イオンを注入する注入ステップと、上記素子領域において上記第２のｐ型層の表面に電極を形成するステップと、を含む半導体装置の製造方法が提供される。 According to another aspect of the present disclosure, a semiconductor substrate includes an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer with a higher acceptor concentration on the first p-type layer. forming a type layer by epitaxial growth; activating the acceptors of the first and second p-type layers; and forming the first and second p-type layers in an electric field relaxation region surrounding an element region. an implantation step of implanting impurity element ions for inactivating part of the acceptors in the first p-type layer and the second p-type layer by a multistage ion implantation method into the element region; and forming an electrode on the surface of the p-type layer of.
　上記他の態様によれば、素子領域においてエピタキシャル成長した第１のｐ型層および第２のｐ型層について素子性能に最適なアクセプタ濃度を設定することができるとともに、素子領域の周囲を囲む電界緩和領域において、第１のｐ型層および第２のｐ型層にアクセプタの一部を不活性化させる不純物元素イオンを注入して高抵抗化した領域を形成して、電界が局所的に集中する電界集中点が形成されることを抑制して、半導体装置の耐圧を向上することができる。 According to the other aspect, it is possible to set the acceptor concentration optimum for the device performance for the first p-type layer and the second p-type layer epitaxially grown in the device region, and to relax the electric field surrounding the device region. In the region, impurity element ions are implanted into the first p-type layer and the second p-type layer to inactivate a part of the acceptor to form a region having a high resistance, so that the electric field is locally concentrated. By suppressing the formation of electric field concentration points, the withstand voltage of the semiconductor device can be improved.
　本願発明によれば、半導体装置の耐圧を向上させることができる。 According to the present invention, the breakdown voltage of the semiconductor device can be improved.
一実施形態に係る半導体装置の構成を示す断面図である。1 is a cross-sectional view showing the configuration of a semiconductor device according to one embodiment; FIG. 一実施形態に係る半導体装置の工程図（その１）の一部である。1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment; 一実施形態に係る半導体装置の工程図（その１）の一部である。1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment; 一実施形態に係る半導体装置の工程図（その１）の一部である。1 is a part of a process drawing (No. 1) of a semiconductor device according to an embodiment; 一実施形態に係る半導体装置の工程図（その２）の一部である。FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to the embodiment. 一実施形態に係る半導体装置の工程図（その２）の一部である。FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to one embodiment. 一実施形態に係る半導体装置の工程図（その２）の一部である。FIG. 2 is a part of the process drawing (No. 2) of the semiconductor device according to the embodiment. 一実施形態に係る半導体装置の多段イオン注入の条件を示す図である。FIG. 3 is a diagram showing conditions for multistage ion implantation of a semiconductor device according to one embodiment; 一実施形態に係る半導体装置の耐圧と注入したホウ素の総ドーズ量との関係を示す図である。FIG. 3 is a diagram showing the relationship between the breakdown voltage of a semiconductor device and the total dose of implanted boron according to one embodiment; 一実施形態に係る半導体装置の耐圧をシミュレーションによって求めた図である。It is the figure which calculated|required the resisting pressure of the semiconductor device which concerns on one Embodiment by simulation. アクセプタ面密度が１．０×１０１３ｃｍ－２の半導体装置のアバランシェ発生時の等ポテンシャル面の分布図である。FIG. 3 is a distribution diagram of equipotential planes when avalanche occurs in a semiconductor device having an acceptor surface density of 1.0×10 13 cm −2 ; ホウ素イオンが電界緩和領域に注入されてない半導体装置（イオン注入無）のアバランシェ発生時の等ポテンシャル面の分布図である。FIG. 4 is a distribution diagram of equipotential planes during avalanche generation in a semiconductor device (no ion implantation) in which boron ions are not implanted into an electric field relaxation region; 実施例１の半導体装置の構成を示す断面図である。1 is a cross-sectional view showing the configuration of a semiconductor device of Example 1; FIG. 実施例１の半導体装置の構成を示す平面図である。1 is a plan view showing the configuration of a semiconductor device of Example 1; FIG. 実施例１の半導体装置の多段イオン注入の条件を示す図である。FIG. 2 is a diagram showing conditions for multistage ion implantation of the semiconductor device of Example 1; 実施例２の半導体装置の構成を示す断面図である。3 is a cross-sectional view showing the configuration of a semiconductor device of Example 2; FIG. 実施例３の半導体装置の構成を示す断面図である。FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 3; 実施例３の半導体装置の耐圧をシミュレーションによって求めた図である。FIG. 11 is a graph obtained by simulation of the breakdown voltage of the semiconductor device of Example 3; 実施例４の半導体装置の構成を示す断面図である。FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 4; 実施例５の半導体装置の構成を示す断面図である。FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device of Example 5;
　以下、図面に基づいて本発明の実施形態を説明する。なお、複数の図面間において共通する要素については同じ符号を付し、その要素の詳細な説明の繰り返しを省略する。 Hereinafter, embodiments of the present invention will be described based on the drawings. Elements that are common among a plurality of drawings are denoted by the same reference numerals, and repeated detailed description of the elements is omitted.
　図１は、一実施形態に係る半導体装置の構成を示す断面図である。本実施形態では、窒化物半導体装置として、素子領域にｐｎダイオードを形成した窒化ガリウム縦型ダイオードを例に説明する。図１では、図示の便宜のため、素子領域からその周囲の端部にあるアイソレーション領域までを示している。
　素子領域、電界緩和領域及びアイソレーション領域は、半導体の面内方向での領域の区分けであり、積層方向に垂直な面（図１に示す断面図では線）を境界とする。
　例えば、半導体を平面視した場合、中央部分に素子領域が位置し、素子領域の周りに素子領域を囲む電界緩和領域が位置し、電界緩和領域の周りに電界緩和領域を囲むアイソレーション領域が位置する。 FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to one embodiment. In this embodiment, a gallium nitride vertical diode in which a pn diode is formed in an element region will be described as an example of a nitride semiconductor device. In FIG. 1, for convenience of illustration, the element region to the isolation region at the edge of the periphery thereof are shown.
The element region, the electric field relaxation region, and the isolation region are divisions of regions in the in-plane direction of the semiconductor, and are bounded by planes (lines in the cross-sectional view shown in FIG. 1) perpendicular to the stacking direction.
For example, when a semiconductor is viewed from above, an element region is positioned in the central portion, an electric field relaxation region surrounding the element region is positioned around the element region, and an isolation region surrounding the electric field relaxation region is positioned around the electric field relaxation region. do.
　図１を参照するに、半導体装置１０は、半導体基板１１上に、ｎ型層１２と、第１ｐ型層１３と、第２ｐ型層１４とがこの順に形成されている。素子領域３１のｎ型層１２、第１ｐ型層１３及び第２ｐ型層１４は、水平方向に少なくとも電界緩和領域３２まで延在する。素子領域３１およびその周囲を囲む電界緩和領域３２では、第２ｐ型層１４上に保護膜１５が形成されている。保護膜１５は、電界緩和領域３２よりも外側にも形成されており、電界緩和領域３２の周囲を囲むアイソレーション領域３３では、ｎ型層１２上に形成されている。素子領域３１では、保護膜１５の開口部に第２ｐ型層１４上にアノード電極１６が形成されている。窒化ガリウム半導体基板１１の裏面側には、カソード電極１８が形成されている。 Referring to FIG. 1, a semiconductor device 10 has an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 formed on a semiconductor substrate 11 in this order. The n-type layer 12 , the first p-type layer 13 and the second p-type layer 14 in the element region 31 extend horizontally at least up to the electric field relaxation region 32 . A protective film 15 is formed on the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 surrounding it. The protective film 15 is also formed outside the electric field relaxation region 32 , and is formed on the n-type layer 12 in the isolation region 33 surrounding the electric field relaxation region 32 . In the element region 31 , the anode electrode 16 is formed on the second p-type layer 14 in the opening of the protective film 15 . A cathode electrode 18 is formed on the back side of the gallium nitride semiconductor substrate 11 .
　半導体基板１１は、例えば不純物元素の濃度１×１０１８ｃｍ－３のｎ＋型であり、窒化ガリウムを用いることができる。窒化ガリウムの半導体基板１１は、ウルツァイト構造（六方晶）の結晶構造を有し、主面は（０００１）面である。不純物元素は、例えばシリコン（Ｓｉ）である。 The semiconductor substrate 11 is, for example, n+ type with an impurity element concentration of 1×10 18 cm −3 , and gallium nitride can be used. The gallium nitride semiconductor substrate 11 has a wurtzite (hexagonal) crystal structure, and the main surface is the (0001) plane. The impurity element is silicon (Si), for example.
　ｎ型層１２は、半導体基板１１上に有機金属気相成長法（ＭＯＣＶＤ法）によりエピタキシャル成長した半導体結晶層（窒化ガリウム）であり、厚さが、例えば１０μｍである
。ｎ型層１２は、ｎ型不純物元素、例えばシリコン（Ｓｉ）を含み、例えば不純物元素の濃度１．３×１０１６ｃｍ－３である。 The n-type layer 12 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the semiconductor substrate 11 by metal organic chemical vapor deposition (MOCVD), and has a thickness of 10 μm, for example. The n-type layer 12 contains an n-type impurity element, such as silicon (Si), and has an impurity element concentration of, for example, 1.3×10 16 cm −3 .
　第１ｐ型層１３は、ｎ型層１２上にＭＯＣＶＤ法によりエピタキシャル成長した半導体結晶層（窒化ガリウム）であり、厚さが、例えば１．０μｍである。第１ｐ型層１３は、ｐ型の不純物元素、例えばマグネシウム（Ｍｇ）を含み、例えば濃度２×１０１８ｃｍ－３またはそれ以下である。 The first p-type layer 13 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the n-type layer 12 by MOCVD, and has a thickness of, for example, 1.0 μm. The first p-type layer 13 contains a p-type impurity element such as magnesium (Mg) and has a concentration of 2×10 18 cm −3 or less, for example.
　第２ｐ型層１４は、第１ｐ型層１３上にＭＯＣＶＤ法によりエピタキシャル成長した半導体結晶層（窒化ガリウム）であり、厚さが、例えば５０ｎｍである。第２ｐ型層１４は、ｐ型の不純物元素、例えばマグネシウム（Ｍｇ）を含み、例えば濃度１×１０２０ｃｍ－３またはそれ以上である。 The second p-type layer 14 is a semiconductor crystal layer (gallium nitride) epitaxially grown on the first p-type layer 13 by MOCVD, and has a thickness of, for example, 50 nm. The second p-type layer 14 contains a p-type impurity element such as magnesium (Mg) and has a concentration of 1×10 20 cm −3 or higher, for example.
　素子領域３１は、ｐｎダイオードの中央に位置し、オン電流が流れる領域である。素子領域３１では、アノード電極１６が第２ｐ型層１４にオーミックコンタクトしている。アノード電極１６は、金（Ａｕ）、白金（Ｐｔ）、パラジウム（Ｐｄ）、ニッケル（Ｎｉ）等の仕事関数の大きな単金属膜またはこれらの合金膜でもよく、スパッタ法によりニッケル（Ｎｉ）膜を下地とした金（Ａｕ）膜の積層膜が好ましい。 The element region 31 is located in the center of the pn diode and is a region through which on-current flows. In the device region 31 , the anode electrode 16 is in ohmic contact with the second p-type layer 14 . The anode electrode 16 may be a single metal film with a large work function such as gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), or an alloy film thereof, and a nickel (Ni) film is formed by sputtering. A layered film of a gold (Au) film as a base is preferable.
　電界緩和領域３２では、第２ｐ型層１４の表面から深さ方向に第２ｐ型層１４および第１ｐ型層１３内に不純物元素注入領域２０が形成されている。不純物元素注入領域２０は、第１ｐ型層１３および第２ｐ型層１４内のアクセプタを不活性化させる不純物元素を含む。不純物元素は、ホウ素（Ｂ）、窒素（Ｎ）、酸素（Ｏ）、リン（Ｐ）、亜鉛（Ｚｎ）および鉄（Ｆｅ）のうち、少なくとも１つの元素を含むことが好ましい。これにより、第１ｐ型層１３および第２ｐ型層１４の活性なアクセプタ濃度が低下する。不純物元素は、特にホウ素（Ｂ）を含むことが、耐圧特性の電気的、熱的安定性の点で好ましい。第１ｐ型層１３とｎ型層１２との境界付近では、第１ｐ型層１３のアクセプタ面密度と直下のｎ型層１２のドナー面密度がバランスするように不純物元素を注入することが好ましい。これにより、ｐｎダイオードへの逆バイアス印加時に電界緩和領域３２を空乏化し易くし、アイソレーション領域３３と電界緩和領域３２との境界のメサエッジ２１への電界集中を抑制することができる。その結果、ｐｎダイオード全体の耐圧を大幅に向上できる。 In the electric field relaxation region 32, the impurity element implantation region 20 is formed in the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14. As shown in FIG. Impurity element-implanted region 20 contains an impurity element that inactivates acceptors in first p-type layer 13 and second p-type layer 14 . Impurity elements preferably include at least one of boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe). Thereby, the active acceptor concentrations of the first p-type layer 13 and the second p-type layer 14 are lowered. It is preferable that the impurity element contains boron (B) in particular from the viewpoint of electrical and thermal stability of withstand voltage characteristics. In the vicinity of the boundary between the first p-type layer 13 and the n-type layer 12, it is preferable to implant the impurity element so that the acceptor areal density of the first p-type layer 13 and the donor areal density of the n-type layer 12 immediately below are balanced. As a result, the electric field relaxation region 32 can be easily depleted when a reverse bias is applied to the pn diode, and electric field concentration on the mesa edge 21 at the boundary between the isolation region 33 and the electric field relaxation region 32 can be suppressed. As a result, the breakdown voltage of the entire pn diode can be greatly improved.
　不純物元素は、イオン注入法によって注入されたものであり、多段注入法によって注入されることが、不純物元素注入領域２０内の不純物元素濃度を均一に形成できる点で好ましい。不純物元素注入領域２０は、第１ｐ型層１３の下部のｎ型層１２に達して形成されていてもよい。 The impurity element is implanted by an ion implantation method, and is preferably implanted by a multistage implantation method in that the impurity element concentration in the impurity element implantation region 20 can be made uniform. The impurity element-implanted region 20 may be formed to reach the n-type layer 12 below the first p-type layer 13 .
　不純物元素注入領域２０は、電界緩和領域３２において、不純物元素濃度が互いに異なる複数の部分領域を素子領域３１に近い側から遠い側（例えば、メサエッジ２１まで）に連続して形成してもよく、不純物元素濃度を素子領域３１に近い側の部分領域よりも遠い側の部分領域の方を大きく設定してもよい。これにより、電界緩和領域３２の外周側のアクセプタ濃度を内周側よりも低下させることができ、電界集中を抑制して耐圧をさらに高めることができる。なお、部分領域は２個でもよく、３個以上でもよい。 The impurity element-implanted region 20 may be formed by forming a plurality of partial regions having different impurity element concentrations in the electric field relaxation region 32 continuously from the side near the element region 31 to the far side (for example, up to the mesa edge 21), The impurity element concentration may be set higher in the partial region on the side farther from the element region 31 than in the partial region on the side closer to the element region 31 . As a result, the acceptor concentration on the outer peripheral side of the electric field relaxation region 32 can be made lower than that on the inner peripheral side, so that electric field concentration can be suppressed and the withstand voltage can be further increased. Note that the number of partial regions may be two, or three or more.
　また、不純物元素注入領域２０は、電界緩和領域３２において、素子領域３１に近い方から遠い方に素子領域３１の周囲を囲むように複数の部分領域を形成してもよい。これにより、電界緩和領域３２に素子領域３１を多重に囲むように不純物元素注入領域を設けることで、製造プロセスに起因する半導体装置の形状異常による局所的な電界集中発生のリスクを低減または回避できる。 Further, the impurity element-implanted region 20 may form a plurality of partial regions in the electric field relaxation region 32 so as to surround the device region 31 from the side closer to the device region 31 to the side farther from the device region 31 . As a result, by providing the impurity element implanted region in the electric field relaxation region 32 so as to surround the element region 31 in a multiple manner, the risk of local electric field concentration occurring due to the shape abnormality of the semiconductor device caused by the manufacturing process can be reduced or avoided. .
　アイソレーション領域３３では、メサ溝２２が形成されており、第１ｐ型層１３および第２ｐ型層１４が除去されたｎ型層１２が形成されている。これにより、半導体装置１０の第１ｐ型層１３および第２ｐ型層１４は周囲から電気的に離間される。アイソレーション領域３３と電界緩和領域３２との境界のメサエッジ２１では、図１では第２ｐ型層１４の表面１４ａと側面との角度が直角（９０度）で示されている。この角度は、９０度よりも大きく（つまり鈍角）でもよく、メサ構造の断面形状が台形でもよい。 In the isolation region 33, the mesa groove 22 is formed, and the n-type layer 12 is formed by removing the first p-type layer 13 and the second p-type layer 14 . Thereby, first p-type layer 13 and second p-type layer 14 of semiconductor device 10 are electrically isolated from the surroundings. At the mesa edge 21 at the boundary between the isolation region 33 and the electric field relaxation region 32, the angle between the surface 14a of the second p-type layer 14 and the side surface is shown as a right angle (90 degrees) in FIG. This angle may be greater than 90 degrees (ie an obtuse angle) and the cross-sectional shape of the mesa structure may be trapezoidal.
　メサ溝２２表面では、半導体層がｎ型層１２になっている。ｎ型層１２の表面近傍のｎ型不純物元素の面密度をバランスするように不純物元素を注入した不純物元素注入領域２３をｎ型層１２の表面から所定の深さまで形成してもよい。これにより、ｎ型層１２の活性なドナー濃度が低下する。注入する不純物元素は、電界緩和領域３２における不純物元素注入領域２０の不純物元素と同様でよい。 The semiconductor layer is the n-type layer 12 on the surface of the mesa groove 22 . An impurity element implanted region 23 may be formed from the surface of the n-type layer 12 to a predetermined depth by implanting an impurity element so as to balance the surface density of the n-type impurity element near the surface of the n-type layer 12 . This reduces the active donor concentration of n-type layer 12 . The impurity element to be implanted may be the same as the impurity element of the impurity element implanted region 20 in the electric field relaxation region 32 .
　変形例として、アイソレーション領域において、メサ溝２２を形成せずに、第１ｐ型層１３および第２ｐ型層１４のアクセプタを不活性化した絶縁領域を形成してもよい。これにより、メサ溝２２を形成する際のドライエッチングの工程が不要になり、メサエッジ２１周辺に生じ易い結晶層（第１ｐ型層１３および第２ｐ型層１４）のダメージを回避することができ、このような製造プロセスに起因する電界集中を抑制することができる。 As a modification, an insulating region may be formed by inactivating the acceptors of the first p-type layer 13 and the second p-type layer 14 without forming the mesa groove 22 in the isolation region. This eliminates the need for dry etching when forming the mesa groove 22, and avoids damage to the crystal layers (the first p-type layer 13 and the second p-type layer 14) that tend to occur around the mesa edge 21. Electric field concentration due to such a manufacturing process can be suppressed.
　保護膜１５は、素子領域３１のアノード電極１６の外周から電界緩和領域３２およびアイソレーション領域３３の第２ｐ型層１４またはｎ型層１２の表面に形成されている。保護膜１５は、絶縁材料からなり、例えば厚さが１、０μｍである。保護膜１５は、ＳｉＯ２膜、ＳｉＮ膜、Ａｌ２Ｏ３膜を用いることができる。ＳｉＯ２膜はＣＶＤ法、ＳｉＮ膜はプラズマＣＶＤ法、Ａｌ２Ｏ３膜は原子層堆積（ＡＬＤ）法により形成することが好ましい。 The protective film 15 is formed from the outer periphery of the anode electrode 16 in the element region 31 to the surface of the second p-type layer 14 or the n-type layer 12 in the electric field relaxation region 32 and the isolation region 33 . The protective film 15 is made of an insulating material and has a thickness of 1.0 μm, for example. A SiO 2 film, a SiN film, or an Al 2 O 3 film can be used for the protective film 15 . It is preferable to form the SiO2 film by the CVD method, the SiN film by the plasma CVD method , and the Al2O3 film by the atomic layer deposition (ALD) method.
　カソード電極１８は、半導体基板１１の裏面に形成されている。カソード電極１８は、チタン（Ｔｉ）膜を下地としたアルミニウム（Ａｌ）膜の積層膜が半導体基板１１とオーミックコンタクトが形成できる点で好ましい。カソード電極１８は、さらに他の金属を積層した３層以上の積層膜としてもよい。 The cathode electrode 18 is formed on the back surface of the semiconductor substrate 11 . Cathode electrode 18 is preferably a laminated film of an aluminum (Al) film with a titanium (Ti) film as a base because it can form an ohmic contact with semiconductor substrate 11 . The cathode electrode 18 may be a laminated film of three or more layers in which other metals are further laminated.
　本実施形態によれば、素子領域３１の周囲を囲む電界緩和領域３２において、第１ｐ型層１３および第２ｐ型層１４にアクセプタを不活性化させる不純物元素を含む不純物元素注入領域２０が形成される。不純物元素注入領域２０はアクセプタの一部が不活性化して高抵抗化されているので、電界が局所的に集中する電界集中点が形成されることを抑制して、半導体装置１０の耐圧を向上することができる。さらに、電界緩和領域３２の周囲を囲むアイソレーション領域３３において、第１ｐ型層１３および第２ｐ型層１４を除去してｎ型層１２を露出したメサ溝２２を形成することで、電界集中をさらに抑制して半導体装置１０の耐圧をさらに向上することができる。 According to this embodiment, in the electric field relaxation region 32 surrounding the device region 31, the impurity element implantation region 20 containing the impurity element that deactivates the acceptor is formed in the first p-type layer 13 and the second p-type layer 14. be. Since the impurity element-implanted region 20 has a high resistance by inactivating a part of the acceptor, formation of an electric field concentration point where an electric field is locally concentrated is suppressed, and the withstand voltage of the semiconductor device 10 is improved. can do. Furthermore, in the isolation region 33 surrounding the electric field relaxation region 32, the first p-type layer 13 and the second p-type layer 14 are removed to form the mesa groove 22 exposing the n-type layer 12, thereby reducing electric field concentration. By further suppressing, the withstand voltage of the semiconductor device 10 can be further improved.
　なお、本実施形態では、ｐ型層として第１ｐ型層１３および第２ｐ型層１４の２層構造としたが、アクセプタ濃度を第２ｐ型層１４と同様にした１層構造でもよい。 In this embodiment, the p-type layer has a two-layer structure of the first p-type layer 13 and the second p-type layer 14, but a one-layer structure having the same acceptor concentration as the second p-type layer 14 may be used.
　図２Ａ～Ｃおよび図３Ａ～Ｃは、一実施形態に係る半導体装置の工程図（その１およびその２）である。図２Ａ～Ｃおよび図３Ａ～Ｃを参照しつつ半導体装置の製造方法を説明する。 2A-C and 3A-C are process diagrams (1 and 2) of a semiconductor device according to an embodiment. A method of manufacturing a semiconductor device will be described with reference to FIGS. 2A to 2C and FIGS. 3A to 3C.
　図２Ａの工程では、半導体基板１１上にｎ型層１２、第１ｐ型層１３および第２ｐ型層１４を順次形成する。具体的には、不純物元素の濃度１×１０１８ｃｍ－３のｎ＋型の窒化ガリウムの半導体基板１１にＭＯＣＶＤ法によりｎ型層１２、第１ｐ型層１３および第２ｐ型層１４を順次エピタキシャル成長させる。なお、このように積層された半導体基板を用いてもよい。次いで、窒素ガス雰囲気中で熱処理を行って第１ｐ型層１３および第２ｐ型層１４のアクセプタ不純物元素の活性化を行う。熱処理の条件は、例えば、８００℃、３０分間であるが、これと異なる条件で行ってもよい。 2A, an n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are sequentially formed on a semiconductor substrate 11. In the step of FIG. Specifically, an n-type layer 12, a first p-type layer 13 and a second p-type layer 14 are epitaxially grown sequentially by MOCVD on an n+-type gallium nitride semiconductor substrate 11 having an impurity element concentration of 1×10 18 cm −3 . . Note that semiconductor substrates laminated in this manner may be used. Next, heat treatment is performed in a nitrogen gas atmosphere to activate the acceptor impurity elements of the first p-type layer 13 and the second p-type layer 14 . The heat treatment conditions are, for example, 800° C. and 30 minutes, but other conditions may be used.
　次いで、図２Ｂの工程では、アイソレーション領域３３における第１ｐ型層１３および第２ｐ型層１４を除去してｎ型層１２を露出してメサ溝２２を形成する。具体的には、第２ｐ型層１４の表面全体にＣＶＤ法により厚さ１．０μｍのＳｉＯ２膜を形成する。次いで、ＳｉＯ２膜上にフォトリソグラフィー法によりレジストマスクを形成して、アイソレーション領域３３のＳｉＯ２膜をウェットエッチングにより除去して第２ｐ型層１４を露出し、ドライエッチング、例えば反応性イオンエッチング法（ＲＩＥ法）により第２ｐ型層１４、第１ｐ型層１３およびｎ型層１２を除去してｎ型層１２を露出する。メサ溝２２は、例えば、第２ｐ型層１４の表面から例えば２．５μｍの深さに形成する。次いで、第２ｐ型層１４の表面のＳｉＯ２膜を除去する。 Next, in the process of FIG. 2B, the first p-type layer 13 and the second p-type layer 14 in the isolation region 33 are removed to expose the n-type layer 12 and form the mesa groove 22 . Specifically, a SiO 2 film having a thickness of 1.0 μm is formed on the entire surface of the second p-type layer 14 by CVD. Next, a resist mask is formed on the SiO2 film by photolithography, the SiO2 film in the isolation region 33 is removed by wet etching to expose the second p-type layer 14, and dry etching such as reactive ion etching is performed. Second p-type layer 14, first p-type layer 13 and n-type layer 12 are removed by a method (RIE method) to expose n-type layer 12. As shown in FIG. The mesa groove 22 is formed, for example, at a depth of 2.5 μm from the surface of the second p-type layer 14 . Next, the SiO 2 film on the surface of the second p-type layer 14 is removed.
　次いで、図２Ｃの工程では、電界緩和領域３２の第２ｐ型層１４、第１ｐ型層１３およびｎ型層１２並びにアイソレーション領域３３のｎ型層１２にアクセプタの一部を不活性化させる不純物元素イオンを注入して、不純物元素注入領域２０および不純物元素注入領域２３を形成する。具体的には、素子領域３１および電界緩和領域３２の第２ｐ型層１４の表面およびアイソレーション領域３３のｎ型層１２の表面にＣＶＤ法によりＳｉＯ２膜２４をイオン注入法のためのスルー膜として形成する。ＳｉＯ２膜２４は、例えば厚さ５０ｎｍとする。素子領域３１のＳｉＯ２膜２４の上にフォトレジスト膜２５を形成してマスクとする。次いで、電界緩和領域３２およびアイソレーション領域３３に、多段イオン注入法により不純物元素イオン源から不純物元素イオンを注入する。不純物元素イオンは、ホウ素（Ｂ）、窒素（Ｎ）、酸素（Ｏ）、リン（Ｐ）、亜鉛（Ｚｎ）および鉄（Ｆｅ）のうち、少なくとも１つの元素のイオンを含むことが好ましく、特にホウ素（Ｂ）を含むことが、耐圧特性の電気的、熱的安定性の点で好ましい。イオン注入角は、第２ｐ型層１４、第１ｐ型層１３およびｎ型層１２の結晶軸のｃ軸（つまり半導体基板１１の結晶軸のｃ軸）に対して、傾けることが好ましく、４°以上７°以下の範囲であることが好ましい。これにより、上記結晶軸に沿ったイオンチャネリングを抑制することができる。 Next, in the process of FIG. 2C, an impurity that inactivates a part of the acceptor is added to the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 of the electric field relaxation region 32 and the n-type layer 12 of the isolation region 33. Elemental ions are implanted to form impurity element-implanted regions 20 and impurity element-implanted regions 23 . Specifically, the surface of the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 and the surface of the n-type layer 12 in the isolation region 33 are formed with a SiO 2 film 24 by a CVD method as a through film for ion implantation. form as The SiO 2 film 24 has a thickness of 50 nm, for example. A photoresist film 25 is formed on the SiO 2 film 24 in the element region 31 to be used as a mask. Next, impurity element ions are implanted from an impurity element ion source into the electric field relaxation region 32 and the isolation region 33 by a multistage ion implantation method. Impurity element ions preferably include ions of at least one of boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe), particularly Containing boron (B) is preferable in terms of electrical and thermal stability of withstand voltage characteristics. The ion implantation angle is preferably 4° with respect to the c-axis of the crystal axes of the second p-type layer 14, the first p-type layer 13 and the n-type layer 12 (that is, the c-axis of the crystal axis of the semiconductor substrate 11). It is preferably in the range of 7° or more. Thereby, ion channeling along the crystallographic axis can be suppressed.
　本実施形態のイオン注入では、１回ごとの注入エネルギーとドーズ量を変えて注入する多段注入法を用いており、不純物元素濃度の深さ分布を制御するため、３回以上に分割して注入することが好ましい。また、最初に最も高い注入エネルギーを用いて注入し、注入エネルギーを回ごとに次第に低下させていくことが、深さ分布の制御性を高める点で好ましい。最大の注入エネルギーは、注入した不純物元素がｐ型層全体に到達するように設定することが好ましく、例えばｐ型層厚１μｍの本実施形態では４００ｋｅＶに設定する。多段イオン注入の総ドーズ量は、第１ｐ型層１３のアクセプタ面密度が１×１０１３ｃｍ－２近辺となるように設定することが電界緩和領域３２の電界集中抑制の点で好ましく（後述する図６、図７参照）、例えば本実施形態では、１×１０１３ｃｍ－２に設定する。 In the ion implantation of this embodiment, a multistage implantation method is used in which the implantation energy and dose are changed for each implantation. preferably. In order to improve the controllability of the depth distribution, it is preferable to perform the implantation using the highest implantation energy at the beginning and then gradually lower the implantation energy each time. The maximum implantation energy is preferably set so that the implanted impurity element reaches the entire p-type layer. The total dose of multistage ion implantation is preferably set so that the surface density of acceptors in the first p-type layer 13 is around 1×10 13 cm −2 in terms of electric field concentration suppression in the electric field relaxation region 32 (described later). 6 and 7), for example, in this embodiment, it is set to 1×10 13 cm −2 .
　図２Ｃで説明した工程により、図３Ａに示すように、電界緩和領域３２では、第２ｐ型層１４の表面から深さ方向に、第２ｐ型層１４、第１ｐ型層１３およびｎ型層１２の表面（第１ｐ型層１３との界面）から所定の深さまで不純物元素注入領域２０が形成される。アイソレーション領域３３では、ｎ型層１２の表面から所定の深さまで不純物元素注入領域２３が形成される。なお、図３Ａの工程においてフォトレジスト膜２５を除去し、窒素ガス雰囲気中で熱処理を行って不純物元素注入領域２０、２３の特性を安定化する。熱処理の条件は、例えば、８００℃、３０分間であるが、これと異なる条件で行ってもよい。さらにＳｉＯ２膜２４をウェットエッチングにより除去する。 2C, in the electric field relaxation region 32, the second p-type layer 14, the first p-type layer 13, and the n-type layer 12 are formed in the depth direction from the surface of the second p-type layer 14, as shown in FIG. 3A. An impurity element implanted region 20 is formed from the surface of (the interface with the first p-type layer 13) to a predetermined depth. In isolation region 33, impurity element implantation region 23 is formed from the surface of n-type layer 12 to a predetermined depth. In the step of FIG. 3A, the photoresist film 25 is removed and heat treatment is performed in a nitrogen gas atmosphere to stabilize the characteristics of the impurity element implanted regions 20 and 23 . The heat treatment conditions are, for example, 800° C. and 30 minutes, but other conditions may be used. Further, the SiO2 film 24 is removed by wet etching.
　なお、図２Ｃの工程において、電界緩和領域３２の第２ｐ型層１４の表面にも、フォトレジスト膜２５を素子領域３１の周囲を囲むように平面視では環状に複数の互いに離隔したフォトレジスト膜を形成して、多段イオン注入を行ってもよい。これにより、不純物元素注入領域が電界緩和領域３２に素子領域３１に近い方から遠い方に素子領域３１の周囲を囲むように、第２ｐ型層１４の表面から深さ方向に、第２ｐ型層１４、第１ｐ型層１３およびｎ型層１２の表面（第１ｐ型層１３との界面）から所定の深さまで複数の不純物元素が注入された部分領域が形成される（後述する実施例１および図８参照。）。 In the process of FIG. 2C, the photoresist film 25 is also formed on the surface of the second p-type layer 14 in the electric field relaxation region 32 so as to surround the element region 31 and to form a plurality of photoresist films separated from each other in an annular shape in plan view. may be formed to perform multistage ion implantation. As a result, the second p-type layer is implanted in the electric field relaxation region 32 in the depth direction from the surface of the second p-type layer 14 so as to surround the device region 31 from the side closer to the device region 31 to the farther side. 14, a partial region is formed by implanting a plurality of impurity elements to a predetermined depth from the surfaces of the first p-type layer 13 and the n-type layer 12 (the interface with the first p-type layer 13) (Example 1 and See Figure 8).
　また、図２Ｃの工程の後に、電界緩和領域３２の不純物元素注入領域２０において、素子領域３１から遠い部分にさらに多段イオン注入法により不純物元素イオンを注入して、素子領域３１に近い不純物元素注入領域２０よりも不純物元素の面密度が高い部分領域を形成してもよい（後述する実施例２および図１０参照。）。 After the step of FIG. 2C, in the impurity element implantation region 20 of the electric field relaxation region 32, impurity element ions are further implanted into a portion distant from the element region 31 by a multistage ion implantation method, and impurity element implantation close to the element region 31 is performed. A partial region having a surface density of impurity elements higher than that of the region 20 may be formed (see Example 2 and FIG. 10, which will be described later).
　次いで、図３Ｂの工程では、素子領域３１および電界緩和領域３２の第２ｐ型層１４の表面、並びにアイソレーション領域３３のｎ型層１２の表面を覆う保護膜１５を形成し、次いで素子領域３１の保護膜１５を開口してアノード電極１６を形成する。具体的には、図３Ａに示した表面全体に保護膜１５、例えばＳｉＯ２膜（厚さ１μｍ）をＣＶＤ法により形成する。次いで、保護膜１５上にフォトリソグラフィー法によりレジストマスクを形成して、アノード電極１６を形成する部分の保護膜１５をウェットエッチングにより除去して第２ｐ型層１４を露出する例えば直径２００μｍの開口部を形成する。次いで、露出した第２ｐ型層１４および保護膜１５を覆う金属層、例えばニッケル（Ｎｉ）膜を蒸着法により厚さ１００ｎｍに形成する。次いで、保護膜１５上の不要な金属層をフォトリソグラフィー法によるレジストマスクを形成してウェットエッチングにより除去してアノード電極１６を形成する。 3B, the protective film 15 is formed to cover the surface of the second p-type layer 14 in the element region 31 and the electric field relaxation region 32 and the surface of the n-type layer 12 in the isolation region 33. An anode electrode 16 is formed by opening the protective film 15 of . Specifically, a protective film 15 such as a SiO 2 film (1 μm thick) is formed on the entire surface shown in FIG. 3A by CVD. Next, a resist mask is formed on the protective film 15 by photolithography, and a portion of the protective film 15 where the anode electrode 16 is to be formed is removed by wet etching to expose the second p-type layer 14, for example, an opening having a diameter of 200 μm. to form Next, a metal layer, such as a nickel (Ni) film, covering the exposed second p-type layer 14 and protective film 15 is formed to a thickness of 100 nm by vapor deposition. Next, an unnecessary metal layer on the protective film 15 is removed by wet etching after forming a resist mask by photolithography to form the anode electrode 16 .
　次いで、図３Ｃの工程では、半導体基板１１の裏面１１ａにカソード電極１８を形成する。具体的には、半導体基板１１の裏面１１ａの酸化膜を除去して洗浄し、裏面１１ａ全体にスパッタ法または蒸着法により金属積層膜、例えば、裏面１１ａの表面からチタン（Ｔｉ）膜、アルミニウム（Ａｌ）膜および窒化チタン（ＴｉＮ）膜を順に堆積してカソード電極１８を形成する。次いで、窒素ガス雰囲気中で熱処理を行ってアノード電極１６およびカソード電極１８のコンタクト抵抗を低減する。熱処理の条件は、例えば、５５０℃、１０分間である。以上により、半導体装置１０が形成される。 Next, in the step of FIG. 3C, the cathode electrode 18 is formed on the back surface 11a of the semiconductor substrate 11. Then, in the step of FIG. Specifically, the oxide film on the rear surface 11a of the semiconductor substrate 11 is removed and washed, and the entire rear surface 11a is coated with a metal laminate film, for example, a titanium (Ti) film, aluminum (Ti) film, aluminum (Ti) film, etc., from the surface of the rear surface 11a by a sputtering method or a vapor deposition method. Al) film and titanium nitride (TiN) film are sequentially deposited to form the cathode electrode 18 . Next, heat treatment is performed in a nitrogen gas atmosphere to reduce the contact resistance of the anode electrode 16 and the cathode electrode 18 . The heat treatment conditions are, for example, 550° C. and 10 minutes. As described above, the semiconductor device 10 is formed.
　本実施形態の半導体装置の製造方法によれば、エピタキシャル成長した第１ｐ型層１３および第２ｐ型層１４について素子領域３１において素子性能に最適なアクセプタ濃度を設定することができるとともに、素子領域３１の周囲を囲む電界緩和領域３２において、第１ｐ型層１３および第２ｐ型層１４にアクセプタの一部を不活性化させる不純物元素イオンを注入して高抵抗化した不純物元素注入領域２０を形成して、電界が局所的に集中する電界集中点が形成されることを抑制して、半導体装置１０の耐圧を向上することができる。さらに、電界緩和領域３２の周囲を囲むアイソレーション領域３３において、第１ｐ型層１３および第２ｐ型層１４を除去してｎ型層１２を露出したメサ溝２２を形成することで、電界集中をさらに抑制して半導体装置１０の耐圧をさらに向上することができる。 According to the manufacturing method of the semiconductor device of the present embodiment, the acceptor concentration optimum for the device performance can be set in the device region 31 for the epitaxially grown first p-type layer 13 and the second p-type layer 14, and the device region 31 In the electric field relaxation region 32 surrounding the periphery, impurity element ions are implanted into the first p-type layer 13 and the second p-type layer 14 to inactivate a part of the acceptors to form the impurity element implanted region 20 having a high resistance. , the formation of an electric field concentration point where the electric field is locally concentrated can be suppressed, and the withstand voltage of the semiconductor device 10 can be improved. Furthermore, in the isolation region 33 surrounding the electric field relaxation region 32, the first p-type layer 13 and the second p-type layer 14 are removed to form the mesa groove 22 exposing the n-type layer 12, thereby reducing electric field concentration. By further suppressing, the withstand voltage of the semiconductor device 10 can be further improved.
　図４は、一実施形態に係る半導体装置の多段イオン注入の条件を示す図であり、図２Ｃの工程における多段イオン注入の条件の一例を示す。ホウ素イオンを例に、注入エネルギーおよびドーズ量を変えて多段でホウ素イオンを注入することで、窒化ガリウム半導体基板の深さ方向の不純物元素の面密度がほぼ一様になる条件を見いだした。
具体的には、図２Ｃに示したように、窒化ガリウム半導体基板の表面に保護用のＳｉＯ２膜（厚さ５０ｎｍ）を形成し、その上に厚さ３μｍのレジストマスクを形成した。図４を参照するに、７段でイオン注入を行った。最初に最大の注入エネルギーである４００ｋｅＶで３．２×１０１２ｃｍ－２を注入し、順次注入エネルギーを減少させて、総ドーズ量を１．０×１０１３ｃｍ－２とした。イオン注入後にＳｉＯ２膜を堆積したまま窒素ガス雰囲気中で８００℃、３０分の熱処理を行った。二次イオン質量分析法（ＳＩＭＳ分析法）によって深さ方向のホウ素のプロファイルを取得したところ、深さ０．７μｍまでホウ素は一様な濃度で分布し、それよりも深いところでは、深さとともに次第に濃度が減少し、少なくとも１．５μｍの深さまで分布していることが分かった。この結果、ホウ素は、第２ｐ型層１４の表面から深さ方向に、第２ｐ型層１４および第１ｐ型層１３の全体分布し、ｎ型層１２まで達していることが確認できた。 FIG. 4 is a diagram showing conditions for multistage ion implantation of a semiconductor device according to one embodiment, and shows an example of conditions for multistage ion implantation in the process of FIG. 2C. Taking boron ions as an example, the inventors have found conditions under which the surface density of impurity elements in the depth direction of a gallium nitride semiconductor substrate becomes substantially uniform by implanting boron ions in multiple stages while changing the implantation energy and dose.
Specifically, as shown in FIG. 2C, a protective SiO 2 film (50 nm thick) was formed on the surface of the gallium nitride semiconductor substrate, and a 3 μm thick resist mask was formed thereon. Referring to FIG. 4, ion implantation was performed in seven stages. First, 3.2×10 12 cm −2 was implanted at the maximum implantation energy of 400 keV, and the implantation energy was successively decreased to give a total dose of 1.0×10 13 cm −2 . After the ion implantation, heat treatment was performed at 800° C. for 30 minutes in a nitrogen gas atmosphere while the SiO 2 film was deposited. When a profile of boron in the depth direction was obtained by secondary ion mass spectrometry (SIMS analysis), boron was distributed with a uniform concentration up to a depth of 0.7 μm, and at deeper points, It was found that the concentration gradually decreased and was distributed to a depth of at least 1.5 μm. As a result, it was confirmed that boron was distributed throughout the second p-type layer 14 and the first p-type layer 13 in the depth direction from the surface of the second p-type layer 14 and reached the n-type layer 12 .
　図５は、一実施形態に係る半導体装置の耐圧と注入したホウ素の総ドーズ量との関係を示す図であり、本実施形態にかかる半導体装置１０のｐｎダイオードの耐圧を総ドーズ量に対して計測した。 FIG. 5 is a diagram showing the relationship between the breakdown voltage of the semiconductor device according to the embodiment and the total dose of implanted boron. Measured.
　図５を参照するに、ホウ素イオンの総ドーズ量を３×１０１２ｃｍ－２～３×１０１３ｃｍ－２としたｐｎダイオードは、最大の耐圧が１３００Ｖとなり、比較例としてホウ素イオンを注入していない場合と比較して耐圧が１００Ｖ～６００Ｖも高いことが分かった。これにより、半導体装置１０に不純物元素イオンを注入して不純物元素注入領域２０を形成することによる耐圧向上効果を確認できた。 Referring to FIG. 5, a pn diode with a total boron ion dose of 3×10 12 cm −2 to 3×10 13 cm −2 has a maximum withstand voltage of 1300 V, and boron ions are implanted as a comparative example. It was found that the breakdown voltage is 100 V to 600 V higher than that in the case without the capacitor. As a result, the effect of improving the breakdown voltage by implanting the impurity element ions into the semiconductor device 10 to form the impurity element implanted region 20 has been confirmed.
　図６は、一実施形態に係る半導体装置の耐圧をシミュレーションによって求めた図である。図１に示したメサ構造の半導体装置１０の層構成を単純化し、ｎ型層を厚さ１０μｍ、ドナー濃度０．８×１０１６ｃｍ－３に形成し、第１ｐ型層１３および第２ｐ型層１４を厚さ１μｍ、アクセプタ濃度２×１０１８ｃｍ－３の１つのｐ型層として形成し、電界緩和領域３２の不純物元素注入領域２０において、ホウ素イオンの多段イオン注入によりアクセプタ面密度がＮＡｃｍ－２となったとして０．５×１０１３ｃｍ－２～５×１０１３ｃｍ－２の範囲で耐圧を求めるシミュレーションを行った。シミュレーションでは、上記構造に対応する２次元モデル構造に対してポアソン方程式を数値的に解き、文献（ＩＥＤＭ、Ｔ．Ｍａｅｄａ　　　ｅｔ．ａｌ、Ｔｅｃｈ．Ｄｉｇ．２０１９、４．２．１ページ～４．２．４ページ）のインパクトイオン化係数を適用して耐圧を計算した。 FIG. 6 is a diagram obtained by simulation of the breakdown voltage of the semiconductor device according to the embodiment. The layer structure of the semiconductor device 10 having the mesa structure shown in FIG. The layer 14 is formed as one p-type layer having a thickness of 1 μm and an acceptor concentration of 2×10 18 cm −3 . Assuming A cm −2 , a simulation was performed to find the withstand voltage in the range of 0.5×10 13 cm −2 to 5×10 13 cm −2 . In the simulation, the Poisson equation was numerically solved for the two-dimensional model structure corresponding to the above structure, and the literature (IEDM, T. Maeda et. al, Tech. Dig. 2019, 4.2.1 pages to 4.2 .4 page) was applied to calculate the breakdown voltage.
　図６を参照するに、アクセプタ面密度が０．５×１０１３ｃｍ－２から増加するにつれて耐圧が９００Ｖから増加し、１．０×１０１３ｃｍ－２において耐圧が１３２０Ｖの最大値を示した。さらにアクセプタ面密度を増加すると、次第に耐圧が低下しほぼ一定の耐圧を示した。この耐圧のアクセプタ面密度との関係は、図５に示した計測結果に対応している。シミュレーションによる耐圧の最大値は、図５において示した計測結果の耐圧１３２０Ｖに近い。耐圧の最大値を示したアクセプタ面密度（１．０×１０１３ｃｍ－２）は、ｎ型層のドナー面密度０．８×１０１３ｃｍ－２に近く、不純物元素注入領域のアクセプタ面密度がｎ型層のドナー面密度にほぼ同一となる条件であることが分かった。 Referring to FIG. 6, as the acceptor areal density increases from 0.5×10 13 cm −2 , the breakdown voltage increases from 900 V, and at 1.0×10 13 cm −2 the breakdown voltage shows a maximum value of 1320 V. . When the acceptor areal density was further increased, the breakdown voltage gradually decreased and remained almost constant. The relationship between this breakdown voltage and the acceptor surface density corresponds to the measurement results shown in FIG. The maximum withstand voltage obtained by the simulation is close to the withstand voltage of 1320 V, which is the measurement result shown in FIG. The acceptor areal density (1.0×10 13 cm −2 ) that showed the maximum breakdown voltage is close to the donor areal density of 0.8×10 13 cm −2 in the n-type layer, and is the acceptor areal density of the impurity element-implanted region. is the condition under which the areal density of donors in the n-type layer is almost the same.
　図７Ａ～Ｂは、半導体装置のアバランシェ発生時の等ポテンシャル面の分布図であり、図７Ａは、図６に示したアクセプタ面密度が１．０×１０１３ｃｍ－２の半導体装置が耐圧１３２０Ｖを示した際の等ポテンシャル面の分布図であり、図７Ｂはホウ素イオンを注入していない例、すなわちホウ素が電界緩和領域３２に注入されてない例として耐圧７５０Ｖを示した際の等ポテンシャル面の分布図である。図７Ａ～Ｂは、シミュレーションによって求めたものである。カソード電極１８とアノード電極１６との印加電圧が耐圧に達して、アバランシェ電流が流れ始める瞬間のポテンシャル分布を示している。横軸は、ｐｎダイオードの中心からの距離Ｘ（μｍ）、縦軸は第２ｐ型層１４の表面からの深さである。なお、図示の便宜のため、第１ｐ型層１３と第２ｐ型層１４とが１つの層に示されており、半導体基板１１とｎ型層１２とが１つの層として示されている。図７Ａ～Ｂの等ポテンシャル面は、７０Ｖごとに示している。 7A and 7B are distribution diagrams of equipotential planes when avalanche occurs in a semiconductor device, and FIG. 7A shows that the semiconductor device shown in FIG. FIG. 7B is a distribution diagram of the equipotential surfaces when showing a breakdown voltage of 750 V as an example in which boron ions are not implanted, that is, an example in which boron is not implanted into the electric field relaxation region 32. It is a distribution map of. 7A and 7B are obtained by simulation. It shows the potential distribution at the moment when the voltage applied to the cathode electrode 18 and the anode electrode 16 reaches the breakdown voltage and the avalanche current starts to flow. The horizontal axis is the distance X (μm) from the center of the pn diode, and the vertical axis is the depth from the surface of the second p-type layer 14 . For convenience of illustration, the first p-type layer 13 and the second p-type layer 14 are shown as one layer, and the semiconductor substrate 11 and the n-type layer 12 are shown as one layer. The equipotential surfaces in FIGS. 7A-B are shown every 70V.
　図７Ａを参照するに、アクセプタ面密度が１．０×１０１３ｃｍ－２の半導体装置は、電界緩和領域３２のｐ型層の表面において等ポテンシャル面がアイソレーション領域３３の方向に等間隔で広がり、電界集中が抑制されていることが分かる。この等ポテンシャル面の分布は、電界緩和領域３２において総ドーズ量が最適化され、耐圧が最大化した場合の分布に近いと考えられる。 Referring to FIG. 7A, in a semiconductor device having an acceptor areal density of 1.0×10 13 cm −2 , equipotential planes are equally spaced in the direction of the isolation region 33 on the surface of the p-type layer of the electric field relaxation region 32 . It can be seen that it spreads and electric field concentration is suppressed. The distribution of this equipotential surface is considered to be close to the distribution when the total dose amount is optimized in the electric field relaxation region 32 and the withstand voltage is maximized.
　一方、図７Ｂを参照するに、ホウ素イオンが電界緩和領域３２に注入されてない例では、電界緩和領域３２のｐ型層の表面において等ポテンシャル面が現れず、メサエッジ付近で等ポテンシャル面が狭まり、電界集中が発生していることが分かる。このため耐圧が７５０Ｖに低下していると考えられる。 On the other hand, referring to FIG. 7B, in the example in which boron ions are not implanted into the electric field relaxation region 32, the equipotential surface does not appear on the surface of the p-type layer of the electric field relaxation region 32, and the equipotential surface narrows near the mesa edge. , it can be seen that electric field concentration occurs. Therefore, it is considered that the breakdown voltage is lowered to 750V.
　以上の図６および図７Ａ～Ｂのシミュレーションの結果によれば、電界緩和領域３２のｐ型層のホウ素注入により、ｐ型層のアクセプタ濃度（およびアクセプタ面密度）が低減され、ｐｎ終端構造の耐圧が向上するというメカニズムが確認できた。 According to the simulation results of FIGS. 6 and 7A to 7B described above, boron implantation into the p-type layer of the electric field relaxation region 32 reduces the acceptor concentration (and acceptor surface density) of the p-type layer, resulting in a pn termination structure. A mechanism for improving the withstand voltage was confirmed.
　実施例１の半導体装置は、縦型ｐｎダイオード素子であり、具体的には図１に示した実施形態に係る半導体装置とは電界緩和領域における不純物元素注入領域の構造が異なる。 The semiconductor device of Example 1 is a vertical pn diode element, and specifically differs from the semiconductor device according to the embodiment shown in FIG. 1 in the structure of the impurity element implantation region in the electric field relaxation region.
　図８Ａ～Ｂは、実施例１の半導体装置の構成を示す図であり、図８Ａは断面図、図８Ｂは平面図である。図８Ｂでは保護膜の下側にある窒化ガリウムの半導体層の不純物元素注入領域の範囲を破線で示している。図８Ａおよび図８Ｂを参照するに、実施例１の半導体装置は、素子領域３１にはｐｎダイオードが形成されており、平面視したときに素子領域３１の中央部には第２ｐ型層１４にオーミックコンタクトする直径２００μｍのアノード電極１６が形成されている。半導体基板１１の裏面には、カソード電極１８が形成されている。半導体基板１１は窒化ガリウム基板であり、表面側がＧａ（０００１）面、厚さ３５０μｍ、Ｓｉがドープされたｎ＋結晶である。Ｓｉ濃度は１×１０１８ｃｍ－３であるがそれよりも高くともよい。 8A and 8B are diagrams showing the configuration of the semiconductor device of Example 1, where FIG. 8A is a cross-sectional view and FIG. 8B is a plan view. In FIG. 8B, the range of the impurity element implantation region of the gallium nitride semiconductor layer under the protective film is indicated by a dashed line. 8A and 8B, in the semiconductor device of Example 1, a pn diode is formed in the element region 31, and the second p-type layer 14 is formed in the central portion of the element region 31 when viewed from above. An anode electrode 16 with a diameter of 200 μm for ohmic contact is formed. A cathode electrode 18 is formed on the back surface of the semiconductor substrate 11 . The semiconductor substrate 11 is a gallium nitride substrate having a Ga (0001) surface on the surface side, a thickness of 350 μm, and an n+ crystal doped with Si. The Si concentration is 1×10 18 cm −3 but may be higher.
　半導体基板１１の上に、ＭＯＣＶＤ法によりエピタキシャル成長により形成された窒化ガリウムのｎ型層１２と、第１ｐ型層１３と、第２ｐ型層１４とがこの順に形成されている。ｎ型層１２は、厚さ１０μｍで、Ｓｉがドープされている。Ｓｉ濃度は、１．２×１０１６ｃｍ－３である。このＳｉ濃度では１３００Ｖを超える耐圧が得られる。ｎ型層１２の厚さを１０μｍ以上、かつＳｉ濃度を１．２×１０１６ｃｍ－３よりも低く設定することで、これよりも高い耐圧が得られる。 An n-type layer 12 of gallium nitride epitaxially grown by MOCVD, a first p-type layer 13 and a second p-type layer 14 are formed in this order on a semiconductor substrate 11 . The n-type layer 12 has a thickness of 10 μm and is doped with Si. The Si concentration is 1.2×10 16 cm -3 . With this Si concentration, a breakdown voltage exceeding 1300 V can be obtained. By setting the thickness of the n-type layer 12 to 10 μm or more and setting the Si concentration lower than 1.2×10 16 cm −3 , a higher withstand voltage can be obtained.
　第１ｐ型層１３は、厚さ１μｍで、Ｍｇがドープされている。Ｍｇ濃度は、１．５×１０１８ｃｍ－３である。なお、この厚さおよびＭｇ濃度でも機能的に有効であるが、Ｍｇ濃度を十分制御して第１ｐ型層１３をエピタキシャル成長が可能である場合は、Ｍｇ濃度がより低濃度であること、具体的には１×１０１８ｃｍ－３以下に設定することが電界緩和領域３２の電界緩和が顕著になる点で好ましい。 The first p-type layer 13 has a thickness of 1 μm and is doped with Mg. The Mg concentration is 1.5×10 18 cm -3 . Although this thickness and Mg concentration are functionally effective, if the Mg concentration is sufficiently controlled and epitaxial growth of the first p-type layer 13 is possible, the Mg concentration should be lower. is preferably set to 1×10 18 cm −3 or less, since the electric field relaxation of the electric field relaxation region 32 becomes remarkable.
　第２ｐ型層１４は、厚さ５０ｎｍで、Ｍｇがドープされている。Ｍｇ濃度は、１×１０２０ｃｍ－３である。なお、この厚さおよびＭｇ濃度以外でも、アノード電極１６とのオーミック抵抗が低くなる条件であれば、適用可能である。 The second p-type layer 14 has a thickness of 50 nm and is doped with Mg. The Mg concentration is 1×10 20 cm -3 . It should be noted that conditions other than this thickness and Mg concentration can be applied as long as the ohmic resistance with the anode electrode 16 is low.
　アノード電極１６は、第２ｐ型層１４上にスパッタ法によりＮｉ膜およびＡｕ膜を積層した積層膜である。これにより、アノード電極１６は、第２ｐ型層１４にオーミックコンタクト可能である。カソード電極１８は、窒化ガリウムの半導体基板１１の裏面にＴｉ膜およびＡｌ膜を積層した積層膜である。 The anode electrode 16 is a laminated film obtained by laminating a Ni film and an Au film on the second p-type layer 14 by sputtering. Thereby, the anode electrode 16 can make ohmic contact with the second p-type layer 14 . The cathode electrode 18 is a laminated film in which a Ti film and an Al film are laminated on the rear surface of the semiconductor substrate 11 made of gallium nitride.
　実施例１の素子領域３１を囲む電界緩和領域３２には、少なくとも第２ｐ型層１４の表面から深さ方向に第２ｐ型層１４および第１ｐ型層１３内にホウ素イオンが注入され、そのホウ素の濃度が異なる素子領域３１に近い内側注入領域４１と素子領域から遠い外側注入領域４２が形成されている。ホウ素の全ドーズ量は内側注入領域４１よりも外側注入領域４２が大きく、それぞれ、３×１０１２ｃｍ－２、１×１０１３ｃｍ－２に設定されている。内側注入領域４１および外側注入領域４２のホウ素濃度の深さ方向の分布は、詳細には、第２ｐ型層１４の表面から第１ｐ型層１３の底面（第１ｐ型層１３とｎ型層１２との界面）に亘ってほぼ一様であり、その界面からｎ型層１２内にかけて急激に減少する。 Boron ions are implanted into the second p-type layer 14 and the first p-type layer 13 in the depth direction from at least the surface of the second p-type layer 14 into the electric field relaxation region 32 surrounding the element region 31 of the first embodiment. An inner injection region 41 close to the element region 31 and an outer injection region 42 far from the element region are formed. The total boron dose is larger in the outer implanted region 42 than in the inner implanted region 41 and is set to 3×10 12 cm −2 and 1×10 13 cm −2 respectively. More specifically, the distribution of the boron concentration in the inner implantation region 41 and the outer implantation region 42 in the depth direction varies from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (the first p-type layer 13 and the n-type layer 12). ), and sharply decreases from the interface to the inside of the n-type layer 12 .
　図９は、実施例１の半導体装置の多段イオン注入の条件を示す図である。図９を図８と合わせて参照するに、ホウ素イオンの多段注入は、図２Ｃで説明した手法および条件で行うが、１回目の多段イオン注入により、内側注入領域４１、外側注入領域４２およびアイソレーション領域３３の不純物元素注入領域４３に全ドーズ量が３×１０１２ｃｍ－２となるようにホウ素イオンを注入し、さらに、新たに、素子領域３１および内側注入領域４１の表面を厚さ３μｍのレジスト膜で覆って、２回目の多段イオン注入により、外側注入領域４２およびアイソレーション領域３３の不純物元素注入領域４３に全ドーズ量が７×１０１２ｃｍ－２になるようにホウ素イオンを注入する。同領域への１回目と２回目のイオン注入を合計した最終的な全ドーズ量は１×１０１３ｃｍ－２になる。 FIG. 9 is a diagram showing the conditions of multistage ion implantation for the semiconductor device of Example 1. FIG. Referring to FIG. 9 together with FIG. 8, the multistep implantation of boron ions is performed by the method and conditions described in FIG. 2C. Boron ions are implanted into the impurity element implanted region 43 of the isolation region 33 so that the total dose is 3×10 12 cm −2 , and the surfaces of the element region 31 and inner implanted region 41 are newly annealed to a thickness of 3 μm. Then, boron ions are implanted into the outer implantation region 42 and the impurity element implantation region 43 of the isolation region 33 so that the total dose is 7.times.10.sup.12 cm.sup. -2 . do. The final total dose of the first and second ion implantations in the same region is 1×10 13 cm −2 .
　内側注入領域４１および外側注入領域４２の主面の面内方向の幅はそれぞれ１０μｍである。内側注入領域４１および外側注入領域４２のこの幅は、長い方が好ましく、１０μｍ以上５０μｍ以下であることが、電界緩和をより確実に行える点で好ましい。 The in-plane widths of the main surfaces of the inner injection region 41 and the outer injection region 42 are each 10 μm. The widths of the inner injection region 41 and the outer injection region 42 are preferably longer, and preferably 10 μm or more and 50 μm or less in order to more reliably relax the electric field.
　アイソレーション領域３３では、第１ｐ型層１３および第２ｐ型層１４の全体が除去されたメサ溝２２が形成されており、メサ溝２２の表面にはｎ型層１２が露出している。ｎ型層１２にはホウ素イオンが注入され、不純物元素注入領域４３が形成されている。不純物元素注入領域４３のホウ素濃度は、７×１０１２ｃｍ－２である。メサ溝２２は、深さ２．５μｍである。メサ溝２２の深さは、第１ｐ型層１３および第２ｐ型層１４が完全に除去される深さであればよく、より深い方が電界緩和の点で好ましい。メサ溝２２の幅は、２０μｍであるが、５０μｍ以上であることが電界緩和の点で好ましい。 In isolation region 33 , mesa groove 22 is formed by removing entire first p-type layer 13 and second p-type layer 14 , and n-type layer 12 is exposed on the surface of mesa groove 22 . Boron ions are implanted into the n-type layer 12 to form an impurity element implanted region 43 . The impurity element-implanted region 43 has a boron concentration of 7×10 12 cm −2 . The mesa groove 22 has a depth of 2.5 μm. The depth of the mesa groove 22 is sufficient as long as the first p-type layer 13 and the second p-type layer 14 are completely removed, and a deeper one is preferable from the viewpoint of electric field relaxation. The width of the mesa groove 22 is 20 μm, but preferably 50 μm or more from the viewpoint of electric field relaxation.
　保護膜１５は、窒化ガリウムの結晶層の表面を覆っている。保護膜１５は、具体的には、アノード電極１６以外の第２ｐ型層１４の表面およびｎ型層１２の表面を覆っている。保護膜１５は、ＣＶＤ法により形成された厚さ１μｍのＳｉＯ２膜である。 The protective film 15 covers the surface of the gallium nitride crystal layer. Protective film 15 specifically covers the surface of second p-type layer 14 and the surface of n-type layer 12 other than anode electrode 16 . The protective film 15 is a 1 μm thick SiO 2 film formed by CVD.
　図８では、平面視したメサ構造の形状を円形としたが、長円形、六角形でもよく、任意の形状を適用することができる。 In FIG. 8, the shape of the mesa structure in plan view is circular, but it may be oval or hexagonal, and any shape can be applied.
　実施例２の半導体装置は、縦型ｐｎダイオード素子であり、実施例１の縦型ｐｎダイオード素子とは終端構造が異なり、具体的には、電界緩和領域における不純物元素注入領域の構造が異なり、それ以外は実施例１と同様である。 The semiconductor device of Example 2 is a vertical pn diode element, and differs from the vertical pn diode element of Example 1 in the termination structure. Other than that, it is the same as the first embodiment.
　図１０は、実施例２の半導体装置の構成を示す断面図である。図１０を参照するに、実施例２の半導体装置５０は、電界緩和領域３２において、ホウ素が注入された不純物元素注入領域５１～５３が、素子領域３１を囲むように形成されている。半導体装置５０は、
平面視した不純物元素注入領域５１～５３が環状に形成されている。 FIG. 10 is a cross-sectional view showing the configuration of the semiconductor device of Example 2. FIG. Referring to FIG. 10, in a semiconductor device 50 of Example 2, impurity element implantation regions 51 to 53 implanted with boron are formed so as to surround an element region 31 in an electric field relaxation region 32 . The semiconductor device 50 is
Impurity element-implanted regions 51 to 53 in a plan view are formed in an annular shape.
　不純物元素注入領域５１～５３は、少なくとも第２ｐ型層１４の表面から深さ方向に第２ｐ型層１４および第１ｐ型層１３内に多段イオン注入によりホウ素イオンが注入されている。不純物元素注入領域５１～５３は、それぞれ、全ドーズ量が１×１０１３ｃｍ－２に設定されている。不純物元素注入領域５１～５３のホウ素濃度の深さ方向の分布は、詳細には、第２ｐ型層１４の表面から第１ｐ型層１３の底面（第１ｐ型層１３とｎ型層１２との界面）に亘ってほぼ一様であり、その界面からｎ型層１２内にかけて急激に減少する。 Boron ions are implanted into the second p-type layer 14 and the first p-type layer 13 in the depth direction from at least the surface of the second p-type layer 14 in the impurity element implantation regions 51 to 53 by multistage ion implantation. The impurity element-implanted regions 51 to 53 are each set to have a total dose of 1×10 13 cm −2 . More specifically, the distribution of the boron concentration in the depth direction of the impurity element-implanted regions 51 to 53 is from the surface of the second p-type layer 14 to the bottom surface of the first p-type layer 13 (between the first p-type layer 13 and the n-type layer 12). interface), and sharply decreases from the interface to the inside of the n-type layer 12 .
　不純物元素注入領域５１～５３の主面の面内方向の幅は、それぞれ１０μｍである。不純物元素注入領域５１～５３のこの幅は、５μｍ以上５０μｍ以下であることが、電界緩和をより確実に行える点で好ましい。不純物元素注入領域５１～５３のこの幅は、互いに異なってもよい。電界緩和領域３２に素子領域３１を多重に囲むように不純物元素注入領域５１～５３を設けることで、製造プロセスに起因する半導体装置５０の形状異常による局所的な電界集中発生のリスクを低減または回避できるという効果を有する。実施例２では３個の不純物元素注入領域５１～５３を設けたが、２個でもよく、４個以上でもよい。 The in-plane width of the main surface of the impurity element-implanted regions 51 to 53 is 10 μm. The width of the impurity element-implanted regions 51 to 53 is preferably 5 μm or more and 50 μm or less in order to more reliably relax the electric field. The widths of the impurity element-implanted regions 51 to 53 may differ from each other. By providing the impurity element implantation regions 51 to 53 in the electric field relaxation region 32 so as to surround the element region 31 in a multiple manner, the risk of local electric field concentration occurring due to the shape abnormality of the semiconductor device 50 caused by the manufacturing process is reduced or avoided. It has the effect of being able to Although the three impurity element implantation regions 51 to 53 are provided in the second embodiment, the number may be two or four or more.
　実施例３の半導体装置は、縦型ｐｎダイオード素子であり、実施例１、２の縦型ｐｎダイオード素子とは終端構造が異なり、具体的には電界緩和領域における不純物元素注入領域の構造が異なることを除いて実施の形態と同様である。
　図１１は、実施例３の半導体装置の構成を示す断面図である。図１１を参照するに、実施例３の半導体装置８０は、電界緩和領域３２において、ホウ素が注入された不純物元素注入領域８１～８５が、環状に素子領域３１を囲むように形成されている。
　不純物元素注入領域８１～８５は、少なくとも第２ｐ型層１４の表面から深さ方向に第２ｐ型層１４および第１ｐ型層１３内に、実施の形態と同様の条件でホウ素イオンの多段注入が行われている。このイオン注入で用いるレジストマスクには、電界緩和領域３２に対応する領域内に、平行な４列のマスク領域が環状にパターニングされており、互いに離間した不純物元素注入領域８１～８５が形成される。図１１の例では、幅２μｍのマスク領域がメサエッジ２１を基準に６μｍ、５μｍ、４μｍ、３μｍの位置に配置されており、各不純物元素注入領域の幅が、外側から内側にかけて順に小さくなるように設計されている。不純物元素注入領域８１～８５のホウ素イオンのドーズ量は、実施の形態と同様に１×１０１３ｃｍ－２であり、注入領域にはさまれたマスク領域のホウ素イオンのドーズ量はこれよりも小さい。したがって、電界緩和領域３２の外側よりでは、マスク領域がより疎に並ぶため実効的なホウ素濃度が高く、電界緩和領域３２の内側寄りではマスク領域がより密に並ぶため実効的なホウ素濃度が低くなる。電界緩和領域内の位置によるホウ素濃度の大小関係は実施例１と類似しているが、本実施例ではホウ素濃度が徐々に変化する点が異なる。このため、逆バイアス印加時には電界緩和領域３２内での空乏層拡がりが大きくなり、電界緩和がより効果的になる。
　すなわち、本実施例の半導体装置では、複数の部分領域の幅は、素子領域に近い方から遠い方に向かってより広くなる。
　不純物注入領域８１～８５（複数の部分領域）のうち、最も素子領域から遠い方に位置する不純物注入領域８５（部分領域）の幅は、１．５μｍ～８μｍ、好ましくは１．５μｍ～５μｍ、より好ましくは１．５μｍ～３μｍであってよい。
　最も素子領域から遠い不純物注入領域８５の幅は、最も素子領域に近い不純物注入領域８１の１．５倍～４倍、好ましくは１．５倍～３倍、より好ましくは１．５倍～２倍であってよい。
　不純物注入領域８１～８５の間の間隔は同じであっても、異なっていてもよい。複数の間隔の一部が同じで、他の一部が異なっていてもよい。
　次に、図１１に示したメサ構造の半導体装置Ｘの構成を単純化し、実施の形態と同様に耐圧をシミュレーションによって求めた。実施の形態と同様に、ｎ型層を厚さ１０μｍ、ドナー濃度０．８×１０１６ｃｍ－３に形成し、第１ｐ型層１３および第２ｐ型層１４を厚さ１μｍ、アクセプタ濃度２×１０１８ｃｍ－３の１つのｐ型層として形成するとした。ホウ素イオンの多段イオン注入により、不純物元素注入領域のアクセプタ面密度を、０．３×１０１３ｃｍ－２～１．５×１０１３ｃｍ－２の範囲で振り、各不純物元素注入領域にはさまれたマスク領域には、アクセプタ面密度ＮＡ＝２．５×１０１３ｃｍ－２、幅１μｍのｐ型領域が残ると仮定した。図１２は、上記の２次元モデル構造に対して計算した耐圧を、電界緩和領域３２の平均アクセプタ面密度ＮＡを関数としてプロットした結果である。実施の形態の結果を示す点線に対し、本実施例を示す実線では、耐圧の最大値が１３６０Ｖに上昇するとともに、耐圧のＮＡ依存性がより小さくなっている。このことは、第１ｐ型層１３のアクセプタ濃度や厚さ、ホウ素イオン注入のドーズ量が変動しても耐圧が変化しにくくなることを意味しており、製造に適用すればプロセスマージンの拡大が可能である。
　本実施例は、実施の形態に述べたプロセスを変更することなく、マスクレイアウトを変更するだけで実現できるため、実用上のメリットが大きい。本実施では５個の不純物元素注入領域を設け、幅および間隔の数値例を示したが、不純物元素注入領域の数は４個以下でも６個以上でも良く、より好ましくは１０個以上であって良い。幅および間隔についても図１１の例に限らない。 The semiconductor device of Example 3 is a vertical pn diode element, and differs from the vertical pn diode elements of Examples 1 and 2 in the termination structure, specifically, in the structure of the impurity element implanted region in the electric field relaxation region. Except for this, it is the same as the embodiment.
FIG. 11 is a cross-sectional view showing the configuration of the semiconductor device of Example 3. FIG. Referring to FIG. 11, in a semiconductor device 80 of Example 3, impurity element implantation regions 81 to 85 implanted with boron are formed in an annular manner to surround an element region 31 in an electric field relaxation region 32 .
Impurity element-implanted regions 81 to 85 are formed by multistage implantation of boron ions into second p-type layer 14 and first p-type layer 13 at least in the depth direction from the surface of second p-type layer 14 under the same conditions as in the embodiment. It is done. In the resist mask used for this ion implantation, four rows of parallel mask regions are annularly patterned in the region corresponding to the electric field relaxation region 32, forming impurity element implantation regions 81 to 85 separated from each other. . In the example of FIG. 11, mask regions with a width of 2 μm are arranged at positions of 6 μm, 5 μm, 4 μm, and 3 μm with respect to the mesa edge 21, and the width of each impurity element implanted region decreases in order from the outside to the inside. Designed. The dose of boron ions in the impurity element implanted regions 81 to 85 is 1×10 13 cm −2 as in the embodiment, and the dose of boron ions in the mask regions sandwiched between the implanted regions is higher than this. small. Therefore, since the mask regions are more sparsely arranged outside the electric field relaxation region 32, the effective boron concentration is high. Become. Although the magnitude relationship of the boron concentration depending on the position in the electric field relaxation region is similar to that of the first embodiment, the present embodiment differs in that the boron concentration changes gradually. Therefore, when a reverse bias is applied, the depletion layer expands in the electric field relaxation region 32, and electric field relaxation becomes more effective.
That is, in the semiconductor device of this embodiment, the widths of the plurality of partial regions become wider from the side closer to the element region to the side farther from the device region.
Among the impurity-implanted regions 81 to 85 (a plurality of partial regions), the impurity-implanted region 85 (partial region) located farthest from the element region has a width of 1.5 μm to 8 μm, preferably 1.5 μm to 5 μm. More preferably, it may be 1.5 μm to 3 μm.
The width of the impurity-implanted region 85 furthest from the element region is 1.5 to 4 times, preferably 1.5 to 3 times, more preferably 1.5 to 2 times, the width of the impurity-implanted region 81 closest to the element region. It can be double.
The distances between the impurity-implanted regions 81-85 may be the same or different. Some of the intervals may be the same and others may be different.
Next, the configuration of the mesa-structured semiconductor device X shown in FIG. 11 was simplified, and the breakdown voltage was obtained by simulation in the same manner as in the embodiment. As in the embodiment, the n-type layer is formed to a thickness of 10 μm and a donor concentration of 0.8×10 16 cm −3 , and the first p-type layer 13 and the second p-type layer 14 are formed to a thickness of 1 μm and an acceptor concentration of 2×. It was assumed to be formed as one p-type layer of 10 18 cm −3 . By multi-stage ion implantation of boron ions, the acceptor surface density of the impurity element implantation region is swung in the range of 0.3×10 13 cm −2 to 1.5×10 13 cm −2 , and the impurity element implantation regions are interposed. It was assumed that the p-type region with an acceptor areal density of N A =2.5×10 13 cm −2 and a width of 1 μm would remain in the masked region. FIG. 12 shows the result of plotting the breakdown voltage calculated for the above two - dimensional model structure as a function of the average acceptor areal density NA of the electric field relaxation region 32 . In contrast to the dotted line showing the results of the embodiment, the solid line showing the present embodiment has a maximum breakdown voltage of 1360 V and a smaller NA dependence of the breakdown voltage. This means that even if the acceptor concentration and thickness of the first p-type layer 13 and the dose amount of the boron ion implantation fluctuate, the breakdown voltage is less likely to change. It is possible.
Since this embodiment can be realized only by changing the mask layout without changing the processes described in the embodiments, it has a great practical advantage. In this embodiment, five impurity element-implanted regions are provided, and numerical examples of the width and spacing are shown. good. The width and spacing are not limited to the examples in FIG. 11 either.
　実施例４の半導体装置は、縦型ｐｎダイオード素子であり、図１に示した実施形態に係る半導体装置１０の変形例である。半導体装置１０では、アイソレーション領域３３において第１ｐ型層１３および第２ｐ型層１４を除去したメサ溝２２を形成した。実施例４の半導体装置は、メサ溝を形成せずに、第１ｐ型層１３および第２ｐ型層１４を絶縁化したものである。 The semiconductor device of Example 4 is a vertical pn diode element, and is a modification of the semiconductor device 10 according to the embodiment shown in FIG. In semiconductor device 10 , mesa groove 22 is formed by removing first p-type layer 13 and second p-type layer 14 in isolation region 33 . In the semiconductor device of Example 4, the first p-type layer 13 and the second p-type layer 14 are insulated without forming a mesa groove.
　図１３は、実施例４の半導体装置の構成を示す断面図である。図１３を参照するに、実施例４の半導体装置６０は、アイソレーション領域３３では、窒化ガリウムの第２ｐ型層１４の表面から第２ｐ型層１４および第１ｐ型層１３の底部の深さまで不純物元素注入領域６１が形成される。不純物元素注入領域６１では、第２ｐ型層１４の表面から第１ｐ型層１３の底部に亘ってホウ素が分布するように最大注入エネルギーを４００ｋｅＶに設定して多段イオン注入によりホウ素イオンを注入する。これにより、第２ｐ型層１４および第１ｐ型層１３の部分に十分に絶縁性をもたせることができ、ｉ型層の不純物元素注入領域６１を形成することができる。 FIG. 13 is a cross-sectional view showing the configuration of the semiconductor device of Example 4. FIG. Referring to FIG. 13, in the semiconductor device 60 of Example 4, in the isolation region 33, impurities are deposited from the surface of the second p-type layer 14 of gallium nitride to the depths of the bottoms of the second p-type layer 14 and the first p-type layer 13. An element-implanted region 61 is formed. In the impurity element implantation region 61 , boron ions are implanted by multistage ion implantation with the maximum implantation energy set to 400 keV so that boron is distributed from the surface of the second p-type layer 14 to the bottom of the first p-type layer 13 . As a result, the portions of the second p-type layer 14 and the first p-type layer 13 can be sufficiently insulative, and the impurity element implantation region 61 of the i-type layer can be formed.
　電界緩和領域３２の不純物元素注入領域２０は、全ドーズ量が１×１０１３ｃｍ－２に設定されている。一方、アイソレーション領域３３の不純物元素注入領域６１は、全ドーズ量が５×１０１４ｃｍ－２に設定しているが、３×１０１４ｃｍ－２～３×１０１５ｃｍ－２に設定することが、電界集中を抑制できる点で好ましい。 The impurity element implantation region 20 of the electric field relaxation region 32 has a total dose of 1×10 13 cm −2 . On the other hand, the impurity element-implanted region 61 of the isolation region 33 has a total dose of 5×10 14 cm −2 , but is set to 3×10 14 cm −2 to 3×10 15 cm −2 . This is preferable in that electric field concentration can be suppressed.
　実施例４によれば、図２Ｂに示した実施形態に係る半導体装置のメサ溝２２を形成するドライエッチングの工程が不要になる。これにより、メサエッジ２１周辺に生じ易い窒化ガリウムの結晶層の表面部分のダメージを回避することができ、このような製造プロセスに起因する電界集中を抑制することができる。これにより、実施例４の半導体装置６０は、図１に示した実施形態に係る半導体装置１０の電界緩和領域３２の不純物元素注入領域２０の耐圧向上の効果に加え、さらに効果的に耐圧を向上できる。 According to Example 4, the dry etching step for forming the mesa groove 22 of the semiconductor device according to the embodiment shown in FIG. 2B is unnecessary. As a result, damage to the surface portion of the gallium nitride crystal layer that tends to occur around the mesa edge 21 can be avoided, and electric field concentration caused by such a manufacturing process can be suppressed. As a result, the semiconductor device 60 of Example 4 can effectively improve the breakdown voltage in addition to the effect of improving the breakdown voltage of the impurity element implanted region 20 of the electric field relaxation region 32 of the semiconductor device 10 according to the embodiment shown in FIG. can.
　実施例５の半導体装置は、素子領域にトレンチＭＯＳトランジスタを形成し、電界緩和領域およびアイソレーション領域を図１３に示した実施例４と同様に形成した半導体装置である。 The semiconductor device of Example 5 is a semiconductor device in which a trench MOS transistor is formed in the element region, and the electric field relaxation region and the isolation region are formed in the same manner as in Example 4 shown in FIG.
　図１４は、実施例５の半導体装置の構成を示す断面図である。図１４を参照するに、半導体装置７０は、図１に示した実施形態に係る半導体装置１０および実施例１～３と同様に半導体基板１１上に、ＭＯＣＶＤ法によりエピタキシャル成長により形成された窒化ガリウムのｎ型層１２と、第１ｐ型層１３と、第２ｐ型層１４とがこの順に形成されている。 FIG. 14 is a cross-sectional view showing the configuration of the semiconductor device of Example 5. FIG. Referring to FIG. 14, a semiconductor device 70 is a gallium nitride film epitaxially grown on a semiconductor substrate 11 by MOCVD, similar to the semiconductor device 10 according to the embodiment shown in FIG. 1 and Examples 1 to 3. An n-type layer 12, a first p-type layer 13, and a second p-type layer 14 are formed in this order.
　素子領域３１には、ｎ型層１２にドリフト領域および第２ｐ型層１４にボディ領域を形成したｎチャネルＭＯＳトランジスタが形成されている。ｎチャネルＭＯＳトランジスタの閾値が＋３Ｖ以上のノーマリオフ動作をするために、第１ｐ型層１３の不純物濃度は、ゲート絶縁膜の種類や厚さ、窒化ガリウムの結晶面に応じて設計するが、５×１０１７ｃｍ－３以上５×１０１８ｃｍ－３に設定することが好ましい。 In element region 31, an n-channel MOS transistor having a drift region formed in n-type layer 12 and a body region formed in second p-type layer 14 is formed. The impurity concentration of the first p-type layer 13 is designed according to the type and thickness of the gate insulating film and the crystal plane of the gallium nitride in order to perform normally-off operation with the threshold value of the n-channel MOS transistor being +3 V or more. It is preferable to set it to 10 17 cm −3 or more and 5×10 18 cm −3 .
　素子領域３１では、第２ｐ型層１４の表面からｎ型層１２までに達する、互いに平行に配列された複数のストライプ状のトレンチ７１が形成される。各トレンチ７１の幅は２μｍである。トレンチ７１には、側壁および底面にＳｉＯ２膜のゲート絶縁膜７２が形成され、その内側にはゲート電極７３が形成される。ゲート電極７３は、例えばＴｉＮ材料を用いることができる。各ゲート電極７３は、素子全体のゲート電極が等電位になるように、長手方向（図１４では紙面に垂直な方向）の端部が互いに接続されている。 In the element region 31 , a plurality of striped trenches 71 are formed in parallel to each other, reaching from the surface of the second p-type layer 14 to the n-type layer 12 . The width of each trench 71 is 2 μm. A gate insulating film 72 of SiO 2 film is formed on the sidewalls and bottom of the trench 71, and a gate electrode 73 is formed inside thereof. A TiN material, for example, can be used for the gate electrode 73 . The gate electrodes 73 are connected to each other at their ends in the longitudinal direction (the direction perpendicular to the plane of the paper in FIG. 14) so that the gate electrodes of the entire element have the same potential.
　各トレンチ７１の両側の窒化ガリウム層の表面の第２ｐ型層１４および第１ｐ型層１３にはｎ＋窒化ガリウム領域７４が形成されている。ｎ＋窒化ガリウム領域７４は、Ｓｉイオンを注入して活性化熱処理を行って形成されている。ｎ＋窒化ガリウム領域７４の表面にはソース電極７５がオーミックコンタクトしている。ソース電極７５は、Ｔｉ膜とＡｌ膜とをこの順に積層した膜である。 An n+ gallium nitride region 74 is formed in the second p-type layer 14 and the first p-type layer 13 on the surface of the gallium nitride layer on both sides of each trench 71 . The n + gallium nitride region 74 is formed by implanting Si ions and performing activation heat treatment. A source electrode 75 is in ohmic contact with the surface of the n+ gallium nitride region 74 . The source electrode 75 is a film in which a Ti film and an Al film are laminated in this order.
　アノード電極７６は、各トレンチ７１の間で第２ｐ型層１４の表面にオーミックコンタクトしている。アノード電極７６は、ソース電極７５と同電位になるように接触している。アノード電極７６には、Ｎｉ膜が用いられる。ドレイン電極は、半導体基板１１の裏面に形成されたカソード電極１８が兼ねている。 The anode electrode 76 is in ohmic contact with the surface of the second p-type layer 14 between each trench 71 . The anode electrode 76 is in contact with the source electrode 75 so as to have the same potential. A Ni film is used for the anode electrode 76 . A cathode electrode 18 formed on the back surface of the semiconductor substrate 11 also serves as the drain electrode.
　実施例５の半導体装置７０は、アイソレーション領域３３および電界緩和領域３２が実施例４と同様に構成されている。アイソレーション領域３３では、不純物元素注入領域６１では、第２ｐ型層１４の表面から第１ｐ型層１３の底部に亘ってホウ素が分布して、十分にｉ型層となるように最大注入エネルギーを４００ｋｅＶに設定して多段イオン注入によりホウ素イオンを注入する。電界緩和領域３２の不純物元素注入領域２０が実施例４と同様の深さまで形成される。不純物元素注入領域２０の全ドーズ量が１×１０１３ｃｍ－２に設定されている。アイソレーション領域３３の不純物元素注入領域６１は、全ドーズ量が５×１０１４ｃｍ－２に設定されているが実施例４と同様に、３×１０１４ｃｍ－２～３×１０１５ｃｍ－２に設定することが、電界集中を抑制できる点で好ましい。 In the semiconductor device 70 of Example 5, the isolation region 33 and the electric field relaxation region 32 are configured similarly to those of Example 4. FIG. In the isolation region 33, in the impurity element implanted region 61, the maximum implantation energy is set so that boron is distributed from the surface of the second p-type layer 14 to the bottom of the first p-type layer 13 to sufficiently form an i-type layer. Boron ions are implanted by multi-step ion implantation with setting to 400 keV. The impurity element implanted region 20 of the electric field relaxing region 32 is formed to the same depth as in the fourth embodiment. The total dose of the impurity element-implanted region 20 is set at 1×10 13 cm −2 . The impurity element-implanted region 61 of the isolation region 33 has a total dose of 5×10 14 cm −2 , but is 3×10 14 cm −2 to 3×10 15 cm − as in the fourth embodiment. Setting to 2 is preferable in that electric field concentration can be suppressed.
　半導体装置７０は、ゲート電極７３に正バイアスを印加するとトレンチＭＯＳトランジスタはオン状態となり、ドレイン電極（カソード電極１８）とソース電極７５との間にオン電流が流れる。ゲート電極７３に０（零）Ｖまたは負バイアスを印加するとトレンチＭＯＳトランジスタはオフ状態となり、ドレイン電極（カソード電極１８）とソース電極７５との間に逆バイアスを印加すると、ｎ型層１２に空乏層が拡がり、耐圧特性を示す。 In the semiconductor device 70 , when a positive bias is applied to the gate electrode 73 , the trench MOS transistor is turned on, and an on-current flows between the drain electrode (cathode electrode 18 ) and the source electrode 75 . When 0 (zero) V or a negative bias is applied to the gate electrode 73, the trench MOS transistor is turned off. When a reverse bias is applied between the drain electrode (cathode electrode 18) and the source electrode 75, the n-type layer 12 is depleted. The layer expands and exhibits withstand voltage characteristics.
　素子領域３１において窒化ガリウムのエピタキャル結晶層に形成するトレンチＭＯＳトランジスタでは、通常、ノーマリオフ設計に必要なｐ型層の不純物濃度はおおよそ１×１０１８ｃｍ－３とされている。一方、電界緩和領域３２では、最適な設計では、ｐ型層の不純物濃度はおおよそ１×１０１７ｃｍ－３であり、素子領域の不純物濃度に対して１／１０の不純物濃度となる。そのため、１回のｐ型層のエピタキシャル成長では、両領域の不純物濃度を両立することは困難であった。実施例５では、電界緩和領域３２の第１ｐ型層１３にホウ素を注入して、素子領域の第１ｐ型層１３よりも不純物濃度を低下させた不純物元素注入領域２０を形成することで、電界集中を抑制または回避でき、電界設計を最適化できる。 In a trench MOS transistor formed in an epitaxial crystal layer of gallium nitride in the device region 31, the impurity concentration of the p-type layer required for normally-off design is generally set to approximately 1×10 18 cm −3 . On the other hand, in the electric field relaxation region 32, the impurity concentration of the p-type layer is approximately 1×10 17 cm −3 in the optimum design, which is 1/10 of the impurity concentration of the element region. Therefore, it has been difficult to achieve both impurity concentrations in both regions by epitaxial growth of the p-type layer once. In Example 5, by implanting boron into the first p-type layer 13 of the electric field relaxation region 32 to form the impurity element implantation region 20 having an impurity concentration lower than that of the first p-type layer 13 of the element region, the electric field is reduced. Concentration can be suppressed or avoided, and the electric field design can be optimized.
　実施例５では、素子領域３１にトレンチＭＯＳトランジスタを形成したが、これに限定されない。例えば、プレーナＭＯＳトランジスタまたは高電子移動度トランジスタ（ＨＥＭＴ）を形成してもよい。 Although the trench MOS transistor is formed in the element region 31 in the fifth embodiment, it is not limited to this. For example, a planar MOS transistor or a high electron mobility transistor (HEMT) may be formed.
　以上、本発明の好ましい実施形態について詳述したが、本発明は係る特定の実施形態に限定されるものではなく、請求の範囲に記載された本発明の範囲内において、種々の変形・変更が可能である。実施例１～４では、半導体エピタキシャル層として、窒化ガリウム基板上にエピタキシャル成長した窒化ガリウムの結晶層を用いたが、ガリウムの一部をアルミニウム（Ａｌ）またはインジウム（Ｉｎ）に置換したＩＩＩ属窒化物半導体エピタキシャル層としてもよい。また、窒化ガリウム基板に代えて、シリコンカーバイト（ＳｉＣ）基板、サファイア基板等の基板上にエピタキシャル成長したＩＩＩ属窒化物半導体の結晶層を適用してもよい。上述したように、本開示では、特にＩＩＩ属窒化物半導体を用いることが好ましいが、他のワイドバンドギャップ半導体、例えば、ＳｉＣ、Ｇａ２Ｏ３等にも適用可能である。また、実施形態および実施例１～４を互いに組み合わせてもよく、例えば、実施例１および実施例２の電界緩和領域における不純物元素注入領域の構成をそれぞれ、実施例４および４の電界緩和領域における不純物元素注入領域に適用してもよい。 Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It is possible. In Examples 1 to 4, a gallium nitride crystal layer epitaxially grown on a gallium nitride substrate was used as the semiconductor epitaxial layer, but a group III nitride in which part of the gallium was replaced with aluminum (Al) or indium (In) It may be a semiconductor epitaxial layer. Also, instead of the gallium nitride substrate, a crystal layer of a Group III nitride semiconductor epitaxially grown on a substrate such as a silicon carbide (SiC) substrate or a sapphire substrate may be applied. As described above, in the present disclosure, it is particularly preferable to use group III nitride semiconductors, but other wide bandgap semiconductors such as SiC and Ga 2 O 3 are also applicable. Further, the embodiment and Examples 1 to 4 may be combined with each other. It may be applied to the impurity element implanted region.
　半導体装置の耐圧を向上させることができる。 The breakdown voltage of semiconductor devices can be improved.
　１０、４０、５０、６０、７０　　半導体装置
　１１　　半導体基板
　１２　　ｎ型層
　１３　　第１ｐ型層
　１４　　第２ｐ型層
　１６　　アノード電極
　１８　　カソード電極
　２０、５１～５３、６１　　不純物元素注入領域
　２２　　メサ溝
　３１　　素子領域
　３２　　電界緩和領域
　３３　　アイソレーション領域
　４１　　内側注入領域
　４２　外側注入領域 10, 40, 50, 60, 70 semiconductor device 11 semiconductor substrate 12 n-type layer 13 first p-type layer 14 second p-type layer 16 anode electrode 18 cathode electrode 20, 51 to 53, 61 impurity element implantation region 22 mesa groove 31 element Region 32 Electric field relaxation region 33 Isolation region 41 Inner injection region 42 Outer injection region

Claims (17)

  1. 　ｎ型層と、該ｎ型層上の第１のｐ型層と、該第１のｐ型層上のこれよりもアクセプタ濃度が高い第２のｐ型層とを有する素子領域とその周囲を囲む電界緩和領域と備え、
    　前記電界緩和領域において、前記第１のｐ型層および前記第２のｐ型層内に、該第１のｐ型層および該第２のｐ型層内のアクセプタの一部を不活性化させる不純物元素を含む領域を有する、半導体装置。     an element region having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer with a higher acceptor concentration than the first p-type layer and its surroundings; With an enclosing electric field relaxation region,
    in the electric field relaxation region, passivating a portion of the acceptors in the first p-type layer and the second p-type layer in the first p-type layer and the second p-type layer; A semiconductor device having a region containing an impurity element.
  2. 　前記電界緩和領域において、前記不純物元素を含む領域が前記素子領域に近い側から遠い側に不純物元素濃度が互いに異なる複数の部分領域が連続して形成され、前記素子領域に近い部分領域よりも遠い部分領域ほど該不純物元素濃度が大きい、請求項１記載の半導体装置。 In the electric field relaxation region, a plurality of partial regions having different impurity element concentrations are continuously formed from the side containing the impurity element to the side farther from the element region, and are farther from the partial region near the element region. 2. The semiconductor device according to claim 1, wherein said impurity element concentration is higher in said partial region.
  3. 　前記電界緩和領域において、前記不純物元素を含む領域は、前記素子領域に近い方から遠い方に前記素子領域の周囲を囲むように複数の部分領域が互いに離隔して形成されてなる、請求項１記載の半導体装置。 2. The region containing the impurity element in the electric field relaxation region is formed by forming a plurality of partial regions spaced apart from each other so as to surround the periphery of the device region from the side closer to the device region to the side farther from the device region. The semiconductor device described.
  4. 　前記複数の部分領域の幅は、前記素子領域に近い方から遠い方に向かってより広くなる、請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein widths of said plurality of partial regions become wider from a side closer to said element region toward a direction farther from said element region.
  5. 　前記電界緩和領域の周囲を囲むアイソレーション領域をさらに備え、
    　前記アイソレーション領域において、前記ｎ型層に達するメサ構造を有し、該ｎ型層の表面から内部に前記不純物元素を含む領域を有する、請求項１～４のうちいずれか一項記載の半導体装置。     further comprising an isolation region surrounding the electric field relaxation region;
    5. The semiconductor according to claim 1, wherein said isolation region has a mesa structure reaching said n-type layer, and has a region containing said impurity element inside from the surface of said n-type layer. Device.
  6. 　前記電界緩和領域の周囲を囲むアイソレーション領域をさらに備え、
    　前記アイソレーション領域において、前記第１および第２のｐ型層が延在し、該第１および第２のｐ型層は、そのアクセプタが前記不純物元素により不活性化されて絶縁領域を形成してなる、請求項１～４のうちいずれか一項記載の半導体装置。     further comprising an isolation region surrounding the electric field relaxation region;
    The first and second p-type layers extend in the isolation region, and the acceptors of the first and second p-type layers are inactivated by the impurity element to form an insulating region. The semiconductor device according to any one of claims 1 to 4, comprising:
  7. 　当該半導体装置が縦型ダイオードを構成し、
    　前記素子領域において、前記第２のｐ型層上にアノード電極が形成され、前記ｎ型層の裏面側にカソード電極が形成される、請求項１～６のうちいずれか一項記載の半導体装置。     The semiconductor device constitutes a vertical diode,
    7. The semiconductor device according to claim 1, wherein, in said element region, an anode electrode is formed on said second p-type layer, and a cathode electrode is formed on a rear surface side of said n-type layer. .
  8. 　当該半導体装置が縦型ＭＯＳパワートランジスタを構成し、
    　前記素子領域において、ソース電極と、ゲート電極とを有し、前記ｎ型層にドリフト領域、および前記第１のｐ型層にボディ領域を有する、請求項１～６のうちいずれか一項記載の半導体装置。     The semiconductor device constitutes a vertical MOS power transistor,
    7. The device region according to claim 1, wherein said element region has a source electrode and a gate electrode, said n-type layer has a drift region, and said first p-type layer has a body region. semiconductor equipment.
  9. 　前記不純物元素は、ホウ素（Ｂ）、窒素（Ｎ）、酸素（Ｏ）、リン（Ｐ）、亜鉛（Ｚｎ）および鉄（Ｆｅ）のうち、少なくとも１つの元素を含む、請求項１～８のうちいずれか一項記載の半導体装置。 The impurity element of claims 1 to 8, wherein the impurity element includes at least one element selected from boron (B), nitrogen (N), oxygen (O), phosphorus (P), zinc (Zn) and iron (Fe). A semiconductor device according to any one of the above.
  10. 　前記不純物元素は、ホウ素（Ｂ）である、請求項１～８のうちいずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 8, wherein said impurity element is boron (B).
  11. 　半導体基板にｎ型層と、該ｎ型層上の第１のｐ型層と、該第１のｐ型層上のこれよりもアクセプタ濃度が高い第２のｐ型層とをエピタキシャル成長により形成するステップと、
    　前記第１および第２のｐ型層のアクセプタを活性化するステップと、
    素子領域の周囲を囲む電界緩和領域において前記第１および第２のｐ型層に多段イオン注入法により該第１のｐ型層および該第２のｐ型層内の前記アクセプタの一部を不活性化させる不純物元素イオンを注入する注入ステップと、
    　前記素子領域において前記第２のｐ型層の表面に電極を形成するステップと、を含む半導体装置の製造方法。     An n-type layer, a first p-type layer on the n-type layer, and a second p-type layer having a higher acceptor concentration on the first p-type layer are formed by epitaxial growth on a semiconductor substrate. a step;
    activating the acceptors of the first and second p-type layers;
    A portion of the acceptor in the first p-type layer and the second p-type layer is partially made non-conductive in the first and second p-type layers in the electric field relaxation region surrounding the element region by a multistage ion implantation method. an implantation step of implanting impurity element ions to be activated;
    and forming an electrode on the surface of the second p-type layer in the element region.
  12. 　前記注入ステップの後に、前記電界緩和領域内の前記素子領域に近い第１の部分領域よりも遠い側の第２の部分領域において前記第１および第２のｐ型層に多段イオン注入法により不純物元素イオンを注入する他の注入ステップをさらに含む請求項１１記載の半導体装置の製造方法。 After the implanting step, impurities are implanted into the first and second p-type layers in a second partial region farther than the first partial region closer to the element region in the electric field relaxation region by a multistage ion implantation method. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising another implanting step of implanting elemental ions.
  13. 　前記注入ステップにおいて、前記素子領域に近い方から遠い方に前記素子領域の周囲を囲むように複数の部分領域が形成されるように前記不純物元素イオンを注入する、請求項１２記載の半導体装置の製造方法。 13. The semiconductor device according to claim 12, wherein in said implanting step, said impurity element ions are implanted so as to form a plurality of partial regions surrounding said element region from a side closer to said element region to a direction farther from said element region. Production method.
  14. 　前記注入ステップの後に、前記電界緩和領域の周囲を囲む領域の前記第１および第２のｐ型層をエッチングして前記ｎ型層を露出させてアイソレーション領域を形成するステップをさらに含む、請求項１０～１３のうちいずれか一項記載の半導体装置の製造方法。 after said implanting step, further comprising etching said first and second p-type layers in a region surrounding said electric field relief region to expose said n-type layer to form an isolation region. 14. A method of manufacturing a semiconductor device according to any one of items 10 to 13.
  15. 　前記注入ステップの後に、前記電界緩和領域の周囲を囲むアイソレーション領域において、前記第１および第２のｐ型層に多段イオン注入法により前記不純物元素イオンを注入してアクセプタを不活性化するその他の注入ステップをさらに含む請求項１０～１３のうちいずれか一項記載の半導体装置の製造方法。 after the implanting step, implanting the impurity element ions into the first and second p-type layers by a multistage ion implantation method in the isolation region surrounding the electric field relaxation region to deactivate the acceptor; 14. The method of manufacturing a semiconductor device according to claim 10, further comprising an implanting step of .
  16. 　前記不純物元素イオンは、ホウ素（Ｂ）イオン、窒素（Ｎ）イオン、酸素（Ｏ）イオン、リン（Ｐ）イオン、亜鉛（Ｚｎ）イオンおよび鉄（Ｆｅ）イオンのうち、少なくとも１つのイオンを含む、請求項１０～１５のうちいずれか一項記載の半導体装置の製造方法。 The impurity element ions include at least one of boron (B) ions, nitrogen (N) ions, oxygen (O) ions, phosphorus (P) ions, zinc (Zn) ions and iron (Fe) ions. The method of manufacturing a semiconductor device according to any one of claims 10 to 15.
  17. 　前記不純物元素イオンは、ホウ素（Ｂ）イオンである、請求項１０～１５のうちいずれか一項記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 10 to 15, wherein said impurity element ions are boron (B) ions.
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