WO2022224883A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2022224883A1 WO2022224883A1 PCT/JP2022/017660 JP2022017660W WO2022224883A1 WO 2022224883 A1 WO2022224883 A1 WO 2022224883A1 JP 2022017660 W JP2022017660 W JP 2022017660W WO 2022224883 A1 WO2022224883 A1 WO 2022224883A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to semiconductor devices.
- Patent Document 1 WO2016/203545
- a first aspect of the present invention provides a semiconductor device.
- the semiconductor device may comprise a semiconductor substrate having a top surface and a bottom surface and having a drift region of a first conductivity type. Any one of the above semiconductor devices may include a first main terminal provided above the upper surface. Any one of the above semiconductor devices may include a second main terminal provided below the bottom surface. Any one of the semiconductor devices described above may include a control terminal for controlling whether or not current flows between the first main terminal and the second main terminal. Any of the above semiconductor devices may include a buffer region provided between the drift region and the bottom surface and having a higher doping concentration than the drift region.
- the power supply voltage is in the region of 500 V or more. , may have a terminal capacitance peak.
- the CV characteristic may have a valley where the inter-terminal capacitance exhibits a minimum value in a region where the power supply voltage is less than 500V.
- the terminal capacitance when the power supply voltage is 500V may be larger than the minimum value.
- the CV characteristic is obtained when the semiconductor device is set to the ON state and the power supply voltage applied between the first main terminal and the second main terminal is set to the initial voltage. , after the current flowing between the first main terminal and the second main terminal is stabilized, the change in the amount of charge at one of the terminals when the power supply voltage is changed by a displacement voltage smaller than the initial voltage is measured in the semiconductor device. It may be a characteristic obtained by analyzing with a device simulator that simulates a transient change in the charge of , and calculating the inter-terminal capacitance based on the analyzed change in the amount of charge.
- a second-conductivity-type base provided opposite to a control terminal and having an inversion layer channel formed in a channel region facing the control terminal by applying a control voltage to the control terminal A region may be provided.
- the buffer region may have an increasing region in which the doping concentration monotonically increases from the boundary with the drift region toward the bottom surface.
- the slope ⁇ at which the value of the common logarithm of the doping concentration in the increased region increases per cm in the depth direction and the total length ⁇ of the channel region may satisfy the following equations. ⁇ >2 ⁇ 10 3 / ⁇
- the doping concentration distribution in the depth direction of the buffer region may have one or less doping concentration peaks.
- the hydrogen chemical concentration distribution in the depth direction of the buffer region may have more hydrogen concentration peaks than doping concentration peaks.
- a plurality of trench portions may be arranged on the upper surface of the semiconductor substrate in the arrangement direction and provided from the upper surface of the semiconductor substrate to the drift region.
- Any one of the above semiconductor devices may include a mesa portion sandwiched between two trench portions.
- the width of the mesa portion in the arrangement direction may be 20% or less of the depth of the trench portion.
- the width of the mesa portion may be 1.1 ⁇ m or less.
- the doping concentration distribution may be flatter than the hydrogen chemical concentration distribution in the increased region.
- a second aspect of the present invention provides a semiconductor device.
- the semiconductor device may comprise a semiconductor substrate having a top surface and a bottom surface and having a drift region of a first conductivity type. Any one of the semiconductor devices described above may include a first main terminal provided above the upper surface. Any one of the above semiconductor devices may include a second main terminal provided below the bottom surface. Any one of the semiconductor devices described above may include a control terminal for controlling whether or not current flows between the first main terminal and the second main terminal. Any of the above semiconductor devices may include a buffer region provided between the drift region and the bottom surface and having a higher doping concentration than the drift region.
- a second-conductivity-type base is provided facing a control terminal, and an inversion layer channel is formed in a channel region facing the control terminal by applying a control voltage to the control terminal.
- a region may be provided.
- the buffer region may have an increasing region in which the doping concentration monotonically increases from the boundary with the drift region toward the bottom surface.
- the slope ⁇ at which the value of the common logarithm of the doping concentration in the increasing region increases per cm in the depth direction and the total length ⁇ of the channel region may satisfy the following equation. ⁇ >2 ⁇ 10 3 / ⁇
- FIG. 1 is a cross-sectional view showing an example of a semiconductor device 100 to be analyzed;
- FIG. 1B is a diagram showing an example of a perspective view with the AA cross section in FIG. 1A as a side surface.
- FIG. 3 is a diagram for explaining inter-terminal capacitance of the semiconductor device 100;
- 3 is a diagram showing an example of CV characteristics of the semiconductor device 100;
- FIG. 4 is a diagram showing an example of doping concentration distribution and hydrogen chemical concentration distribution in the depth direction of a portion of the drift region 116, the buffer region 118 and the collector region 120; It is a figure explaining inclination (alpha) of doping density
- 4 is a diagram showing a numerical example of an approximate straight line 122;
- FIG. 4 is a diagram showing an example of CV characteristics; It is a figure which shows the example of the doping concentration distribution of the buffer region 118 "with a peak.” It is a figure showing an example of analysis device 10 concerning one embodiment of the present invention.
- 3 is an example of a circuit 300 schematically showing the semiconductor device 100.
- FIG. 4 is a diagram for explaining an operation example of a charge amount analysis unit 14;
- FIG. 4 is a diagram showing an example of a CV characteristic calculated by a capacity calculator 16;
- FIG. 10 is a diagram showing another operation example of the charge amount analysis unit 14;
- 1 is a diagram showing an example of a general CV characteristic;
- 4 is a diagram showing an example of a measurement circuit 405;
- FIG. 17 is a diagram showing an example of CV characteristics calculated based on the measurement circuit 405 shown in FIG. 16;
- FIG. A circuit 420 showing the operation when the semiconductor device 100 is in the ON state in the reference example is shown.
- the analytical value of the terminal capacitance CGC when the semiconductor device 100 is turned on and the analytical value of the terminal capacitance CGC when the semiconductor device 100 is turned off are shown. It is the figure which analyzed each current waveform from the charge amount calculated by the analysis method demonstrated in FIGS. 9-13.
- FIG. 14 is a flow chart showing an example of an analysis method using the analysis device 10 shown in FIGS. 9 to 13;
- FIG. 12 shows an example configuration of a computer 1200 in which aspects of the present invention may be embodied in whole or in part.
- one side in the direction parallel to the depth direction of the semiconductor substrate is called “upper”, and the other side is called “lower”.
- One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface.
- the directions of “up” and “down” are not limited to the direction of gravity or the direction when the semiconductor device is mounted.
- the Cartesian coordinate axes only specify the relative positions of the components and do not limit any particular orientation.
- the Z axis does not limit the height direction with respect to the ground.
- the +Z-axis direction and the ⁇ Z-axis direction are directions opposite to each other.
- the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.
- orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis.
- the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis.
- the Z-axis direction may be referred to as the depth direction.
- a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as a horizontal direction.
- the term "upper surface side of the semiconductor substrate” refers to a region from the center to the upper surface in the depth direction of the semiconductor substrate. When the lower surface side of the semiconductor substrate is referred to, it means a region from the center to the lower surface in the depth direction of the semiconductor substrate.
- the conductivity type of the doping region doped with impurities is described as P-type or N-type.
- impurities may specifically refer to either N-type donors or P-type acceptors, and may also be referred to as dopants.
- doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.
- doping concentration means the concentration of donors or the concentration of acceptors at thermal equilibrium.
- the net doping concentration means the net concentration including charge polarity, where the donor concentration is the positive ion concentration and the acceptor concentration is the negative ion concentration.
- the donor concentration is N D and the acceptor concentration is N A , then the net net doping concentration at any location is N D ⁇ N A.
- a donor has the function of supplying electrons to a semiconductor.
- the acceptor has the function of receiving electrons from the semiconductor.
- Donors and acceptors are not limited to impurities per se. For example, VOH defects in which vacancies (V), oxygen (O), and hydrogen (H) are combined in semiconductors function as donors that supply electrons.
- references herein to P-type or N-type refer to higher doping concentrations than P-type or N-type; references to P-type or N-type refer to higher doping than P-type or N-type. It means that the concentration is low.
- the term P++ type or N++ type in this specification means that the doping concentration is higher than that of the P+ type or N+ type.
- chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation.
- Chemical concentrations can be measured, for example, by secondary ion mass spectroscopy (SIMS).
- the net doping concentrations mentioned above can be measured by the voltage-capacitance method (CV method).
- the carrier density measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration.
- the carrier density measured by the CV method or SR method may be a value in thermal equilibrium.
- the donor concentration is sufficiently higher than the acceptor concentration in the N-type region, the carrier density in the region may be used as the donor concentration.
- the carrier density in that region may be used as the acceptor concentration.
- the peak value may be the concentration of donors, acceptors, or net doping in the region.
- the average value of the concentration of donors, acceptors or net doping in the region may be used as the concentration of donors, acceptors or net doping.
- the carrier density measured by the SR method may be lower than the donor or acceptor concentration.
- the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state.
- a decrease in carrier mobility is caused by scattering of carriers due to disorder of the crystal structure due to lattice defects or the like.
- the donor or acceptor concentration calculated from the carrier density measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
- the donor concentration of phosphorus or arsenic as a donor or the acceptor concentration of boron (boron) as an acceptor in a silicon semiconductor is about 99% of these chemical concentrations.
- the donor concentration of hydrogen serving as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
- FIG. 1A is a cross-sectional view showing an example of a semiconductor device 100 to be analyzed.
- the semiconductor device 100 of this example has a transistor element such as an IGBT (Insulated Gate Bipolar Transistor).
- IGBT Insulated Gate Bipolar Transistor
- the structure of the semiconductor device 100 is not limited to the structure of FIG. 1A.
- the semiconductor device 100 includes a semiconductor substrate 111 , first main terminals 101 , second main terminals 102 and an interlayer insulating film 110 .
- a control terminal 103 is provided inside the semiconductor substrate 111 .
- the control terminal 103 controls whether or not the main current flows between the first main terminal 101 and the second main terminal 102 depending on the applied voltage.
- the control terminal 103 is, for example, the gate or base terminal of a transistor element.
- the first main terminal 101 and the second main terminal 102 are terminals through which the main current flows.
- the first main terminal 101 is, for example, the emitter or source terminal of a transistor element.
- the second main terminal 102 is, for example, the collector or drain terminal of a transistor element.
- the first main terminal 101 in this example is the emitter electrode, and the second main terminal 102 is the collector electrode.
- the first main terminal 101 and the second main terminal 102 are made of metal material such as aluminum.
- the semiconductor substrate 111 is a substrate made of a semiconductor material such as silicon or a compound semiconductor material such as silicon carbide or gallium arsenide.
- the semiconductor substrate 111 may be formed by the MCZ (Magnetic Field Applied CZ) method.
- the semiconductor substrate 111 may be in the shape of a wafer containing a plurality of chips, or may be in the shape of individualized chips.
- Semiconductor substrate 111 has a top surface 113 and a bottom surface 115 .
- the semiconductor device 100 of this example is a vertical device in which a first main terminal 101 is provided above an upper surface 113 and a second main terminal 102 is provided below a lower surface 115 .
- the semiconductor substrate 111 of this example has a gate structure 105 , an emitter region 112 , a base region 114 , a drift region 116 , a buffer region 118 and a collector region 120 .
- Drift region 116 is a region of the first conductivity type (N ⁇ type in this example).
- Emitter region 112 is positioned between drift region 116 and top surface 113 .
- the emitter region 112 is an N+ type contact region that contacts the first main terminal 101 .
- the base region 114 is a contact region of the second conductivity type (P-type in this example) that contacts the first main terminal 101 . At least a portion of base region 114 is disposed between emitter region 112 and drift region 116 .
- the first conductivity type is the N type and the second conductivity type is the P type, but the conductivity types may be reversed.
- the collector region 120 is a P+ type region provided in contact with the bottom surface 115 .
- Collector region 120 is electrically connected to second main terminal 102 .
- Buffer region 118 is an N+ type region provided between collector region 120 and drift region 116 .
- the doping concentration of buffer region 118 is higher than the doping concentration of drift region 116 .
- Buffer region 118 functions as a field stop layer that prevents depletion layer 117 spreading from upper surface 113 side from reaching collector region 120 .
- the gate structure portion 105 is provided at a position facing the base region 114 between the emitter region 112 and the drift region 116 .
- the gate structure portion 105 of this example is of a trench type provided from the upper surface 113 of the semiconductor substrate 111 through the emitter region 112 and the base region 114 to the drift region 116 .
- the gate structure portion 105 of this example is an example of the trench portion.
- the depth from the upper surface 113 to the lower end of the gate structure portion 105 is assumed to be Zt (cm).
- Another example of gate structure 105 may be planar over top surface 113 of semiconductor substrate 111 .
- the gate structure portion 105 is insulated from the first main terminal 101 by the interlayer insulating film 110 .
- the gate structures 105 are repeatedly arranged at predetermined intervals in a predetermined arrangement direction (the X-axis direction in the example of FIG. 1A).
- the gate structure portion 105 has a gate insulating film 104 and a control terminal 103 .
- the control terminal 103 in this example is a gate electrode.
- the control terminal 103 may be made of a conductive material such as polysilicon.
- Control terminal 103 and base region 114 are provided to at least partially face each other.
- the gate insulating film 104 may be a film formed by thermally oxidizing or thermally nitriding the semiconductor substrate 111 .
- the gate insulating film 104 insulates the control terminal 103 and the semiconductor substrate 111 from each other.
- a region of the base region 114 that is in contact with the gate insulating film 104 and arranged to face the control terminal 103 with the gate insulating film 104 interposed therebetween is referred to as a channel region 106 .
- an inversion layer channel having an inverted conductivity type is formed in the channel region 106 of the base region 114 .
- the emitter region 112 and the drift region 116 are connected by an inversion layer channel, and current flows.
- the semiconductor substrate 111 of this example has a mesa portion 160 .
- the mesa portion 160 is a portion sandwiched between the two gate structure portions 105 in the semiconductor substrate 111 .
- the position of the upper end of the mesa portion 160 in this example is the same as the position of the upper end of the gate structure portion 105 (that is, the upper surface 113), and the position of the lower end of the mesa portion 160 is the same as the position of the lower end of the gate structure portion 105. be.
- Wm (cm) be the width of the mesa portion 160 in the arrangement direction of the gate structure portion 105 .
- the width Wm of the mesa portion 160 corresponds to the distance between two adjacent gate structure portions 105 in the X-axis direction.
- the width Wm of the mesa portion 160 may be measured on the top surface 113 of the semiconductor substrate 111 .
- the state in which the inversion layer channel is formed in the channel region 106 of the base region 114 may be referred to as the ON state, and the state in which the inversion layer channel is not formed may be referred to as the OFF state.
- a direction perpendicular to the direction in which current flows in the inversion layer channel (the Z-axis direction in the example of FIG. 1A) and perpendicular to the direction in which the base region 114 and the control terminal 103 face each other (the X-axis direction in the example of FIG. 1A) is referred to as the channel length direction (the Y-axis direction in the example of FIG. 1A).
- the length of the channel region 106 in the channel length direction is called channel length.
- FIG. 1B is a diagram showing an example of a perspective view with the AA cross section in FIG. 1A as a side surface.
- the AA section is the YZ section passing through the channel region 106 of the base region 114 .
- Each member shown in FIG. 1A is arranged to extend in the Y-axis direction. Therefore, the channel region 106 is also arranged extending in the Y-axis direction.
- the portion of the base region 114 that is adjacent to the control terminal 103 with the gate insulating film 104 interposed therebetween and that is sandwiched between the emitter region 112 and the drift region 116 is the channel region 106 .
- the length of the channel region 106 in the Y-axis direction be the channel length L CH (cm).
- the sum of the channel lengths L CH in the semiconductor substrate 111 is referred to as the total length ⁇ of the channel region 106 .
- FIG. 2 is a diagram for explaining the inter-terminal capacitance of the semiconductor device 100.
- the semiconductor device 100 has an inter-terminal capacitance CCE between the first main terminal 101 and the second main terminal 102, an inter-terminal capacitance CGE between the first main terminal 101 and the control terminal 103, and a It has an inter-terminal capacitance C GC between the two main terminals 102 and the control terminal 103 .
- FIG. 3 is a diagram showing an example of CV characteristics of the semiconductor device 100.
- the power supply voltage applied between the first main terminal 101 and the second main terminal 102 shown in FIG. 1A is V CE (V).
- FIG. 3 shows the relationship between the power supply voltage VCE and the inter-terminal capacitance CGC .
- a characteristic 151 is the CV characteristic of the semiconductor device 100 according to the example shown in FIG. 1A
- a characteristic 154 is the CV characteristic of the semiconductor device 100 according to the reference example.
- a characteristic 151 and a characteristic 154 are CV characteristics when the semiconductor device is in the ON state.
- the voltage waveform between the first main terminal 101 and the second main terminal 102 tends to oscillate. Therefore, by arranging the peak 180 in the region where the power supply voltage VCE is high, it is possible to suppress the oscillation of the voltage waveform in the range where the power supply voltage VCE is relatively low.
- a characteristic 151 has a peak 180 of the inter-terminal capacitance C GC in a region where the power supply voltage V CE is 500 V or more.
- the voltage at the apex of the peak 180 is the voltage at which the peak 180 is located.
- oscillation of the voltage waveform can be suppressed when the power supply voltage VCE is less than 500V.
- Peak 180 may be located in the region above 550V, may be located in the region above 600V, and may be located in the region above 700V. Peak 180 may be located in the region below 1000V and may be located in the region below 800V.
- the position of peak 180 can be adjusted by at least one of the shape of the doping concentration distribution in buffer region 118 and the width Wm of mesa portion 160 .
- the characteristic 151 has a trough 181 where the inter-terminal capacitance C GC exhibits a minimum value in a region where the power supply voltage V CE is less than 500V.
- the trough 181 changes the inter-terminal capacitance C GC more gently than the peak 180 .
- the width of valley 181 is greater than the full width at half maximum (FWHM) of peak 180 .
- the width of the valley portion 181 is the difference between the two power supply voltages VCE before and after the minimum value at which the inter-terminal capacitance CGC is twice the minimum value.
- the width of valley 181 may be two times or more the full width at half maximum of peak 180 .
- the valley portion 181 may be arranged in a region where the power supply voltage VCE is 100V or higher, or may be arranged in a region where the power supply voltage is 200V or higher.
- the power supply voltage VCE at which the inter-terminal capacitance CGC exhibits a minimum value is the voltage at which the valley portion 181 is arranged.
- the inter-terminal capacitance C GC when the power supply voltage V CE is 500 V is larger than the minimum value of the valley portion 181 . From the local minimum of valley 181 to the apex of peak 180, the terminal capacitance CGC may increase monotonically. With such an arrangement, it is possible to suppress a sharp decrease in the inter-terminal capacitance CGC in a region where the power supply voltage VCE is less than 500V.
- a characteristic 154 according to the reference example has a peak in a region where the power supply voltage VCE is 100V to 500V. Therefore, the inter-terminal capacitance CGC is rapidly reduced in this region. Therefore, the voltage VCE tends to oscillate. For example, when the semiconductor device is turned off, the power supply voltage VCE increases, so the voltage waveform tends to oscillate.
- FIG. 4 is a diagram showing an example of doping concentration distribution and hydrogen chemical concentration distribution in the depth direction of part of the drift region 116, the buffer region 118 and the collector region 120.
- FIG. Collector region 120 is formed by implanting a P-type dopant such as boron. Collector region 120 has a peak doping concentration.
- the buffer region 118 is formed by implanting an N-type dopant such as hydrogen.
- the PN junction at the boundary between buffer region 118 and collector region 120 is the lower end of buffer region 118 .
- Dd be the doping concentration of the drift region 116 .
- the doping concentration of drift region 116 may be substantially constant in the depth direction. Substantially constant may refer to a doping concentration variation of less than ⁇ 20% of the average doping concentration Dd in the depth range of the drift region 116 .
- the semiconductor substrate 111 may have bulk donors distributed substantially uniformly across the substrate. Bulk donors are donors that are present from the formation of the ingot of the semiconductor substrate. The bulk donor is, for example but not limited to, phosphorus.
- the doping concentration of the drift region 116 may be the same as the bulk donor concentration.
- the buffer region 118 of this example is in contact with the drift region 116 .
- the boundary Zb between the drift region 116 and the buffer region 118 may be the first position where the doping concentration is 1.2 ⁇ Dd when the doping concentration distribution is observed from the drift region 116 toward the bottom surface 115 .
- the buffer region 118 of this example has an increasing region 124 in which the doping concentration monotonically increases from the boundary Zb with the drift region 116 toward the bottom surface 115 .
- the increasing region 124 may be provided over 1/2 or more of the buffer region 118 in the depth direction, or may be formed over 3/4 or more.
- the increased region 124 may be provided over 10 ⁇ m or more, may be provided over 20 ⁇ m or more, or may be provided over 30 ⁇ m or more.
- a monotonically increasing doping concentration refers to a state in which the doping concentration is continuously increased or maintained when the doping concentration distribution is observed toward the lower surface 115 . That is, increased region 124 does not have a region of decreasing doping concentration toward lower surface 115 . However, the increased region 124 may contain minor doping concentration decreases due to measurement noise or other factors.
- the doping concentration distribution is observed toward the lower surface 115, if the minimum value of the doping concentration is 80% or more of the previous maximum value, the doping concentration does not decrease in the portion containing the minimum value. You can judge. If the minimum value of the doping concentration is 90% or more of the previous maximum value, it may be determined that the doping concentration has not decreased in the portion containing the minimum value.
- Increased region 124 does not include a doping concentration peak because the doping concentration of increased region 124 increases monotonically. By providing the increased region 124 in which the doping concentration peak does not substantially exist, it is possible to suppress the sudden change in the inter-terminal capacitance CGC when the depletion layer 117 reaches the region.
- the buffer region 118 may have one or less doping concentration peaks 121 . That is, the buffer region 118 may have only one doping concentration peak 121 or no doping concentration peak 121 may exist.
- the doping concentration peak 121 has an upper skirt with decreasing doping concentration from the apex toward the top surface 113 and a lower skirt with decreasing doping concentration from the apex toward the bottom surface 115 .
- the doping concentration peak 121 in this example has an apex at the depth position Z1.
- the doping concentration at the upper and lower tails may be reduced to at least half or less, and may be reduced to 0.1 times or less, with respect to the doping concentration Dp at the vertex.
- the increased region 124 does not include the doping concentration peak 121.
- the position at which the slope starts to increase toward the apex of the depth position Z1 may be the lower end position of the increasing region 124.
- FIG. The lower end position of the increasing region 124 may be the position where the second-order differentiation of the doping concentration in the depth direction has a maximum value.
- the end position of the doping concentration peak 121 may be a depth position 5 ⁇ m away from the depth position Z1.
- the doping concentration peak 121 is located below the increased region 124 as shown in FIG.
- the buffer region 118 includes a plurality of hydrogen concentration peaks 141
- the depth position Z2 of the hydrogen concentration peak 141-2 located second closest to the lower surface 115 is set at the lower end of the increase region 124. position.
- the slope of the doping concentration in the enhancement region 124 is ⁇ .
- the slope ⁇ is the rate at which the value logD of the common logarithm of the doping concentration D increases per 1 cm in the depth direction, and its unit is (cm ⁇ 1 ).
- the slope ⁇ may be the slope of the approximation straight line 122 obtained by approximating the doping concentration distribution of the increase region 124 by the method of least squares.
- the slope ⁇ and the above-described total length ⁇ of the channel region 106 satisfy the following formula (1).
- ⁇ >2 ⁇ 10 3 / ⁇ Formula (1) the lower limit of the slope ⁇ is determined according to the reciprocal 1/ ⁇ of the total length ⁇ .
- the lower limit of the slope ⁇ becomes large.
- the increased region 124 becomes shorter in the depth direction.
- the upper limit of the slope ⁇ is determined according to the reciprocal 1/ ⁇ of the total length ⁇ .
- the total length ⁇ of the channel region 106 is large, the channel region 106 on the upper surface 113 of the semiconductor substrate 111 is large, and the carriers injected into the semiconductor substrate 111 are increased.
- the lower limit of the slope ⁇ becomes smaller.
- the increasing region 124 may be lengthened in the depth direction.
- the increased region 124 may be 30% or more, 40% or more, or 50% or more of the length from the bottom of the trench to the end face of the collector region 120 on the side of the buffer region 118 . .
- equation (1) shows that when the active region is large or the total length ⁇ is large, a rapid change in the inter-terminal capacitance CGC can be suppressed by making the slope ⁇ relatively small.
- a straight line 123-H is obtained by doubling the doping concentration of the approximate straight line 122, and a straight line 123-L is obtained by multiplying it by 1/2.
- the doping concentration in augmented region 124 may be between line 123-H and line 123-L throughout augmented region 124.
- FIG. 1 since the doping concentration does not abruptly increase or decrease, abrupt changes in the inter-terminal capacitance CGC in the CV characteristic can be suppressed.
- the hydrogen chemical concentration distribution in the depth direction of the buffer region 118 may have more hydrogen concentration peaks 141 than doping concentration peaks 121 .
- a plurality of hydrogen concentration peaks 141 can be formed by implanting hydrogen ions at a plurality of depth positions from the lower surface 115 . After implanting hydrogen ions, the semiconductor substrate 111 is annealed to form VOH defects in which vacancy defects (V), oxygen (O), and hydrogen (H) are combined. VOH defects act as donors. Therefore, by implanting hydrogen ions at a plurality of depth positions while decreasing the dose according to the depth distance from the lower surface 115, the doping concentration distribution as shown in FIG. 4 can be formed.
- the buffer region 118 of this example has hydrogen concentration peaks 141-1, 141-2, 141-3 and 141-4 at depth positions Z1, Z2, Z3 and Z4. Hydrogen concentration peak 141 - 1 located closest to bottom surface 115 is located at the same depth as doping concentration peak 121 . “Two peaks are arranged at the same depth” means that the apex of one peak is arranged within the range of the full width at half maximum of the other peak.
- the hydrogen concentration peak 141-1 has a higher hydrogen chemical concentration than the other hydrogen concentration peaks 141.
- the peak concentration refers to the concentration at the apex of the peak.
- the hydrogen concentration peak 141-1 may be 5 times or more, 10 times or more, or 100 times or more the maximum hydrogen chemical concentration of the other hydrogen concentration peaks 141. may have a concentration of
- the increased region 124 can be formed without providing peaks in the doping concentration distribution.
- the depth range from the apex of the hydrogen concentration peak 141-4 formed at the deepest position to the apex of the hydrogen concentration peak 141-2 formed at the second shallowest position may be the increased region 124.
- the concentration of each hydrogen concentration peak 141 decreases as the distance from the lower surface 115 increases.
- a straight line obtained by approximating the vertices of the hydrogen concentration peaks 141-2, 141-3, and 141-4 other than the hydrogen concentration peak 141-1 by the method of least squares is defined as a straight line 142.
- FIG. The slope of the straight line 142 is approximately equal to the slope ⁇ of the approximation straight line 122 .
- the slope of the straight line 142 may be 0.5 times or more and 2 times or less of the slope ⁇ .
- the doping concentration distribution is flatter than the hydrogen chemical concentration distribution.
- the depth position of the minimum value between the hydrogen concentration peak 141-4 farthest from the bottom surface 115 and the hydrogen concentration peak 141-3 second from the bottom surface 115 is Z5.
- the difference in doping concentration at depth locations Z4 and Z5 is less than the difference in hydrogen chemical concentration at depth locations Z4 and Z5.
- the doping concentration difference may be 0.5 times or less, may be 0.1 times or less, or may be 0.05 times or less than the hydrogen chemical concentration difference.
- FIG. 5 is a diagram for explaining the slope ⁇ of the doping concentration distribution.
- the doping concentration at the depth position Z4 is D4
- the doping concentration at the depth position Z3 is D3.
- the doping concentration distribution in the increase region 124 may have an upward convex portion 125 and a downward convex concave portion 126 .
- the convex portion 125 is arranged in a range including the depth position Z4.
- the recess 126 is arranged at a position including the depth position Z5.
- the doping concentration distribution in the increased region 124 may be a convex portion 125 that is convex upward as a whole.
- the doping concentration distribution in the increase region 124 may be a concave portion 126 that is entirely downwardly convex.
- the doping concentration profile in the enhancement region 124 may be linear.
- FIG. 6 is a diagram showing numerical examples of the approximate straight line 122.
- the depth positions at both ends of the approximate straight line are X1 and X2, and the doping concentrations at the depth positions X1 and X2 are N1 and N2.
- N1 1.8 ⁇ 10 14 /cm 3
- log(N1) 15.55
- N2 7.0 ⁇ 10 12 /cm 3
- log(N2) 13.46.
- the right side of equation (1) is 2.45 cm. Therefore, it is preferred that the total length ⁇ of channel region 106 is greater than 2.45 cm.
- FIG. 7 is a diagram showing an example of CV characteristics.
- an example in which the doping concentration distribution of the buffer region 118 has two or more doping concentration peaks is called “peak”, and an example in which there is one or less doping concentration peaks as in the example of FIG. 4 is called “no peak”. called.
- An example in which the width Wm of the mesa portion 160 is 20% or less of the depth Zt of the gate structure portion 105 is called a "narrow mesa", and an example in which the width Wm is greater than 20% of the depth Zt is called a "wide mesa”. .
- a characteristic 152 is an example characteristic of "no peak” and “narrow mesa”. Also, characteristic 151 is an example characteristic of "no peak” and “wide mesa”. A characteristic 153 is an example characteristic of "with peak” and “narrow mesa”. Also, characteristic 154 is an example characteristic of "peaked” and “wide mesa”. Zt in this example is 5.5 ⁇ m, the width Wm of the “narrow mesa” is 1.1 ⁇ m, and the width Wm of the “wide mesa” is 2.5 ⁇ m.
- the peak of the inter-terminal capacitance CGC is located in the region of 500V or more. Therefore, oscillation of the voltage VCE can be suppressed.
- the inter-terminal capacitance CGC can be further shifted to the high voltage side.
- the width Wm of the mesa portion 160 may be 1.1 ⁇ m or less.
- the peak of the inter-terminal capacitance CGC is arranged in the region of less than 500V. Therefore, voltage VCE is likely to oscillate.
- FIG. 8 is a diagram showing an example of the doping concentration distribution of the buffer region 118 "with a peak".
- Buffer region 118 in this example has a plurality of doping concentration peaks 127 closer to top surface 113 than doping concentration peaks 121 .
- doping concentration peak 127 is located relatively close to top surface 113 .
- the terminal capacitance CGC tends to decrease rapidly. Therefore, as shown in FIG. 7, the peak of the inter-terminal capacitance CGC appears in a region where the power supply voltage VCE is relatively low.
- the CV characteristics shown in FIGS. 3 and 7 can be analyzed with high accuracy.
- the CV characteristics may be characteristics acquired by the analysis device 10, which will be described later.
- FIG. 9 is a diagram showing an example of the analysis device 10.
- the analysis device 10 analyzes the characteristics of the semiconductor device 100 described with reference to FIGS. 1A to 8.
- FIG. The analysis device 10 analyzes any terminal capacitance of the semiconductor device 100 .
- the terminal capacitance may be the parasitic capacitance of either terminal.
- the terminal capacitance may be parasitic capacitance between any two terminals.
- the analysis device 10 may be a device realized by a computer.
- the computer may be provided with a program for causing the computer to function as the analysis device 10 .
- the computer executes the analysis method by the analysis device 10 by executing the program.
- the analysis device 10 includes an input unit 12, a charge amount analysis unit 14, a capacity calculation unit 16 and an output unit 18.
- Data relating to the semiconductor device 100 to be analyzed is input to the input unit 12 .
- the data may be input by the user of the analysis device 10 or the like.
- the data may include information such as the position, size, shape, impurity concentration, electrical resistance, and capacitance of each portion of the semiconductor device 100 .
- the charge amount analysis unit 14 analyzes the charge amount in a predetermined region within the semiconductor device 100 under predetermined analysis conditions.
- the predetermined analysis conditions may include conditions specifying the control voltage to be applied to the control terminal and the power supply voltage to be applied between the first main terminal 101 and the second main terminal 102 .
- the charge amount analysis unit 14 analyzes the charge in the semiconductor device 100 using a device simulator capable of simulating transient changes in the charge amount in the semiconductor device 100 .
- a transient change is, for example, a temporal change in the amount of charge in the semiconductor device 100 .
- the device simulator analyzes temporal changes in the amount of charge in the semiconductor device 100 when, for example, the power supply voltage is changed.
- the device simulator may analyze the charge density in a predetermined region in the semiconductor device 100 using, for example, Poisson's equation, and integrate the charge density to calculate the amount of charge in the region.
- the charge amount analysis unit 14 may analyze the charge amount in the semiconductor device 100 using a known simulator.
- the charge amount analysis unit 14 sets the control voltage to be applied to the control terminal 103 to a predetermined value to set the semiconductor device 100 to the ON state, and to apply the control voltage between the first main terminal 101 and the second main terminal 102 .
- the supplied power supply voltage is set to a predetermined initial voltage. Then, the charge amount analysis unit 14 uses a device simulator to analyze the change in charge amount at any terminal when the power supply voltage VCE is changed by a displacement voltage smaller than the initial voltage.
- the capacitance calculation unit 16 calculates any terminal capacitance based on the change in the amount of charge analyzed by the charge amount analysis unit 14 .
- the output unit 18 outputs information regarding the terminal capacitance calculated by the capacitance calculation unit 16 .
- the output unit 18 may display information about the terminal capacity on a display device, may transmit the information to an external device, or may store the information in a storage medium.
- FIG. 10 is an example of a circuit 300 schematically showing the semiconductor device 100.
- the analysis device 10 may analyze the operation of the semiconductor device 100 using the circuit 300 .
- a control voltage V GE is applied to the control terminal 103 from a power supply 135 .
- the first main terminal 101 is connected to a reference potential such as ground potential.
- a power supply voltage V CE is applied from a power supply 134 between the first main terminal 101 and the second main terminal 102 .
- the charge amount analysis unit 14 may set the control voltage V GE and the power supply voltage V CE to analyze the charge amount in the semiconductor device 100 .
- the capacitance between the first main terminal 101 and the second main terminal 102 of the semiconductor device 100 be an inter-terminal capacitance CCE .
- the capacitance between the first main terminal 101 and the control terminal 103 be the inter-terminal capacitance CGE
- the capacitance between the second main terminal 102 and the control terminal 103 be the inter-terminal capacitance CGC .
- the capacitance calculation unit 16 calculates the capacitance between any terminals.
- the inter-terminal capacitance CGC of the semiconductor device 100 may differ in value when the semiconductor device 100 is on and when it is off. When the semiconductor device 100 is in the ON state, it is difficult to accurately measure or calculate the inter-terminal capacitance CGC if the current density is high. In the following example, an example in which the inter-terminal capacitance CGC is accurately calculated even when the semiconductor device 100 is in the ON state will be described.
- FIG. 11A and 11B are diagrams for explaining an operation example of the charge amount analysis unit 14.
- the charge amount analysis unit 14 sets the control voltage VGE so as to turn on the semiconductor device 100 . That is, the charge amount analysis unit 14 sets the control voltage V GE higher than the threshold voltage of the semiconductor device 100 . Also, the charge amount analysis unit 14 sets the power supply voltage VCE to a predetermined initial value. Then, after the current ICE between the collector electrode C and the emitter electrode E becomes constant, the charge amount analysis unit 14 changes the power supply voltage VCE by the displacement voltage ⁇ VCE . Calculate the change in the charge amount of The displacement voltage ⁇ V CE is sufficiently small with respect to the power supply voltage V CE .
- the displacement voltage ⁇ V CE may be, for example, 10% or less, 1% or less, or 0.1% or less of the power supply voltage V CE .
- a constant current ICE between the collector electrode C and the emitter electrode E means, for example, a state in which the current ICE between the collector electrode C and the emitter electrode E is a constant current value and does not substantially change over time. and a state in which the current flowing through the control terminal 103 is substantially zero.
- “Not substantially changing” may mean, for example, that the fluctuation range is 20% or less of the average value. Since the control voltage VGE does not change, the terminal capacitance CGE does not change.
- the inter-terminal capacitance C GC is obtained by calculating the amount of change ⁇ Q GC in the charge between the electrodes GC from the space charge density of the gate oxide film and the drift region, for example, and dividing the amount of change ⁇ V CE in the voltage between the electrodes CE ( ⁇ Q GC / ⁇ V CE ) may be calculated.
- the charge amount analysis unit 14 may set the magnitude of the displacement voltage ⁇ V CE according to the change in the magnitude of the power supply voltage V CE .
- the displacement voltage ⁇ V CE may be a voltage obtained by multiplying the power supply voltage V CE by a predetermined coefficient.
- the displacement voltage ⁇ V CE may be a constant voltage regardless of changes in the power supply voltage V CE .
- the charge amount of the terminal may be the charge amount of the contact area in contact with the terminal on the semiconductor substrate 111 .
- the amount of charge on the second main terminal 102 includes the collector region 120 contacting the second main terminal 102 .
- the charge amount of the first main terminal 101 includes the charge amount of the emitter region 112 and the base region 114 that are in contact with the first main terminal 101 .
- the charge amount analysis unit 14 may calculate the charge amount of the collector region 120 using the Poisson's equation shown below.
- ⁇ 2 ⁇ ⁇ q(pn+N D ⁇ N A )/ ⁇
- ⁇ is the differential operator
- ⁇ is the electrostatic potential
- q is the elementary charge
- p is the hole density
- n is the electron density
- ND is the donor concentration
- NA is the acceptor concentration
- ⁇ is the dielectric constant of the semiconductor substrate 111.
- the dielectric constant ⁇ of the semiconductor substrate 111 is a value obtained by multiplying the vacuum dielectric constant ⁇ 0 by the relative dielectric constant ⁇ r of the semiconductor substrate 111 .
- the term pn+N D -N A corresponds to the charge density.
- the dielectric constant ⁇ may be given to the charge amount analysis unit 14 as an analysis condition.
- the power supply voltage VCE determines the electrostatic potential ⁇ at each position in the semiconductor region.
- the charge amount analysis unit 14 calculates the charge density when the power supply voltage is V CE and the charge density when the power supply voltage is V CE + ⁇ V CE using the above Poisson's equation.
- the donor concentration N D and the acceptor concentration N A at each position on the semiconductor substrate 111 may be preset as analysis conditions in the charge amount analysis unit 14 .
- the charge amount analysis unit 14 calculates the total charge density of the collector region 120 .
- the charge amount analysis unit 14 may integrate the charge density described above. The charge amount can be calculated by multiplying the integral value of the charge density by the elementary charge amount.
- the charge amount analysis unit 14 may calculate the time change of the charge amount when the power supply voltage is changed as shown in FIG. .
- the charge amount analysis unit 14 may calculate the charge amount when the change in the charge amount converges as the charge amount when the power supply voltage is V CE + ⁇ V CE .
- the charge amount analysis unit 14 may calculate the difference ⁇ Q between the charge amount when the power supply voltage is V CE and the charge amount when the power supply voltage is V CE + ⁇ V CE .
- the charge amount analysis unit 14 may further calculate the charge density in at least part of the drift region 116 .
- the charge density of the drift region 116 can also be analyzed from the power supply voltage V CE and the displacement voltage ⁇ V CE using Poisson's equation, similarly to the collector region 120 .
- the charge amount analysis unit 14 may calculate the charge density of the drift region 116 in the range where the depletion layer 117 spreads when the power supply voltage VCE is applied.
- the charge amount analysis unit 14 may integrate the charge density of the region of the drift region 116 to calculate the charge amount of the region.
- the charge amount analysis unit 14 may include the charge amount of the region in the charge amount of the second main terminal 102 . Since the inter-terminal capacitance CGC can change depending on how the depletion layer 117 spreads, the inter-terminal capacitance CGC can be analyzed more accurately by considering the amount of charge in the region.
- the capacitance calculation unit 16 calculates the inter-terminal capacitance CGC based on the charge amount difference ⁇ Q and the displacement voltage ⁇ V CE calculated by the charge amount analysis unit 14 .
- the capacitance calculator 16 may calculate the inter-terminal capacitance CGC by the following equation.
- C GC ⁇ Q/ ⁇ V CE
- FIG. 12 is a diagram showing an example of the CV characteristic calculated by the capacity calculator 16.
- the charge amount analysis unit 14 changes the power supply voltage VCE from the initial voltage, and calculates the charge amount when the power supply voltage VCE is changed by the displacement voltage ⁇ VCE for each changed power supply voltage VCE . Analyze the change ⁇ Q.
- the charge amount analysis unit 14 changes the power supply voltage V CE to 10 V, 50 V, 100 V, 500 V , .
- a change ⁇ Q in charge amount is calculated.
- the capacitance calculator 16 calculates the inter-terminal capacitance CGC for each power supply voltage VCE based on the change ⁇ Q in the amount of charge analyzed for each power supply voltage VCE . As a result, a CV characteristic as shown in FIG. 12 is obtained.
- the capacitance calculator 16 may use the calculated inter-terminal capacitance CGC as the capacitance value at the power supply voltage VCE . That is, the calculated inter-terminal capacitance CGC may be used as the capacitance value at the power supply voltage VCE before the change. In another example, the capacitance calculator 16 may use the calculated inter-terminal capacitance C GC as the capacitance value for the power supply voltage V CE + ⁇ V CE .
- the calculated inter-terminal capacitance C GC may be the capacitance value for the power supply voltage V CE + ⁇ V CE after changing the power supply voltage V CE by the displacement voltage ⁇ V CE .
- the capacitance calculator 16 may use the calculated inter-terminal capacitance C GC as the capacitance value for the power supply voltage V CE +0.5 ⁇ V CE . That is, the calculated inter-terminal capacitance CGC may be used as the capacitance value for the average power supply voltage before and after the change.
- FIG. 13A and 13B are diagrams showing another operation example of the charge amount analysis unit 14.
- the charge amount analysis unit 14 of this example provides a first change ⁇ Q1 in the charge amount when the first displacement voltage ⁇ V CE1 is added to the first power supply voltage V CE1 and a second change ⁇ Q1 from the second power supply voltage V CE2 to the second A second change .DELTA.Q2 in the amount of charge when the displacement voltage .DELTA.VCE2 of is reduced is analyzed.
- the first power supply voltage VCE1 and the second power supply voltage VCE2 may be the same voltage. In other words, each voltage may be set so that the power supply voltage before the change is the same.
- the charge amount analysis unit 14 may calculate a change ⁇ Q1 in the charge amount when the voltage is increased from the power supply voltage VCE and a change ⁇ Q2 in the charge amount when the voltage is decreased from the same power supply voltage VCE . .
- the first displacement voltage ⁇ V CE1 and the second displacement voltage ⁇ V CE2 may be the same or different.
- the charge amount analysis unit 14 may calculate a weighted average of ⁇ Q1 and ⁇ Q2 according to the ratio between the first displacement voltage ⁇ V CE1 and the second displacement voltage ⁇ V CE2 .
- the capacitance calculator 16 may use the inter-terminal capacitance CGC calculated from the average value ⁇ Q of changes in the amount of charge as the capacitance for the power supply voltage VCE . Also in this case, the CV characteristics shown in FIG. 12 can be obtained by changing the respective power supply voltages from their initial values.
- the first power supply voltage VCE1 and the second power supply voltage VCE2 may be different voltages.
- a voltage V CE1 + ⁇ V CE1 obtained by adding the first displacement voltage ⁇ V CE1 to the first power supply voltage V CE1 and a voltage V CE2 + ⁇ V CE2 obtained by subtracting the second displacement voltage ⁇ V CE2 from the second power supply voltage V CE2 .
- Each voltage may be set such that . In other words, each voltage may be set so that the power supply voltage after the change is the same.
- the first displacement voltage ⁇ V CE1 and the second displacement voltage ⁇ V CE2 may be the same or different.
- the charge amount analysis unit 14 calculates a charge amount change ⁇ Q1 when the first displacement voltage ⁇ VCE1 is added to the first power supply voltage VCE1 , and the second displacement voltage ⁇ VCE2 from the second power supply voltage VCE2 .
- a change ⁇ Q2 in the charge amount when the charge amount is reduced may be calculated.
- the CV characteristics shown in FIG. 12 can be obtained by changing the respective power supply voltages from their initial values.
- the device simulator of the charge amount analysis unit 14 may have a convergence determination function for determining whether or not the processing for analyzing changes in the charge amount has converged.
- the convergence judgment function converges the analysis process when the charge amount after changing the power supply voltage VCE by the displacement voltage ⁇ VCE cannot be calculated within the set calculation period or within the set calculation processing amount. You can decide not to.
- the displacement voltage ⁇ V CE is reduced, it becomes difficult for the analysis process to converge.
- the smaller the displacement voltage ⁇ V CE the more accurately the CV characteristics can be analyzed.
- the charge amount analysis unit 14 may set the displacement voltage to be as small as possible within the range where it is determined that the analysis process converges.
- the charge amount analysis unit 14 may set the smallest displacement voltage within a range in which it is determined that the analysis processing converges.
- the set displacement voltage may have a predetermined margin with respect to the minimum displacement voltage that satisfies the conditions.
- FIG. 14 is a diagram showing an example of a general CV characteristic.
- the horizontal axis in FIG. 14 indicates VCE , and the vertical axis indicates CGC .
- Capacitor C GC may begin to saturate when power supply voltage V CE falls below a predetermined saturation voltage.
- a voltage at which the capacitance CGC becomes half of the maximum value Cmax when the power supply voltage VCE is lowered may be taken as the saturation voltage.
- the saturation voltage is about 1V.
- the charge amount analysis section 14 may set the lower limit voltage of the fluctuation range of the power supply voltage V CE according to the saturation voltage.
- the lower limit voltage may be the saturation voltage.
- the charge amount analysis unit 14 may determine the displacement voltage ⁇ V CE according to the saturation voltage.
- the charge amount analysis unit 14 may determine the displacement voltage ⁇ V CE by multiplying the saturation voltage by a predetermined coefficient.
- the coefficient may be, for example, 0.2 or less, 0.1 or less, or 0.01 or less.
- the saturation voltage may be set in advance by a user or the like, and may be analyzed by the charge amount analysis unit 14 based on input information.
- the saturation voltage may be calculated by analyzing the CV characteristics when the semiconductor device 100 is off.
- FIG. 15 is a diagram explaining a measurement method according to a reference example.
- the measurement method of this example measures the CV characteristic by applying a small signal voltage to the semiconductor device 100, measuring the current flowing through the semiconductor device 100, and calculating the impedance.
- FIG. 15 is an equivalent circuit showing only the capacitive component of the semiconductor device 100.
- an AC small-signal voltage is applied to the capacitor C whose CV characteristic is to be measured, and the flowing current is measured.
- FIG. 16 is a diagram showing an example of the measurement circuit 405 used in the reference example. In this example, an example of measuring the capacitance CGC is shown, but other capacitances C can be similarly measured.
- the first main terminal 101 shown in FIG. 15 is connected to the ground potential via an AC guard that allows AC signals to pass. This makes it possible to measure the impedance of the capacitor CGC while excluding the capacitors C_GE and C_CE .
- a small signal source 401 and a power supply VCC are connected in parallel to the second main terminal 102 .
- an ammeter 402 is connected to the control terminal 103 .
- the capacitance CGC can be calculated by the following formula.
- C GC I/j ⁇ V
- FIG. 17 is a diagram showing an example of CV characteristics calculated based on the measurement circuit 405 shown in FIG. In FIG. 17, generally reasonable CV characteristics are obtained.
- the CV characteristics are characteristics when the semiconductor device 100 is in the off state.
- the CV characteristic of the semiconductor device 100 may change depending on whether the semiconductor device 100 is on or off.
- Semiconductor device 100 is often used in an ON state. Therefore, it is preferable to be able to analyze the CV characteristics of the semiconductor device 100 in the ON state.
- FIG. 18 shows a circuit 420 showing the operation when the semiconductor device 100 is in the ON state in the reference example.
- circuit 420 the small signal source 401 is omitted.
- Circuit 420 analyzes the behavior of the DC component.
- the main current I is included in the current IC flowing through the second main terminal 102 .
- the main current I is usually much larger than the current flowing through each capacitor when the power supply voltage VCE changes.
- the current Iac includes the main current I component in addition to the current flowing through each capacitance. put away. As a result, the apparent amount of current becomes very large, and the terminal capacitance CGC becomes a very large value.
- FIG. 19 shows the analytical value of the terminal capacitance CGC when the semiconductor device 100 is turned on and the analytical value of the terminal capacitance CGC when the semiconductor device 100 is turned off.
- the analytical value of the terminal capacitance CGC in the ON state becomes much larger than the analytical value of the terminal capacitance CGC in the OFF state.
- the analysis method of the reference example cannot accurately analyze the capacitance when the semiconductor device 100 is in the ON state.
- FIG. 20 is a diagram obtained by analyzing each current waveform from the amount of charge calculated by the analysis method described in FIGS. 1A to 14.
- FIG. 20 shows the change ⁇ Ic in the collector current flowing through the second main terminal 102 shown in FIG. 10 and the change ⁇ Icgc in the current flowing through the inter-terminal capacitance CGC .
- the amount of change ⁇ Ic is the difference in the current Ic when the power supply voltage is changed.
- the amount of change ⁇ I Cgc can be calculated from the integrated value of the charges in the collector region 120 .
- the collector current IC increases as the main current increases.
- the current I Cgc flowing through the inter-terminal capacitance C GC fluctuates during the voltage transition period, but is substantially zero except during the voltage transition period.
- the charge amount calculated by the analysis method described in FIGS. 1A to 14 does not include the charge contributing to the collector current IC. Therefore, the CV characteristics of the ON state of the semiconductor device 100 can be accurately analyzed.
- the CV characteristics in the ON state shown in FIG. 12 differ little from the CV characteristics in the OFF state shown in FIG. 19, and are generally appropriate values. Since the charge calculated by this analysis method does not include the charge that contributes to the collector current I.sub.C , the terminal capacitance C.sub.GC can be calculated without affecting the collector current I.sub.C.
- FIG. 21 is a flow chart showing an example of an analysis method using the analysis device 10 shown in FIGS. 1A to 14.
- the analysis method includes an input stage S1500, a charge amount analysis stage S1502, a capacity calculation stage S1504, and an output stage S1506.
- the processing in the input step S1500 is the same as the processing in the input unit 12.
- the processing in the charge amount analysis step S1502 is the same as that of the charge amount analysis unit 14.
- FIG. The processing in the capacity calculation step S1504 is the same as the processing of the capacity calculation unit 16.
- FIG. The processing in the output step S1506 is the same as the processing of the output unit 18.
- FIG. 22 shows an example configuration of a computer 1200 in which aspects of the present invention may be embodied in whole or in part.
- Programs installed on the computer 1200 cause the computer 1200 to function as one or more "parts" of operations or one or more "parts” of an apparatus according to embodiments of the invention, or to and/or cause computer 1200 to perform processes or steps of processes according to embodiments of the present invention.
- Such programs may be executed by CPU 1212 to cause computer 1200 to perform certain operations associated with some or all of the blocks in the flowcharts and block diagrams described herein. Also, processes or steps of such processes according to embodiments of the present invention may be performed on the cloud.
- a computer 1200 includes a CPU 1212 , a RAM 1214 , a graphics controller 1216 and a display device 1218 , which are interconnected by a host controller 1210 .
- Computer 1200 also includes input/output units such as communication interface 1222 , hard disk drive 1224 , DVD-ROM drive 1226 , and IC card drive, which are connected to host controller 1210 via input/output controller 1220 .
- the computer also includes legacy input/output units such as ROM 1230 and keyboard 1242 , which are connected to input/output controller 1220 through input/output chip 1240 .
- the CPU 1212 operates according to programs stored in the ROM 1230 and RAM 1214, thereby controlling each unit.
- Graphics controller 1216 takes image data generated by CPU 1212 into a frame buffer or the like provided in RAM 1214 or into itself, and causes the image data to be displayed on display device 1218 .
- a communication interface 1222 communicates with other electronic devices via a network.
- Hard disk drive 1224 stores programs and data used by CPU 1212 within computer 1200 .
- DVD-ROM drive 1226 reads programs or data from DVD-ROM 1201 and provides programs or data to hard disk drive 1224 via RAM 1214 .
- the IC card drive reads programs and data from IC cards and/or writes programs and data to IC cards.
- the ROM 1230 stores internally programs such as boot programs executed by the computer 1200 upon activation and/or programs dependent on the hardware of the computer 1200 .
- Input/output chip 1240 may also connect various input/output units to input/output controller 1220 via parallel ports, serial ports, keyboard ports, mouse ports, and the like.
- a program is provided by a computer-readable storage medium such as a DVD-ROM 1201 or an IC card.
- the program is read from a computer-readable storage medium, installed in hard disk drive 1224 , RAM 1214 , or ROM 1230 , which are also examples of computer-readable storage media, and executed by CPU 1212 .
- the information processing described within these programs is read by computer 1200 to provide coordination between the programs and the various types of hardware resources described above.
- An apparatus or method may be configured by implementing information operations or processing according to the use of computer 1200 .
- the CPU 1212 executes a communication program loaded into the RAM 1214 and sends communication processing to the communication interface 1222 based on the processing described in the communication program. you can command.
- the communication interface 1222 reads transmission data stored in a transmission buffer area provided in a recording medium such as the RAM 1214, the hard disk drive 1224, the DVD-ROM 1201, or an IC card. Data is transmitted to the network, or received data received from the network is written in a receive buffer area or the like provided on the recording medium.
- the CPU 1212 causes the RAM 1214 to read all or necessary portions of files or databases stored in external recording media such as a hard disk drive 1224, a DVD-ROM drive 1226 (DVD-ROM 1201), an IC card, etc. Various types of processing may be performed on the data in RAM 1214 . CPU 1212 may then write back the processed data to an external recording medium.
- external recording media such as a hard disk drive 1224, a DVD-ROM drive 1226 (DVD-ROM 1201), an IC card, etc.
- Various types of processing may be performed on the data in RAM 1214 .
- CPU 1212 may then write back the processed data to an external recording medium.
- CPU 1212 performs various types of operations on data read from RAM 1214, information processing, conditional decisions, conditional branching, unconditional branching, and information retrieval, which are described throughout this disclosure and are specified by instruction sequences of programs. Various types of processing may be performed, including /replace, etc., and the results written back to RAM 1214 . In addition, the CPU 1212 may search for information in a file in a recording medium, a database, or the like.
- the CPU 1212 selects the first attribute from among the plurality of entries. search for an entry that matches the specified condition for the attribute value of the attribute, read the attribute value of the second attribute stored in the entry, and thereby associate the attribute with the first attribute that satisfies the predetermined condition.
- the attribute value of the second attribute may be obtained.
- the programs or software modules described above may be stored on the computer 1200 or in a computer-readable storage medium near the computer 1200 .
- a recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can be used as a computer-readable storage medium, whereby the program can be transferred to the computer 1200 via a network. offer.
- DESCRIPTION OF SYMBOLS 10 ... Analysis apparatus, 12... Input part, 14... Charge amount analysis part, 16... Capacity calculation part, 18... Output part, 100... Semiconductor device, 101... Second 1 main terminal 102 second main terminal 103 control terminal 104 gate insulating film 105 gate structure portion 106 channel region 110 interlayer insulating film , 111... semiconductor substrate, 112... emitter region, 113... upper surface, 114... base region, 115... lower surface, 116... drift region, 117... depletion layer, 118...
- Buffer region 120 Collector region 121 Doping concentration peak 122 Approximate straight line 123 Straight line 124 Increasing region 125 Convex portion 126 Recess 127 Doping concentration peak 134 Power source 135 Power source 141 Hydrogen concentration peak 142 Straight line 151, 152, 153, 154 Characteristic 160 ... mesa portion, 180 ... peak, 181 ... valley, 300 ... circuit, 401 ... small signal source, 402 ... ammeter, 405 ... measurement circuit, 420 ... circuit, 1200... computer, 1201... DVD-ROM, 1210... host controller, 1212... CPU, 1214... RAM, 1216... graphic controller, 1218... display device, 1220... input/output controller, 1222... communication interface, 1224... hard disk drive, 1226... DVD-ROM drive, 1230... ROM, 1240... input/output chip, 1242... keyboard
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Abstract
Description
特許文献1 WO2016/203545号
β>2×103/α
β>2×103/α
β>2×103/α ・・・式(1)
式(1)によれば、傾きαの下限が総長さβの逆数1/βに応じて定まる。チャネル領域106の総長さβが小さい場合、半導体基板111の上面113におけるチャネル領域106が少なくなり、半導体基板111に注入されるキャリアは減少する。この場合、傾きαの下限は大きくなる。傾きαが大きくなると、増加領域124が深さ方向に短くなる。一方、式(1)によれば、傾きαの上限が総長さβの逆数1/βに応じて定まる。チャネル領域106の総長さβが大きい場合、半導体基板111の上面113におけるチャネル領域106が多くなり、半導体基板111に注入されるキャリアは増加する。この場合、傾きαの下限は小さくなる。傾きαが小さくなる場合、増加領域124を深さ方向に長くしてよい。一例として、増加領域124は、トレンチ部底面からコレクタ領域120のバッファ領域118側端面までの長さの、30%以上であってよく、40%以上であってよく、50%以上であってよい。総長さβが大きい場合は、例えば半導体装置100の活性領域の面積が大きい場合である。つまり式(1)は、活性領域が大きいまたは総長さβが大きい場合に、傾きαを比較的に小さくすることで、端子間容量CGCの急激な変化を抑制できることを示す。
α=|log(D3)-log(D4)|/|Z3-Z4| ・・・式(2)
α=|15.55-13.46|/|4.3×10―4―29.9×10―4|≒816.5
この場合、式(1)の右辺は2.45cmとなる。従ってチャネル領域106の総長さβが2.45cmより大きいことが好ましい。
∇2・φ=-q(p-n+ND-NA)/ε
ただし、∇は微分演算子、φは静電ポテンシャル、qは電荷素量、pはホール密度、nは電子密度、NDはドナー濃度、NAはアクセプタ濃度、εは半導体基板111の誘電率である。半導体基板111の誘電率εは、真空の誘電率ε0に、半導体基板111の比誘電率εrを乗じた値である。p-n+ND-NAの項が、電荷密度に相当する。
CGC=ΔQ/ΔVCE
CGC=I/jωV
電源電圧VCCを変化させて容量CGCを測定することで、C-V特性を取得できる。図14において説明した飽和電圧に関する情報は、参考例の測定結果から取得してよい。
Claims (10)
- 上面および下面を有し、第1導電型のドリフト領域を有する半導体基板と、
前記上面の上方に設けられた第1主端子と、
前記下面の下方に設けられた第2主端子と、
前記第1主端子および前記第2主端子の間に電流を流すか否かを制御する制御端子と、
前記ドリフト領域および前記下面の間に設けられ、前記ドリフト領域よりもドーピング濃度が高いバッファ領域と
を備え、
前記第1主端子および前記第2主端子の間に印加する電源電圧と、前記制御端子および前記第2主端子の間の端子間容量との関係を示すC-V特性において、前記電源電圧が500V以上の領域に、前記端子間容量のピークを有する
半導体装置。 - 前記C-V特性は、前記電源電圧が500V未満の領域において前記端子間容量が極小値を示す谷部を有し、
前記電源電圧が500Vのときの前記端子間容量が、前記極小値よりも大きい
請求項1に記載の半導体装置。 - 前記C-V特性は、前記半導体装置をオン状態に設定し、且つ、前記第1主端子と前記第2主端子の間に印加される電源電圧を初期電圧に設定した状態で、前記第1主端子と前記第2主端子の間に流れる電流を安定させた後に、前記電源電圧を前記初期電圧より小さい変位電圧だけ変化させたときのいずれかの端子における電荷量の変化を、前記半導体装置内の電荷の過渡的な変化を模擬するデバイスシミュレータにより解析し、解析した電荷量の変化に基づいて前記端子間容量を計算することで取得された特性である
請求項1に記載の半導体装置。 - 前記制御端子と対向して設けられ、前記制御端子に制御電圧が印加されることで、前記制御端子と対向するチャネル領域に反転層チャネルが形成される第2導電型のベース領域と
を更に備え、
前記バッファ領域は、前記ドリフト領域との境界から前記下面に向かってドーピング濃度が単調に増加する増加領域を有し、
前記増加領域における前記ドーピング濃度の常用対数の値が、深さ方向の1cm当たりに増加する傾きαと、前記チャネル領域の総長さβとが、下式を満たす
β>2×103/α
請求項1に記載の半導体装置。 - 前記バッファ領域の深さ方向におけるドーピング濃度分布が有するドーピング濃度ピークは1つ以下である
請求項1から4のいずれか一項に記載の半導体装置。 - 前記バッファ領域の深さ方向における水素化学濃度分布は、前記ドーピング濃度ピークよりも多くの水素濃度ピークを有する
請求項5に記載の半導体装置。 - 前記半導体基板の前記上面において配列方向に並んで配置され、且つ、前記半導体基板の前記上面から前記ドリフト領域まで設けられた複数のトレンチ部と、
2つのトレンチ部に挟まれたメサ部と
を更に備え、
前記メサ部の前記配列方向における幅は、前記トレンチ部の深さの20%以下である
請求項1から4のいずれか一項に記載の半導体装置。 - 前記メサ部の幅が1.1μm以下である
請求項7に記載の半導体装置。 - 前記増加領域において、ドーピング濃度分布は、水素化学濃度分布よりも平坦である
請求項4に記載の半導体装置。 - 上面および下面を有し、第1導電型のドリフト領域を有する半導体基板と、
前記上面の上方に設けられた第1主端子と、
前記下面の下方に設けられた第2主端子と、
前記第1主端子および前記第2主端子の間に電流を流すか否かを制御する制御端子と、
前記ドリフト領域および前記下面の間に設けられ、前記ドリフト領域よりもドーピング濃度が高いバッファ領域と、
前記制御端子と対向して設けられ、前記制御端子に制御電圧が印加されることで、前記制御端子と対向するチャネル領域に反転層チャネルが形成される第2導電型のベース領域と
を備え、
前記バッファ領域は、前記ドリフト領域との境界から前記下面に向かってドーピング濃度が単調に増加する増加領域を有し、
前記増加領域における前記ドーピング濃度の常用対数の値が、深さ方向の1cm当たりに増加する傾きαと、前記チャネル領域の総長さβとが、下式を満たす
β>2×103/α
半導体装置。
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