WO2022222042A1 - 发光二极管芯片 - Google Patents

发光二极管芯片 Download PDF

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Publication number
WO2022222042A1
WO2022222042A1 PCT/CN2021/088496 CN2021088496W WO2022222042A1 WO 2022222042 A1 WO2022222042 A1 WO 2022222042A1 CN 2021088496 W CN2021088496 W CN 2021088496W WO 2022222042 A1 WO2022222042 A1 WO 2022222042A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
layer
emitting diode
diode chip
light
Prior art date
Application number
PCT/CN2021/088496
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English (en)
French (fr)
Inventor
黄敏
刘小亮
何安和
Original Assignee
厦门三安光电有限公司
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Filing date
Publication date
Application filed by 厦门三安光电有限公司 filed Critical 厦门三安光电有限公司
Priority to PCT/CN2021/088496 priority Critical patent/WO2022222042A1/zh
Priority to DE112021007541.1T priority patent/DE112021007541T5/de
Priority to CN202180003076.8A priority patent/CN113875029A/zh
Publication of WO2022222042A1 publication Critical patent/WO2022222042A1/zh
Priority to US18/489,155 priority patent/US20240047621A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings

Definitions

  • the present application relates to the technical field of light-emitting diodes, and in particular, to a light-emitting diode chip.
  • light-emitting diode chips Due to the characteristics of high reliability, long life and low power consumption, light-emitting diode chips are widely used in various fields. Among them, most of the insulating layers in light-emitting diode chips are single-layer silicon oxide layers with large thickness. When other structural layers are formed on the silicon layer, due to the large slope of the ends or through holes of the single-layer silicon oxide layer, when other structural layers are formed on the single-layer silicon oxide layer, large stress is generated inside the other structural layers, resulting in other The structural layer is prone to cracks or the entire layer is broken, which reduces the reliability of the light-emitting diode chip.
  • the purpose of the present application is to provide a light emitting diode chip, wherein the insulating layer is formed of at least a first insulating layer and a second insulating layer, and the first insulating layer extends beyond the second insulating layer by a predetermined length in the horizontal direction, so that the second structure
  • the stress generated inside the second insulating layer is reduced, the second insulating layer is prevented from cracking or the whole layer is broken under the action of the stress, and the reliability of the light emitting diode chip is improved.
  • an embodiment of the present application provides a light-emitting diode chip, which has a semiconductor stack layer and an insulating layer, the insulating layer at least includes a first insulating layer and a second insulating layer formed on the upper surface of the first insulating layer; the insulating layer has The stepped structure includes a first step formed by a first insulating layer and a second step formed by a second insulating layer, and the first step exceeds the second step in a horizontal direction.
  • the thickness of the second insulating layer is greater than that of the first insulating layer, and the thickness of the second insulating layer is equal to or greater than 1 ⁇ m.
  • the length L 1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 5000 nm.
  • the length L 1 of the first step beyond the second step is equal to or greater than 100 nm and less than or equal to 5000 nm.
  • the length L 1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 100 nm.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction is smaller than the angle ⁇ 2 between the side surface of the second step and the horizontal direction.
  • the side surface of the second step is a slope surface, and the angle ⁇ 2 between the slope surface and the horizontal direction ranges from 20° to 40°, 40° to 60° or 60° to 70°.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle ⁇ 1 ranges from 10° to 30° or 30° to 45°.
  • the insulating layer is provided with a through hole penetrating the insulating layer, and the sidewall of the through hole is configured as the above-mentioned stepped structure;
  • the end portion of the insulating layer is arranged in the above-described stepped structure.
  • the thickness of the first insulating layer is between 30 and 200 nm;
  • the second insulating layer is a high density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer or an evaporation deposition layer.
  • HDPCVD high density plasma chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • the thickness of the first insulating layer is between 400 and 1000 nm;
  • the second insulating layer is an evaporation deposition layer.
  • the first insulating layer and the second insulating layer are prepared by the same preparation process, and the preparation materials of the first insulating layer and the second insulating layer are different; the first insulating layer and the second insulating layer are made of different materials;
  • the material for making the layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.
  • the preparation material of the first insulating layer is aluminum oxide.
  • the second insulating layer is a distributed Bragg reflector (DBR).
  • DBR distributed Bragg reflector
  • the insulating layer further includes a third insulating layer formed on the upper surface of the second insulating layer; the step structure further includes a third step formed by the third insulating layer; the second step in the horizontal direction exceeds The length L 2 of the third step is less than the length L 1 of the first step beyond the second step.
  • a second structural layer is formed on the surface of the insulating layer away from the first insulating layer, and the elongation ⁇ of the second structural layer is equal to or less than 50%.
  • the preparation material of the second structural layer is nickel, gold, titanium, chromium, indium tin oxide, titanium oxide, silicon oxide, aluminum oxide, silicon nitride, titanium nitride or aluminum nitride. a kind of.
  • a first structural layer is formed on the surface of the insulating layer close to the first insulating layer, and the first structural layer is a transparent insulating layer, a transparent conductive layer or a metal layer.
  • the semiconductor stack is used as the first structural layer, the insulating layer is formed on the semiconductor stack, and the second insulating layer is remote from the semiconductor stack.
  • the light-emitting diode chip further includes:
  • the substrate is used as the first structure layer; the semiconductor stack layer forms a mesa structure on the substrate, and the insulating layer covers at least the sidewall of the semiconductor stack layer and the partial area of the substrate except the semiconductor stack layer; the second insulating layer is far away from the semiconductor stack Floor.
  • an insulating layer which at least includes:
  • the stepped structure includes a first step formed by a first insulating layer and a second step formed by a second insulating layer, and the first step exceeds the second step in a horizontal direction.
  • the thickness of the second insulating layer is greater than that of the first insulating layer, and the thickness of the second insulating layer is equal to or greater than 1 ⁇ m.
  • the length L 1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 5000 nm.
  • the length L 1 of the first step beyond the second step is equal to or greater than 100 nm and less than or equal to 5000 nm.
  • the length L 1 of the first step beyond the second step is equal to or greater than 50 nm and less than or equal to 100 nm.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction is smaller than the angle ⁇ 2 between the side surface of the second step and the horizontal direction.
  • the side surface of the second step is a slope surface, and the angle ⁇ 2 between the slope surface and the horizontal direction ranges from 20° to 40°, 40° to 60° or 60° to 70°.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle ⁇ 1 ranges from 10° to 30° or 30° to 45°.
  • the insulating layer is provided with a through hole penetrating the insulating layer, and the sidewall of the through hole is configured as the above-mentioned stepped structure;
  • the end portion of the insulating layer is arranged in the above-described stepped structure.
  • the thickness of the first insulating layer is between 30 and 200 nm;
  • the second insulating layer is a high density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer or an evaporation deposition layer.
  • HDPCVD high density plasma chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • the thickness of the first insulating layer is between 400 and 1000 nm;
  • the second insulating layer is an evaporation deposition layer.
  • the first insulating layer and the second insulating layer are prepared by the same preparation process, and the preparation materials of the first insulating layer and the second insulating layer are different; the first insulating layer and the second insulating layer are made of different materials;
  • the material for making the layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.
  • the preparation material of the first insulating layer is aluminum oxide.
  • the second insulating layer is a distributed Bragg reflector (DBR).
  • DBR distributed Bragg reflector
  • the insulating layer further includes a third insulating layer formed on the upper surface of the second insulating layer; the step structure further includes a third step formed by the third insulating layer; the second step in the horizontal direction exceeds The length L 2 of the third step is less than the length L 1 of the first step beyond the second step.
  • the present application at least has the following beneficial effects:
  • the insulating layer is formed by at least a first insulating layer and a second insulating layer, which can prevent cracks or whole layer fractures in the insulating layer, and improve the reliability of the insulating layer.
  • the first insulating layer exceeds the predetermined length of the second insulating layer in the horizontal direction, then the excess portion can play a buffering role when the subsequent second structural layer is formed on the insulating layer, reducing the stress generated inside the second structural layer , to avoid cracks in the second structure layer or breakage of the whole layer under the action of stress, and improve the reliability of the light-emitting diode chip.
  • the exceeding part can also block the entry of water vapor to avoid the aging failure of the light emitting diode chip.
  • FIG. 1 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application
  • FIG. 4 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional view of a light-emitting diode chip according to an embodiment of the present application.
  • FIG. 11 is a schematic cross-sectional view of an insulating layer according to an embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional view of an insulating layer according to an embodiment of the present application.
  • FIG. 13 is a schematic cross-sectional view of an insulating layer according to an embodiment of the present application.
  • FIG. 14 is a schematic cross-sectional view of an insulating layer according to an embodiment of the present application.
  • 210 substrate 220 semiconductor stack layer; 221 first type semiconductor layer; 222 active layer; 223 second type semiconductor layer; 230 transparent conductive layer; 240 reflective layer; 251 first electrode; 252 second electrode; 260 first protective layer; 271 first pad; 272 second pad; 280 second protective layer;
  • 310 substrate 320 semiconductor stack layer; 321 first type semiconductor layer; 322 active layer; 323 second type semiconductor layer; 330 transparent conductive layer; 340 first protective layer; 350 reflective layer; 360 second protective layer; 370 The first electrode; 380 the second electrode; 390 the third protective layer;
  • 410 substrate 420 semiconductor stack layer; 421 first type semiconductor layer; 422 active layer; 423 second type semiconductor layer; 430 current blocking layer; 440 transparent conductive layer; 451 first electrode; 452 second electrode; 453 mutual Connect electrode; 460 protective layer; 471 first pad; 472 second pad.
  • orientation or positional relationship indicated by the terms “upper”, “lower”, “altitude”, etc. is based on the orientation or positional relationship shown in the accompanying drawings, or when the product of the application is used.
  • the orientation or positional relationship that is usually placed is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a Application restrictions.
  • the light emitting diode chip includes a semiconductor stack layer 40 and an insulating layer 10 .
  • the insulating layer 10 at least includes a first insulating layer 11 and a second insulating layer 12 formed on the upper surface of the first insulating layer 11 , and the insulating layer 10 has a stepped structure 14 .
  • the step structure 14 includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12, and the first step exceeds the second step in the horizontal direction, which can also be described as the first step in the horizontal direction.
  • the insulating layer 11 extends beyond the second insulating layer 12 .
  • the insulating layer 10 is formed by at least the first insulating layer 11 and the second insulating layer 12 , which can prevent the insulating layer 10 from cracking or break the whole layer, and improve the reliability of the insulating layer 10 .
  • the first insulating layer 11 exceeds the predetermined length of the second insulating layer 12 in the horizontal direction, and the excess portion can play a buffering role when the second structural layer 30 is formed on the insulating layer 10 subsequently, reducing the interior of the second structural layer 30 .
  • the generated stress can prevent the second structural layer 30 from cracking or breaking the whole layer under the action of the stress, thereby improving the reliability of the light emitting diode chip.
  • a first structural layer 20 is formed on the surface of the insulating layer 10 close to the first insulating layer 11 , and the first structural layer 20 is a transparent insulating layer, a transparent conductive layer or a metal layer.
  • a second structure layer 30 is formed on the surface of the insulating layer 10 away from the first insulating layer 11 , and the second structure layer 30 covers the upper surface of the insulating layer 10 and the stepped structure 14 .
  • the elongation ⁇ of the second structural layer 30 is equal to or less than 50%, according to the relationship of the elongation ⁇ among the metals: aluminum 70.92%, silver 54.38%, copper 53.2%, nickel 48.4%, gold 35%, platinum 24.2%, Titanium 24.94%, chromium 20.99%, tungsten 8.84%, the preparation material of the second structural layer 30 is preferably nickel, gold, titanium, chromium, indium tin oxide, titanium oxide, silicon oxide, aluminum oxide, silicon nitride, titanium nitride or one of aluminum nitride.
  • the semiconductor stack layer 40 is used as the first structure layer 20 , the insulating layer 10 is formed on the semiconductor stack layer 40 , and the second insulating layer 12 is away from the semiconductor stack layer 40 .
  • the light emitting diode chip further includes a substrate 50 .
  • the substrate 50 is used as the first structural layer 20, the semiconductor stack layer 40 forms a mesa structure on the substrate 50, and the insulating layer 10 covers at least the sidewall of the semiconductor stack layer 40 and a partial area of the substrate 50 except the semiconductor stack layer 40;
  • the second insulating layer 12 is away from the semiconductor stack layer 40 .
  • the thickness of the second insulating layer 12 is greater than that of the first insulating layer 11 , and the thickness of the second insulating layer 12 is equal to or greater than 1 ⁇ m. Since the second insulating layer 12 has a larger thickness, the second step has a larger slope. When the second structure layer 30 is formed on the second step, the part of the first step beyond the second step can be better for the second step.
  • the structural layer 30 plays a buffering role, reduces the stress generated inside the second structural layer 30, and prevents the second structural layer 30 from cracking or the entire layer breaking under the action of the stress.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction is smaller than the angle ⁇ 2 between the side surface of the second step and the horizontal direction.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle ⁇ 1 ranges from 10° to 30° or 30° to 45°.
  • the side surface of the second step is a slope surface, and the angle ⁇ 2 between the slope surface and the horizontal direction is 20° ⁇ 40°, 40° ⁇ 60° or 60° ⁇ 70°.
  • the sides of the first step and the second step are vertical surfaces.
  • the stepped structure 14 is located at an end or a middle portion of the insulating layer 10 .
  • the insulating layer 10 is provided with a through hole penetrating the insulating layer 10 , and the sidewall of the through hole is configured as a stepped structure 14 ( FIG. 1 ).
  • the end portion of the insulating layer 10 is configured as a stepped structure 14 ( FIG. 2 ).
  • the preparation materials of the first insulating layer 11 and the second insulating layer 12 include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.
  • the material for preparing the first insulating layer 11 is aluminum oxide, and the first insulating layer 11 prepared by using aluminum oxide has good water resistance.
  • the second insulating layer 12 is a distributed Bragg reflector (DBR).
  • the thickness of the first insulating layer 11 is between 30 and 200 nm, preferably, the thickness of the first insulating layer 11 is between 30 and 100 nm; 100-150 nm; or, the thickness of the first insulating layer 11 is between 150-200 nm.
  • the thickness of the first insulating layer 11 is between 400 and 1000 nm, preferably, the thickness of the first insulating layer 11 is between 400 and 600 nm; or, The thickness of the first insulating layer 11 is between 600 and 800 nm; or, the thickness of the first insulating layer 11 is between 800 and 1000 nm.
  • HDPCVD high-density plasma chemical vapor deposition
  • the density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12 .
  • the first insulating layer 11 and the second insulating layer 12 may be prepared by different processes, and the preparation materials may be the same or different.
  • the second insulating layer 12 is a high density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer or an evaporation deposition layer.
  • the first insulating layer 11 is a high density plasma chemical vapor deposition (HDPCVD) layer
  • the second insulating layer 12 is a vapor deposition layer.
  • the first insulating layer 11 and the second insulating layer 12 can also be prepared by the same preparation process, and the preparation materials of the first insulating layer 11 and the second insulating layer 12 are different.
  • the first insulating layer 11 and the second insulating layer 12 are both atomic layer deposition layers, or both the first insulating layer 11 and the second insulating layer 12 are high-density plasma chemical vapor deposition (HDPCVD) layers.
  • HDPCVD high-density plasma chemical vapor deposition
  • the dry etching method is an inductively coupled plasma method (ICP).
  • the length L 1 of the first step beyond the second step in the horizontal direction is equal to or greater than 50 nm, and less than or equal to 5000 nm.
  • the size of the length L 1 is related to the density between the first insulating layer 11 and the second insulating layer 12 .
  • L 1 is equal to or greater than 100 nm and less than or equal to 5000 nm.
  • L 1 is equal to or greater than 50 nm and less than or equal to 100 nm.
  • the insulating layer 10 further includes a third insulating layer 13 formed on the upper surface of the second insulating layer 12 , and correspondingly, the stepped structure 14 further includes a third insulating layer 13 formed by the third insulating layer 13 .
  • the thickness of the third insulating layer 13 is equal to or greater than the thickness of the second insulating layer 12 , and the density of the third insulating layer 13 is equal to or less than the minimum density of the second insulating layer 12 .
  • the third insulating layer 13 , the first insulating layer 11 , and the second insulating layer 12 can be prepared by different processes.
  • the first insulating layer 11 is an atomic layer deposition layer
  • the second insulating layer 12 is a high-density plasma chemical vapor phase. deposition (HDPCVD) layer
  • the third insulating layer 13 is an evaporation deposition layer.
  • the third insulating layer 13 , the first insulating layer 11 and the second insulating layer 12 can also be prepared by the same preparation process, and the preparation materials of the third insulating layer 13 , the first insulating layer 11 and the second insulating layer 12 are different .
  • the light-emitting diode chips provided in this embodiment are different in 1) 85°C+1500mA; 2) 115°C+1500mA; 3) high temperature and high humidity; 4) dual 85°C+15mA and 5) -45°C ⁇ 125°C cold and heat cycles The aging test is carried out under the conditions, and the LED chips after the test have high reliability.
  • this embodiment provides a flip-chip light emitting diode chip.
  • Figure a is an overall structural diagram of the light-emitting diode chip
  • Figure b is an enlarged view of the black frame area in Figure a.
  • the light emitting diode chip includes a substrate 110 and a semiconductor stack layer 120 on the upper surface of the substrate 110 .
  • the semiconductor stack layer 120 forms a mesa structure on the upper surface of the substrate 110 .
  • the semiconductor stack layer 120 includes a first-type semiconductor layer 121 , an active layer 122 and a second-type semiconductor layer 123 sequentially arranged from bottom to top, and is provided with extending from the second-type semiconductor layer 123 to the inside of the first-type semiconductor layer 121 The groove exposes part of the first type semiconductor layer 121 .
  • the first type semiconductor layer 121 is an N type semiconductor layer
  • the second type semiconductor layer 123 is a P type semiconductor layer
  • the active layer 122 is a multilayer quantum well layer.
  • the substrate 110 is a sapphire flat bottom substrate or a sapphire patterned substrate.
  • the light emitting diode chip further includes a current blocking layer 130 , a transparent conductive layer 140 , an electrode layer, a protective layer 160 and a pad layer arranged in sequence.
  • the current blocking layer 130 is formed on the upper surface of the second type semiconductor layer 123 , and the length of the transparent conductive layer 140 is greater than that of the current blocking layer 130 , so that the transparent conductive layer 140 covers the upper surface and sidewalls of the current blocking layer 130 .
  • the electrode layer includes a first electrode 151 electrically connected to the first type semiconductor layer 121 , and a second electrode 152 electrically connected to the second type semiconductor layer 123 .
  • the pad layer includes a first pad 171 electrically connected to the first electrode 151 and a second pad 172 electrically connected to the second electrode 152 .
  • the protective layer 160 covers the upper surface, the sidewalls of the semiconductor stack layer 120 and the upper surface of the substrate 110 except for the semiconductor stack layer 120 .
  • the electrode layer corresponds to the first structure layer
  • the pad layer corresponds to the second structure layer
  • the protective layer 160 corresponds to the insulating layer.
  • the protective layer 160 is provided with through holes at positions corresponding to the first electrode 151 and the second electrode 152, respectively, the first pad 171 fills the through hole and is electrically connected to the first electrode 151, and the second pad 172 fills the through hole and is electrically connected to the first electrode 151.
  • the second electrodes 152 are electrically connected.
  • the sidewalls of the through holes in the protective layer 160 are configured in the above-mentioned stepped structure.
  • the preparation material of the current blocking layer 130 is silicon oxide, specifically including one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.
  • the transparent conductive layer 140 is generally made of a transparent conductive material.
  • the transparent conductive layer 140 is made of indium tin oxide, which mainly plays the role of ohmic contact and lateral current spreading.
  • the preparation materials of the first electrode 151 and the second electrode 152 both include Au or an Au alloy.
  • the structure and preparation material of the protective layer 160 are the same as the structure and preparation material of the insulating layer provided in the above-mentioned embodiment.
  • FIG. 8 this embodiment provides a flip-chip light emitting diode chip.
  • Figure a is an overall structural diagram of the light-emitting diode chip
  • Figure b is an enlarged view of the black frame area in Figure a.
  • the light emitting diode chip includes a substrate 210 and a semiconductor stack layer 220 on the upper surface of the substrate 210 .
  • the semiconductor stack layer 220 forms a mesa structure on the upper surface of the substrate 210 .
  • the semiconductor stack layer 220 includes a first type semiconductor layer 221 , an active layer 222 and a second type semiconductor layer 223 sequentially arranged from bottom to top, and is provided with extending from the second type semiconductor layer 223 to the inside of the first type semiconductor layer 221 The groove exposes part of the first type semiconductor layer 221 .
  • the first type semiconductor layer 221 is an N type semiconductor layer
  • the second type semiconductor layer 223 is a P type semiconductor layer
  • the active layer 222 is a multilayer quantum well layer.
  • the substrate 210 is a sapphire flat bottom substrate or a sapphire patterned substrate.
  • the light emitting diode chip further includes a transparent conductive layer 230, a reflective layer 240, an electrode layer, a first protective layer 260, a first pad 271, a second protective layer 280 and a second pad arranged in sequence 272.
  • the transparent conductive layer 230 is formed on the upper surface of the second type semiconductor layer 223 , and the length of the reflective layer 240 is greater than that of the transparent conductive layer 230 , so that the reflective layer 240 covers the upper surface and sidewalls of the transparent conductive layer 230 .
  • the electrode layer includes a first electrode 251 electrically connected to the first type semiconductor layer 221 and a second electrode 252 electrically connected to the second type semiconductor layer 223 .
  • the first pad 271 is electrically connected to the first electrode 251
  • the second pad 272 is electrically connected to the second electrode 252 .
  • the height of the upper surface of the first pad 271 is smaller than the height of the upper surface of the second pad 272
  • a second protective layer 280 is formed between the first pad 271 and the second pad 272 .
  • the second pads 272 are continuously or intermittently disposed on the upper surface of the second protective layer 280 .
  • the first protective layer 260 and the second protective layer 280 both cover the upper surface, sidewalls of the semiconductor stack layer 220 and regions of the upper surface of the substrate 210 excluding the semiconductor stack layer 220 .
  • the electrode layer corresponds to the above-mentioned first structural layer
  • the pad layer corresponds to the above-mentioned second structural layer
  • the first protective layer 260 and the second protective layer 280 correspond to the above-mentioned insulating layer.
  • a through hole is formed in the first protective layer 260 at a position corresponding to the first electrode 251 , and the first pad 271 fills the through hole and is electrically connected to the first electrode 251 .
  • a through hole is formed in the second protective layer 280 at a position corresponding to the second electrode 252 , and the second pad 272 fills the through hole and is electrically connected to the second electrode 252 . As shown in FIG.
  • the sidewalls of the through holes in the second protective layer 280 are configured in the above-mentioned stepped structure.
  • the sidewalls of the through holes in the first protective layer 260 are also configured as the above-mentioned stepped structure.
  • the transparent conductive layer 230 is generally made of a transparent conductive material.
  • the transparent conductive layer 230 is made of indium tin oxide, which mainly plays the role of ohmic contact and lateral current spreading.
  • the preparation material of the reflective layer 240 is silver.
  • the preparation materials of the first electrode 251 and the second electrode 252 both include Au or an alloy of Au.
  • the structures and preparation materials of the first protective layer 260 and the second protective layer 280 are the same as those of the insulating layers provided in the foregoing embodiments.
  • this embodiment provides a vertical structure light emitting diode chip.
  • Figure a is an overall structural diagram of the light-emitting diode chip
  • Figure b is an enlarged view of the black frame area in Figure a.
  • the light emitting diode chip includes a substrate 310 , a semiconductor stack layer 320 , and a functional layer between the substrate 310 and the semiconductor stack layer 320 .
  • the two sides of the semiconductor stack layer 320 are staggered from the two sides of the substrate 310 , and the two sides of the functional layer are aligned with the two sides of the substrate 310 .
  • Part of the surface, sidewalls and the upper surface of the substrate 310 except for the semiconductor stacked layer 320 are covered with a third protective layer 390, and the third protective layer 390 can use the insulating layer provided in the above embodiment.
  • the semiconductor stack layer 320 includes a first-type semiconductor layer 321 , an active layer 322 and a second-type semiconductor layer 323 sequentially arranged from top to bottom, and is provided with extending from the second-type semiconductor layer 323 to the inside of the first-type semiconductor layer 321 The groove exposes part of the first type semiconductor layer 321 .
  • the first type semiconductor layer 321 is an N type semiconductor layer
  • the second type semiconductor layer 323 is a P type semiconductor layer
  • the active layer 322 is a multilayer quantum well layer.
  • the preparation material of the substrate 310 is selected from GaAs, Ge, Si, Cu, Mo, WCu or MoCu.
  • the functional layer includes a sequentially arranged transparent conductive layer 330 , a first protective layer 340 , a reflective layer 350 , a second protective layer 360 and a first electrode 370 electrically connected to the first type semiconductor layer 321 .
  • the transparent conductive layer 330 is connected to the second type semiconductor layer 323
  • the first electrode 370 is connected to the substrate 310 .
  • a second electrode 380 is provided above the functional layer except for the semiconductor stack layer 320
  • the first protective layer 340 is provided with an opening connecting the reflective layer 350 and the second electrode 380
  • the reflective layer 350 fills the opening and communicates with the second electrode 380 Electrical connection.
  • the transparent conductive layer 330 corresponds to the above-mentioned first structural layer
  • the reflective layer 350 corresponds to the above-mentioned second structural layer
  • the first protective layer 340 corresponds to the above-mentioned insulating layer.
  • the height of the first protective layer 340 is greater than the height of the transparent conductive layer 330 , and covers the periphery of the transparent conductive layer 330 to electrically isolate the transparent conductive layer 340 from the reflective layer 350 .
  • the bottom of the first protective layer 340 is provided with a through hole connecting the reflective layer 350 and the transparent conductive layer 330 , and the reflective layer 350 fills the through hole and is electrically connected to the transparent conductive layer 330 . As shown in FIG.
  • the sidewalls of the through holes in the first protective layer 340 are configured in the above-mentioned stepped structure.
  • the sidewall of the opening in the first protective layer 340 that communicates with the reflective layer 350 and the second electrode 380 is also configured as the above-mentioned stepped structure.
  • the semiconductor stack layer 320 can be equivalent to the above-mentioned first structure layer
  • the third protective layer 390 can be equivalent to the above-mentioned insulating layer
  • other structural layers can be further deposited on the third protective layer 390 .
  • the transparent conductive layer 330 is generally made of a transparent conductive material.
  • the transparent conductive layer 330 is made of indium tin oxide, which mainly plays the role of ohmic contact and lateral current spreading.
  • the preparation material of the second electrode 360 includes any combination of Au, Ti, Al, Cr, Pt, TiW alloy or Ni.
  • the preparation material of the first electrode 380 includes Au or an alloy of Au.
  • the structures and preparation materials of the first protective layer 340 and the second protective layer 370 are the same as those of the insulating layers provided in the above embodiments.
  • FIG. 10 this embodiment provides a light emitting diode chip with a high voltage structure.
  • Figure a is an overall structural diagram of the light-emitting diode chip
  • Figure b is an enlarged view of the black frame area in Figure a.
  • the light emitting diode chip includes a substrate 410 and a plurality of semiconductor stacked layers 420 arranged at intervals, and adjacent semiconductor stacked layers 420 are separated by dicing lines.
  • Each semiconductor stack layer 420 includes a first type semiconductor layer 421 , an active layer 422 and a second type semiconductor layer 423 sequentially arranged from bottom to top, and is provided with extending from the second type semiconductor layer 423 to the first type semiconductor layer
  • the groove inside 421 exposes part of the first type semiconductor layer 421 .
  • the light emitting diode chip further includes a current blocking layer 430 , a transparent conductive layer 440 , an electrode layer, a protective layer 460 and a pad layer arranged in sequence.
  • the current blocking layer 430 covers the upper surface of the second type semiconductor layer 123 , the sidewalls of the semiconductor stack layer 420 and part of the scribe lines.
  • the transparent conductive layer 44 covers part of the current blocking layer 430 .
  • the electrode layers include a first electrode 451 electrically connected to the first type semiconductor layer 421 , a second electrode 452 electrically connected to the second type semiconductor layer 423 , and an interconnection electrode 453 connected to the adjacent semiconductor stack layers 420 .
  • the pad layer includes a first pad 471 electrically connected to the first electrode 451 and a second pad 472 electrically connected to the second electrode 452 .
  • the protective layer 460 covers the upper surface, sidewalls and dicing lines of the semiconductor stack layer 420 .
  • the substrate 410 corresponds to the above-mentioned first structural layer
  • the interconnection electrode 453 corresponds to the above-mentioned second structural layer
  • the current blocking layer 430 corresponds to the above-mentioned insulating layer.
  • the ends of the current blocking layer 430 are configured in the above-described stepped structure.
  • the first electrode 451 and the second electrode 452 correspond to the first structure layer
  • the pad layer corresponds to the second structure layer
  • the protective layer 460 corresponds to the insulating layer.
  • the protective layer 460 is provided with through holes at the positions corresponding to the first electrodes 451 and the second electrodes 452, respectively, the first pads 471 fill the through holes and are electrically connected to the first electrodes 451, and the second pads 472 fill the through holes and connect with the through holes.
  • the second electrodes 452 are electrically connected.
  • the sidewalls of the through holes in the protective layer 460 are also configured as the above-mentioned stepped structure.
  • the preparation material of the current blocking layer 430 is silicon oxide, specifically including one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.
  • the transparent conductive layer 440 is generally made of a transparent conductive material.
  • the transparent conductive layer 440 is made of indium tin oxide, which mainly plays the role of ohmic contact and lateral current spreading.
  • the preparation materials of the first electrode 451, the second electrode 452 and the interconnection electrode 453 all include Au or an alloy of Au.
  • the structure and preparation materials of the protective layer 460 are the same as those of the insulating layers provided in the above-mentioned embodiments.
  • the structures of the light-emitting diode chips involved in Embodiment 1, Embodiment 2, Embodiment 3 and Embodiment 4 are only exemplary, and the light-emitting diode chips claimed in this application are in addition to the above flip-chip structure
  • the light-emitting diode chip, the vertical structure light-emitting diode chip, the high-voltage structure light-emitting diode chip, and the light-emitting diode chip of other structures are also applicable.
  • an insulating layer is provided.
  • the insulating layer 10 at least includes a first insulating layer 11 and a second insulating layer 12 formed on the upper surface of the first insulating layer 11 .
  • the insulating layer 10 has a stepped structure 14.
  • the stepped structure 14 includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12. In the horizontal direction, the first step exceeds the second step. It is described that the first insulating layer 11 protrudes beyond the second insulating layer 12 in the horizontal direction.
  • the insulating layer 10 is formed by at least the first insulating layer 11 and the second insulating layer 12 , which can prevent the insulating layer 10 from cracking or break the whole layer, and improve the reliability of the insulating layer 10 .
  • the first insulating layer 11 exceeds the predetermined length of the second insulating layer 12 in the horizontal direction, and the excess portion can play a buffering role for the second structural layer 30 in the subsequent process of forming the second structural layer 30 on the insulating layer 10 , reducing the stress generated inside the second structure layer 30, avoiding cracks or whole layer fracture of the second structure layer 30 under the action of stress, and improving the reliability of the light emitting diode chip using the insulating layer.
  • the thickness of the second insulating layer 12 is greater than that of the first insulating layer 11 , and the thickness of the second insulating layer 12 is equal to or greater than 1 ⁇ m. Since the second insulating layer 12 has a larger thickness, the second step has a larger slope. When the second structure layer 30 is formed on the second step, the part of the first step beyond the second step can be better for the second step.
  • the structural layer 30 plays a buffering role, reduces the stress generated inside the second structural layer 30, and prevents the second structural layer 30 from cracking or the entire layer breaking under the action of the stress.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction is smaller than the angle ⁇ 2 between the side surface of the second step and the horizontal direction.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle ⁇ 1 ranges from 10° to 30° or 30° to 45°. °.
  • the side surface of the second step is a slope surface, and the angle ⁇ 2 between the slope surface and the horizontal direction is 20° ⁇ 40°, 40° ⁇ 60° or 60° ⁇ 70°.
  • the sides of the first step and the second step are vertical surfaces.
  • the stepped structure 14 is located at an end or a middle portion of the insulating layer 10 .
  • the insulating layer 10 is provided with a through hole penetrating the insulating layer 10 , and the sidewall of the through hole is configured as a stepped structure 14 ( FIG. 11 ).
  • the end portion of the insulating layer 10 is configured as a stepped structure 14 ( FIG. 12 ).
  • the preparation materials of the first insulating layer 11 and the second insulating layer 12 include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.
  • the material for preparing the first insulating layer 11 is aluminum oxide, and the first insulating layer 11 prepared by using aluminum oxide has good water resistance.
  • the second insulating layer 12 is a distributed Bragg reflector (DBR).
  • the thickness of the first insulating layer 11 is between 30 and 200 nm, preferably, the thickness of the first insulating layer 11 is between 30 and 100 nm; 100-150 nm; or, the thickness of the first insulating layer 11 is between 150-200 nm.
  • the thickness of the first insulating layer 11 is between 400 and 1000 nm, preferably, the thickness of the first insulating layer 11 is between 400 and 600 nm; or, The thickness of the first insulating layer 11 is between 600 and 800 nm; or, the thickness of the first insulating layer 11 is between 800 and 1000 nm.
  • HDPCVD high-density plasma chemical vapor deposition
  • the density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12 .
  • the first insulating layer 11 and the second insulating layer 12 may be prepared by different processes, and the preparation materials may be the same or different.
  • the second insulating layer 12 is a high density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer or an evaporation deposition layer.
  • the first insulating layer 11 is a high density plasma chemical vapor deposition (HDPCVD) layer
  • the second insulating layer 12 is a vapor deposition layer.
  • the first insulating layer 11 and the second insulating layer 12 can also be prepared by the same preparation process, and the preparation materials of the first insulating layer 11 and the second insulating layer 12 are different.
  • the first insulating layer 11 and the second insulating layer 12 are both atomic layer deposition layers, or both the first insulating layer 11 and the second insulating layer 12 are high-density plasma chemical vapor deposition (HDPCVD) layers.
  • HDPCVD high-density plasma chemical vapor deposition
  • the dry etching method is an inductively coupled plasma method (ICP).
  • the length L 1 of the first step beyond the second step in the horizontal direction is equal to or greater than 50 nm, and less than or equal to 5000 nm.
  • the size of the length L 1 is related to the density between the first insulating layer 11 and the second insulating layer 12 .
  • L 1 is equal to or greater than 100 nm and less than or equal to 5000 nm.
  • L 1 is equal to or greater than 50 nm and less than or equal to 100 nm.
  • the insulating layer 10 further includes a third insulating layer 13 formed on the upper surface of the second insulating layer 12 , and correspondingly, the stepped structure 14 further includes a third insulating layer 13 formed by the third insulating layer 13 .
  • the thickness of the third insulating layer 13 is equal to or greater than the thickness of the second insulating layer 12 , and the density of the third insulating layer 13 is equal to or less than the minimum density of the second insulating layer 12 .
  • the third insulating layer 13 , the first insulating layer 11 , and the second insulating layer 12 can be prepared by different processes.
  • the first insulating layer 11 is an atomic layer deposition layer
  • the second insulating layer 12 is a high-density plasma chemical vapor phase. deposition (HDPCVD) layer
  • the third insulating layer 13 is an evaporation deposition layer.
  • the third insulating layer 13 , the first insulating layer 11 and the second insulating layer 12 can also be prepared by the same preparation process, and the preparation materials of the third insulating layer 13 , the first insulating layer 11 and the second insulating layer 12 are different .
  • the preparation method includes the following steps:
  • the thickness of the second insulating layer 12 is greater than that of the first insulating layer 11 , and the thickness of the second insulating layer 12 is equal to or greater than 1 ⁇ m.
  • the density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12 .
  • the first insulating layer 11 and the second insulating layer 12 can be fabricated by different processes, and the fabrication materials include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.
  • the first insulating layer 11 is prepared by atomic layer deposition
  • the second insulating layer 12 is prepared by high density plasma chemical vapor deposition (HDPCVD) method, plasma chemical vapor deposition (PECVD) method or vapor deposition method. to make.
  • the first insulating layer 11 is prepared by a high density plasma chemical vapor deposition (HDPCVD) method
  • the second insulating layer 12 is prepared by an evaporation deposition method.
  • the first insulating layer 11 and the second insulating layer 12 can also be prepared by the same preparation process, and the preparation materials of the first insulating layer 11 and the second insulating layer 12 are different.
  • the first insulating layer 11 and the second insulating layer 12 are both prepared by atomic layer deposition, or both the first insulating layer 11 and the second insulating layer 12 are prepared by high density plasma chemical vapor deposition (HDPCVD) method made.
  • HDPCVD high density plasma chemical vapor deposition
  • the material for preparing the first insulating layer 11 is aluminum oxide, and the first insulating layer 11 prepared by using aluminum oxide has good water resistance.
  • the second insulating layer 12 is a distributed Bragg reflector (DBR).
  • the step structure 14 includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12, in the horizontal direction
  • the first step exceeding the second step can also be described as the first insulating layer 11 exceeding the second insulating layer 12 in the horizontal direction.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction is smaller than the angle ⁇ 2 between the side surface of the second step and the horizontal direction.
  • the angle ⁇ 1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle ⁇ 1 ranges from 10° to 30° or 30° to 45°.
  • the side surface of the second step is a slope surface, and the angle ⁇ 2 between the slope surface and the horizontal direction is 20° ⁇ 40°, 40° ⁇ 60° or 60° ⁇ 70°.
  • the sides of the first step and the second step are vertical surfaces.
  • the length L 1 of the first step beyond the second step in the horizontal direction is equal to or greater than 50 nm and less than or equal to 5000 nm.
  • the size of the length L 1 is related to the density between the first insulating layer 11 and the second insulating layer 12 .
  • L 1 is equal to or greater than 100 nm and less than or equal to 5000 nm.
  • L 1 is equal to or greater than 50 nm and less than or equal to 100 nm.
  • step S1 the first insulating layer 10, the second insulating layer 12 and the third insulating layer 13 are prepared; in step S2, the insulating layer 10 is etched, and the step structure 14 is formed on the insulating layer 10,
  • the stepped structure 14 further includes a third step formed by the third insulating layer 13 .
  • the length L 2 of the second step beyond the third step in the horizontal direction is smaller than the length L 1 of the first step beyond the second step.
  • the insulating layer 10 in the present application is formed by at least the first insulating layer 11 and the second insulating layer 12 , which can prevent cracks or whole layer fractures in the insulating layer and improve the reliability of the insulating layer.
  • the first insulating layer 11 exceeds the predetermined length of the second insulating layer 12 in the horizontal direction, then the excess portion can play a buffer role when the second structural layer 30 is formed on the insulating layer 10 subsequently, reducing the size of the second structural layer 30
  • the internal stress can prevent the second structural layer 30 from cracking or the entire layer being broken under the action of stress, thereby improving the reliability of the light-emitting diode chip.
  • the exceeding portion can also block the entry of water vapor to avoid the aging failure of the LED chip.

Abstract

本申请公开了一种发光二极管芯片。该发光二极管芯片包括半导体堆叠层和绝缘层；绝缘层至少包括第一绝缘层和第二绝缘层；绝缘层具有台阶结构，台阶结构包括由第一绝缘层形成的第一台阶和由第二绝缘层形成的第二台阶，在水平方向上第一台阶超出第二台阶。本申请中绝缘层至少由第一绝缘层和第二绝缘层形成，其能够避免绝缘层出现裂缝或者整层断裂，提高绝缘层的可靠性。并且第一绝缘层在水平方向上超出第二绝缘层预定长度，则该超出部分能够在后续第二结构层形成在绝缘层上时起到缓冲作用，减小第二结构层内部所产生的应力，避免第二结构层在应力作用下出现裂缝或者整层断裂，提高发光二极管芯片的可靠性。

Description

发光二极管芯片 技术领域
本申请涉及发光二极管相关技术领域，尤其涉及一种发光二极管芯片。
 背景技术
发光二极管芯片由于可靠性高、寿命长、功耗低的特点，广泛应用于各个领域，其中，发光二极管芯片中的绝缘层大多为单层氧化硅层，且厚度较大，若在单层氧化硅层上形成其他结构层时，由于单层氧化硅层的端部或通孔存在较大坡度，其他结构层形成在单层氧化硅层时，其他结构层的内部产生较大应力，导致其他结构层易出现裂缝或者整层断裂的情况，降低发光二极管芯片的可靠性。
 技术解决方案
本申请的目的在于提供一种发光二极管芯片，其中绝缘层至少由第一绝缘层和第二绝缘层形成，且第一绝缘层在水平方向上超出第二绝缘层预定长度，以在第二结构层形成在第二绝缘层上时减小第二绝缘层内部所产生的应力，避免第二绝缘层在应力作用下出现裂缝或者整层断裂，并提高发光二极管芯片的可靠性。
第一方面，本申请实施例提供了一种发光二极管芯片，具有半导体堆叠层和绝缘层，绝缘层至少包括第一绝缘层和形成于第一绝缘层上表面的第二绝缘层；绝缘层具有台阶结构，台阶结构包括由第一绝缘层形成的第一台阶和由第二绝缘层形成的第二台阶，在水平方向上第一台阶超出第二台阶。
在一种可能的实施方案中，第二绝缘层的厚度大于第一绝缘层的厚度，且第二绝缘层的厚度等于或大于1μm。
在一种可能的实施方案中，第一台阶超出第二台阶的长度L 1等于或者大于 50nm，且小于或等于 5000nm。
在一种可能的实施方案中，第一绝缘层为原子层沉积层时，第一台阶超出第二台阶的长度L 1等于或者大于100nm，且小于或等于5000nm。
在一种可能的实施方案中，第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，第一台阶超出第二台阶的长度L 1等于或者大于50nm，且小于或等于100nm。
在一种可能的实施方案中，第一台阶的侧面与水平方向之间的角度α 1小于第二台阶的侧面与水平方向之间的角度α 2。
在一种可能的实施方案中，第二台阶的侧面为斜坡面，且斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
在一种可能的实施方案中，第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。
在一种可能的实施方案中，绝缘层开设有贯穿该绝缘层的通孔，通孔的侧壁被配置为上述台阶结构；
绝缘层的端部被配置为上述台阶结构。
在一种可能的实施方案中，第一绝缘层为原子层沉积层时，第一绝缘层的厚度介于30~200nm；
第二绝缘层为高密度等离子体化学气相沉积（HDPCVD）层、等离子体化学气相沉积（PECVD）层或蒸镀沉积层。
在一种可能的实施方案中，第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，第一绝缘层的厚度介于400~1000nm；
第二绝缘层为蒸镀沉积层。
在一种可能的实施方案中，第一绝缘层和第二绝缘层由同种制备工艺制备而成，且第一绝缘层和第二绝缘层的制备材料不同；第一绝缘层和第二绝缘层的制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。
在一种可能的实施方案中，第一绝缘层的制备材料为氧化铝。
在一种可能的实施方案中，第二绝缘层为分布式布拉格反射镜（DBR）。
在一种可能的实施方案中，绝缘层还包括形成于第二绝缘层上表面的第三绝缘层；台阶结构还包括由第三绝缘层形成的第三台阶；在水平方向上第二台阶超出第三台阶的长度L 2小于第一台阶超出所述第二台阶的长度L 1。
在一种可能的实施方案中，绝缘层远离第一绝缘层的表面形成有第二结构层，第二结构层的延伸率δ等于或小于50%。
在一种可能的实施方案中，第二结构层的制备材料为镍、金、钛、铬、 氧化铟锡、氧化钛、氧化硅、 氧化铝、氮化硅、氮化钛或氮化铝中的一种。
在一种可能的实施方案中，绝缘层靠近第一绝缘层的表面形成有第一结构层，第一结构层为透明绝缘层、透明导电层或者金属层。
在一种可能的实施方案中，半导体堆叠层作为第一结构层，绝缘层形成在半导体堆叠层上，且第二绝缘层远离半导体堆叠层。
在一种可能的实施方案中，该发光二极管芯片还包括：
衬底，作为第一结构层；半导体堆叠层在衬底上形成台面结构，绝缘层至少覆盖半导体堆叠层的侧壁以及衬底除半导体堆叠层之外的部分区域；第二绝缘层远离半导体堆叠层。
第二方面，本申请实施例提供了一种绝缘层，其至少包括：
第一绝缘层和形成于第一绝缘层上表面的第二绝缘层；
台阶结构，包括由第一绝缘层形成的第一台阶和由第二绝缘层形成的第二台阶，在水平方向上第一台阶超出第二台阶。
在一种可能的实施方案中，第二绝缘层的厚度大于第一绝缘层的厚度，且第二绝缘层的厚度等于或大于1μm。
在一种可能的实施方案中，第一台阶超出第二台阶的长度L 1等于或者大于 50nm，且小于或等于5000nm。
在一种可能的实施方案中，第一绝缘层为原子层沉积层时，第一台阶超出第二台阶的长度L 1等于或者大于100nm，且小于或等于5000nm。
在一种可能的实施方案中，第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，第一台阶超出第二台阶的长度L 1等于或者大于50nm，且小于或等于100nm。
在一种可能的实施方案中，第一台阶的侧面与水平方向之间的角度α 1小于第二台阶的侧面与水平方向之间的角度α 2。
在一种可能的实施方案中，第二台阶的侧面为斜坡面，且斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
在一种可能的实施方案中，第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。
在一种可能的实施方案中，绝缘层开设有贯穿该绝缘层的通孔，通孔的侧壁被配置为上述台阶结构；
绝缘层的端部被配置为上述台阶结构。
在一种可能的实施方案中，第一绝缘层为原子层沉积层时，第一绝缘层的厚度介于30~200nm；
第二绝缘层为高密度等离子体化学气相沉积（HDPCVD）层、等离子体化学气相沉积（PECVD）层或蒸镀沉积层。
在一种可能的实施方案中，第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，第一绝缘层的厚度介于400~1000nm；
第二绝缘层为蒸镀沉积层。
在一种可能的实施方案中，第一绝缘层和第二绝缘层由同种制备工艺制备而成，且第一绝缘层和第二绝缘层的制备材料不同；第一绝缘层和第二绝缘层的制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。
在一种可能的实施方案中，第一绝缘层的制备材料为氧化铝。
在一种可能的实施方案中，第二绝缘层为分布式布拉格反射镜（DBR）。
在一种可能的实施方案中，绝缘层还包括形成于第二绝缘层上表面的第三绝缘层；台阶结构还包括由第三绝缘层形成的第三台阶；在水平方向上第二台阶超出第三台阶的长度L 2小于第一台阶超出所述第二台阶的长度L 1。
有益效果
与现有技术相比，本申请至少具有如下有益效果：
本申请中绝缘层至少由第一绝缘层和第二绝缘层形成，其能够避免绝缘层出现裂缝或者整层断裂，提高绝缘层的可靠性。并且第一绝缘层在水平方向上超出第二绝缘层预定长度，则该超出部分能够在后续第二结构层形成在绝缘层上时起到缓冲作用，减小第二结构层内部所产生的应力，避免第二结构层在应力作用下出现裂缝或者整层断裂，提高发光二极管芯片的可靠性。另外，若第一绝缘层在水平方向上超出第二绝缘层的部分位于绝缘层端部时，该超出部分也能够阻挡水汽进入，避免该发光二极管芯片的老化失效。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图2为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图3为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图4为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图5为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图6为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图7为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图8为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图9为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图10为根据本申请实施例示出的一种发光二极管芯片的截面示意图；
图11为根据本申请实施例示出的一种绝缘层的截面示意图；
图12为根据本申请实施例示出的一种绝缘层的截面示意图；
图13为根据本申请实施例示出的一种绝缘层的截面示意图；
图14为根据本申请实施例示出的一种绝缘层的截面示意图。
图示说明：
10绝缘层；11第一绝缘层；12第二绝缘层；13第三绝缘层；14台阶结构；20第一结构层；30第二结构层；40半导体堆叠层；50衬底；
110衬底；120半导体堆叠层；121第一类型半导体层；122有源层；123第二类型半导体层；130电流阻挡层；140透明导电层；151第一电极；152第二电极；160保护层；171第一焊盘；172第二焊盘；
210衬底；220半导体堆叠层；221第一类型半导体层；222有源层；223第二类型半导体层；230透明导电层；240反射层；251第一电极；252第二电极；260第一保护层；271第一焊盘；272第二焊盘；280第二保护层；
310衬底；320半导体堆叠层；321第一类型半导体层；322有源层；323第二类型半导体层；330透明导电层；340第一保护层；350反射层；360第二保护层；370第一电极；380第二电极；390第三保护层；
410衬底；420半导体堆叠层；421第一类型半导体层；422有源层；423第二类型半导体层；430电流阻挡层；440透明导电层；451第一电极；452第二电极；453互连电极；460保护层；471第一焊盘；472第二焊盘。
 本发明的实施方式
以下通过特定的具体实施例说明本申请的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本申请的其他优点与功效。本申请还可以通过另外不同的具体实施方式加以实施或营业，本申请中的各项细节也可以基于不同观点与应用，在没有背离本申请的精神下进行各种修饰或改变。
在本申请的描述中，需要说明的是，术语“上”、“下”、“高度”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
根据本申请的一个方面，提供一种发光二极管芯片。参见图1和图2，该发光二极管芯片包括半导体堆叠层40和绝缘层10。绝缘层10至少包括第一绝缘层11和形成于第一绝缘层11上表面的第二绝缘层12，且该绝缘层10具有台阶结构14。台阶结构14包括由第一绝缘层11形成的第一台阶和由第二绝缘层12形成的第二台阶，在水平方向上第一台阶超出第二台阶，也可以描述为在水平方向上第一绝缘层11超出第二绝缘层12。
绝缘层10至少由第一绝缘层11和第二绝缘层12形成，其能够避免绝缘层10出现裂缝或者整层断裂，提高绝缘层10的可靠性。并且第一绝缘层11在水平方向上超出第二绝缘层12预定长度，该超出部分能够在后续第二结构层30形成在绝缘层10上时起到缓冲作用，减小第二结构层30内部所产生的应力，避免第二结构层30在应力作用下出现裂缝或者整层断裂，提高发光二极管芯片的可靠性。
在一种实施方式中，参见图1和图2，绝缘层10靠近第一绝缘层11的表面形成有第一结构层20，第一结构层20为透明绝缘层、透明导电层或者金属层。绝缘层10远离第一绝缘层11的表面形成有第二结构层30，该第二结构层30覆盖绝缘层10上表面以及台阶结构14。第二结构层30的延伸率δ等于或小于50%，根据各金属之间的延伸率δ关系：铝70.92%、银54.38%、铜53.2%、镍48.4%、金35%、铂24.2%、钛24.94%、铬20.99%、钨8.84%，第二结构层30的制备材料优选为镍、金、钛、铬、 氧化铟锡、氧化钛、氧化硅、 氧化铝、氮化硅、氮化钛或氮化铝中的一种。
作为可替换的实施方式，参见图5，半导体堆叠层40作为第一结构层20，绝缘层10形成在半导体堆叠层40上，且第二绝缘层12远离半导体堆叠层40。
作为可替换的实施方式，参见图6，该发光二极管芯片还包括衬底50。衬底50作为第一结构层20，半导体堆叠层40在衬底50上形成台面结构，绝缘层10至少覆盖半导体堆叠层40的侧壁以及衬底50除半导体堆叠层40之外的部分区域；第二绝缘层12远离半导体堆叠层40。
在一种实施方式中，第二绝缘层12的厚度大于第一绝缘层11的厚度，且第二绝缘层12的厚度等于或大于1μm。由于第二绝缘层12具有较大厚度，则第二台阶具有较大坡度，在第二结构层30形成在第二台阶时，第一台阶所超出第二台阶的部分能够更好地对第二结构层30起到缓冲作用，减小第二结构层30内部所产生的应力，并避免第二结构层30在应力作用下出现裂缝或者整层断裂。
参见图1和图2，第一台阶的侧面与水平方向之间的角度α 1小于第二台阶的侧面与水平方向之间的角度α 2。优选地，第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。第二台阶的侧面为斜坡面，且斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
作为可替换的实施方式，参见图3，第一台阶和第二台阶的侧面为竖直面。
在一种实施方式中，参见图1和图2，台阶结构14位于绝缘层10的端部或者中间部分。绝缘层10开设有贯穿该绝缘层10的通孔，通孔的侧壁被配置为台阶结构14（图1）。绝缘层10的端部被配置为台阶结构14（图2）。在台阶结构14位于绝缘层10端部时，第一绝缘层11在水平方向上超出第二绝缘层12的部分能够阻挡水汽进入，避免该发光二极管芯片的老化失效。
在一种实施方式中，第一绝缘层11和第二绝缘层12的制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。优选地，第一绝缘层11的制备材料为氧化铝，利用氧化铝所制备成的第一绝缘层11具有良好的防水性。第二绝缘层12为分布式布拉格反射镜（DBR）。
第一绝缘层11为原子层沉积时，第一绝缘层11的厚度介于30~200nm，优选地，第一绝缘层11的厚度介于30~100nm；或者，第一绝缘层11的厚度介于100~150nm；或者，第一绝缘层11的厚度介于150~200nm。第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，第一绝缘层11的厚度介于400~1000nm，优选地，第一绝缘层11的厚度介于400~600nm；或者，第一绝缘层11的厚度介于600~800nm；或者，第一绝缘层11的厚度介于800~1000nm。
第一绝缘层11的致密度大于第二绝缘层12的最大致密度。第一绝缘层11和第二绝缘层12可采用不同工艺制备而成，且制备材料可相同，也可不相同。例如，在第一绝缘层11为原子层沉积层时，第二绝缘层12为高密度等离子体化学气相沉积（HDPCVD）层、等离子体化学气相沉积（PECVD）层或者蒸镀沉积层。在第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，第二绝缘层12为蒸镀沉积层。第一绝缘层11和第二绝缘层12也可采用同种制备工艺制备而成，且第一绝缘层11和第二绝缘层12的制备材料不同。例如，第一绝缘层11和第二绝缘层12均为原子层沉积层，或者，第一绝缘层11和第二绝缘层12均为高密度等离子体化学气相沉积（HDPCVD）层。
由于第一绝缘层11的致密度大于第二绝缘层12的最大致密度，则采用干法刻蚀法或湿法蚀刻法蚀刻绝缘层10时，其对第一绝缘层11的蚀刻速率小于其对第二绝缘层12的蚀刻速率，因此，在绝缘层10形成台阶结构14。优选地，干法刻蚀法为电感藕合等离子体法（ICP）。
在一种实施方式中，参见图1~图3，第一台阶在水平方向上超出第二台阶的长度L 1等于或者大于50nm，且小于或等于5000nm。该长度L 1的大小与第一绝缘层 11和第二绝缘层12之间的致密度有关，第一绝缘层11和第二绝缘层12之间的致密度相差越大，则L 1越大。例如，第一绝缘层11为原子层沉积层时，L 1等于或者大于100nm，且小于或等于5000nm。第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，L 1为等于或者大于50nm，且小于或等于100nm。
在一种实施方式中，参见图4，绝缘层10还包括形成于第二绝缘层12上表面的第三绝缘层13，相对应地，台阶结构14还包括由第三绝缘层13形成的第三台阶。在水平方向上第二台阶超出第三台阶的长度L 2小于第一台阶超出第二台阶的长度L 1。
第三绝缘层13的厚度等于或大于第二绝缘层12的厚度，且第三绝缘层13的致密度等于或小于第二绝缘层12的最小致密度。第三绝缘层13和第一绝缘层11、第二绝缘层12可采用不同工艺制备而成，例如，第一绝缘层11为原子层沉积层，第二绝缘层12为高密度等离子体化学气相沉积（HDPCVD）层，第三绝缘层13为蒸镀沉积层。第三绝缘层13和第一绝缘层11、第二绝缘层12也可采用同种制备工艺制备而成，且第三绝缘层13和第一绝缘层11和第二绝缘层12的制备材料不同。
将本实施例所提供的发光二极管芯片在不同条件下进行试验，验证该发光二极管芯片的可靠性：
本实施例所提供的发光二极管芯片在1）85℃+1500mA；2）115℃+1500mA；3）高温高湿；4）双85℃+15mA以及5）-45℃~125℃冷热循环不同条件下进行老化试验，试验后的发光二极管芯片均具有高的可靠性。
下面以发光二极管芯片的具体实施结构进行示例说明：
实施例 1
参见图7，本实施例提供一种倒装结构的发光二极管芯片。图a为该发光二极管芯片的整体结构图，图b为图a中黑框区域的放大图。该发光二极管芯片包括衬底110及位于衬底110上表面的半导体堆叠层120。半导体堆叠层120在衬底110上表面形成台面结构。半导体堆叠层120包括自下而上顺序排列的第一类型半导体层121、有源层122和第二类型半导体层123，且设有自第二类型半导体层123延伸至第一类型半导体层121内部的凹槽，该凹槽暴露出部分第一类型半导体层121。
较佳地，第一类型半导体层121为N型半导体层，第二类型半导体层123为P型半导体层，有源层122为多层量子阱层。衬底110为蓝宝石平底衬底或蓝宝石图形化衬底。
在一种实施方式中，该发光二极管芯片还包括顺序排列的电流阻挡层130、透明导电层140、电极层、保护层160以及焊盘层。电流阻挡层130形成在第二类型半导体层123的上表面，且透明导电层140的长度大于电流阻挡层130的长度，以使透明导电层140覆盖电流阻挡层130的上表面以及侧壁。电极层包括与第一类型半导体层121电性连接的第一电极151，以及与第二类型半导体层123电性连接的第二电极152。焊盘层包括与第一电极151电性连接的第一焊盘171，以及与第二电极152电性连接的第二焊盘172。保护层160覆盖半导体堆叠层120的上表面、侧壁以及衬底110上表面除半导体堆叠层120之外的区域。
其中，电极层相当于上述第一结构层，焊盘层相当于上述第二结构层，保护层160相当于上述绝缘层。保护层160与第一电极151、第二电极152对应的位置分别开设有通孔，第一焊盘171填充通孔并与第一电极151电性连接，第二焊盘172填充通孔并与第二电极152电性连接。如图b所示，保护层160中通孔的侧壁被配置为上述台阶结构。
较佳地，电流阻挡层130的制备材料为硅的氧化物，具体包括氧化硅、氮化硅、碳化硅或氮氧化硅的一种或多种。
较佳地，透明导电层140的制备材料一般选择具有透明性质的导电材料，在本实施例中，透明导电层140的制备材料为氧化铟锡，其主要起到欧姆接触与横向电流扩展作用。
较佳地，第一电极151和第二电极152的制备材料均包括Au或Au的合金。保护层160的结构和制备材料与上述实施例所提供的绝缘层的结构和制备材料相同。
实施例 2
参见图8，本实施例提供一种倒装结构的发光二极管芯片。图a为该发光二极管芯片的整体结构图，图b为图a中黑框区域的放大图。该发光二极管芯片包括衬底210及位于衬底210上表面的半导体堆叠层220。半导体堆叠层220在衬底210上表面形成台面结构。半导体堆叠层220包括自下而上顺序排列的第一类型半导体层221、有源层222和第二类型半导体层223，且设有自第二类型半导体层223延伸至第一类型半导体层221内部的凹槽，该凹槽暴露出部分第一类型半导体层221。
较佳地，第一类型半导体层221为N型半导体层，第二类型半导体层223为P型半导体层，有源层222为多层量子阱层。衬底210为蓝宝石平底衬底或蓝宝石图形化衬底。
在一种实施方式中，该发光二极管芯片还包括顺序排列的透明导电层230、反射层240、电极层、第一保护层260、第一焊盘271、第二保护层280以及第二焊盘272。透明导电层230形成在第二类型半导体层223的上表面，且反射层240的长度大于透明导电层230的长度，以使反射层240覆盖透明导电层230的上表面以及侧壁。电极层包括与第一类型半导体层221电性连接的第一电极251，以及与第二类型半导体层223电性连接的第二电极252。
第一焊盘271与第一电极251电性连接，第二焊盘272与第二电极252电性连接。第一焊盘271的上表面高度小于第二焊盘272的上表面高度，且第一焊盘271和第二焊盘272之间形成有第二保护层280。第二焊盘272连续或间断设置在第二保护层280上表面。第一保护层260和第二保护层280均覆盖半导体堆叠层220的上表面、侧壁以及衬底210上表面除半导体堆叠层220之外的区域。
其中，电极层相当于上述第一结构层，焊盘层相当于上述第二结构层，第一保护层260和第二保护层280相当于上述绝缘层。第一保护层260与第一电极251对应的位置开设有通孔，第一焊盘271填充该通孔并与第一电极251电性连接。第二保护层280与第二电极252对应的位置开设有通孔，第二焊盘272填充该通孔并与第二电极252电性连接。如图b所示，第二保护层280中通孔的侧壁被配置为上述台阶结构。同理，第一保护层260中通孔的侧壁也被配置为上述台阶结构。
较佳地，透明导电层230的制备材料一般选择具有透明性质的导电材料，在本实施例中，透明导电层230的制备材料为氧化铟锡，其主要起到欧姆接触与横向电流扩展作用。
较佳地，反射层240的制备材料为银。第一电极251和第二电极252的制备材料均包括Au或Au的合金。第一保护层260、第二保护层280的结构和制备材料与上述实施例所提供的绝缘层的结构和制备材料相同。
实施例 3
参见图9，本实施例提供一种垂直结构的发光二极管芯片。图a为该发光二极管芯片的整体结构图，图b为图a中黑框区域的放大图。该发光二极管芯片包括衬底310、半导体堆叠层320以及位于衬底310与半导体堆叠层320之间的功能层。半导体堆叠层320的两侧与衬底310的两侧错位设置，功能层的两侧与衬底310的两侧对齐设置，即半导体堆叠层320在衬底310上表面形成台面结构。半导体堆叠层320的部分表面、侧壁以及衬底310上表面除半导体堆叠层320之外的区域覆盖有第三保护层390，该第三保护层390可采用上述实施例所提供的绝缘层。
半导体堆叠层320包括自上而下顺序排列的第一类型半导体层321、有源层322和第二类型半导体层323，且设有自第二类型半导体层323延伸至第一类型半导体层321内部的凹槽，该凹槽暴露出部分第一类型半导体层321。
较佳地，第一类型半导体层321为N型半导体层，第二类型半导体层323为P型半导体层，有源层322为多层量子阱层。衬底310的制备材料选自GaAs、Ge、Si、Cu、Mo、WCu或MoCu。
在一种实施方式中，功能层包括顺序排列的透明导电层330、第一保护层340、反射层350、第二保护层360以及与第一类型半导体层321电性连接的第一电极370。透明导电层330与第二类型半导体层323连接，第一电极370与衬底310连接。功能层上方除半导体堆叠层320之外的区域设有第二电极380，第一保护层340设有连通反射层350和第二电极380的开口，反射层350填充该开口并与第二电极380电性连接。
其中，透明导电层330相当于上述第一结构层，反射层350相当于上述第二结构层，第一保护层340相当于上述绝缘层。第一保护层340的高度大于透明导电层330的高度，并包覆在透明导电层330的外围，以将透明导电层340与反射层350电性隔离。第一保护层340的底部设有连通反射层350和透明导电层330的通孔，反射层350填充该通孔并与透明导电层330电性连接。如图b所示，第一保护层340中通孔的侧壁被配置为上述台阶结构。同理，第一保护层340中连通反射层350和第二电极380的开口的侧壁也被配置为上述台阶结构。
半导体堆叠层320可相当于上述第一结构层，第三保护层390相当于上述绝缘层，在第三保护层390上可继续沉积形成其他结构层。
较佳地，透明导电层330的制备材料一般选择具有透明性质的导电材料，在本实施例中，透明导电层330的制备材料为氧化铟锡，其主要起到欧姆接触与横向电流扩展作用。
较佳地，第二电极360的制备材料包括Au、Ti、Al、Cr、Pt、TiW合金或Ni的任意组合。第一电极380的制备材料包括Au或Au的合金。
较佳地，第一保护层340和第二保护层370的结构和制备材料与上述实施例所提供的绝缘层的结构和制备材料相同。
实施例 4
参见图10，本实施例提供一种高压结构的发光二极管芯片。图a为该发光二极管芯片的整体结构图，图b为图a中黑框区域的放大图。该发光二极管芯片包括衬底410及多个间隔布置的半导体堆叠层420，相邻半导体堆叠层420通过切割道相隔开。每个半导体堆叠层420包括自下而上顺序排列的第一类型半导体层421、有源层422和第二类型半导体层423，且设有自第二类型半导体层423延伸至第一类型半导体层421内部的凹槽，该凹槽暴露出部分第一类型半导体层421。
在一种实施方式中，该发光二极管芯片还包括顺序排列的电流阻挡层430、透明导电层440、电极层、保护层460以及焊盘层。电流阻挡层430覆盖第二类型半导体层123上表面、半导体堆叠层420侧壁以及部分切割道。透明导电层44覆盖部分电流阻挡层430。电极层包括与第一类型半导体层421电性连接的第一电极451，与第二类型半导体层423电性连接的第二电极452，以及连接相邻半导体堆叠层420的互连电极453。焊盘层包括与第一电极451电性连接的第一焊盘471，以及与第二电极452电性连接的第二焊盘472。保护层460覆盖半导体堆叠层420的上表面、侧壁以及切割道。
其中，衬底410相当于上述第一结构层，互连电极453相当于上述第二结构层，电流阻挡层430相当于上述绝缘层。如图b所示，电流阻挡层430的端部被配置为上述台阶结构。
电极层中第一电极451、第二电极452相当于上述第一结构层，焊盘层相当于上述第二结构层，保护层460相当于上述绝缘层。保护层460与第一电极451、第二电极452对应的位置分别开设有通孔，第一焊盘471填充通孔并与第一电极451电性连接，第二焊盘472填充通孔并与第二电极452电性连接。同理，保护层460中通孔的侧壁也被配置为上述台阶结构。
较佳地，电流阻挡层430的制备材料为硅的氧化物，具体包括氧化硅、氮化硅、碳化硅或氮氧化硅的一种或多种。
较佳地，透明导电层440的制备材料一般选择具有透明性质的导电材料，在本实施例中，透明导电层440的制备材料为氧化铟锡，其主要起到欧姆接触与横向电流扩展作用。
较佳地，第一电极451、第二电极452和互连电极453的制备材料均包括Au或Au的合金。保护层460的结构和制备材料与上述实施例所提供的绝缘层的结构和制备材料相同。
需要说明的是，实施例1、实施例2、实施例3以及实施例4所涉及到的发光二极管芯片的结构仅是示例性的，本申请中所要求保护的发光二极管芯片除了上述倒装结构的发光二极管芯片、垂直结构的发光二极管芯片、高压结构的发光二极管芯片，还适用于其他结构的发光二极管芯片。
根据本申请的一个方面，提供了一种绝缘层。参见图11和图12，该绝缘层10至少包括第一绝缘层11和形成于第一绝缘层11上表面的第二绝缘层12。绝缘层10具有台阶结构14，台阶结构14包括由第一绝缘层11形成的第一台阶和由第二绝缘层12形成的第二台阶，在水平方向上第一台阶超出第二台阶，也可以描述为在水平方向上第一绝缘层11超出第二绝缘层12。
绝缘层10至少由第一绝缘层11和第二绝缘层12形成，其能够避免绝缘层10出现裂缝或者整层断裂，提高绝缘层10的可靠性。并且第一绝缘层11在水平方向上超出第二绝缘层12预定长度，该超出部分能够在后续第二结构层30形成在绝缘层10上的工艺中，对第二结构层30起到缓冲作用，减小第二结构层30内部所产生的应力，避免第二结构层30在应力作用下出现裂缝或者整层断裂，提高使用该绝缘层的发光二极管芯片的可靠性。
在一种实施方式中，第二绝缘层12的厚度大于第一绝缘层11的厚度，且第二绝缘层12的厚度等于或大于1μm。由于第二绝缘层12具有较大厚度，则第二台阶具有较大坡度，在第二结构层30形成在第二台阶时，第一台阶所超出第二台阶的部分能够更好地对第二结构层30起到缓冲作用，减小第二结构层30内部所产生的应力，并避免第二结构层30在应力作用下出现裂缝或者整层断裂。
参见图11和图12，第一台阶的侧面与水平方向之间的角度α 1小于第二台阶的侧面与水平方向之间的角度α 2。优选地，第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。°。第二台阶的侧面为斜坡面，且斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
作为可替换的实施方式，参见图13，第一台阶和第二台阶的侧面为竖直面。
在一种实施方式中，参见图11和图12，台阶结构14位于绝缘层10的端部或者中间部分。绝缘层10开设有贯穿该绝缘层10的通孔，通孔的侧壁被配置为台阶结构14（图11）。绝缘层10的端部被配置为台阶结构14（图12）。在台阶结构14位于绝缘层10端部时，第一绝缘层11在水平方向上超出第二绝缘层12的部分能够阻挡水汽进入，避免该发光二极管芯片的老化失效。
在一种实施方式中，第一绝缘层11和第二绝缘层12的制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。优选地，第一绝缘层11的制备材料为氧化铝，利用氧化铝所制备成的第一绝缘层11具有良好的防水性。第二绝缘层12为分布式布拉格反射镜（DBR）。
第一绝缘层11为原子层沉积时，第一绝缘层11的厚度介于30~200nm，优选地，第一绝缘层11的厚度介于30~100nm；或者，第一绝缘层11的厚度介于100~150nm；或者，第一绝缘层11的厚度介于150~200nm。第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，第一绝缘层11的厚度介于400~1000nm，优选地，第一绝缘层11的厚度介于400~600nm；或者，第一绝缘层11的厚度介于600~800nm；或者，第一绝缘层11的厚度介于800~1000nm。
第一绝缘层11的致密度大于第二绝缘层12的最大致密度。第一绝缘层11和第二绝缘层12可采用不同工艺制备而成，且制备材料可相同，也可不相同。例如，在第一绝缘层11为原子层沉积层时，第二绝缘层12为高密度等离子体化学气相沉积（HDPCVD）层、等离子体化学气相沉积（PECVD）层或者蒸镀沉积层。在第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，第二绝缘层12为蒸镀沉积层。第一绝缘层11和第二绝缘层12也可采用同种制备工艺制备而成，且第一绝缘层11和第二绝缘层12的制备材料不同。例如，第一绝缘层11和第二绝缘层12均为原子层沉积层，或者，第一绝缘层11和第二绝缘层12均为高密度等离子体化学气相沉积（HDPCVD）层。
由于第一绝缘层11的致密度大于第二绝缘层12的最大致密度，则采用干法刻蚀法或湿法蚀刻法蚀刻绝缘层10时，其对第一绝缘层11的蚀刻速率小于其对第二绝缘层12的蚀刻速率，因此，在绝缘层10形成台阶结构14。优选地，干法刻蚀法为电感藕合等离子体法（ICP）。
在一种实施方式中，参见图11~图13，第一台阶在水平方向上超出第二台阶的长度L 1等于或者大于50nm，且小于或等于5000nm。该长度L 1的大小与第一绝缘层11和第二绝缘层12之间的致密度有关，第一绝缘层11和第二绝缘层12之间的致密度相差越大，则L 1越大。例如，第一绝缘层11为原子层沉积层时，L 1等于或者大于100nm，且小于或等于5000nm。第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，L 1等于或者大于50nm，且小于或等于100nm。
在一种实施方式中，参见图14，绝缘层10还包括形成于第二绝缘层12上表面的第三绝缘层13，相对应地，台阶结构14还包括由第三绝缘层13形成的第三台阶。在水平方向上第二台阶超出第三台阶的长度L 2小于第一台阶超出第二台阶的长度L 1。
第三绝缘层13的厚度等于或大于第二绝缘层12的厚度，且第三绝缘层13的致密度等于或小于第二绝缘层12的最小致密度。第三绝缘层13和第一绝缘层11、第二绝缘层12可采用不同工艺制备而成，例如，第一绝缘层11为原子层沉积层，第二绝缘层12为高密度等离子体化学气相沉积（HDPCVD）层，第三绝缘层13为蒸镀沉积层。第三绝缘层13和第一绝缘层11、第二绝缘层12也可采用同种制备工艺制备而成，且第三绝缘层13和第一绝缘层11和第二绝缘层12的制备材料不同。
根据本申请的一个方面，提供了一种上述实施例中绝缘层的制备方法。该制备方法包括以下步骤：
S1、制备第一绝缘层11和第二绝缘层12。第二绝缘层12的厚度大于第一绝缘层11的厚度，且第二绝缘层12的厚度等于或大于1μm。
第一绝缘层11的致密度大于第二绝缘层12的最大致密度。第一绝缘层11和第二绝缘层12可采用不同工艺制备而成，其制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。例如，第一绝缘层11由原子层沉积法制备而成，第二绝缘层12由高密度等离子体化学气相沉积（HDPCVD）法、等离子体化学气相沉积（PECVD）法或者蒸镀沉积法制备而成。或者，第一绝缘层11由高密度等离子体化学气相沉积（HDPCVD）法制备而成，第二绝缘层12由蒸镀沉积法制备而成。
第一绝缘层11和第二绝缘层12也可采用同种制备工艺制备而成，且第一绝缘层11和第二绝缘层12的制备材料不同。例如，第一绝缘层11和第二绝缘层12均由原子层沉积法制备而成，或者，第一绝缘层11和第二绝缘层12均由高密度等离子体化学气相沉积（HDPCVD）法制备而成。
优选地，第一绝缘层11的制备材料为氧化铝，利用氧化铝所制备成的第一绝缘层11具有良好的防水性。第二绝缘层12为分布式布拉格反射镜（DBR）。
S2、蚀刻绝缘层10，并在绝缘层10上形成台阶结构14；台阶结构14包括由第一绝缘层11形成的第一台阶和由第二绝缘层12形成的第二台阶，在水平方向上第一台阶超出第二台阶，也可以描述为在水平方向上第一绝缘层11超出第二绝缘层12。
第一台阶的侧面与水平方向之间的角度α 1小于第二台阶的侧面与水平方向之间的角度α 2。优选地，第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。第二台阶的侧面为斜坡面，且斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
作为可替换的实施方式，第一台阶和第二台阶的侧面为竖直面。
较佳地，第一台阶在水平方向上超出第二台阶的长度L 1等于或者大于50nm，且小于或等于5000nm。该长度L 1的大小与第一绝缘层11和第二绝缘层12之间的致密度有关，第一绝缘层11和第二绝缘层12之间的致密度相差越大，则L 1越大。例如，第一绝缘层11为原子层沉积层时，L 1等于或者大于100nm，且小于或等于5000nm。第一绝缘层11为高密度等离子体化学气相沉积（HDPCVD）层时，L 1等于或者大于50nm，且小于或等于100nm。
在一种实施方式中，步骤S1中，制备第一绝缘层10、第二绝缘层12和第三绝缘层13；步骤S2中，蚀刻绝缘层10，并在绝缘层10上形成台阶结构14，该台阶结构14还包括由第三绝缘层13形成的第三台阶。在水平方向上第二台阶超出第三台阶的长度L 2小于第一台阶超出第二台阶的长度L 1。
由以上的技术方案可知，本申请中绝缘层10至少由第一绝缘层11和第二绝缘层12形成，其能够避免绝缘层出现裂缝或者整层断裂，提高绝缘层的可靠性。并且第一绝缘层11在水平方向上超出第二绝缘层12预定长度，则该超出部分能够在后续第二结构层30形成在绝缘层10上时起到缓冲作用，减小第二结构层30内部所产生的应力，避免第二结构层30在应力作用下出现裂缝或者整层断裂，提高发光二极管芯片的可靠性。另外，若第一绝缘层11在水平方向上超出第二绝缘层12的部分位于绝缘层10端部时，该超出部分也能够阻挡水汽进入，避免该发光二极管芯片的老化失效。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本申请的保护范围。

Claims (20)

  1. 一种发光二极管芯片，具有半导体堆叠层和绝缘层，其特征在于，所述绝缘层至少包括第一绝缘层和形成于所述第一绝缘层上表面的第二绝缘层；所述绝缘层具有台阶结构，所述台阶结构包括由所述第一绝缘层形成的第一台阶和由所述第二绝缘层形成的第二台阶，在水平方向上所述第一台阶超出所述第二台阶。
  2. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第二绝缘层的厚度大于所述第一绝缘层的厚度，且所述第二绝缘层的厚度等于或大于1μm。
  3. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一台阶超出所述第二台阶的长度L 1等于或者大于50nm，且小于或等于 5000nm。
  4. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层为原子层沉积层时，所述第一台阶超出所述第二台阶的长度L 1等于或者大于100nm，且小于或等于5000nm。
  5. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，所述第一台阶超出所述第二台阶的长度L 1等于或者大于50nm，且小于或等于100nm。
  6. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一台阶的侧面与水平方向之间的角度α 1小于所述第二台阶的侧面与水平方向之间的角度α 2。
  7. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第二台阶的侧面为斜坡面，且所述斜坡面与水平方向之间的角度α 2介于20°~40°、40°~60°或者60°~70°。
  8. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一台阶的侧面与水平方向之间的角度α 1在竖直方向上递减，且该角度α 1介于10°~30°或者30°~45°。
  9. 根据权利要求1所述的发光二极管芯片，其特征在于，所述绝缘层开设有贯穿该绝缘层的通孔，所述通孔的侧壁被配置为所述台阶结构；
    所述绝缘层的端部被配置为所述台阶结构。
  10. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层为原子层沉积层时，所述第一绝缘层的厚度介于30~200nm；
    所述第二绝缘层为高密度等离子体化学气相沉积（HDPCVD）层、等离子体化学气相沉积（PECVD）层或蒸镀沉积层。
  11. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层为高密度等离子体化学气相沉积（HDPCVD）层时，所述第一绝缘层的厚度介于400~1000nm；
    所述第二绝缘层为蒸镀沉积层。
  12. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层和第二绝缘层由同种制备工艺制备而成，且所述第一绝缘层和第二绝缘层的制备材料不同；所述第一绝缘层和第二绝缘层的制备材料包括氧化硅、氮化硅、氮氧化硅、氧化铝或氧化钛的一种或多种。
  13. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第一绝缘层的制备材料为氧化铝。
  14. 根据权利要求1所述的发光二极管芯片，其特征在于，所述第二绝缘层为分布式布拉格反射镜（DBR）。
  15. 根据权利要求1所述的发光二极管芯片，其特征在于，所述绝缘层还包括形成于所述第二绝缘层上表面的第三绝缘层；所述台阶结构还包括由所述第三绝缘层形成的第三台阶；在水平方向上所述第二台阶超出所述第三台阶的长度L 2小于所述第一台阶超出所述第二台阶的长度L 1。
  16. 根据权利要求1所述的发光二极管芯片，其特征在于，所述绝缘层远离第一绝缘层的表面形成有第二结构层，所述第二结构层的延伸率δ等于或小于50%。
  17. 根据权利要求16所述的发光二极管芯片，其特征在于，所述第二结构层的制备材料为镍、金、钛、铬、 氧化铟锡、氧化钛、氧化硅、 氧化铝、氮化硅、氮化钛或氮化铝中的一种。
  18. 根据权利要求1所述的发光二极管芯片，其特征在于，所述绝缘层靠近第一绝缘层的表面形成有第一结构层，所述第一结构层为透明绝缘层、透明导电层或者金属层。
  19. 根据权利要求1所述的发光二极管芯片，其特征在于，所述半导体堆叠层作为第一结构层，所述绝缘层形成在所述半导体堆叠层上，且所述第二绝缘层远离所述半导体堆叠层。
  20. 根据权利要求1所述的发光二极管芯片，其特征在于，还包括：
    衬底，作为第一结构层；所述半导体堆叠层在所述衬底上形成台面结构，所述绝缘层至少覆盖所述半导体堆叠层的侧壁以及所述衬底除半导体堆叠层之外的部分区域；所述第二绝缘层远离所述半导体堆叠层。
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