WO2022218026A1 - 光电器件及其制造方法 - Google Patents

光电器件及其制造方法 Download PDF

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WO2022218026A1
WO2022218026A1 PCT/CN2022/076206 CN2022076206W WO2022218026A1 WO 2022218026 A1 WO2022218026 A1 WO 2022218026A1 CN 2022076206 W CN2022076206 W CN 2022076206W WO 2022218026 A1 WO2022218026 A1 WO 2022218026A1
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layer
insulating layer
optoelectronic device
partial area
luminescent material
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PCT/CN2022/076206
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English (en)
French (fr)
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狄大卫
徐宠恩
田顺
连亚霄
赵保丹
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浙江大学
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Priority to KR1020227042024A priority Critical patent/KR20230034209A/ko
Priority to JP2022574337A priority patent/JP2023530077A/ja
Publication of WO2022218026A1 publication Critical patent/WO2022218026A1/zh
Priority to US18/072,584 priority patent/US11818941B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/135—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising mobile ions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/221—Changing the shape of the active layer in the devices, e.g. patterning by lift-off techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/50—Organic perovskites; Hybrid organic-inorganic perovskites [HOIP], e.g. CH3NH3PbI3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/15—Hole transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/16—Electron transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/30—Coordination compounds

Definitions

  • the present invention relates to semiconductor technology, in particular to an optoelectronic device.
  • mini-LED and micro-LED small and micro light-emitting diodes
  • mini-LED and micro-LED have received extensive attention due to their low power consumption, high contrast ratio, high brightness, high response speed, and high efficiency.
  • some high-end miniaturized LED displays have been launched on the market, such as Samsung's "The Wall” display wall and PlayNitride's “PixelLED display”, which have been recognized by the industry.
  • the current mini-LEDs and micro-LEDs have the above advantages, the quality requirements for III-V epitaxial semiconductors have become more stringent.
  • metal halide perovskites have emerged as an emerging semiconductor material with properties similar to III-V materials.
  • PeLEDs halide perovskite light-emitting diodes
  • the present application provides a method for manufacturing an optoelectronic device.
  • the feature size of a single light-emitting pixel or effective working area of the optoelectronic device is less than or equal to 500 microns, including: S1: providing a semiconductor substrate; S2: forming a photoresist layer ; S3: Use a mask to expose and develop the photoresist layer, so that the first partial area on the semiconductor substrate is protected by the remaining photoresist layer, and the second partial area around the first partial area is exposed.
  • S4 form a first insulating layer, the first insulating layer covers the upper surface of the remaining photoresist layer, the upper surface of the semiconductor substrate corresponding to the second partial area, and the thickness of the photoresist layer is greater than that of the first layer Thickness of the insulating layer;
  • S5 performing a degumming process to remove the remaining photoresist layer and the first insulating layer on the remaining photoresist layer;
  • S6 forming a first transmission layer to cover the first transmission layer The upper surface of the first insulating layer and the semiconductor substrate in the first partial area;
  • S7 forming an interface layer on the first transport layer;
  • S8 forming a light-emitting material layer on the interface layer;
  • S9 forming a second layer layer insulating layer, so that the second insulating layer covers the luminescent material layer located in the second partial area, and covers the luminescent material layer located in the first partial area adjacent to the side of the second partial area, so that the central area in the first partial area is
  • S11 is also included: forming a metal electrode on the electron transport layer in the central region in the first partial region, and extending the metal electrode to the second insulating layer on one side of the central region.
  • the first transport layer is a hole transport layer.
  • the interface layer is a lithium fluoride layer.
  • the material of the first insulating layer is any one of silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, and aluminum nitride, or a combination of multiple materials.
  • the light-emitting material layer is a perovskite material layer.
  • the light-emitting material layer is one of perovskite material and organic material, III-V group material, II-VI group material, IV group material, rare earth material, oxide material, semiconductor nanomaterial, insulating material or various combinations.
  • the luminescent material layer is in direct contact with the interface layer.
  • the second insulating layer is a lithium fluoride layer.
  • the position where the second insulating layer is formed is limited by a mask, so that only the luminescent material layer in the first partial region adjacent to the side of the second partial region is covered by the second insulating layer.
  • the position where the electron transport layer is formed is restricted by a mask, so that the electron transport layer is formed only in the central region of the first partial region.
  • the present invention also provides an optoelectronic device, the characteristic size of a single light-emitting pixel point or effective working area of the optoelectronic device is less than or equal to 500 microns, comprising: a semiconductor substrate, wherein a first transmission is formed on a first partial area of the semiconductor substrate layer, a first insulating layer is formed on the second partial area around the first partial area, and a first transmission layer is formed on the first insulating layer; an interface layer is formed on the first transmission layer; on the interface layer A layer of luminescent material is formed thereon; a second insulating layer is formed on the luminescent material layer in the second partial area and on the luminescent material layer adjacent to the second partial area in the first partial area, and the center in the first partial area An electron transport layer is formed on the luminescent material layer in the region.
  • the first transport layer is a hole transport layer.
  • the interface layer and the second insulating layer are lithium fluoride layers.
  • the light-emitting material layer is a perovskite material layer.
  • the luminescent material layer is in direct contact with the interface layer.
  • the material of the first insulating layer is any one of silicon dioxide, aluminum oxide, silicon nitride, silicon carbide, and aluminum nitride, or a combination of multiple materials.
  • 1 to 12 are schematic cross-sectional views of one of the manufacturing processes of the optoelectronic device according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of photoelectric performance test data of an optoelectronic device according to an embodiment of the present application and an optoelectronic device formed by using the optoelectronic device according to an embodiment of the present application.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • a method for manufacturing an optoelectronic device wherein the feature size of a single light-emitting pixel or effective working area of the optoelectronic device is less than or equal to 500 microns.
  • perovskite light-emitting diodes As an example, generally the feature size of a single light-emitting pixel or effective working area is greater than or equal to 200 microns and less than or equal to 500 microns is a small perovskite light-emitting diode (mini-PeLED), a single light-emitting pixel point Or the feature size of the effective working area is less than or equal to 200 microns is a micro-perovskite light-emitting diode (micro-PeLED).
  • mini-PeLED small perovskite light-emitting diode
  • micro-PeLED micro-perovskite light-emitting diode
  • S1 provide a semiconductor substrate
  • a semiconductor substrate 1 is provided, and the semiconductor substrate 1 can be formed of any material that can be used as a substrate, such as conductive glass (FTO), silicon substrate, polytetrafluoroethylene (PTFE), pressure Electric ceramics, etc.
  • FTO conductive glass
  • PTFE polytetrafluoroethylene
  • pressure Electric ceramics etc.
  • the semiconductor substrate can be ultrasonically cleaned for 15 minutes in five steps of deionized water, acetone, isopropanol, deionized water, and isopropanol, respectively, before use.
  • the cleaned semiconductor substrate was placed in a UV ozone cleaning machine for 30 minutes of ozone cleaning.
  • a photoresist layer 2 is formed on the semiconductor substrate 1 .
  • the photoresist layer 2 can be formed from a negative photoresist solution or a positive photoresist solution.
  • 50 ⁇ L of negative photoresist solution can be applied to the semiconductor substrate 1 with a pipette with a range of 100 ⁇ L, and then the vacuum spin coater is turned on for 60 s at a rotational speed of 4000 r.p.m. to obtain a photoresist layer 2 with a thickness of about 420 nm. .
  • the thickness of the photoresist layer 2 is 420 nm.
  • the thickness of the above-mentioned photoresist layer 2 may have a certain deviation of 420 nm, and the deviation may be 20%, preferably 10%, and more preferably 5%. Specifically, it can be any value between 380 nm and 460 nm.
  • the first partial area 11 on the semiconductor substrate 1 is protected by the remaining photoresist layer 21 , and the second partial area 12 around the first partial area 11 is revealed, that is, the second partial area The semiconductor substrate 1 corresponding to 12 is exposed.
  • the exposed negative photoresist is shown.
  • rinse with isopropyl alcohol (IPA) several times to wash off the unexposed negative photoresist, and then bake it on a hot stage at 85° C. for 20 minutes to obtain the structure shown in FIG. 4 .
  • IPA isopropyl alcohol
  • a first insulating layer 3 is formed, and the first insulating layer 3 covers the upper surface of the remaining photoresist layer 21 (that is, the photoresist layer in the first partial area 11 ), the exposed semiconductor substrate The upper surface of the bottom 1 (ie, the semiconductor substrate corresponding to the second partial region 12 ), and the thickness of the photoresist layer 21 is greater than the thickness of the first insulating layer 3 .
  • the thickness of the first insulating layer is any value between 40 nm and 80 nm.
  • the thickness of the first insulating layer is 60 nm.
  • the material of the first insulating layer 3 may be silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), nitrogen Any one or a combination of materials of aluminum oxide (AlN).
  • the material of the first insulating layer 3 is silicon dioxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ).
  • the first insulating layer 3 is formed by at least one process of magnetron sputtering, MOCVD, thermal evaporation, and the like.
  • the remaining photoresist layer 21 and the first insulating layer 3 located on the remaining photoresist layer 21 are removed, so that the semiconductor substrate 1 in the first partial region 11 is exposed, while the remaining photoresist layer 21 remains exposed.
  • the first insulating layer 3 in the second partial region 12 Specifically, the structure formed in step S4 is immersed in a degumming solution for 12 hours for degumming, and the structure shown in FIG. 6 is obtained. Rinse with deionized water, acetone and isopropanol in sequence for 5 minutes, and put it into a UV ozone cleaning machine for 30 minutes of ozone cleaning.
  • the first transfer layer 4 covers the upper surface of the first insulating layer 3 and the semiconductor substrate 1 in the first partial region 11 .
  • the first transport layer 4 is a hole transport layer. In one embodiment, it includes nickel oxide (NiO x ) and poly(9-vinylcarbazole) (PVK).
  • Nickel oxide (NiO x ) powder was purchased from Beijing Huamin New Material Technology Co., Ltd., dispersed in deionized water, the concentration was 15 mg/mL, and 50 ⁇ L of NiO x solution was drawn with a pipette with a range of 100 ⁇ L and applied to the solution after step S5.
  • the vacuum spin coater was turned on to spin at 4000 rpm for 60 s, and the NiO x structure after spin coating was placed on a hot stage for annealing at 150° C. for 15 min.
  • PVK was purchased from Sigma-aldrich, with an average molecular weight of 25,000-50,000. It was dissolved in chlorobenzene (CB) at a concentration of 6 mg/mL. The PVK solution was drawn with a 100 ⁇ L pipette to coat 50 uL of PVK solution, and the vacuum spin coater was turned on. Spin coating at 4500r.pm for 60s, and then placed on a hot stage for annealing at 150°C for 30min to form.
  • CB chlorobenzene
  • the hole transport layer can be an organic hole transport layer and an inorganic hole transport layer, wherein the organic hole transport layer includes but is not limited to: TFB, PTAA, TAPC, PEDOT:PSS, Poly-TPD, PVK, TCTA, CBP, TPD , at least one of CuPc, M-MTDATA, NPB, Rubrene; inorganic hole transport layers include but are not limited to: copper oxide (CuO), nickel oxide (NiO x ), molybdenum trioxide (MoO 3 ), tungsten trioxide At least one of (WO 3 ) and vanadium pentoxide (V 2 O 5 ).
  • the organic hole transport layer includes but is not limited to: TFB, PTAA, TAPC, PEDOT:PSS, Poly-TPD, PVK, TCTA, CBP, TPD , at least one of CuPc, M-MTDATA, NPB, Rubrene
  • inorganic hole transport layers include but are not limited to: copper oxide (CuO),
  • the thickness of the first transmission layer 4 can be designed according to the requirements of different devices.
  • an interface layer 5 is formed on the first transport layer 4 .
  • the interface layer 5 is a lithium fluoride (LiF) layer, and the interface layer 5 can also be sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride ( A combination of one or more of CsF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), and the like.
  • the thickness of the interface layer 5 is any value between 0.7 nm and 1.3 nm, and preferably, the thickness of the interface layer 5 is 1 nm.
  • the structure formed in step S6 is transferred to a vacuum coating machine for polar interface, such as LiF, vapor deposition.
  • a vacuum coating machine for polar interface such as LiF
  • the pressure of vacuum evaporation was 5 ⁇ 10 -4 Pa
  • the evaporation rate was measured by a quartz crystal oscillator
  • the evaporation rate was 0.1 nm/s until the evaporation was completed.
  • the interface layer 5 can play an insulating role.
  • a light-emitting material layer 6 is formed on the interface layer 5 .
  • the luminescent material layer 6 can be formed of any electroluminescent material, and any electroluminescent material currently available or generated with the development of technology is within the protection scope of the present application. Such as organic light-emitting materials, perovskite materials, or quantum dot materials.
  • the light-emitting material layer 6 is a perovskite material layer.
  • Metal halide perovskites are emerging semiconductor materials with properties similar to III-V materials.
  • the light-emitting material layer is a perovskite material and an organic material, a group III-V material, a group II-VI material, a group IV material, a rare earth material, an oxide material, a semiconductor nanomaterial, an insulating material, and the like.
  • the organic material includes small molecules and polymers.
  • the structure after step S7 is transferred to a glove box filled with high-purity nitrogen and spin-coated with the perovskite material layer as the light-emitting material layer 6 .
  • the perovskite precursor solution is MOPEA n Cs x FA 1-x Pbn Br 3n+1 , which is composed of 110 mg of lead bromide (PbBr 2 ), 64 mg of cesium bromide (CsBr), 6 mg of formamidine Hydroiodide (FABr) and 28 mg of 2-(4-methoxyphenyl)ethylamine hydrobromide (MOPEABr) and 5.5 mg of 18-crown-6 were dissolved in 1 mL of dimethyl sulfoxide (DMSO) solution, the solution concentration is 0.3M. Then, the prepared 0.3M perovskite precursor solution was drawn and 50 ⁇ L was spin-coated on the interface layer 5 at a speed of 4000r.pm for 60s, and annealed at 70°C for 10min.
  • MOPEA n Cs x FA 1-x Pbn Br 3n+1 which is composed of 110 mg of lead bromide (PbBr 2 ), 64 mg of cesium
  • the structural formula of the perovskite material layer is ABX 3 , wherein the A site is a monovalent cation, the B site is a divalent cation, and the X site is a halogen anion.
  • A-site cations include: cesium ion (Cs + ), methylamine ion (MA + ), methylamine ion (FA + ), ethylamine ion (EA + ), hydrazine ion (HA + ), guanidine ion (GA + ), Isopropylamine ion (IPA + ), imidazolium ion (IA + ), etc.
  • B-site cations include lead ions (Pb 2+ ), tin ions (Sn 2+ ), germanium ions (Ge 2+ ), indium ions (In 2+ ), bismuth ions (Bi 2+ ) and the like.
  • X-position anions include: chloride ion (Cl - ), bromide ion (Br - ), iodide ion (I - ), etc.
  • the perovskite material layer can be one or more of one-dimensional, quasi-two-dimensional, and three-dimensional components combination of species.
  • the thickness of the light-emitting material layer 6 can be designed according to the requirements of different devices.
  • the luminescent material layer 6 is located on the interface layer 5. Specifically, the luminescent material layer 6 is in direct contact with the interface layer 5, so that the luminescent material can be spread more easily. 5 are more closely combined, thereby improving the flatness of the surface of the formed luminescent material layer 6 .
  • the second insulating layer 7 covers the luminescent material layer 6 located in the second partial area 12 and covers the luminescent material layer 6 located in the first partial area 11 adjacent to the second partial area 12, so that the The luminescent material layer 6 in the central region 111 within the first partial region 11 (ie, the region within the first partial region 11 excluding the region covered by the second insulating layer 7 ) is not covered by the second insulating layer 7 , but The luminescent material layer 6 in the central region 111 is exposed.
  • the central area in the first partial area 11 that is not covered by the second insulating layer 7 is adjusted. 111 size.
  • the second insulating layer 7 is a lithium fluoride (LiF) layer, and the second insulating layer 7 can also be sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF) ), cesium fluoride (CsF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), and a combination of one or more of them.
  • the thickness of the second insulating layer 7 is any value between 24 nm and 36 nm, and preferably, the thickness of the second insulating layer 7 is 30 nm.
  • the structure formed in step S8 is put into a vacuum coating machine for lithium fluoride (LiF) insulating layer evaporation, the pressure of vacuum evaporation is 5 ⁇ 10 -4 Pa, and the evaporation rate is determined by a quartz crystal oscillator. For sheet measurement, the evaporation rate was 0.4 nm/s until the evaporation was completed.
  • the position where the second insulating layer 7 is formed is limited by a mask, so that the first partial area 11 is not entirely covered by the second insulating layer 7, but only the luminescent material on the side adjacent to the second partial area 12. The layers are covered by a second insulating layer 7 .
  • S10 An electron transport layer is formed in the central region within the first partial region.
  • the electron transport layer 8 is formed so that the formed electron transport layer 8 covers only the central region 111 in the first partial region 11 .
  • the electron transport layer 8 is formed by an evaporation process.
  • the name of the electron transport layer 8 is 2,2',2"-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole) (TPBi), vacuum-evaporated
  • TTBi 2,2',2"-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole)
  • TPBi 2,2',2"-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole)
  • TPBi 2,2',2"-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole)
  • TPBi 2,2',2"-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole)
  • TPBi 2,2',2"-(
  • the position where the electron transport layer 8 is formed is restricted by a mask, so that the electron transport layer 8 is formed only in the central region 111 of the first partial region 11 .
  • the electron transport layer 8 can be of two types: organic electron transport layer and inorganic electron transport layer, wherein the organic electron transport layer includes but is not limited to: TPBi, BAlq, Phen-m-PhDPO, POPy 2 , PO-T2T, Alq 3 , B3PYMPM At least one of etc.; the inorganic electron transport layer has but is not limited to: Ga 2 O 3 , Si 3 N 4 , ZrO 2 , V 2 O 5 , Al 2 O 3 , NiO x , MoO 3 , ZnO, MgO, NiO At least one of , SnO 2 , TiO 2 and the like.
  • the organic electron transport layer includes but is not limited to: TPBi, BAlq, Phen-m-PhDPO, POPy 2 , PO-T2T, Alq 3 , B3PYMPM At least one of etc.
  • the inorganic electron transport layer has but is not limited to: Ga 2 O 3 , Si 3
  • the size of the luminescent material layer 6 covered by the second insulating layer 7 in the first partial region can be adjusted, so that the size of the subsequently formed electron transport layer can be adjusted, that is, the light emitting area of the optoelectronic device.
  • the size can be adjusted, and then the feature size of a single light-emitting pixel or effective working area can be adjusted, that is, the second insulating layer is used as a feature size limiting layer, and combined with the first insulating layer to realize small and miniature optoelectronic devices.
  • the device structure is optimized, and the problems of low external quantum efficiency, low brightness and large leakage current of small and miniature optoelectronic devices are solved.
  • the optoelectronic device of the present application does not need an etching process during the manufacturing process, and avoids the etching process.
  • the luminescent material layer is seriously damaged by chemical corrosion, ion beam or electron beam etching, which leads to the disadvantages of many optoelectronic devices in batch preparation, difficult processing, and long time.
  • the method for manufacturing an optoelectronic device of the present application further includes: S11 : forming a metal electrode on the electron transport layer in the central region in the first partial region, and extending the metal electrode to the center region of the first partial region. on one side of the second insulating layer.
  • the metal electrode 9 covers the electron transport layer 8 in the central area 111 in the first partial area 11 and extends to the second insulating layer 7 on the right side of the central area 111 to form a strip of metal electrode 9.
  • the metal electrode 9 is formed by a metal electrode evaporation process. In one embodiment, the area where the metal electrode 9 is formed is limited by a reticle. In one embodiment, the width of the metal electrode 9 is any value between 150 ⁇ m and 250 ⁇ m. In one embodiment, electrode materials LiF and metal Al are sequentially evaporated during the metal electrode evaporation process, and the evaporation rate is measured by a quartz crystal. The LiF evaporation rate is 0.1 nm/s, and the thickness of LiF is 0.8 nm to 1.2 nm. Any value between nm, the thickness of the Al electrode is any value between 80 nm and 120 nm.
  • the thickness of the LiF is 1 nm, and the thickness of the Al electrode is 100 nm.
  • the metal electrode has oxides and metal materials with high conductivity, the oxides with high conductivity include transparent electrodes such as ITO, FTO, TCO, etc., and the metal materials include Al, Mg, Ca, Ag, Cu, Mg: Ag, Li:Al, Mn, etc.
  • an optoelectronic device is also provided.
  • the feature size of a single light-emitting pixel or effective working area of the optoelectronic device is less than or equal to 500 microns, including:
  • a layer of interface layer 5 is formed on the first transmission layer 4;
  • a layer of luminescent material layer 6 is formed on the interface layer 5;
  • a second insulating layer 7 is formed on the luminescent material layer 6 in the second partial region 12 and on the luminescent material layer 6 in the first partial region 11 adjacent to the second partial region side 12 , and the central region in the first partial region 11 is formed with a second insulating layer 7 .
  • An electron transport layer 8 is formed on the light-emitting material layer 6 in 111 .
  • the thickness of the first insulating layer is any value between 40 nm and 80 nm
  • the thickness of the interface layer is any value between 0.7 nm and 1.3 nm
  • the thickness of the second insulating layer is 24 nm. Any value between 36 nm and any value between 40 nm and 50 nm in thickness of the electron transport layer.
  • the thickness of the first insulating layer is 60 nm
  • the thickness of the interface layer 5 is 1 nm
  • the thickness of the second insulating layer 7 is 30 nm
  • the thickness of the electron transport layer 8 is 45 nm.
  • the thicknesses of the first transport layer 4 and the luminescent material layer 6 can be designed according to the requirements of different devices.
  • the semiconductor substrate 1 can be formed of any material that can be used as a substrate, for example, it can be conductive glass, silicon substrate, polytetrafluoroethylene material (PTFE), piezoelectric ceramics, and the like.
  • PTFE polytetrafluoroethylene material
  • the material of the first insulating layer 3 may be silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), nitrogen Any one or a combination of materials of aluminum oxide (AlN).
  • the material of the first insulating layer 3 is silicon dioxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ).
  • the first transport layer 4 is a hole transport layer. In one embodiment, it includes nickel oxide (NiO x ) and poly(9-vinylcarbazole) (PVK).
  • the hole transport layer can be an organic hole transport layer and an inorganic hole transport layer, wherein the organic hole transport layer includes but is not limited to: TFB, PTAA, TAPC, PEDOT:PSS, Poly-TPD, PVK, TCTA, CBP, TPD , at least one of CuPc, M-MTDATA, NPB, Rubrene; inorganic hole transport layers include but are not limited to: copper oxide (CuO), nickel oxide (NiO x ), molybdenum trioxide (MoO 3 ), tungsten trioxide At least one of (WO 3 ) and vanadium pentoxide (V 2 O 5 ).
  • the interface layer 5 is a lithium fluoride (LiF) layer, and the interface layer 5 can also be sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride ( A combination of one or more of CsF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), and the like.
  • the interface layer 5 can play an insulating role.
  • the luminescent material layer 6 can be formed of any electroluminescent material. Any electroluminescent material currently existing or generated with the development of technology is within the scope of protection of the present application, preferably, it is a perovskite material , it can also be one or more of perovskite materials and organic materials, III-V materials, II-VI materials, IV materials, rare earth materials, oxide materials, semiconductor nanomaterials, insulating materials, etc. combination. Preferably, in one embodiment, the light-emitting material layer 6 is a perovskite material layer. Metal halide perovskites are emerging semiconductor materials with properties similar to III-V materials.
  • the structural formula of the perovskite material layer is ABX 3 , wherein the A site is a monovalent cation, the B site is a divalent cation, and the X site is a halogen anion.
  • A-site cations include: cesium ion (Cs + ), methylamine ion (MA + ), methylamine ion (FA + ), ethylamine ion (EA + ), hydrazine ion (HA + ), guanidine ion (GA + ), Isopropylamine ion (IPA + ), imidazolium ion (IA + ), etc.
  • B-site cations include lead ions (Pb 2+ ), tin ions (Sn 2+ ), germanium ions (Ge 2+ ), indium ions (In 2+ ), bismuth ions (Bi 2+ ) and the like.
  • X-position anions include: chloride ion (Cl - ), bromide ion (Br - ), iodide ion (I - ), etc.
  • the perovskite material layer can be one or more of one-dimensional, quasi-two-dimensional, and three-dimensional components combination of species.
  • the luminescent material layer 6 is located on the interface layer 5. Specifically, the luminescent material layer 6 is in direct contact with the interface layer 5, so that the luminescent material can be spread more easily. 5 are more closely combined, thereby improving the flatness of the surface of the formed luminescent material layer 6 .
  • the second insulating layer 7 covers the luminescent material layer 6 located in the second partial area 12 and covers the luminescent material layer 6 located in the first partial area 11 on the side adjacent to the second partial area 12 , so that the The luminescent material layer 6 in the central region 111 in the first partial region 11 is not covered by the second insulating layer 7 , and the luminescent material layer 6 in the central region 111 is exposed.
  • the central area in the first partial area 11 that is not covered by the second insulating layer 7 is adjusted. 111 size.
  • the second insulating layer 7 is a lithium fluoride (LiF) layer, and the second insulating layer 7 can also be sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF) ), cesium fluoride (CsF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), and a combination of one or more of them.
  • NaF sodium fluoride
  • KF potassium fluoride
  • RbF rubidium fluoride
  • CsF cesium fluoride
  • MgF 2 magnesium fluoride
  • CaF 2 calcium fluoride
  • the electron transport layer 8 covers only the central region 111 in the first partial region 11 .
  • the electron transport layer 8 can be of two types: organic electron transport layer and inorganic electron transport layer, wherein the organic electron transport layer includes but is not limited to: TPBi, BAlq, Phen-m-PhDPO, POPy 2 , PO-T2T, Alq 3 , B3PYMPM At least one of etc.; the inorganic electron transport layer has but is not limited to: Ga 2 O 3 , Si 3 N 4 , ZrO 2 , V 2 O 5 , Al 2 O 3 , NiO x , MoO 3 , ZnO, MgO, NiO At least one of , SnO 2 , TiO 2 and the like.
  • the size of the luminescent material layer covered by the second insulating layer in the first partial region can be adjusted, so that the size of the subsequently formed electron transport layer can be adjusted, that is, the size of the light-emitting area of the optoelectronic device can be adjusted, thereby achieving
  • the feature size of a single light-emitting pixel or effective working area is adjustable, that is, the second insulating layer acts as a feature size limiting layer, and combines with the first insulating layer to realize small and micro optoelectronic devices. It solves the problems of low external quantum efficiency, low brightness and large leakage current of small and micro optoelectronic devices.
  • the optoelectronic device further includes: a metal electrode 9 , the metal electrode 9 covers the electron transport layer 8 in the central region 111 in the first partial region 11 and extends to one side of the central region 111 . 7 on the second insulating layer.
  • the above-mentioned optoelectronic device is a light emitting diode.
  • the optoelectronic device of the present invention can also be extended to other optoelectronic device fields, including but not limited to solar cells, photodetectors, fluorescent films, phosphors, semiconductor transistors, laser optoelectronic devices and materials, and the like.
  • the small and micro light-emitting diodes manufactured by the method provided in this application can be applied to display screens (screens of electronic products such as high-end TVs, mobile phones, computers and iPads), smart watches, wearable devices, AR smart glasses, micro projectors, etc. .
  • Small and micro light-emitting diodes can also be combined with flexible substrates to achieve flexible displays.
  • Miniaturized light-emitting diodes can also realize backlight displays (TV screens and car displays, etc.), RGB small-pitch displays, and the like.
  • the optoelectronic device provided by the application and the optoelectronic device formed by the manufacturing method of the optoelectronic device provided by the application are tested.
  • the optoelectronic device as the light-emitting diode as an example
  • the OLED photochromic test system is used to test the external quantum efficiency (EQE) during the test.
  • the luminometer is used to detect the spectrum and spectral power of the light-emitting diode.
  • the Keithley source meter 2400 is used as the power source of the light-emitting diode to undertake the functions of power output and current detection.
  • the positive and negative electrodes are connected with the 2400.
  • the voltage range loaded on the light-emitting device is 1V ⁇ 5V, the voltage step interval is 0.1V, the current through the light-emitting diode is measured by the four-wire method, the current detection range is 1nA ⁇ 100mA, and the current density range is 10 -4 –10 3 mA cm -2 , so it can meet the current testing requirements of light-emitting diodes.
  • the computer host computer realizes the function of interactive communication with the luminance meter, Keithley source meter 2400, and industrial control camera CCD, obtains the collected spectrum, spectral power, voltage, current and detection images, and realizes the real-time display function.
  • the sample test bench is responsible for light-emitting diodes The sample is placed to achieve the three-dimensional position adjustment function, which makes the observation clearer and the measurement more accurate, so as to achieve the purpose of optimizing the performance test.
  • FIG. 13 is a schematic diagram of photoelectric performance test data of an optoelectronic device according to an embodiment of the present application and an optoelectronic device formed by using the optoelectronic device according to an embodiment of the present application.
  • the horizontal axis in (a) is the voltage applied across the light-emitting diode (Voltage), in volts (V); the vertical axis is the current density (Current density) flowing through the light-emitting diode, in mA cm -2 .
  • the light-on voltage of the miniaturized light-emitting diode is 2.8V. At a voltage of 6.0 V, the current density reaches 923.8 mA cm -2 .
  • the horizontal axis in (b) is the voltage applied across the light-emitting diode (Voltage), in volts (V); the vertical axis is the luminance of the light-emitting diode (Luminance), in cd m -2 . At 5.7V, the brightness of the light-emitting diode reaches 1070.5cd m -2 , and the area of the light-emitting area is 0.04mm 2 .
  • the horizontal axis in (c) is the current density (Current density) flowing through the light-emitting diode, in mA cm ⁇ 2 ; the vertical axis is the external quantum efficiency (EQE) of the light-emitting diode, in %.
  • the device of miniature light-emitting diode has the highest EQE of about 15.2% (4.11 ⁇ 10 -2 mA cm -2 ). It can be seen that the optoelectronic device provided by the present application and the optoelectronic device formed by using the optoelectronic device provided by the present application not only realize miniaturization and miniaturization, but also solve the problems of low external quantum efficiency, low brightness and leakage current of small and micro optoelectronic devices. big problem.
  • the optoelectronic device and the method for manufacturing an optoelectronic device provided by the present application are suitable for small and micro optoelectronic devices, wherein the feature size of a single light-emitting pixel or effective working area is greater than or equal to 200 microns and less than or equal to 500 microns.
  • the device, the feature size of a single light-emitting pixel point or effective working area is less than or equal to 200 microns is a miniature optoelectronic device.
  • the optoelectronic devices provided in this application can also be prepared by: method 1, directly on a small or micro substrate with a size of less than or equal to 500 microns; or method 2, by etching a conventional size optoelectronic device Prepared, the etching method includes laser processing, plasma etching, FIB etching, EBL etching and the like.

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Abstract

本发明涉及光电器件，涉及半导体器件，光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，包括：半导体衬底，其第一部分区域上形成有第一传输层，位于第一部分区域周围的第二部分区域上形成有第一层绝缘层，并在第一层绝缘层上形成有第一传输层；第一传输层上形成有一层界面层；界面层上形成有一层包含钙钛矿材料的发光材料层；第二部分区域内的发光材料层上及第一部分区域内的临近第二部分区域侧的发光材料层上形成有第二层绝缘层，以实现单个发光像素点或有效工作区域的特征尺寸可调，且其制备成本低、工艺复杂度低、器件光谱纯度高，可有效解决小型与微型光电器件外量子效率低、亮度低和漏电流大的问题。

Description

光电器件及其制造方法 技术领域
本发明涉及半导体技术，尤其涉及一种光电器件。
背景技术
随着对显示产品基本元器件的小型化、集成化、低功耗程度要求越来越高，对于微型光电器件如发光二极管的单位尺寸、低功耗也需要更高标准。近年来，小型与微型发光二极管(mini-LED与micro-LED)受到了人们广泛的关注，因其低功耗、高对比度、高亮度、高响应速度和高效率等优点。最近，市场上已经推出了一些高端的微型化发光二极管显示器，如三星公司的“The Wall”显示墙和PlayNitride公司的“PixelLED显示”等，均得到产业界的认可。虽然目前的mini-LED与micro-LED具有上述优势，但对于III-V族外延半导体的质量要求变得更加严格，在制程中发光层侧壁会产生大量非辐射损耗通道和大面板显示器中微型化发光二极管的巨量转移问题，这些无形之中都会增加产品制造的成本。
近年来，金属卤化物钙钛矿作为一个新兴的半导体材料其性能与III-V族材料相似。其作为一类低成本和可溶液法制备的半导体材料，表现出了优异的光电性能，如带隙可调、荧光量子产率高、离子迁移距离长和发光带隙窄等特点。自2014年首次实现室温电致发光钙钛矿发光二极管以来，制备高效的卤化物钙钛矿发光二极管(PeLED)的技术日益成熟，最近研究人员已经成功制备了外量子效率超过20％和内量子效率接近100％的钙钛矿发光器件，尽管PeLED有潜力成为低成本LED技术的替代品，但如何构建微型像素大小的高效PeLED技术仍难以实现。
目前制备高效率钙钛矿发光二极管的技术路线包括两种，一种是通过优化低维度、混合维度钙钛矿结构中的辐射复合过程，另一种是通过抑制不同材料体系中的非辐射复合过程。尽管通过钝化钙钛矿薄膜和优化器件结构能够制备高外量子效率的钙钛矿发光器件，但制备芯片结构为微米尺度的高效率钙钛矿发光二极管仍然有限。其具有诸多缺点，如需要选择流变性能适当的喷涂油墨、低能量的电子束或表面张力适当的溶液来制备不易损坏的微型化发光二极管图案。
综上所述，如何通过低成本工艺制备高性能且像素点或有效工作区域尺寸大小可调的发光与光电器件将成为业界未来的技术方向，以及市场的迫切需求。
发明内容
本申请在于提供一种光电器件的制造方法，光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，包括：S1：提供一半导体衬底；S2：形成一层光刻胶层；S3：利用一掩模版对光刻胶层进行曝光显影工艺，使半导体衬底上的第一部分区域被剩余的光刻胶层保护起来，而位于第一部分区域周围的第二部分区域被显开；S4：形成第一层绝缘层，第一层绝缘层覆盖剩余的光刻胶层的上表面、第二部分区域对应的半导体衬底的上表面，并光刻胶层的厚度大于第一层绝缘层的厚度；S5：进行去胶工艺，以去除剩余的光刻胶层及位于剩余的光刻胶层上的第一层绝缘层；S6：形成第一传输层，使第一传输层覆盖第一层绝缘层的上表面及第一部分区域内的半导体衬底；S7：在第一传输层上形成一层界面层；S8：在界面层上形成一层发光材料层；S9：形成第二层绝缘层，使第二层绝缘层覆盖位于第二部分区域内的发光材料层，并覆盖位于第一部分区域内的临近第二部分区域侧的发光材料层，以使第一部分区域内的中心区域内没有被第二层绝缘层覆盖；以及S10：在第一部分区域内的中心区域内形成电子传输层。
更进一步的，还包括S11：在第一部分区域内的中心区域内的电子传输层上形成金属电极，并将金属电极延伸至中心区域的其中一侧的第二层绝缘层上。
更进一步的，第一传输层为空穴传输层。
更进一步的，界面层为氟化锂层。
更进一步的，第一层绝缘层的材料为二氧化硅、氧化铝、氮化硅、碳化硅、氮化铝中的任一者或多种材料的组合。
更进一步的，发光材料层为钙钛矿材料层。
更进一步的，发光材料层为钙钛矿材料与有机材料、III-V族材料、II-VI族材料、IV族材料、稀土材料、氧化物材料、半导体纳米材料、绝缘材料中的一种或多种的组合。
更进一步的，发光材料层与界面层直接接触。
更进一步的，通过调节第一部分区域内的被第二层绝缘层覆盖的发光材料层的尺寸，而调节第一部分区域内的没有被第二层绝缘层覆盖的中心区域尺寸，而调节电子传输层的尺寸。
更进一步的，第二层绝缘层为氟化锂层。
更进一步的，通过掩模版限制形成第二层绝缘层的位置，而使第一部分区域内仅临近第二部分区域侧的发光材料层被第二层绝缘层覆盖。
更进一步的，通过掩模版限制形成电子传输层的位置，而使仅在第一部分区域内的中心区域内形成有电子传输层。
本发明还提供一种光电器件，所述光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，包括：半导体衬底，其中半导体衬底的第一部分区域上形成有第一传输层，位于第一部分区域周围的第二部分区域上形成有第一层绝缘层，并第一层绝缘层上形成有第一传输层；在第一传输层上形成有一层界面层；在界面层上形成有一层发光材料层；第二部分区域内的发光材料层上及第一部分区域内的临近第二部分区域侧的发光材料层上形成有第二层绝缘层，而第一部分区域内的中心区域内的发光材料层上形成有一层电子传输层。
更进一步的，第一传输层为空穴传输层。
更进一步的，界面层和第二层绝缘层为氟化锂层。
更进一步的，发光材料层为钙钛矿材料层。
更进一步的，发光材料层与界面层直接接触。
更进一步的，通过调节第一部分区域内的被第二层绝缘层覆盖的发光材料层的尺寸，而调节第一部分区域内的没有被第二层绝缘层覆盖的中心区域尺寸，而调节电子传输层的尺寸。
更进一步的，第一层绝缘层的材料为二氧化硅、氧化铝、氮化硅、碳化硅、氮化铝中的任一者或多种材料的组合。
附图说明
图1至图12为本发明一实施例的光电器件的制造过程之一的剖面示意图。
图13为对本申请一实施例的光电器件及采用本申请一实施例的光电器件的制造形成的光电器件的光电性能测试数据示意图。
具体实施方式
下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
应当理解，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大，自始至终相同附图标记表示相同的元件。应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明一实施例中，在于提供一种光电器件的制造方法，光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米。以钙钛矿发光二极管(PeLED)为例，一般单个发光像素点或有效工作区域的特征尺寸大于等于200微米而小于等于500微米是小型钙钛矿发光二极管(mini-PeLED)，单个发光像素点或有效工作区域的特征尺寸小于等于200微米是微型钙钛矿发光二极管(micro-PeLED)。请参阅图1至图12所示的本发明一实施例的光电器件的制造过程之一的剖面示意图。具体的，本发明一实施例的光电器件的制造方法包括：
S1：提供一半导体衬底；
如图1所示，提供一半导体衬底1，半导体衬底1可为任何可作为衬底的材料形成，如其可为导电玻璃(FTO)、硅基板、聚四氟乙烯材料(PTFE)、压电陶瓷等。
通常，半导体衬底在使用前可用去离子水、丙酮、异丙醇、去离子水、异丙醇5个步骤分别进行15分钟超声清洗。清洗完成的半导体衬底放到UV臭氧清洗机中进行30分钟臭氧清洗。
S2：形成一层光刻胶层；
如图2所示，在半导体衬底1上形成光刻胶层2。光刻胶层2可由负性光刻胶溶液形成，也可由正性光刻胶溶液形成。如可用量程100μL的移液枪吸取50μL的负性光刻胶溶液涂覆 到半导体衬底1上，开启真空旋涂机以4000r.p.m.转速旋涂60s，得到厚度约420nm的光刻胶层2。较佳的，光刻胶层2的厚度为420nm。当然上述的光刻胶层2的厚度420nm可有一定的偏差，所述偏差可为20％，较佳的为10％，更佳的为5％。具体的，其可为380nm至460nm之间的任一值。
S3：利用一掩模版对光刻胶层进行曝光显影工艺，使半导体衬底上的第一部分区域被剩余的光刻胶层保护起来，而位于第一部分区域周围的第二部分区域被显开；
如图4所示，半导体衬底1上的第一部分区域11被剩余的光刻胶层21保护起来，而位于第一部分区域11周围的第二部分区域12被显开，也即第二部分区域12对应的半导体衬底1裸露出来。
具体的，以负性光刻胶为例，将经步骤S2之后形成的结构放到掩模版上，用紫外光源(λ＝365nm，100mJ cm -2)曝光7-8秒，可得到如图3所示的被曝光的负性光刻胶。然后用异丙醇(IPA)润洗数次，洗掉未被曝光的负性光刻胶，之后放到85℃的热台上烘烤20分钟，可得到如图4所示的结构。
S4：形成第一层绝缘层，第一层绝缘层覆盖剩余的光刻胶层的上表面、第二部分区域对应的半导体衬底的上表面，并光刻胶层的厚度大于第一层绝缘层的厚度；
如图5所示，形成第一层绝缘层3，第一层绝缘层3覆盖剩余的光刻胶层21(也即第一部分区域11内的光刻胶层)的上表面、裸露的半导体衬底1(也即第二部分区域12对应的半导体衬底)的上表面，并光刻胶层21的厚度大于第一层绝缘层3的厚度。具体的，在一实施例中，第一层绝缘层的厚度为40nm至80nm之间的任一值。较佳的，第一层绝缘层的厚度为60nm。
在一实施例中，第一层绝缘层3的材料可为二氧化硅(SiO 2)、氧化铝(Al 2O 3)、氮化硅(Si 3N 4)、碳化硅(SiC)、氮化铝(AlN)中的任一者或多种材料的组合。较佳的，第一层绝缘层3的材料为二氧化硅(SiO 2)或氧化铝(Al 2O 3)。在一实施例中，通过磁控溅射、MOCVD、热蒸镀等中的至少一种工艺形成第一层绝缘层3。
S5：进行去胶工艺，以去除剩余的光刻胶层及位于剩余的光刻胶层上的第一层绝缘层；
如图6所示，将剩余的光刻胶层21及位于剩余的光刻胶层21上的第一层绝缘层3去除，如此第一部分区域11内的半导体衬底1裸露出来，而保留位于第二部分区域12内的第一层绝缘层3。具体的，将经步骤S4形成的结构浸泡于去胶液12小时进行去胶，得到如图6所示的结构。再依次用去离子水、丙酮和异丙醇冲洗5分钟，并放到UV臭氧清洗机中进行30分钟臭氧清洗。
S6：形成第一传输层，使第一传输层覆盖第一层绝缘层的上表面及第一部分区域内的半导体衬底；
具体的，如图7所示，第一传输层4覆盖第一层绝缘层3的上表面及第一部分区域11内的半导体衬底1。
在一实施例中，第一传输层4为空穴传输层。在一实施例中，其包括氧化镍(NiO x)和聚(9-乙烯基咔唑)(PVK)。氧化镍(NiO x)粉体购自如北京华敏新材料科技有限公司，分散在去离子水中，浓度为15mg/mL，用量程100μL的移液枪吸取50μL的NiO x溶液涂覆到经步骤S5形成的结构上，开启真空旋涂机以4000r.p.m.转速旋涂60s，旋涂完NiO x的结构放置到热台上进行150℃退火15min。之后转移到充满高纯氮的手套箱，在真空旋涂机上进行PVK旋涂。PVK购自如Sigma-aldrich，平均分子量为25,000-50,000，溶解在氯苯(CB)中，浓度为6mg/mL，用量程100μL的移液枪吸取50uL的PVK溶液涂覆，开启真空旋涂机以4500r.p.m.转速旋涂60s，然后放置到热台上进行150℃退火30min而形成。
空穴传输层可为有机空穴传输层和无机空穴传输层，其中有机空穴传输层有但不限于：TFB、PTAA、TAPC、PEDOT:PSS、Poly-TPD、PVK、TCTA、CBP、TPD、CuPc、M-MTDATA、NPB、Rubrene中的至少一者；无机空穴传输层有但不限于：氧化铜(CuO)、氧化镍(NiO x)、三氧化钼(MoO 3)、三氧化钨(WO 3)、五氧化二钒(V 2O 5)中的至少一者。
在一实施例中，第一传输层4的厚度可根据不同器件的需求而设计。
S7：在第一传输层上形成一层界面层；
如图8所示，在第一传输层4上形成一层界面层5。在一实施例中，界面层5为氟化锂(LiF)层，另界面层5还可为氟化钠(NaF)、氟化钾(KF)、氟化铷(RbF)、氟化铯(CsF)、氟化镁(MgF 2)、氟化钙(CaF 2)等中的一种或者多种的组合。在一实施例中，界面层5的厚度为0.7nm至1.3nm之间的任一值，较佳的，界面层5的厚度为1nm。在一实施例中，将经步骤S6形成的结构转移到真空镀膜机中进行极性界面，如LiF，蒸镀。真空蒸镀的气压为5×10 -4Pa，蒸镀速率由石英晶振片测量，蒸镀速率为0.1nm/s，直至蒸镀完成。
其中界面层5可起到绝缘的作用。
S8：在界面层上形成一层发光材料层；
如图9所示，在界面层5上形成一层发光材料层6。发光材料层6可为由任何电致发光的材料形成，目前现有的或随着技术的发展产生的任何电致发光的材料均在本申请的保护范围内。如有机发光材料、钙钛矿材料、或量子点材料等。较佳的，在一实施例中，发光材料层6为钙钛矿材料层。金属卤化物钙钛矿作为新兴的半导体材料其性能与III-V族材料相似。其作为一类低成本和可溶液法制备的半导体材料，表现出了优异的光电性能，如带隙可调、荧光量子产率高、离子迁移距离长和发光带隙窄等特点。在一实施例中，发光材料层为钙钛矿材料与有机材料、III-V族材料、II-VI族材料、IV族材料、稀土材料、氧化物材料、半导体纳米材料、绝缘材料等中的一种或多种的组合，其中有机材料包括小分子与聚合物。
以发光材料层6为钙钛矿材料层为例，经步骤S7之后的结构转移到充满高纯氮的手套箱旋涂钙钛矿材料层作为发光材料层6。具体的，钙钛矿前驱体溶液为MOPEA nCs xFA 1-xPb nBr 3n+1，其由110mg的溴化铅(PbBr 2)、64mg的溴化铯(CsBr)、6mg的甲脒氢碘酸盐(FABr)和28mg的2-(4-甲氧基苯基)乙胺氢溴酸盐(MOPEABr)和5.5mg的18-冠醚-6溶解在1mL的二甲基亚砜(DMSO)溶液中，溶液浓度为0.3M。随后将配好的0.3M钙钛矿前驱体溶液，吸取50μL以4000r.p.m.转速旋涂60s涂布到界面层5上，并在70℃退火10min。
在一实施例中，钙钛矿材料层的结构式为ABX 3，其中A位是一价阳离子，B位是二价 阳离子，X位是卤素阴离子。A位阳离子包括：铯离子(Cs +)、甲胺离子(MA +)、甲眯离子(FA +)、乙胺离子(EA +)、肼离子(HA +)、胍离子(GA +)、异丙基胺离子(IPA +)、咪唑离子(IA +)等。B位阳离子包括：铅离子(Pb 2+)、锡离子(Sn 2+)、锗离子(Ge 2+)、铟离子(In 2+)、铋离子(Bi 2+)等。X位阴离子包括：氯离子(Cl -)、溴离子(Br -)、碘离子(I -)等，钙钛矿材料层可以为一维、准二维、三维组分中的一种或者多种的组合。
在一实施例中，发光材料层6的厚度可根据不同器件的需求而设计。
另发光材料层6位于界面层5上，具体的，发光材料层6与界面层5直接接触，以使发光材料更容易铺展开，发光材料如钙钛矿溶液在界面层5上会与界面层5结合的更加紧密，从而提高形成的发光材料层6的表面的平整度。
S9：形成第二层绝缘层，使第二层绝缘层覆盖位于第二部分区域内的发光材料层，并覆盖位于第一部分区域内的临近第二部分区域侧的发光材料层，以使第一部分区域内的中心区域内没有被第二层绝缘层覆盖；
如图10所示，第二层绝缘层7覆盖位于第二部分区域12内的发光材料层6，并覆盖位于第一部分区域11内的临近第二部分区域12侧的发光材料层6，以使第一部分区域11内的中心区域111(即第一部分区域11内的除被第二层绝缘层7覆盖的区域之外的区域)内的发光材料层6没有被第二层绝缘层7覆盖，而裸露出中心区域111内的发光材料层6。在一实施例中，通过调节第一部分区域11内的被第二层绝缘层7覆盖的发光材料层6的尺寸，而调节第一部分区域11内的没有被第二层绝缘层7覆盖的中心区域111尺寸。
在一实施例中，第二层绝缘层7为氟化锂(LiF)层，另第二层绝缘层7还可为氟化钠(NaF)、氟化钾(KF)、氟化铷(RbF)、氟化铯(CsF)、氟化镁(MgF 2)、氟化钙(CaF 2)等中的一种或者多种的组合。在一实施例中，第二层绝缘层7的厚度为24nm至36nm之间的任一值，较佳的，第二层绝缘层7的厚度为30nm。在一实施例中，将经步骤S8形成的结构再放入真空镀膜机进行氟化锂(LiF)绝缘层蒸镀，真空蒸镀的气压为5×10 -4Pa，蒸镀速率由石英晶振片测量，蒸镀速率为0.4nm/s，直至蒸镀完成。在一实施例中，通过掩模版限 制形成第二层绝缘层7的位置，而使第一部分区域11内没有全部被第二层绝缘层7覆盖，而仅临近第二部分区域12侧的发光材料层被第二层绝缘层7覆盖。
S10：在第一部分区域内的中心区域内形成电子传输层。
如图11所示，形成电子传输层8，使形成的电子传输层8仅覆盖第一部分区域11内的中心区域111。
在一实施例中，采用蒸镀工艺形成电子传输层8。电子传输层8的名称为2，2'，2“-(1,3,5-苯并咪唑)-三(1-苯基-1-H-苯并咪唑)(TPBi)，真空蒸镀的气压为5×10 -4Pa，蒸镀速率由石英晶振片测量，蒸镀速率为0.4nm/s，直至蒸镀完成。在一实施例中，电子传输层8的厚度为40nm至50nm之间的任一值，较佳的，电子传输层8的厚度为45nm。
在一实施例中，通过掩模版限制形成电子传输层8的位置，而使仅在第一部分区域11内的中心区域111内形成有电子传输层8。
电子传输层8可为有机电子传输层和无机电子传输层两大类，其中有机电子传输层有但不限于：TPBi、BAlq、Phen-m-PhDPO、POPy 2、PO-T2T、Alq 3、B3PYMPM等中的至少一者；无机电子传输层有但不限于：Ga 2O 3、Si 3N 4、ZrO 2、V 2O 5、Al 2O 3、NiO x、MoO 3、ZnO、MgO、NiO、SnO 2、TiO 2等中的至少一者。
如上所述，本申请通过第一部分区域内的被第二层绝缘层7覆盖的发光材料层6的尺寸可调，而使得后续形成的电子传输层的尺寸可调，也即光电器件的发光面积大小可调，进而实现单个发光像素点或有效工作区域的特征尺寸可调，也即第二层绝缘层作为特征尺寸限制层，并结合第一绝缘层实现小型与微型光电器件，如此，不但使器件结构优化，且解决了小型与微型光电器件外量子效率低、亮度低和漏电流大的问题，另本申请的光电器件在制造的过程中无需刻蚀工艺，而避免了刻蚀工艺中的化学腐蚀、离子束或电子束刻蚀造成的发光材料层严重破坏，导致批量制备中的光电器件坏点多、加工难度大、耗时长等缺点。
在一实施例中，更进一步的，本申请的光电器件的制造方法还包括：S11：在第一部分区域内的中心区域内的电子传输层上形成金属电极，并将金属电极延伸至中心区域的其中一 侧的第二层绝缘层上。
如图12所示，金属电极9覆盖第一部分区域11内的中心区域111内的电子传输层8，并延伸至中心区域111的右侧的第二层绝缘层7上，而形成一带状金属电极9。
在一实施例中，通过金属电极蒸镀工艺形成金属电极9。在一实施例中，通过掩模版限制形成金属电极9的区域。在一实施例中，金属电极9的宽度为150μm至250μm之间的任一值。在一实施例中，在金属电极蒸镀过程中依次蒸镀电极材料LiF和金属Al，蒸镀速率由石英晶振片测量，LiF蒸镀速率为0.1nm/s，LiF的厚度为0.8nm至1.2nm之间的任一值，Al电极的厚度为80nm至120nm之间的任一值。较佳的，LiF的厚度为1nm，Al电极的厚度为100nm。在一实施例中，金属电极具有高导电率的氧化物和金属材料，高导电率的氧化物包括ITO、FTO、TCO等透明电极，金属材料包括Al、Mg、Ca、Ag、Cu、Mg:Ag、Li:Al、Mn等。
请继续参阅图12，在本发明一实施例中，还提供一种光电器件，光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，包括：
半导体衬底1，其中半导体衬底1的第一部分区域11上形成有第一传输层4，位于第一部分区域11周围的第二部分区域12上形成有第一层绝缘层3，并第一层绝缘层3上形成有第一传输层4；
第一传输层4上形成有一层界面层5；
在界面层5上形成有一层发光材料层6；
第二部分区域12内的发光材料层6上及第一部分区域11内的临近第二部分区域侧12的发光材料层6上形成有第二层绝缘层7，而第一部分区域11内的中心区域111内的发光材料层6上形成有一层电子传输层8。
在一实施例中，第一层绝缘层的厚度为40nm至80nm之间的任一值，界面层的厚度为0.7nm至1.3nm之间的任一值，第二层绝缘层的厚度为24nm至36nm之间的任一值，电子传输层的厚度为40nm至50nm之间的任一值。较佳的，第一层绝缘层的厚度为60nm， 界面层5的厚度为1nm，第二层绝缘层7的厚度为30nm，电子传输层8的厚度为45nm。
在一实施例中，第一传输层4和发光材料层6的厚度可根据不同器件的需求而设计。
在一实施例中，半导体衬底1可为任何可作为衬底的材料形成，如其可为导电玻璃、硅基板、聚四氟乙烯材料(PTFE)、压电陶瓷等。
在一实施例中，第一层绝缘层3的材料可为二氧化硅(SiO 2)、氧化铝(Al 2O 3)、氮化硅(Si 3N 4)、碳化硅(SiC)、氮化铝(AlN)中的任一者或多种材料的组合。较佳的，第一层绝缘层3的材料为二氧化硅(SiO 2)或氧化铝(Al 2O 3)。
在一实施例中，第一传输层4为空穴传输层。在一实施例中，其包括氧化镍(NiO x)和聚(9-乙烯基咔唑)(PVK)。空穴传输层可为有机空穴传输层和无机空穴传输层，其中有机空穴传输层有但不限于：TFB、PTAA、TAPC、PEDOT:PSS、Poly-TPD、PVK、TCTA、CBP、TPD、CuPc、M-MTDATA、NPB、Rubrene中的至少一者；无机空穴传输层有但不限于：氧化铜(CuO)、氧化镍(NiO x)、三氧化钼(MoO 3)、三氧化钨(WO 3)、五氧化二钒(V 2O 5)中的至少一者。
在一实施例中，界面层5为氟化锂(LiF)层，另界面层5还可为氟化钠(NaF)、氟化钾(KF)、氟化铷(RbF)、氟化铯(CsF)、氟化镁(MgF 2)、氟化钙(CaF 2)等中的一种或者多种的组合。其中界面层5可起到绝缘的作用。
发光材料层6可为由任何电致发光的材料形成，目前现有的或随着技术的发展产生的任何电致发光的材料均在本申请的保护范围内，优选的，为钙钛矿材料，也可以是钙钛矿材料与有机材料、III-V族材料、II-VI族材料、IV族材料、稀土材料、氧化物材料、半导体纳米材料、绝缘材料等中的一种或多种的组合。较佳的，在一实施例中，发光材料层6为钙钛矿材料层。金属卤化物钙钛矿作为新兴的半导体材料其性能与III-V族材料相似。其作为一类低成本和可溶液法制备的半导体材料，表现出了优异的光电性能，如带隙可调、荧光量子产率高、离子迁移距离长和发光带隙窄等特点。在一实施例中，钙钛矿材料层的结构式为ABX 3，其中A位是一价阳离子，B位是二价阳离子，X位是卤素阴离子。A位阳离子包括：铯离子(Cs +)、 甲胺离子(MA +)、甲眯离子(FA +)、乙胺离子(EA +)、肼离子(HA +)、胍离子(GA +)、异丙基胺离子(IPA +)、咪唑离子(IA +)等。B位阳离子包括：铅离子(Pb 2+)、锡离子(Sn 2+)、锗离子(Ge 2+)、铟离子(In 2+)、铋离子(Bi 2+)等。X位阴离子包括：氯离子(Cl -)、溴离子(Br -)、碘离子(I -)等，钙钛矿材料层可以为一维、准二维、三维组分中的一种或者多种的组合。
另发光材料层6位于界面层5上，具体的，发光材料层6与界面层5直接接触，以使发光材料更容易铺展开，发光材料如钙钛矿溶液在界面层5上会与界面层5结合的更加紧密，从而提高形成的发光材料层6的表面的平整度。
如图12所示，第二层绝缘层7覆盖位于第二部分区域12内的发光材料层6，并覆盖位于第一部分区域11内的临近第二部分区域12侧的发光材料层6，以使第一部分区域11内的中心区域111内的发光材料层6没有被第二层绝缘层7覆盖，而裸露出中心区域111内的发光材料层6。在一实施例中，通过调节第一部分区域11内的被第二层绝缘层7覆盖的发光材料层6的尺寸，而调节第一部分区域11内的没有被第二层绝缘层7覆盖的中心区域111尺寸。
在一实施例中，第二层绝缘层7为氟化锂(LiF)层，另第二层绝缘层7还可为氟化钠(NaF)、氟化钾(KF)、氟化铷(RbF)、氟化铯(CsF)、氟化镁(MgF 2)、氟化钙(CaF 2)等中的一种或者多种的组合。
如图12所示，电子传输层8仅覆盖第一部分区域11内的中心区域111。电子传输层8可为有机电子传输层和无机电子传输层两大类，其中有机电子传输层有但不限于：TPBi、BAlq、Phen-m-PhDPO、POPy 2、PO-T2T、Alq 3、B3PYMPM等中的至少一者；无机电子传输层有但不限于：Ga 2O 3、Si 3N 4、ZrO 2、V 2O 5、Al 2O 3、NiO x、MoO 3、ZnO、MgO、NiO、SnO 2、TiO 2等中的至少一者。
本申请通过第一部分区域内的被第二层绝缘层覆盖的发光材料层的尺寸可调，而使得后续形成的电子传输层的尺寸可调，也即光电器件的发光面积大小可调，进而实现单个发光像素点或有效工作区域的特征尺寸可调，也即第二层绝缘层作为特征尺寸限制层，并结合第一 绝缘层实现小型与微型光电器件，如此，不但使器件结构优化，且解决了小型与微型光电器件外量子效率低、亮度低和漏电流大的问题。
在一实施例中，更进一步的，光电器件还包括：金属电极9，金属电极9覆盖第一部分区域11内的中心区域111内的电子传输层8，并延伸至中心区域111的其中一侧的第二层绝缘层上7。
在一实施例中，上述的光电器件为发光二极管。但本发明的光电器件还可拓展到其它光电器件领域，包括但不限于太阳能电池、光电探测器、荧光薄膜、荧光粉、半导体晶体管、激光光电子器件与材料等方面。采用本申请提供的方法制造的小型与微型发光二极管可被应用于显示屏(高端电视、手机、电脑和iPad等电子产品的屏幕)、智能手表、可穿戴设备、AR智能眼镜、微型投影仪等。小型与微型发光二极管还可以和柔性基板结合，实现柔性显示。小型化发光二极管还能够实现背光显示器(电视机屏幕和车载显示器等)、RGB小间距显示器等。
对本申请提供的光电器件及采用本申请提供的光电器件的制造方法形成的光电器件进行测试。以光电器件为发光二极管为例，在测试时采用OLED光色电测试系统测试外量子效率(EQE)，系统由亮度计、吉时利源表2400、电脑上位机、工控摄像头CCD、样品测试台等组成，亮度计用以检测发光二极管的光谱及光谱功率，吉时利源表2400作为发光二极管动力源，承担动力输出和电流检测的功能，以2400引出正负极接线后连接发光二极管正负极，加载到发光器件上的电压范围为1V～5V，电压步进间隔为0.1V，通过发光二极管的电流以四线法测量，电流检测范围1nA～100mA，电流密度范围为10 -4–10 3mA cm -2，故可满足发光二极管电流测试需求。电脑上位机实现与亮度计、吉时利源表2400、工控摄像头CCD交互通讯的功能，获取采集的光谱、光谱功率、电压、电流及检测图像，并实现实时显示功能，样品测试台承担发光二极管样品放置，达到三维位置调节功能，使得观察更清晰、测量更准确，以实现最优化性能测试目的。
图13为对本申请一实施例的光电器件及采用本申请一实施例的光电器件的制造形成的 光电器件的光电性能测试数据示意图。其中(a)中的横轴为加在发光二极管两端的电压(Voltage)，单位为伏特(V)；纵轴是流过发光二极管的电流密度(Current density)，单位为mA cm -2。微型化发光二极管的起亮电压是2.8V。在电压为6.0V的情况下，电流密度达到923.8mA cm -2。其中(b)中的横轴为加在发光二极管两端的电压(Voltage)，单位伏特(V)；纵轴是发光二极管的亮度(Luminance)，单位是cd m -2。在5.7V的时候，发光二极管的亮度达到1070.5cd m -2，发光区域面积为0.04mm 2。其中(c)中的横轴是流过发光二极管的电流密度(Current density)，单位为mA cm -2；纵轴是发光二极管的外量子效率(EQE)，单位为％。微型发光二极管的器件最高EQE约15.2％(4.11×10 -2mA cm -2)。由此可见本申请提供的光电器件及采用本申请提供的光电器件的制造形成的光电器件，不但实现了小型与微型化，且解决了小型与微型光电器件外量子效率低、亮度低和漏电流大的问题。
在一实施例中，本申请提供的光电器件及光电器件的制造方法适用于小型及微型光电器件，其中单个发光像素点或有效工作区域的特征尺寸大于等于200微米而小于等于500微米是小型光电器件，单个发光像素点或有效工作区域的特征尺寸小于等于200微米是微型光电器件。
更进一步的，本申请提供的光电器件还可通过：方法一、直接在小于或等于五百微米尺寸的小型或微型衬底上制备出；或方法二、将常规尺寸的光电器件通过刻蚀方法制备出，所述刻蚀方法包括激光加工、等离子体刻蚀、FIB刻蚀、EBL刻蚀等。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (16)

  1. 一种光电器件的制造方法，所述光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，其特征在于，包括：
    S1：提供一半导体衬底；
    S2：形成一层光刻胶层；
    S3：利用一掩模版对光刻胶层进行曝光显影工艺，使半导体衬底上的第一部分区域被剩余的光刻胶层保护起来，而位于第一部分区域周围的第二部分区域被显开；
    S4：形成第一层绝缘层，第一层绝缘层覆盖剩余的光刻胶层的上表面、第二部分区域对应的半导体衬底的上表面，并光刻胶层的厚度大于第一层绝缘层的厚度；
    S5：进行去胶工艺，以去除剩余的光刻胶层及位于剩余的光刻胶层上的第一层绝缘层；
    S6：形成第一传输层，使第一传输层覆盖第一层绝缘层的上表面及第一部分区域内的半导体衬底；
    S7：在第一传输层上形成一层界面层；
    S8：在界面层上形成一层发光材料层；
    S9：形成第二层绝缘层，使第二层绝缘层覆盖位于第二部分区域内的发光材料层，并覆盖位于第一部分区域内的临近第二部分区域侧的发光材料层，以使第一部分区域内的中心区域内没有被第二层绝缘层覆盖；以及
    S10：在第一部分区域内的中心区域内形成电子传输层。
  2. 根据权利要求1所述的光电器件的制造方法，其特征在于，还包括S11：在第一部分区域内的中心区域内的电子传输层上形成金属电极，并将金属电极延伸至中心区域的其中一侧的第二层绝缘层上。
  3. 根据权利要求1所述的光电器件的制造方法，其特征在于，发光材料层为钙钛矿材料层。
  4. 根据权利要求1所述的光电器件的制造方法，其特征在于，发光材料层为钙钛矿材料与有机材料、III-V族材料、II-VI族材料、IV族材料、稀土材料、氧化物材料、半导体纳米材 料、绝缘材料中的一种或多种的组合。
  5. 根据权利要求1所述的光电器件的制造方法，其特征在于，第一传输层为空穴传输层。
  6. 根据权利要求1所述的光电器件的制造方法，其特征在于，第一层绝缘层的材料为二氧化硅、氧化铝、氮化硅、碳化硅、氮化铝中的任一者或多种材料的组合。
  7. 根据权利要求1所述的光电器件的制造方法，其特征在于，发光材料层与界面层直接接触。
  8. 根据权利要求1所述的光电器件的制造方法，其特征在于，通过调节第一部分区域内的被第二层绝缘层覆盖的发光材料层的尺寸，而调节第一部分区域内的没有被第二层绝缘层覆盖的中心区域尺寸，而调节电子传输层的尺寸。
  9. 根据权利要求1所述的光电器件的制造方法，其特征在于，通过掩模版限制形成第二层绝缘层的位置，而使第一部分区域内仅临近第二部分区域侧的发光材料层被第二层绝缘层覆盖。
  10. 根据权利要求1所述的光电器件的制造方法，其特征在于，通过掩模版限制形成电子传输层的位置，而使仅在第一部分区域内的中心区域内形成有电子传输层。
  11. 一种光电器件，所述光电器件的单个发光像素点或有效工作区域的特征尺寸小于等于500微米，其特征在于，包括：
    半导体衬底，其中半导体衬底的第一部分区域上形成有第一传输层，位于第一部分区域周围的第二部分区域上形成有第一层绝缘层，并第一层绝缘层上形成有第一传输层；
    在第一传输层上形成有一层界面层；
    在界面层上形成有一层发光材料层；
    第二部分区域内的发光材料层上及第一部分区域内的临近第二部分区域侧的发光材料层上形成有第二层绝缘层，而第一部分区域内的中心区域内的发光材料层上形成有一层电子传输层。
  12. 根据权利要求11所述的光电器件，其特征在于，发光材料层为钙钛矿材料层。
  13. 根据权利要求11所述的光电器件，其特征在于，第一传输层为空穴传输层。
  14. 根据权利要求11所述的光电器件，其特征在于，发光材料层与界面层直接接触。
  15. 根据权利要求11所述的光电器件，其特征在于，通过调节第一部分区域内的被第二层绝缘层覆盖的发光材料层的尺寸，而调节第一部分区域内的没有被第二层绝缘层覆盖的中心区域尺寸，而调节电子传输层的尺寸。
  16. 根据权利要求11所述的光电器件，其特征在于，第一层绝缘层的材料为二氧化硅、氧化铝、氮化硅、碳化硅、氮化铝中的任一者或多种材料的组合。
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