WO2022217795A1 - 失效位置的修补方法和装置 - Google Patents

失效位置的修补方法和装置 Download PDF

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Publication number
WO2022217795A1
WO2022217795A1 PCT/CN2021/112689 CN2021112689W WO2022217795A1 WO 2022217795 A1 WO2022217795 A1 WO 2022217795A1 CN 2021112689 W CN2021112689 W CN 2021112689W WO 2022217795 A1 WO2022217795 A1 WO 2022217795A1
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WIPO (PCT)
Prior art keywords
historical
potential
potential failure
target
failure
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PCT/CN2021/112689
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English (en)
French (fr)
Inventor
仰蕾
陈予郎
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长鑫存储技术有限公司
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Priority to US17/666,552 priority Critical patent/US20220334913A1/en
Publication of WO2022217795A1 publication Critical patent/WO2022217795A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • the present application relates to, but is not limited to, a method and device for repairing a failure location.
  • the corresponding spare circuit is usually allocated for the fail bit (Fail Bit, FB) position and the predicted fail bit position in the wafer; and in the fusing stage, according to Corresponding backup circuits patch the failed bit locations and predicted failed bit locations.
  • the failed bit position refers to the row position or column position of the currently faulty bit; the predicted failed bit position refers to the current faulty bit, and the subsequent prediction based on artificial experience may occur in multiple channels.
  • the embodiments of the present application provide a method and device for repairing a failure position.
  • the failure bit position can be avoided to a certain extent from being missed, thereby effectively reducing the probability of wafer failure.
  • an embodiment of the present application provides a method for repairing a failure position, and the method for repairing the failure position includes:
  • the mining rule base Based on the mining rules in the mining rule base, determine the target potential invalid bits associated with the invalid bits; wherein, the mining rule base includes potential mining rules, and the potential mining rules are determined based on preset mining rules of potential failure locations.
  • an embodiment of the present application further provides a device for repairing a failure position, and the device for repairing a failure position may include:
  • the determining unit is used for determining the failed bits in the wafer to be processed.
  • a processing unit configured to determine, based on the mining rules in the mining rule base, a target potential failure bit associated with the failed bit; wherein, the mining rule base includes potential mining rules, and the potential mining rules are based on Potential failure locations determined by preset mining rules.
  • the repairing unit is used for repairing the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit to obtain a repaired target wafer.
  • an embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the failure described in any possible implementation manner of the first aspect above location fixes.
  • an embodiment of the present application further provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor, the processor implementing the above-mentioned first program when the processor executes the program.
  • a computer device including a memory, a processor, and a computer program stored in the memory and running on the processor, the processor implementing the above-mentioned first program when the processor executes the program.
  • an embodiment of the present application further provides a computer program product, where the computer program product includes: a computer program, where the computer program is stored in a readable storage medium, and at least one processor of an electronic device can download the computer program from the computer program.
  • the readable storage medium reads the computer program, and the at least one processor executes the computer program to cause the electronic device to execute the method for repairing the failure location described in any possible implementation manner of the first aspect above.
  • FIG. 1 is a schematic flowchart of a method for repairing a failure position according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a method for determining a potential mining rule provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of the relationship between a historical potential failure position and a historical target potential failure position provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of the relationship between another historical potential failure position and a historical target potential failure position provided by an embodiment of the present application;
  • FIG. 5 is a schematic diagram of the relationship between another historical potential failure position and a historical target potential failure position according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a sequence curve provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a differential curve provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a position corresponding to a maximum differential value provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for dynamically updating a mining rule base according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a repairing device for a failure position provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another computer device provided by an embodiment of the present application.
  • “at least one” refers to one or more, and “a plurality” refers to two or more.
  • “And/or”, which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.
  • the character "/" generally indicates that the contextual object is an "or" relationship.
  • a wafer includes many arrays, each array includes a plurality of cells, and each cell can be recorded as a bit, that is, each wafer includes tens of thousands of bits.
  • the tens of thousands of bits may include multiple failed bits. Therefore, in the circuit probe test (CP Test) stage, the location of the failed bits in the wafer is usually determined and predicted. Then, in the fusing stage, according to the corresponding spare circuit, the position of the failed bit and the predicted failure bit position are assigned to the corresponding spare circuit. Meta location for patching.
  • CP Test circuit probe test
  • the embodiment of the present application provides a method for repairing a failure position.
  • the failed bit in the wafer to be processed can be determined first; Mining rules, to determine the target potential failure bits associated with the failed bits; wherein, the mining rule base includes potential mining rules, and the potential mining rules are obtained based on the potential failure positions determined by the preset mining rules; After the bit has a target potential failure bit associated with it, the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit can be repaired to obtain a repaired target wafer.
  • the mining rules in the mining rule base may include, in addition to the potential mining rules obtained based on the potential failure positions determined by the preset mining rules, preset mining rules, which may be specifically set according to actual needs.
  • the preset mining rules may be understood as existing mining rules obtained by relying on manual experience in the prior art. Usually, the preset mining rules are some explicit mining rules that are easier to find.
  • the mining rule is used to describe the association relationship between the faulty failed bits and the potentially failed bits. Therefore, after determining the failed bits in the wafer to be processed, Based on the potential mining rules included in the mining rule base, the target potential failure bits associated with the failed bits can be determined, so that more potential failure bits can be mined, so that the subsequent failure positions corresponding to the failed bits, When the target potential failure position corresponding to the target potential failure bit is repaired, the missing position of the failed bit can be avoided to a certain extent, thereby effectively reducing the probability of wafer failure.
  • the failed bit in the wafer to be processed when repairing the failure position of the wafer, can be determined first; and based on the potential mining rules included in the mining rule library, the In this way, based on the potential mining rules in the mining rule base, the target potential failure bits associated with the failed bits can be determined, and more target potential failure bits associated with the failed bits can be mined. Failure bit, so that the subsequent repair of the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit can avoid the missing bit position to a certain extent, thus effectively reducing the cost of Probability of wafer failure.
  • the target potential failure bits associated with the failed bits can be determined.
  • the time cost of manual observation can be reduced, thereby reducing the time cost of manual observation.
  • the mining efficiency of potentially failed bits has been improved.
  • FIG. 1 is a schematic flowchart of a method for repairing a failure position provided by an embodiment of the present application.
  • the method for repairing a failure position may be performed by software and/or a hardware device, and the hardware device may be a repair device for the failure position.
  • the repairing method of the failure position may include:
  • the failed bit refers to the currently determined failed bit that has a fault.
  • a testing machine when determining the failed bits in the wafer to be processed, a testing machine, probe card, probe station, etc. can be used to test various test items on the wafer to be processed, such as each chip in the wafer to be processed. The voltage, current, timing and function of the chip are verified, and the bits that do not meet the test results in each chip are screened out as invalid bits.
  • the target potential failure bit associated with the failed bit can be determined based on the potential mining rules included in the mining rule base, that is, the following S102 is performed:
  • the mining rule base includes potential mining rules, and the potential mining rules are obtained based on the potential failure positions determined by the preset mining rules.
  • the mining rules in the mining rule base may include, in addition to the potential mining rules obtained based on the potential failure positions determined by the preset mining rules, preset mining rules, which may be specifically set according to actual needs.
  • the preset mining rules may be understood as existing mining rules obtained by relying on manual experience in the prior art. Usually, the preset mining rules are some explicit mining rules that are easier to find.
  • the potential mining rules included in the mining rule base can be used to mine rules to determine the target potential failure bits associated with the failed bits, so as to dig out more potential failure bits, so that the subsequent failure positions corresponding to the failed bits and the target potential failure bits corresponding to the target potential failure bits When the position is repaired, it can avoid the missing of the failed bit position to a certain extent, thereby effectively reducing the probability of wafer failure.
  • a spare integrated circuit can be used to repair the failure position corresponding to the failed bit and the target potential failure bit.
  • the corresponding target potential failure position is carried out, so as to realize the repair of the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit.
  • the failed bit in the wafer to be processed when repairing the failure position of the wafer, can be determined first; and based on the potential mining rules included in the mining rule library, the In this way, based on the potential mining rules in the mining rule base, the target potential failure bits associated with the failed bits can be determined, and more target potential failure bits associated with the failed bits can be mined. Failure bit, so that the subsequent repair of the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit can avoid the missing bit position to a certain extent, thus effectively reducing the cost of Probability of wafer failure.
  • the potential mining rule can be constructed based on historical sample data. The following will describe in detail how to construct a potential mining rule based on historical sample data in this embodiment of the present application through the embodiment shown in FIG. 2 below. .
  • FIG. 2 is a schematic flowchart of a method for determining a potential mining rule provided by an embodiment of the present application.
  • the method for determining a potential mining rule may be executed by software and/or a hardware device, and the hardware device may also be a repairing device at a failure location.
  • the method for determining potential mining rules may include:
  • the historical failure bit can be understood as the failure bit determined to have a fault in the historical CP Test stage.
  • the historical potential failure position can be understood as the potential failure position predicted by the preset mining rules formed by artificial experience prediction based on the determined failure bits in the historical CP Test stage.
  • the newly added expired bits in the history can be understood as the aging bits added in the subsequent test stages after the historical CP Test stage.
  • the historical sample data includes historical new failure bits and historical potential failure positions, and may also include historical failure bits, which can be set according to actual needs.
  • the historical newly added failure bits and historical potential failure positions are taken as examples for description, but it does not mean that the embodiments of the present application are limited thereto.
  • more potential mining rules can be mined based on historical sample data, and based on the potential mining rules, Dig out more potential failed bits associated with the failed bits, so that when repairing the failed location, the location of the failed bit can be avoided to a certain extent, thus effectively reducing the probability of wafer failure .
  • the position of the adjacent bits around the historical potential failure position may be determined as the historical target potential failure position, that is, the following S202 is performed. :
  • the target type to which the historical potential failure position belongs may be combined; wherein, the target type includes redundant word line types and redundant bit lines. type; and according to the target type, determine the position of the bit adjacent to the historical potential failure position as the historical target potential failure position.
  • the position immediately around the historical potential failure position when the position of the position immediately around the historical potential failure position is determined as the historical target potential failure position according to the target type, the position immediately around the historical potential failure position can be determined according to the target type, and the distance between the historical potential failure position and the historical potential failure position is the first.
  • the bit position of the preset number of bits is determined as the potential failure position of the historical target.
  • the first preset number may be one or two, and may be specifically set according to actual needs.
  • the first preset number may be one, which is only used as an example for description, but does not mean that the embodiment of the present application is limited to this.
  • the target type when determining the position of the historical target potential failure position that is immediately adjacent to the historical potential failure position and is away from the historical potential failure position by the first preset number of bits as the historical target potential failure position, in one case, If the target type is a redundant word line type, the bit position in the bit line direction that is away from the historical potential failure position by the first preset number of bits is determined as the historical target potential failure position.
  • the first preset number of 1 as an example, reference can be made to FIG. 3 , which is a schematic diagram of a relationship between a historical potential failure position and a historical target potential failure position provided by an embodiment of the present application, as shown in FIG. 3 .
  • the position with a slash in position N is the historical potential failure position
  • the position numbered #1 and the position numbered #2 in position N are the historical target of the bit position 1 bit away from the historical potential failure position Potential failure location.
  • FIG. 4 is a schematic diagram of the relationship between another historical potential failure position and a historical target potential failure position provided by an embodiment of the present application.
  • the positions shown with a slash in position N are historical potential failure positions, position number #1 in position N, position number #4 in position N, position number #2 in position N-1, and position N+
  • the position numbered #3 in 1 is the historical target potential failure position of the bit position that is 1 bit away from the historical potential failure position.
  • FIG. 5 is a schematic diagram of the relationship between another historical potential failure position and a historical target potential failure position provided by an embodiment of the present application.
  • the positions shown with small square dots in position N are general repair positions containing failed bits, positions with slashes in position N-1, positions with slashes in position N, and positions with slashes in position n+1 are historical potential failure positions associated with the failure position; the position numbered #5 in position N-2, the position numbered #3 in position N-1, and the position numbered #7 in position N-1 are The historical target potential failure position of the historical potential failure position with a slash in position N-1; the position numbered #1 in position N and the position numbered #2 in position N are the historical potential failure position with a slash in position N Historical target potential failure locations for locations; location #4 in location N+1, location #8 in location N+1, and location #6 in location N+2 are in location N+1 The historical target potential failure position of the slashed
  • the potential failure position of the historical target is determined based on the positions of the adjacent bits around the historical potential failure position, because the potential failure position of the historical target is not necessarily the real failure position, therefore , it is impossible to directly determine the relationship between the position of the historical failure bit and the potential failure position of the historical target as a potential mining rule; instead, it is necessary to combine the historically newly added failed bits included in the historical sample data, that is, to add new failure bits according to the historical data.
  • the failure bit and the potential failure position of the historical target jointly determine the potential mining rule, that is, execute the following S203:
  • the number of potential failure locations of the historical target may be one or multiple, which may be set according to actual needs.
  • the embodiment of the present application does not further limit the number of potential failure locations of the historical target.
  • the potential failure position of the historical target for each potential failure position of the historical target among the potential failure positions of the multiple historical targets, if it is determined that the potential failure position of the historical target does not include a historically newly added failure bit, it indicates the potential failure position of the historical target. There is no relationship with the failure position, that is, when there is a failure at the failure position, the potential failure position of the historical target will not fail.
  • the potential failure position of the target includes the newly added failure bits in history, indicating that the potential failure position of the historical target is related to the failure position, that is, when there is a failure in the failure position, the potential failure position of the historical target is likely to fail. Therefore, , the number of times of updating the relationship combination corresponding to the potential failure position of the historical target. For example, 1 can be added to the previous number to obtain the updated number of the relationship combination corresponding to the potential failure position of the historical target, so that the potential failure of each historical target can be obtained. The number of times the relationship combination corresponding to the position is updated.
  • the relationship combination includes the identification of the preset mining rule and the identification of the potential failure position of the historical target.
  • the relationship combination corresponding to the potential failure position of each historical target can be sorted according to the updated times of the relationship combination corresponding to the potential failure position of each historical target. Sort the sequence in the smallest order to get the relationship sequence; fit the relationship sequence corresponding to the potential failure position of each historical target after sorting, and obtain the sequence curve corresponding to the potential failure position of each historical target.
  • FIG. 6 is a schematic diagram of a sequence curve provided by an embodiment of the present application.
  • the horizontal axis in FIG. 6 represents the relationship combination, and the vertical axis represents the number of times after the relationship combination is updated.
  • the potential mining rules can be further determined according to the sequence curve.
  • the sequence curve may be differentiated to obtain the differential curve corresponding to the potential failure position of each historical target.
  • FIG. 7 is a schematic diagram of a differential curve provided by an embodiment of the present application.
  • the horizontal axis in FIG. 7 still represents the relationship combination, and the vertical axis still represents the number of times after the relationship combination is updated.
  • the potential mining rule can be determined according to the differential curve.
  • FIG. 8 is a schematic diagram of a position corresponding to a maximum differential value provided by an embodiment of the present application, the horizontal axis in FIG. 8 still represents the relationship combination, and the vertical axis still represents the number of times after the relationship combination is updated.
  • the historical target potential failure position ⁇ corresponding to the differential value After the historical target potential failure position ⁇ corresponding to the differential value, for the historical target potential failure position greater than the number of times of the relationship combination corresponding to the historical target potential failure position corresponding to the maximum differential value, when there is a fault at the failure position, because it is greater than the maximum differential value corresponding to the historical target potential failure position.
  • the number of times the relationship between the potential failure positions of the historical target and the potential failure position of the historical target will also fail to a large extent. Therefore, the history of the number of times the relationship between the potential failure positions of the historical target corresponding to the maximum differential value can be directly combined.
  • the relationship between the target potential failure position and the historical failure position corresponding to the historical failure bit is determined as the potential mining rule, thus the acquired potential mining rule.
  • the potential failure positions of the historical targets can be respectively Determine the number of historically newly added failure bits included in the potential failure positions of each historical target; and determine potential mining rules according to the number of historically newly added failure bits included in the potential failure positions of each historical target.
  • the potential failure position of the historical target will also fail to a large extent, and the number of failed bits in the potential failure position of the historical target is relatively large. Therefore, in a possible way, it can be In the order of the number from large to small, among the potential failure positions of multiple historical targets, the second preset number of potential failure positions of historical targets are ranked first, and the relationship between them and the historical failure positions corresponding to the historical failure bits is determined. Rules for potential mining.
  • the number of historical target potential failure positions included in the multiple historical target potential failure positions can be directly compared with the historical target failure positions respectively.
  • the relationship between the corresponding historical failure positions is determined as a potential mining rule.
  • the values of the second preset number and the third preset number may be set according to actual needs.
  • the values of the second preset number and the third preset number are not further discussed in this embodiment of the present application. limit.
  • the historical sample data when determining the potential mining rule, can be used to determine the position of the adjacent bits around the historical potential failure position included in the historical sample data as the historical target potential failure position; and
  • the potential mining rules are determined according to the historical newly added failed bits and the historical target potential failure positions included in the historical sample data.
  • the target potential failure bits associated with the failed bits can be determined based on the potential mining rules in the future, and more target potential failure bits associated with the failed bits can be mined, so that the corresponding potential failure bits can be subsequently identified.
  • the mining rules included in the above mining rule base are not always able to accurately determine the target potential failure bit associated with the failed bit.
  • inaccurate mining rules need to be excluded, that is, the mining rule base is dynamic, not just increasing.
  • FIG. 9 how to effectively dynamically update the mining rule base in this embodiment of the present application will be described in detail through the embodiment shown in FIG. 9 below.
  • FIG. 9 is a schematic flowchart of a method for dynamically updating a mining rule base according to an embodiment of the present application.
  • the method for dynamically updating a mining rule base may be executed by software and/or a hardware device, and the hardware device may also be Repair device at the location of failure.
  • the method for dynamically updating the mining rule base may include:
  • the preset mining corresponding to the historical potential failure positions in which the number of historically newly added failure bits included in the multiple historical potential failure positions is less than the fourth preset number can be directly mined.
  • Rule which is determined to be an invalid mining rule.
  • the value of the fourth preset number may be set according to actual needs.
  • the value of the fourth preset number is not further limited in this embodiment of the present application.
  • the invalid mining rules can be deleted from the mining rule base, thereby realizing dynamic updating of the mining rule base.
  • invalid mining rules can be determined according to the historical newly added invalid bits and historical potential failure positions, and the invalid mining rules are deleted from the mining rule base, so that inaccurate invalid mining can be excluded.
  • the rules realize the dynamic update of the mining rule base, thereby improving the accuracy of the mining rule base.
  • FIG. 10 is a schematic structural diagram of a repairing device 100 at a failure position according to an embodiment of the present application.
  • the repairing device 100 at the failure position may include:
  • the determining unit 1001 is used for determining the failed bits in the wafer to be processed.
  • the processing unit 1002 is configured to determine, based on the mining rules in the mining rule base, the target potential failure bits associated with the failed bits; wherein, the mining rule base includes potential mining rules, and the potential mining rules are determined based on preset mining rules of potential failure locations.
  • the repairing unit 1003 is used for repairing the failure position corresponding to the failed bit and the target potential failure position corresponding to the target potential failure bit to obtain a repaired target wafer.
  • the repairing device 100 at the failure position further includes an acquiring unit 1004 .
  • the obtaining unit 1004 is configured to obtain historical sample data, wherein the historical sample data includes historically newly added failed bits associated with the historically failed bits, and historical potential failure positions determined based on preset mining rules.
  • the processing unit 1002 is further configured to determine the position of the bit adjacent to the historical potential failure position as the historical target potential failure position; and determine the potential mining rule according to the historical newly added failed bit and the historical target potential failure position.
  • the processing unit 1002 is specifically used to determine the target type to which the historical potential failure position belongs; wherein, the target type includes redundant word line type and redundant bit line type; The bit position of is determined as the historical target potential failure position.
  • the processing unit 1002 is specifically configured to determine, according to the target type, a bit position that is immediately adjacent to the historical potential failure position and is away from the historical potential failure position by a first preset number of bits as the historical target potential failure position.
  • the processing unit 1002 is specifically configured to, if the target type is a redundant word line type, determine the bit position in the direction of the bit line that is a first preset number of bits away from the historical potential failure position as the historical target. Potential failure position; if the target type is a redundant bit line type, the bit position in the word line direction that is away from the historical potential failure position by the first preset number of bits is determined as the historical target potential failure position.
  • the number of potential failure positions of the historical target is multiple; the processing unit 1002 is specifically configured to, for each potential failure position of the historical target in the potential failure positions of the multiple historical targets, if it is determined that the potential failure position of the historical target includes the historical target potential failure position If a new failure bit is added, the times of the relationship combination corresponding to the potential failure position of the historical target is updated; wherein, the relationship combination includes the identification of the preset mining rule and the identification of the potential failure position of the historical target; and according to the updated potential failure position of each historical target
  • the number of relationship combinations corresponding to the failure positions sort the relationship combinations corresponding to the potential failure positions of each historical target according to the order of times from large to small, and obtain the relationship sequence; By fitting, the sequence curve corresponding to the potential failure position of each historical target is obtained; the potential mining rule is determined according to the sequence curve.
  • the processing unit 1002 is specifically configured to perform differential processing on the sequence curve to obtain a differential curve corresponding to the potential failure position of each historical target; and determine the potential mining rule according to the differential curve corresponding to the potential failure position of each historical target.
  • the processing unit 1002 is specifically configured to determine the potential failure position of the historical target corresponding to the maximum differential value in the differential curve corresponding to the potential failure position of each historical target; and determine the potential mining potential according to the potential failure position of the historical target corresponding to the maximum differential value. rule.
  • the processing unit 1002 is specifically configured to combine, among the relationship combinations corresponding to the potential failure positions of each historical target, the potential failure positions of the historical target that are greater than the number of times of the relationship combination of the potential failure positions of the historical target corresponding to the maximum differential value, and the potential failure position of the historical target.
  • the association relationship between the historical failure positions corresponding to the bits is determined as a potential mining rule.
  • the number of potential failure positions of the historical target is multiple; the processing unit 1002 is specifically configured to, for each potential failure position of the historical target in the potential failure positions of the multiple historical targets, respectively determine the potential failure positions included in the potential failure positions of each historical target.
  • the number of newly added failed bits in history; and the potential mining rules are determined according to the number of newly newly added failed bits included in the potential failure positions of each historical target.
  • the processing unit 1002 is specifically configured to, in the order of the number from large to small, the first second preset number of potential failure positions of the historical target among the potential failure positions of the multiple historical targets, respectively correspond to the historical failure bits.
  • the association relationship between the historical failure positions is determined as the potential mining rule.
  • the processing unit 1002 is specifically configured to compare the number of historically newly added failure bits included in the multiple historical target potential failure locations with the historical target potential failure locations that are greater than the third preset number, respectively, with the historical target potential failure locations.
  • the relationship between the corresponding historical failure positions is determined as a potential mining rule.
  • processing unit 1002 is further configured to determine invalid mining rules according to the newly added invalid bits and historical potential failure positions; and delete the invalid mining rules from the mining rule base.
  • the processing unit 1002 is specifically configured to, for each historical potential failure position in a plurality of historical potential failure positions, respectively determine the number of historically newly added bits included in each historical potential failure position; and according to each historical potential failure position The number of historically added invalid bits included in the location determines invalid mining rules.
  • the processing unit 1002 is specifically configured to determine the preset mining rules corresponding to the historical potential failure positions where the number of historically newly added failure bits included in the multiple historical potential failure positions is less than the fourth preset number as: Invalid mining rule.
  • the repairing device 100 for the failure position shown in the embodiment of the present application can perform the repairing method for the failure position shown in any of the above embodiments, and its implementation principle and beneficial effects are similar to the realization principle and beneficial effect of the repairing method for the failure position, Please refer to the implementation principle and beneficial effects of the method for repairing the failure position, which will not be repeated here.
  • FIG. 11 is a schematic structural diagram of another computer device provided by an embodiment of the application.
  • the computer device includes:
  • the realization principle and beneficial effects thereof are similar to those of the method for repairing the failure position. Please refer to the realization principle and beneficial effects of the method for repairing the failure position, which will not be repeated here.
  • Embodiments of the present application also provide a readable storage medium on which a computer program is stored.
  • the program is executed by a processor, the method for repairing the failure position shown in any of the above embodiments is implemented, and the implementation principle and beneficial effects thereof are the same as The implementation principle and beneficial effects of the method for repairing the failure position are similar, and reference may be made to the realization principle and beneficial effects of the method for repairing the failure position, which will not be repeated here.
  • An embodiment of the present application further provides a computer program product, the computer program product includes: a computer program, where the computer program is stored in a readable storage medium, and at least one processor of an electronic device can download the computer program from the readable storage medium Read the computer program, the at least one processor executes the computer program to make the electronic device execute the method for repairing the failure position shown in any of the above embodiments, its implementation principle and beneficial effects and the realization of the method for repairing the failure position The principles and beneficial effects are similar, and reference may be made to the implementation principles and beneficial effects of the method for repairing the failure position, which will not be repeated here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.
  • the above-mentioned integrated modules implemented in the form of software functional modules may be stored in a computer-readable storage medium.
  • the above-mentioned software function modules are stored in a storage medium, and include several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute the methods of the various embodiments of the present application. some steps.
  • processor may be a central processing unit (English: Central Processing Unit, referred to as: CPU), or other general-purpose processors, digital signal processors (English: Digital Signal Processor, referred to as: DSP), dedicated Integrated circuit (English: Application Specific Integrated Circuit, referred to as: ASIC) and so on.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the invention can be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the memory may include high-speed RAM memory, and may also include non-volatile storage NVM, such as at least one magnetic disk memory, and may also be a U disk, a removable hard disk, a read-only memory, a magnetic disk or an optical disk, and the like.
  • NVM non-volatile storage
  • the bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, or the like.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of the present application are not limited to only one bus or one type of bus.
  • the above computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM) , Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic Disk or Optical Disk.
  • SRAM Static Random Access Memory
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • EPROM Erasable Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Magnetic Disk Magnetic Disk or Optical Disk.
  • a storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

Abstract

本申请实施例提供了一种失效位置的修补方法和装置，在对晶圆的失效位置进行修补时，可以先确定待处理晶圆中的失效位元；并基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元；这样基于挖掘规则库中的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，可以挖掘出更多的与失效位元存在关联的目标潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。

Description

失效位置的修补方法和装置
本申请基于申请号为202110407955.9，申请日为2021年04月15日，申请名称为“失效位置的修补方法和装置”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于一种失效位置的修补方法和装置。
背景技术
在电路探针测试(Circuit Probe Test，CP Test)阶段，通常会为晶圆中的失效位元(Fail Bit，FB)位置和预测失效位元位置分配对应的备用电路；并在熔断阶段，根据对应的备用电路对失效位元位置和预测失效位元位置进行修补。
其中，失效位元位置是指当前已经出现故障的位元所在的行位置或者列位置；预测失效位元位置是指基于当前已经出现故障的位元，依靠人工经验预测的后续可能会在多道测试阶段出现故障的位元所在的行位置或者列位置。
但是，依靠人工经验确定预测失效位元位置，会存在部分失效位元位置被遗漏的问题，从而无法及时对这些部分失效位元位置进行修补，从而导致晶圆出现故障的概率较高。
发明内容
本申请实施例提供了一种失效位置的修补方法和装置，在对失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
第一方面，本申请实施例提供了一种失效位置的修补方法，该失效位置的修补方法包括：
确定待处理晶圆中的失效位元。
基于挖掘规则库中的挖掘规则，确定与所述失效位元存在关联的目标潜在失效位元；其中，所述挖掘规则库中包括潜在挖掘规则，所述潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的。
对所述失效位元对应的失效位置，和所述目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
第二方面，本申请实施例还提供了一种失效位置的修补装置，该失效位置的修补装置可以包括：
确定单元，用于确定待处理晶圆中的失效位元。
处理单元，用于基于挖掘规则库中的挖掘规则，确定与所述失效位元存在关联的目标潜在失效位元；其中，所述挖掘规则库中包括潜在挖掘规则，所述潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的。
修补单元，用于对所述失效位元对应的失效位置，和所述目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
第三方面，本申请实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述第一方面任一种可能的实现方式中所述的失效位置的修补方法。
第四方面，本申请实施例还提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述第一方面任一种可能的实现方式中所述的失效位置的修补方法。
第五方面，本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序，所述计算机程序存储在可读存储介质中，电子设备的至少一个处理器可以从所述可读存储介质读取所述计算机程序，所述至少一个处理器执行所述计算机程序使得电子设备执行上述第一方面任一种可能的实现方式中所述的失效位置的修补方法。
附图说明
图1为本申请实施例提供的一种失效位置的修补方法的流程示意图；
图2为本申请实施例提供的一种确定潜在挖掘规则的方法的流程示意图；
图3为本申请实施例提供的一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图；
图4为本申请实施例提供的另一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图；
图5为本申请实施例提供的又一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图；
图6为本申请实施例提供的一种序列曲线的示意图；
图7为本申请实施例提供的一种微分曲线的示意图；
图8为本申请实施例提供的一种最大微分值对应的位置的示意图；
图9为本申请实施例提供的一种对挖掘规则库进行动态更新的方法的流程示意图；
图10为本申请实施例提供的一种失效位置的修补装置的结构示意图；
图11为本申请实施例提供的另一种计算机设备的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在本申请的实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。在本申请的文字描述中，字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例提供的技术方案可以应用于晶圆检测场景中。晶圆中包括很多阵列，每一个阵列中包括多个单元，每一个单元可记为一个位元，即每一个晶圆中包括数以万计的位元。该数以万计的位元中可能会包括多个失效位元，因此，在电路探针测试(Circuit Probe Test，CP Test)阶段，通常会确定晶圆中的失效位元位置和预测失效位元位置，并为晶圆中的失效位元(Fail  Bit，FB)位置和预测失效位元位置分配对应的备用电路；之后在熔断阶段，根据对应的备用电路对失效位元位置和预测失效位元位置进行修补。但是，依靠人工经验确定预测失效位元位置，会存在部分失效位元位置被遗漏的问题，从而无法及时对这些部分失效位元位置进行修补，从而导致晶圆出现故障的概率较高。
为了能够在CP Test阶段，挖掘出更多的失效位元位置，以及时对这些失效位元位置进行修补，可以考虑结合更多的挖掘规则挖掘出更多的与失效位元存在关联的潜在失效位元，而不只是依靠人工经验确定预测失效位元位置，这样就可以挖掘出更多的与失效位元存在关联的潜在失效位元，使得在对失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
基于上述技术构思，本申请实施例提供了一种失效位置的修补方法，在对晶圆的失效位置进行修补时，可以先确定待处理晶圆中的失效位元；并基于挖掘规则库中的挖掘规则，确定与失效位元存在关联的目标潜在失效位元；其中，挖掘规则库中包括潜在挖掘规则，潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的；在确定出与失效位元存在关联的目标潜在失效位元后，可以对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
示例的，挖掘规则库中的挖掘规则除了包括基于预设挖掘规则确定的潜在失效位置得到的潜在挖掘规则之外，还可以包括预设挖掘规则，具体可以根据实际需要进行设置。其中，预设挖掘规则可以理解为现有技术中，依靠人工经验得到的已经存在的挖掘规则。通常情况下，预设挖掘规则是一些显式的，比较容易发现的挖掘规则。
可以理解的是，在本申请实施例中，挖掘规则用于描述存在故障的失效位元与潜在失效位元之间的关联关系，因此，在确定出待处理晶圆中的失效位元后，就可以基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，从而挖掘出更多的潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
可以看出，本申请实施例中，在对晶圆的失效位置进行修补时，可以先 确定待处理晶圆中的失效位元；并基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元；这样基于挖掘规则库中的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，可以挖掘出更多的与失效位元存在关联的目标潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
此外，通过挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，与依靠人工经验确定潜在失效位元相比，可以减少人工观察所花费的时间成本，从而提高了潜在失效位元的挖掘效率。
下面，将通过具体的实施例对本申请实施例提供的失效位置的修补方法进行详细的说明。可以理解的是，在本申请实施例中，下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。
图1为本申请实施例提供的一种失效位置的修补方法的流程示意图，该失效位置的修补方法可以由软件和/或硬件装置执行，该硬件装置可以为失效位置的修补装置。示例的，请参见图1所示，该失效位置的修补方法可以包括：
S101、确定待处理晶圆中的失效位元。
可以理解的是，失效位元指的是当前已经确定的存在故障的失效位元。
示例的，在确定待处理晶圆中的失效位元时，可以利用测试机、探针卡、探针台等对待处理晶圆进行多种测试项目的测试，例如对待处理晶圆中每个芯片的电压、电流、时序和功能进行验证，将各芯片中不符合测试结果的位元作为失效位元筛选出来。
在确定出待处理晶圆中当前已经存在故障的失效位元后，就可以基于挖掘规则库中包括的潜在挖掘规则确定与失效位元存在关联的目标潜在失效位元，即执行下述S102：
S102、基于挖掘规则库中的挖掘规则，确定与失效位元存在关联的目标潜在失效位元。其中，挖掘规则库中包括潜在挖掘规则，潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的。
示例的，挖掘规则库中的挖掘规则除了包括基于预设挖掘规则确定的潜 在失效位置得到的潜在挖掘规则之外，还可以包括预设挖掘规则，具体可以根据实际需要进行设置。其中，预设挖掘规则可以理解为现有技术中，依靠人工经验得到的已经存在的挖掘规则。通常情况下，预设挖掘规则是一些显式的，比较容易发现的挖掘规则。
鉴于挖掘规则用于描述存在故障的失效位元与潜在失效位元之间的关联关系，因此，在确定出待处理晶圆中的失效位元后，就可以基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，从而挖掘出更多的潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
S103、对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
示例的，在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以采用备用的集成电路对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行，从而实现对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置的修补。
可以看出，本申请实施例中，在对晶圆的失效位置进行修补时，可以先确定待处理晶圆中的失效位元；并基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元；这样基于挖掘规则库中的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，可以挖掘出更多的与失效位元存在关联的目标潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
基于上述图1所示的实施例，可以理解的是，在上述S102中，基于挖掘规则库中包括的潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元之前，需要先构造该潜在挖掘规则，之后，才能基于潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元。在构造潜在挖掘规则时，可以基于历史样本数据构造该潜在挖掘规则，下面，将通过下述图2所示的实施例，详细描述在本申请实施例中，如何基于历史样本数据构造潜在挖掘规则。
图2为本申请实施例提供的一种确定潜在挖掘规则的方法的流程示意图，该确定潜在挖掘规则的方法可以由软件和/或硬件装置执行，该硬件装置同样可以为失效位置的修补装置。示例的，请参见图2所示，该确定潜在挖掘规则的方法可以包括：
S201、获取历史样本数据；其中，历史样本数据包括与历史失效位元关联的历史新增失效位元、以及基于预设挖掘规则确定的历史潜在失效位置。
其中，历史失效位元可以理解为在历史CP Test阶段中，确定的存在故障的失效位元。历史潜在失效位置可以理解为在历史CP Test阶段中，基于已确定的存在故障的失效位元，依赖人工经验预测形成的预设挖掘规则预测得到的潜在失效位置。历史新增失效位元可以理解为经过历史CP Test阶段，在后续的测试阶段中新增的时效位元。
示例的，历史样本数据包括历史新增失效位元和历史潜在失效位置之外，还可以包括历史失效位元，具体可以根据实际需要进行设置，在此，本申请实施例只是以历史样本数据包括历史新增失效位元和历史潜在失效位置为例进行说明，但并不代表本申请实施例仅局限于此。
在本申请实施例中，为了在对失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，因此，可以基于历史样本数据挖掘更多的潜在挖掘规则，并基于潜在挖掘规则，挖掘出更多的与失效位元存在关联的潜在失效位元，这样在对失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
在基于历史样本数据挖掘更多的潜在挖掘规则时，可以基于历史样本数据中的历史潜在失效位置，将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置，即执行下述S202：
S202、将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置。
示例的，在将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置时，可以结合历史潜在失效位置所属的目标类型；其中，目标类型包括冗余字线类型和冗余位线类型；并根据目标类型，将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置。
示例的，在根据目标类型，将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置时，可以根据目标类型，将历史潜在失效位置周 围紧邻的，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置。
示例的，第一预设数量可以为1个，也可以为2个，具体可以根据实际需要进行设置。在本申请实施例中，第一预设数量可以为1个，只是以此为例进行说明，但并不代表本申请实施例仅局限于此。
示例的，在根据目标类型，将历史潜在失效位置周围紧邻的，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置时，在一种情况下，若目标类型为冗余字线类型，则将位线方向上，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置。以第一预设数量为1个为例，可参见图3所示，图3为本申请实施例提供的一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图，图3所示的位置N中有斜线的位置为历史潜在失效位置，位置N中编号为#1的位置和编号为#2的位置，为与历史潜在失效位置距离1个位元的位元位置的历史目标潜在失效位置。
在另一种情况下，若目标类型为冗余位线类型，则将字线方向上，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置。同样以第一预设数量为1个为例，可参见图4所示，图4为本申请实施例提供的另一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图，图4所示的位置N中有斜线的位置为历史潜在失效位置，位置N中编号为#1的位置、编号为#4的位置，位置N-1中编号为#2的位置、以及位置N+1中编号为#3的位置，为与历史潜在失效位置距离1个位元的位元位置的历史目标潜在失效位置。
同样以第一预设数量为1个为例，可参见图5所示，图5为本申请实施例提供的又一种历史潜在失效位置和历史目标潜在失效位置之间的关系示意图，图5所示的位置N中有小方点的位置为包含失效位元的一般修补位置，位置N-1中有斜线的位置、位置N中有斜线的位置以及位置n+1中有斜线的位置均为与失效位置关联的历史潜在失效位置；位置N-2中编号为#5的位置、位置N-1中编号为#3的位置、以及N-1中编号为#7的位置为位置N-1中有斜线的历史潜在失效位置的历史目标潜在失效位置；位置N中编号为#1的位置和位置N中编号为#2的位置为位置N中有斜线的历史潜在失效位置的历史目标潜在失效位置；位置N+1中编号为#4的位置、位置N+1中编号为#8的位 置、以及N+2中编号为#6的位置为位置N+1中有斜线的历史潜在失效位置的历史目标潜在失效位置。
如上述图3、图4或者图5所示，在基于历史潜在失效位置周围紧邻的位元位置确定出历史目标潜在失效位置后，由于该历史目标潜在失效位置不一定是真实的失效位置，因此，无法直接将历史失效位元的位置和该历史目标潜在失效位置之间的关联关系确定为潜在挖掘规则；而是需要结合历史样本数据中包括的历史新增失效位元，即根据历史新增失效位元和历史目标潜在失效位置，共同确定潜在挖掘规则，即执行下述S203：
S203、根据历史新增失效位元和历史目标潜在失效位置，确定潜在挖掘规则。
示例的，历史目标潜在失效位置的数量可以为一个，也可以为多个，具体可以根据实际需要进行设置，在此，对于历史目标潜在失效位置的数量，本申请实施例不做进一步地限制。
在本申请实施例中，以历史目标潜在失效位置的数量为多个为例，在根据历史新增失效位元和历史目标潜在失效位置，确定潜在挖掘规则时，可以包括下述至少两种可能的实现方式。可以理解的是，在本申请实施例中，只是以下述两种可能的实现方式为例进行说明，但并不代表本申请实施例仅局限于此。
在一种可能的实现方式中，针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，若确定历史目标潜在失效位置中不包括历史新增失效位元，说明该历史目标潜在失效位置与失效位置不存在关联关系，即当失效位置存在故障时，该历史目标潜在失效位置不会发生故障，因此，无需更新历史目标潜在失效位置对应的关系组合的次数；相反的，若确定出历史目标潜在失效位置中包括历史新增失效位元，说明该历史目标潜在失效位置与失效位置存在关联关系，即当失效位置存在故障时，该历史目标潜在失效位置很有可能也会发生故障，因此，更新历史目标潜在失效位置对应的关系组合的次数，例如，可以在更前的次数上加1，得到历史目标潜在失效位置对应的关系组合更新后的次数，这样就可以得到各历史目标潜在失效位置对应的关系组合更新后的次数。其中，关系组合中包括预设挖掘规则的标识和历史目标潜在失效位置的标识。
在得到各历史目标潜在失效位置对应的关系组合更新后的次数后，可以 根据各历史目标潜在失效位置对应的关系组合更新后的次数，对各历史目标潜在失效位置对应的关系组合按照次数由大到小的顺序进行排序，得到关系序列；对排序后的各历史目标潜在失效位置对应的关系序列进行拟合，得到各历史目标潜在失效位置对应的序列曲线。示例的，请参见图6所示，图6为本申请实施例提供的一种序列曲线的示意图，图6中的横轴表示关系组合，纵轴表示关系组合更新后的次数，在得到例如图6所示的序列曲线后，可以进一步根据序列曲线确定潜在挖掘规则。
示例的，在根据序列曲线确定潜在挖掘规则时，可以对序列曲线进行微分处理，得到各历史目标潜在失效位置对应微分曲线。示例的，请参见图7所示，图7为本申请实施例提供的一种微分曲线的示意图，图7中的横轴仍表示关系组合，纵轴仍表示关系组合更新后的次数，在得到例如图7所示的微分曲线后，可以根据微分曲线确定潜在挖掘规则。
示例的，在根据微分曲线确定潜在挖掘规则时，可以先确定各历史目标潜在失效位置对应微分曲线中，最大微分值对应的历史目标潜在失效位置α，示例的，请参见图8所示，图8为本申请实施例提供的一种最大微分值对应的位置的示意图，图8中的横轴仍表示关系组合，纵轴仍表示关系组合更新后的次数，在得到例如图8所示的最大微分值对应的历史目标潜在失效位置α后，针对大于最大微分值对应的历史目标潜在失效位置的关系组合的次数的历史目标潜在失效位置，在失效位置存在故障时，由于大于最大微分值对应的历史目标潜在失效位置的关系组合的次数的历史目标潜在失效位置，在很大程度上也会发生故障，因此，可以直接将大于最大微分值对应的历史目标潜在失效位置的关系组合的次数的历史目标潜在失效位置，与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则，从而获取到的潜在挖掘规则。
在另一种可能的实现方式中，在根据历史新增失效位元和历史目标潜在失效位置，确定潜在挖掘规则时，针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，可以分别确定各历史目标潜在失效位置中包括的历史新增失效位元的数量；并根据各历史目标潜在失效位置包括的历史新增失效位元的数量，确定潜在挖掘规则。
示例的，在根据各历史目标潜在失效位置包括的历史新增失效位元的数量，确定潜在挖掘规则时，历史目标潜在失效位置包括的历史新增失效位元 的数量越多，说明在失效位置存在故障时，该历史目标潜在失效位置在很大程度上也会发生故障，且该历史目标潜在失效位置中发生故障的失效位元数量较多，因此，在一种可能的方式中，可以按照数量由大到小的顺序，将多个历史目标潜在失效位置中，排名前第二预设数量个历史目标潜在失效位置，分别与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则。在另一种可能的方式中，可以直接将多个历史目标潜在失效位置中，包括的历史新增失效位元的数量大于第三预设数量的历史目标潜在失效位置，分别与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则。
其中，第二预设数量和第三预设数量的取值可以根据实际需要进行设置，在此，对于第二预设数量和第三预设数量的取值，本申请实施例不做进一步地限制。
可以看出，本申请实施例中，在确定潜在挖掘规则时，可以借助于历史样本数据，将历史样本数据中包括的历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置；并根据历史样本数据中包括的历史新增失效位元和历史目标潜在失效位置，确定潜在挖掘规则。这样后续就可以基于潜在挖掘规则，确定与失效位元存在关联的目标潜在失效位元，可以挖掘出更多的与失效位元存在关联的目标潜在失效位元，使得后续在对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补时，可以在一定程度上避免失效位元位置被遗漏，从而有效地降低了晶圆出现故障的概率。
基于上述任一实施例，可以理解的是，在本申请实施例中，针对上述挖掘规则库，其包括的挖掘规则也不是一直都可以准确地确定出与失效位元关联的目标潜在失效位元，例如，当新增失效位元不再符合挖掘规则库中包括的某些挖掘规则时，需要排除掉不准确的挖掘规则，即挖掘规则库是动态变化的，并非只增不减的。下面，将通过下述图9所示的实施例，详细描述在本申请实施例中，如何有效地对挖掘规则库进行动态更新。
图9为本申请实施例提供的一种对挖掘规则库进行动态更新的方法的流程示意图，该对挖掘规则库进行动态更新的方法可以由软件和/或硬件装置执行，该硬件装置同样可以为失效位置的修补装置。示例的，请参见图9所示，该对挖掘规则库进行动态更新的方法可以包括：
S901、根据历史新增失效位元和历史潜在失效位置，确定无效挖掘规则。
示例的，在根据历史新增失效位元和历史潜在失效位置，确定无效挖掘规则时，针对多个历史潜在失效位置中的各历史潜在失效位置，同样可以分别确定各历史潜在失效位置中包括的历史新增位元的数量；并根据各历史潜在失效位置包括的历史新增失效位元的数量，确定无效挖掘规则。
示例的，在根据各历史潜在失效位置包括的历史新增失效位元的数量，确定无效挖掘规则时，历史目标潜在失效位置包括的历史新增失效位元的数量越少，说明失效位置与该历史目标潜在失效位置的关联度越低，因此，可以直接将多个历史潜在失效位置中，包括的历史新增失效位元的数量小于第四预设数量的历史潜在失效位置对应的预设挖掘规则，确定为无效挖掘规则。其中，第四预设数量的取值可以根据实际需要进行设置，在此，对于第四预设数量的取值，本申请实施例不做进一步地限制。
在确定出无效挖掘规则之后，就可以将无效挖掘规则从挖掘规则库中删除，从而实现对挖掘规则库的动态更新。
S902、将无效挖掘规则从挖掘规则库中删除。
可以看出，本申请实施例中，可以根据历史新增失效位元和历史潜在失效位置，确定无效挖掘规则，并将无效挖掘规则从挖掘规则库中删除，这样可以排除掉不准确的无效挖掘规则，实现了对挖掘规则库的动态更新，从而提高了挖掘规则库的准确度。
图10为本申请实施例提供的一种失效位置的修补装置100的结构示意图，示例的，请参见图10所示，该失效位置的修补装置100可以包括：
确定单元1001，用于确定待处理晶圆中的失效位元。
处理单元1002，用于基于挖掘规则库中的挖掘规则，确定与失效位元存在关联的目标潜在失效位元；其中，挖掘规则库中包括潜在挖掘规则，潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的。
修补单元1003，用于对失效位元对应的失效位置，和目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
可选的，该失效位置的修补装置100还包括获取单元1004。
获取单元1004，用于获取历史样本数据；其中，历史样本数据包括与历史失效位元关联的历史新增失效位元、以及基于预设挖掘规则确定的历史潜在失效位置。
处理单元1002，还用于将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置；并根据历史新增失效位元和历史目标潜在失效位置，确定潜在挖掘规则。
可选的，处理单元1002，具体用于确定历史潜在失效位置所属的目标类型；其中，目标类型包括冗余字线类型和冗余位线类型；并根据目标类型，将历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置。
可选的，处理单元1002，具体用于根据目标类型，将历史潜在失效位置周围紧邻的，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置。
可选的，处理单元1002，具体用于若目标类型为冗余字线类型，则将位线方向上，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置；若目标类型为冗余位线类型，则将字线方向上，与历史潜在失效位置距离第一预设数量个位元的位元位置确定为历史目标潜在失效位置。
可选的，历史目标潜在失效位置的数量为多个；处理单元1002，具体用于针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，若确定出历史目标潜在失效位置中包括历史新增失效位元，则更新历史目标潜在失效位置对应的关系组合的次数；其中，关系组合中包括预设挖掘规则的标识和历史目标潜在失效位置的标识；并根据更新后的各历史目标潜在失效位置对应的关系组合的次数，对各历史目标潜在失效位置对应的关系组合按照次数由大到小的顺序进行排序，得到关系序列；对排序后的各历史目标潜在失效位置对应的关系序列进行拟合，得到各历史目标潜在失效位置对应的序列曲线；根据序列曲线确定潜在挖掘规则。
可选的，处理单元1002，具体用于对序列曲线进行微分处理，得到各历史目标潜在失效位置对应微分曲线；并根据各历史目标潜在失效位置对应微分曲线，确定潜在挖掘规则。
可选的，处理单元1002，具体用于确定各历史目标潜在失效位置对应微分曲线中，最大微分值对应的历史目标潜在失效位置；并根据最大微分值对应的历史目标潜在失效位置，确定潜在挖掘规则。
可选的，处理单元1002，具体用于将各历史目标潜在失效位置对应的关系组合中，大于最大微分值对应的历史目标潜在失效位置的关系组合的次数 的历史目标潜在失效位置，与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则。
可选的，历史目标潜在失效位置的数量为多个；处理单元1002，具体用于针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，分别确定各历史目标潜在失效位置中包括的历史新增失效位元的数量；并根据各历史目标潜在失效位置包括的历史新增失效位元的数量，确定潜在挖掘规则。
可选的，处理单元1002，具体用于按照数量由大到小的顺序，将多个历史目标潜在失效位置中，前第二预设数量个历史目标潜在失效位置，分别与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则。
可选的，处理单元1002，具体用于将多个历史目标潜在失效位置中，包括的历史新增失效位元的数量大于第三预设数量的历史目标潜在失效位置，分别与历史失效位元对应的历史失效位置之间的关联关系，确定为潜在挖掘规则。
可选的，处理单元1002，还用于根据历史新增失效位元和历史潜在失效位置，确定无效挖掘规则；并将无效挖掘规则从挖掘规则库中删除。
可选的，处理单元1002，具体用于针对多个历史潜在失效位置中的各历史潜在失效位置，分别确定各历史潜在失效位置中包括的历史新增位元的数量；并根据各历史潜在失效位置包括的历史新增失效位元的数量，确定无效挖掘规则。
可选的，处理单元1002，具体用于将多个历史潜在失效位置中，包括的历史新增失效位元的数量小于第四预设数量的历史潜在失效位置对应的预设挖掘规则，确定为无效挖掘规则。
本申请实施例所示的失效位置的修补装置100，可以执行上述任一实施例所示的失效位置的修补方法，其实现原理以及有益效果与失效位置的修补方法的实现原理及有益效果类似，可参见失效位置的修补方法的实现原理及有益效果，此处不再进行赘述。
图11为本申请实施例提供的另一种计算机设备的结构示意图，示例的，请参见图11所示，该计算机设备包括：
存储器1101、处理器1102及存储在存储器1101上，并可在处理器1102上运行的计算机程序，所述处理器1102执行所述程序时实现上述任一实施例所示的失效位置的修补方法，其实现原理以及有益效果与失效位置的修补方 法的实现原理及有益效果类似，可参见失效位置的修补方法的实现原理及有益效果，此处不再进行赘述。
本申请实施例还提供了一种可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述任一实施例所示的失效位置的修补方法，其实现原理以及有益效果与失效位置的修补方法的实现原理及有益效果类似，可参见失效位置的修补方法的实现原理及有益效果，此处不再进行赘述。
本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序，所述计算机程序存储在可读存储介质中，电子设备的至少一个处理器可以从所述可读存储介质读取所述计算机程序，所述至少一个处理器执行所述计算机程序使得电子设备执行上述任一实施例所示的失效位置的修补方法，其实现原理以及有益效果与失效位置的修补方法的实现原理及有益效果类似，可参见失效位置的修补方法的实现原理及有益效果，此处不再进行赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所展示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元展示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(英文：processor)执行本申请各个实施例方法的部分步骤。
应理解的是，上述处理器可以是中央处理单元(英文：Central Processing Unit，简称：CPU)，还可以是其他通用处理器、数字信号处理器(英文：Digital Signal Processor，简称：DSP)、专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合发明所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
存储器可能包含高速RAM存储器，也可能还包括非易失性存储NVM，例如至少一个磁盘存储器，还可以为U盘、移动硬盘、只读存储器、磁盘或光盘等。
总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外部设备互连(Peripheral Component，PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，本申请附图中的总线并不限定仅有一根总线或一种类型的总线。
上述计算机可读存储介质可以是由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。存储介质可以是通用或专用计算机能够存取的任何可用介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种失效位置的修补方法，包括：
    确定待处理晶圆中的失效位元；
    基于挖掘规则库中的挖掘规则，确定与所述失效位元存在关联的目标潜在失效位元；其中，所述挖掘规则库中包括潜在挖掘规则，所述潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的；
    对所述失效位元对应的失效位置，和所述目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
  2. 根据权利要求1所述的方法，其中，所述基于挖掘规则库中的挖掘规则，确定与所述失效位元存在关联的目标潜在失效位元之前，所述方法还包括：
    获取历史样本数据；其中，所述历史样本数据包括与历史失效位元关联的历史新增失效位元、以及基于所述预设挖掘规则确定的历史潜在失效位置；
    将所述历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置；
    根据所述历史新增失效位元和所述历史目标潜在失效位置，确定所述潜在挖掘规则。
  3. 根据权利要求2所述的方法，其中，所述将所述历史潜在失效位置周围紧邻的位元位置确定为历史目标潜在失效位置，包括：
    确定所述历史潜在失效位置所属的目标类型；其中，所述目标类型包括冗余字线类型和冗余位线类型；
    根据所述目标类型，将所述历史潜在失效位置周围紧邻的位元位置确定为所述历史目标潜在失效位置。
  4. 根据权利要求3所述的方法，其中，所述根据所述目标类型，将所述历史潜在失效位置周围紧邻的位元位置确定为所述历史目标潜在失效位置，包括：
    根据所述目标类型，将所述历史潜在失效位置周围紧邻的，与所述历史潜在失效位置距离第一预设数量个位元的位元位置确定为所述历史目标潜在失效位置。
  5. 根据权利要求4所述的方法，其中，所述根据所述目标类型，将所述 历史潜在失效位置周围紧邻的，与所述历史潜在失效位置距离第一预设数量个位元的位元位置确定为所述历史目标潜在失效位置，包括：
    若所述目标类型为冗余字线类型，则将位线方向上，与所述历史潜在失效位置距离第一预设数量个位元的位元位置确定为所述历史目标潜在失效位置；
    若所述目标类型为冗余位线类型，则将字线方向上，与所述历史潜在失效位置距离第一预设数量个位元的位元位置确定为所述历史目标潜在失效位置。
  6. 根据权利要求2-5任一项所述的方法，其中，所述历史目标潜在失效位置的数量为多个；所述根据所述历史新增失效位元和所述历史目标潜在失效位置，确定所述潜在挖掘规则，包括：
    针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，若确定出所述历史目标潜在失效位置中包括历史新增失效位元，则更新所述历史目标潜在失效位置对应的关系组合的次数；其中，所述关系组合中包括所述预设挖掘规则的标识和所述历史目标潜在失效位置的标识；
    根据更新后的所述各历史目标潜在失效位置对应的关系组合的次数，对所述各历史目标潜在失效位置对应的关系组合按照次数由大到小的顺序进行排序，得到关系序列；
    对排序后的所述各历史目标潜在失效位置对应的关系序列进行拟合，得到所述各历史目标潜在失效位置对应的序列曲线；
    根据所述序列曲线确定所述潜在挖掘规则。
  7. 根据权利要求6所述的方法，其中，所述根据所述序列曲线确定所述潜在挖掘规则，包括：
    对所述序列曲线进行微分处理，得到所述各历史目标潜在失效位置对应微分曲线；
    根据所述各历史目标潜在失效位置对应微分曲线，确定所述潜在挖掘规则。
  8. 根据权利要求7所述的方法，其中，所述根据所述各历史目标潜在失效位置对应微分曲线，确定所述潜在挖掘规则，包括：
    确定所述各历史目标潜在失效位置对应微分曲线中，最大微分值对应的历史目标潜在失效位置；
    根据所述最大微分值对应的历史目标潜在失效位置，确定所述潜在挖掘规则。
  9. 根据权利要求8所述的方法，其中，所述根据所述最大微分值对应的历史目标潜在失效位置，确定所述潜在挖掘规则，包括：
    将所述各历史目标潜在失效位置对应的关系组合中，大于所述最大微分值对应的历史目标潜在失效位置的关系组合的次数的历史目标潜在失效位置，与所述历史失效位元对应的历史失效位置之间的关联关系，确定为所述潜在挖掘规则。
  10. 根据权利要求2-5任一项所述的方法，其中，所述历史目标潜在失效位置的数量为多个；所述根据所述历史新增失效位元和所述历史目标潜在失效位置，确定所述潜在挖掘规则，包括：
    针对多个历史目标潜在失效位置中的各历史目标潜在失效位置，分别确定所述各历史目标潜在失效位置中包括的历史新增失效位元的数量；
    根据所述各历史目标潜在失效位置包括的历史新增失效位元的数量，确定所述潜在挖掘规则。
  11. 根据权利要求10所述的方法，其中，所述根据所述各历史目标潜在失效位置包括的历史新增失效位元的数量，确定所述潜在挖掘规则，包括：
    按照数量由大到小的顺序，将所述多个历史目标潜在失效位置中，前第二预设数量个历史目标潜在失效位置，分别与所述历史失效位元对应的历史失效位置之间的关联关系，确定为所述潜在挖掘规则。
  12. 根据权利要求10所述的方法，其中，所述根据所述各历史目标潜在失效位置包括的历史新增失效位元的数量，确定所述潜在挖掘规则，包括：
    将所述多个历史目标潜在失效位置中，包括的历史新增失效位元的数量大于第三预设数量的历史目标潜在失效位置，分别与所述历史失效位元对应的历史失效位置之间的关联关系，确定为所述潜在挖掘规则。
  13. 根据权利要求2-5任一项所述的方法，所述方法还包括：
    根据所述历史新增失效位元和所述历史潜在失效位置，确定无效挖掘规则；
    将所述无效挖掘规则从所述挖掘规则库中删除。
  14. 根据权利要求13所述的方法，其中，所述根据所述历史新增失效位元和所述历史潜在失效位置，确定无效挖掘规则，包括：
    针对多个历史潜在失效位置中的各历史潜在失效位置，分别确定所述各历史潜在失效位置中包括的历史新增位元的数量；
    根据所述各历史潜在失效位置包括的历史新增失效位元的数量，确定所述无效挖掘规则。
  15. 根据权利要求14所述的方法，其中，所述根据所述各历史潜在失效位置包括的历史新增失效位元的数量，确定所述潜在挖掘规则，包括：
    将所述多个历史潜在失效位置中，包括的历史新增失效位元的数量小于第四预设数量的历史潜在失效位置对应的预设挖掘规则，确定为所述无效挖掘规则。
  16. 一种失效位置的修补装置，包括：
    确定单元，用于确定待处理晶圆中的失效位元；
    处理单元，用于基于挖掘规则库中的挖掘规则，确定与所述失效位元存在关联的目标潜在失效位元；其中，所述挖掘规则库中包括潜在挖掘规则，所述潜在挖掘规则是基于预设挖掘规则确定的潜在失效位置得到的；
    修补单元，用于对所述失效位元对应的失效位置，和所述目标潜在失效位元对应的目标潜在失效位置进行修补，得到修补后的目标晶圆。
  17. 一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现权利要求1-15任一项所述的失效位置的修补方法。
  18. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现权利要求1-15任一项所述的失效位置的修补方法。
  19. 一种计算机程序产品，包括计算机程序，所述计算机程序在被处理器执行时，实现权利要求1-15任一项所述的失效位置的修补方法。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060053357A1 (en) * 2004-09-06 2006-03-09 Janusz Rajski Integrated circuit yield and quality analysis methods and systems
CN102157203A (zh) * 2010-02-12 2011-08-17 台湾积体电路制造股份有限公司 存储器电路及其操作方法
US20130016895A1 (en) * 2011-07-15 2013-01-17 International Business Machines Corporation Method and system for defect-bitmap-fail patterns matching analysis including peripheral defects
US20130163851A1 (en) * 2011-12-21 2013-06-27 Michele Dalla-Torre System, method and computer program product for classification within inspection images
CN104866731A (zh) * 2015-06-16 2015-08-26 南昌航空大学 面向小批量生产的潜在工艺失效模式挖掘方法
CN110968985A (zh) * 2018-09-30 2020-04-07 长鑫存储技术有限公司 集成电路修补算法确定方法及装置、存储介质、电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060053357A1 (en) * 2004-09-06 2006-03-09 Janusz Rajski Integrated circuit yield and quality analysis methods and systems
CN102157203A (zh) * 2010-02-12 2011-08-17 台湾积体电路制造股份有限公司 存储器电路及其操作方法
US20130016895A1 (en) * 2011-07-15 2013-01-17 International Business Machines Corporation Method and system for defect-bitmap-fail patterns matching analysis including peripheral defects
US20130163851A1 (en) * 2011-12-21 2013-06-27 Michele Dalla-Torre System, method and computer program product for classification within inspection images
CN104866731A (zh) * 2015-06-16 2015-08-26 南昌航空大学 面向小批量生产的潜在工艺失效模式挖掘方法
CN110968985A (zh) * 2018-09-30 2020-04-07 长鑫存储技术有限公司 集成电路修补算法确定方法及装置、存储介质、电子设备

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