WO2022052542A1 - 失效位元的修补方案的确定方法和装置 - Google Patents

失效位元的修补方案的确定方法和装置 Download PDF

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Publication number
WO2022052542A1
WO2022052542A1 PCT/CN2021/100004 CN2021100004W WO2022052542A1 WO 2022052542 A1 WO2022052542 A1 WO 2022052542A1 CN 2021100004 W CN2021100004 W CN 2021100004W WO 2022052542 A1 WO2022052542 A1 WO 2022052542A1
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failure
redundant circuit
ary
redundant
combination
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PCT/CN2021/100004
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English (en)
French (fr)
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陈予郎
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长鑫存储技术有限公司
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Priority to US17/412,372 priority Critical patent/US11776654B2/en
Publication of WO2022052542A1 publication Critical patent/WO2022052542A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a method and apparatus for determining a repair scheme for a failed bit.
  • FB fail bit
  • redundancy (RD) circuits can be used to repair the failed bits in the chip.
  • the failed bits will be generated after the wafer test.
  • the failed bits generated after the wafer test are called new Fail bit (new fail bit, NFB).
  • NFB is generated in the RD circuit, it is equivalent to failure to repair the failed bit, resulting in low repairing efficiency and repairing accuracy of the failed bit.
  • the present application provides a method and device for determining a repairing scheme of a failed bit, so as to solve the problems of low repairing efficiency and repairing accuracy of the failed bit.
  • a first aspect of the present application provides a method for determining a defective bit repair scheme, which is applied to a chip including multiple subfields, and the chip further includes a redundant circuit, and the redundant circuit is used to repair the failure in the subfield. bits, including:
  • the wafer test result includes position information of the failed bit in the chip, and the failed bit in the chip includes the failed bit in the subfield and all the failed bits in the redundant circuit;
  • the reliability list of redundant circuits includes reliability values of multiple redundant circuits
  • a repair scheme for the target failed bit is determined according to the reliability value of the available redundant circuit.
  • the method before acquiring the reliability value of the available redundant circuits from the pre-acquired reliability list of redundant circuits, the method further includes: establishing a reliability list of the redundant circuits.
  • the establishing the reliability list of the redundant circuit includes:
  • the reliability value of each redundant circuit in the chip is determined according to the test data of the failed unit in the chip and the statistical data of the detected failure mode stored in the database, wherein the statistical data of the failure mode
  • the data includes the identifiers of multiple failure combinations and the total number of occurrences of the failure combinations, and the failure combination consists of at least one of the redundant circuit where the new failed bit is located and the statistical range of the redundant circuit where the new failed bit is located.
  • the failure bit is composed, and the failure bit test data in the chip includes a plurality of wafer test results;
  • the reliability value of each redundant circuit in the chip is stored in the reliability list of the redundant circuit.
  • determining the reliability value of each redundant circuit in the chip according to the test data of the failed unit in the chip and the statistical data of the detected failure mode stored in the database including:
  • n is composed of the current redundant circuit and at least one failed bit within the statistical range of the current redundant circuit;
  • the reliability value of the current redundant circuit is determined according to m ⁇ 1 n-ary unreliable values of the current redundant circuit.
  • the method further includes:
  • n-ary failure combinations from a database, where the statistical data of n-ary failure combinations include the identification of each failure combination and the total number of occurrences of the failure combination;
  • the n-ary failure mode corresponding to the n-ary failure combination is determined.
  • the method before obtaining the statistical data of the n-ary failure combination from the database, the method further includes:
  • combination data of n-ary failure combinations includes redundant circuits constituting the failure combination, the positional relationship of the failed bits within the statistical range of the redundant circuits, and the type of the redundant circuits;
  • the statistical data of the n-ary failure combination is updated according to the number of occurrences of each failure combination.
  • the obtaining the combination data of the n-ary failure combination includes:
  • the information of the target newly failed unit includes the type and position of the target redundant circuit where the target newly failed unit is located information
  • the newly failed unit test data includes information of a newly failed unit that occurs in redundant circuits of multiple chips, and the information of the newly failed unit includes type and location information of the redundant circuit where the newly failed unit is located;
  • n-ary failure combination includes the target new failure unit and n-1 failures unit.
  • the method and device for determining a repairing scheme for a failed bit provided by the present application, after determining one or more available redundant circuits for the target failed bit currently to be repaired in the sub-domain, select the reliability list from the redundant circuit Obtain the reliability value of each available redundant circuit, the reliability list of the redundant circuit includes the reliability values of multiple redundant circuits, and determine the target failure bit in the subfield according to the reliability value of the available redundant circuit. patching scheme. Among them, the reliability value of the redundant circuit is obtained from the big data analysis of the relationship between the failed bits that have already occurred and the redundant circuit where the new failed bits are located. The reliability of the redundant circuit is high, thereby improving the repairing efficiency and repairing accuracy of the failed bits.
  • FIG. 1 is a schematic structural diagram of a chip to which an embodiment of the present application is applicable;
  • FIG. 2 is a schematic diagram of a chip detection and repair process provided by the application
  • FIG. 3 is a schematic diagram of an analysis range of redundant word lines
  • Fig. 4 is the schematic diagram of the analysis scope of redundant bit line
  • Fig. 5 is the schematic diagram of 2-element failure combination
  • FIG. 6 is a schematic diagram of a 3-element failure combination
  • FIG. 7 is a flowchart of a method for determining a repair scheme for a failed bit provided in Embodiment 1 of the present application;
  • FIG. 8 is a flowchart of a method for determining a reliability value of a redundant circuit according to Embodiment 2 of the present application;
  • Embodiment 9 is a flowchart of a method for determining a failure mode provided by Embodiment 3 of the present application.
  • Fig. 10 is a kind of dynamic transformation schematic diagram of the determination mode of the first threshold value
  • FIG. 11 is a flowchart of a method for establishing statistical data provided in Embodiment 4 of the present application.
  • FIG. 12 is a flowchart of a method for establishing statistical data according to Embodiment 5 of the present application.
  • DRAM Dynamic Random Access Memory
  • a typical Dynamic Random Access Memory (DRAM) chip has as many as 64 million bits, which can be arrayed in rows and columns through word lines. (word line) and bit line (bit line) can address the bits in the array.
  • FB Fail Bit
  • Redundancy bits are also called backup circuits. Redundancy circuits are further divided into Global Redundancy (GR) and Local Redundancy (LR).
  • the global redundancy circuit is used to repair the target global and all The failed bits in any subfield in the adjacent whole field of the target field, the subfield redundancy circuit is used to repair the target subfield to which the target redundancy circuit belongs and the adjacent subfield of the target subfield Invalid bits in .
  • the global redundant circuit can be a redundant word line (Redundant Word Line, referred to as RWL), also known as a column redundant circuit, and the sub-domain redundant circuit can be a redundant bit line (Redundant Bit Line, referred to as RBL), also known as Line redundant circuit.
  • the subfield is the smallest repair unit (or called the smallest repair area) when the FB is repaired, and the whole field is a larger repair unit than the subfield. Domain composition.
  • the chip 100 includes a main matrix area 110 and a redundant unit area 120 , and the redundant unit area 120 is used for repairing the main matrix area 110 . Since the number of bits contained in the chip 100 is large, in order to improve the repairing efficiency, the main array of the chip 100 , that is, the main matrix area 110 may be divided into a plurality of subfields 111 , and each subfield 111 may contain a certain number of bits.
  • the redundant unit area 120 includes a global redundant circuit 121 and a sub-domain redundant circuit 122, wherein the global redundant circuit 121 is used to repair the failed bits in any sub-domain 111, and the sub-domain redundant circuit 122 is used to repair the specified For the failed bits in the subfield 111, for example, as shown in FIG. 1, the subfield redundancy circuit 122' can only repair the failed bits in the subfield 111'.
  • the global redundancy circuit 121 is a column redundancy circuit, which can be used to replace a word line, so as to repair the failed bits on the word line, and one global redundancy circuit 121 can repair one at the same time.
  • the sub-field redundancy circuit 122 is a row redundancy circuit that can be used to replace a bit line to repair the failed bits on the bit line, and a sub-field redundancy circuit 122 can Multiple failed bits on a bit line are repaired at the same time.
  • the FBs obtained by the wafer test include the FBs in the sub-domain of the chip and the chip.
  • FB in the redundant circuit In the redundancy allocation stage, the FBs in the subdomain are allocated corresponding redundant circuits for repair, but after the wafer test, FBs may also be generated in the redundant circuits. If the FBs in the subdomain are allocated The redundant circuit of , generates a new fail bit (new fail bit, NFB), which causes the repair of the FB in the sub-domain to fail.
  • NFB new fail bit
  • the failed bit detected in the wafer test phase is called FB
  • the failed bit generated after the wafer test is called the new fail bit (New Fail Bit, NFB).
  • the failed bits generated in two different stages can be distinguished by other names.
  • the failed bits detected in the wafer test stage are called the first type FB
  • the failed bits generated after the wafer test are called the second type.
  • FB or the failed bit detected in the wafer testing stage is called the first FB
  • the failed bit generated after the wafer test is called the second FB, which is not limited in this embodiment.
  • FB test data also known as FB historical test data
  • NFB test data also known as NFB historical test data
  • FB test data also known as NFB historical test data
  • big data analysis on chip FB test data and NFB test data
  • the circuit gives the FB in the sub-domain
  • FIG. 2 is a schematic diagram of a chip inspection and repair process provided by the application. As shown in FIG. 2 , the chip manufacturing process includes: a wafer testing stage, a redundant circuit detection stage, a redundant circuit allocation stage, and other tests. stage.
  • the wafer test result is obtained through the wafer test.
  • the wafer test result includes the position information of the FB in the chip.
  • the FB in the chip includes the FB in the subdomain and the FB in the redundant circuit, and the position information of the FB is stored.
  • the application database includes a first database and a second database, the FB test data and the NFB test data stored in the first database, and the location information of the FB is specifically stored in the test data of the FB.
  • the second database stores the statistical data of the 2-element failure mode, the statistical data of the 3-element failure mode, and the reliability list of the redundant circuit.
  • the NFB test data includes the chip's historical NFB test results.
  • the NFB test results are measured after the FB is repaired, that is, the chip is measured in other test stages in Figure 2.
  • the bits in the subdomain and the bits in the redundant circuit may also have NFB, so the NFB of the chip also includes the NFB in the subdomain and the NFB in the redundant circuit.
  • the test result of the NFB includes the information of the NFB, and the information of the NFB in the redundant circuit includes the position of the NFB, the type and position information of the redundant circuit where the NFB is located.
  • Types of redundant circuits may include redundant word lines and redundant bit lines.
  • the stage of checking the pros and cons of redundant circuits is a newly added stage of the present application.
  • the allocation stage of redundant circuits is directly performed after wafer testing.
  • the reliability value of each redundant circuit in the chip can be obtained.
  • the reliability value of the redundant circuit can be obtained according to the reliability value of the redundant circuit. Redundant circuits are allocated to the FBs in the sub-domains.
  • the detection phase of the pros and cons of redundant circuits is divided into two sub-phases: a failure mode establishment phase and a failure mode implementation phase.
  • the failure mode establishment phase includes the following four processes: timer activation, definition of the analysis scope of redundant circuits, establishment of statistical data, and failure mode mining.
  • the starting process of the timer is to obtain more unknown failure modes or update the number of occurrences of established failure modes.
  • the timer can be started at a fixed time to obtain more unknown failure modes or update the occurrence of established failure modes. . Since the test data of the chip's FB and NFB are constantly updated, more unknown failure modes may appear, and the established failure modes may also appear in other chips after the failure modes are established. The number of occurrences of established failure modes is also constantly changing, and both require constant updating.
  • the definition process of the analysis scope of the redundant circuit is to define the scope that various types of redundant circuits are affected by the FB position of the chip, wherein the analysis scope may vary from chip to chip.
  • Common types of redundant circuits include redundant word lines and redundant bit lines.
  • the analysis scope of the redundant circuit is the entire domain to which the redundant circuit belongs (also referred to as a section) and the entire domain adjacent to the entire domain to which the redundant circuit belongs.
  • the universe may be referred to as the target universe.
  • FIG. 3 is a schematic diagram of the analysis range of redundant word lines. As shown in FIG. 3 , the bits of the chip are divided into multiple regions in the direction of the bit lines, and the bits of the chip are not divided in the direction of the word lines. The division method forms multiple universes.
  • the entire domain to which the redundant circuit belongs is N
  • the analysis scope of the redundant circuit is the sub-domain to which the redundant circuit belongs and the adjacent sub-domains of the sub-domain to which the redundant circuit belongs, and the sub-domain to which the redundant circuit belongs may be called the target subdomain.
  • FIG. 4 is a schematic diagram of the analysis range of redundant bit lines. As shown in FIG. 4 , the bits of the chip are divided into multiple regions in the direction of the bit lines, and the bits of the chip are also divided into multiple regions in the direction of the word lines. , and multiple sub-domains are formed through this division method.
  • the sub-domain is a smaller area than the whole area, and a whole area can be divided into a plurality of smaller areas in the word line direction to form a sub-domain, or a plurality of sub-domains located in the word line direction
  • Consecutive subfields constitute a whole field.
  • each whole field includes 4 subfields of the same size. This is just an example, and the number of subfields included in a whole field is not limited in this embodiment.
  • the sub-domain to which the redundant circuit belongs has a total of 4 adjacent sub-domains, which are the sub-domains adjacent to the top, bottom, left and right of the sub-domain to which the redundant circuit belongs. It can be understood that when the redundant circuit is located at the edge of the chip , the number of adjacent sub-domains of the sub-domain to which the redundant circuit belongs may be less than 4. For example, when the redundant circuit is located in the first row of the entire domain N, there is no sub-domain above the redundant circuit, so the redundant circuit has only There are 3 adjacent subfields. When the backup circuit is located in the first row of the whole field N-3, there are no subfields to the left and above of the redundant circuit, so the redundant circuit has only 2 adjacent subfields.
  • one type of domain includes a main matrix (main array, referred to as abbreviation).
  • MA main array
  • redundant bit lines excluding redundant word lines.
  • Another type of universe includes MA, redundant bit lines, and redundant word lines.
  • the redundant circuits in the chip also include sub-domain redundant circuits and global redundant circuits.
  • the sub-domain redundant circuits can only repair the FB in the corresponding sub-domain, and the global redundant circuits can repair the corresponding global redundant circuits. FB in any subdomain of .
  • the establishment of the statistical data is to obtain the redundant circuit where each NFB is located in the test data of the NFBs in the redundant circuit and the failure combination formed by the FBs within the statistical range of the redundant circuit where the NFB is located.
  • the currently detected NFB is called the target NFB, and the information of the target NFB is read from the NFB test data.
  • the information of the target NFB includes the type of the redundant circuit where the target NFB is located and the position of the redundant circuit.
  • the redundant circuit may be referred to as the target redundant circuit.
  • the analysis scope of the target redundant circuit is determined, and the FB within the analysis scope of the target redundant circuit is obtained from the test data of the FB in the chip.
  • a failure combination is formed according to the target redundant circuit and the FB within the analysis scope of the target redundant circuit, wherein each failure combination includes the target redundant circuit and at least one FB composition within the analysis scope of the target redundant circuit.
  • an n-element failure combination can be formed. For example, if the number of FBs within the analysis range of the target redundant circuit is 4, then the maximum value of m is 5. In the actual use process, the value of n can be smaller than the maximum value of m. For example, in general, 2 and 3 for n can meet the requirements, that is, for each NFB, it is only necessary to determine the corresponding 2-element failure combination and 3 yuan failure combination.
  • Figure 5 is a schematic diagram of a combination of 2-element failures. As shown in Figure 5, there are 4 FBs in the analysis range of the target redundant circuit, and the redundant circuit where the NFB is located forms a 2-element failure with a FB within the analysis scope. Combination, a total of 4 2-element failure combinations can be formed.
  • Figure 6 is a schematic diagram of a 3-element failure combination. As shown in Figure 6, there are 4 FBs in the analysis range of the target redundant circuit, and the redundant circuit where the NFB is located forms a 3-element with the two FBs in the analysis scope. A total of 6 3-element failure combinations can be formed.
  • the 4-element failure combination consists of the redundant circuit where the NFB is located and the analysis scope.
  • the 5-element failure combination is composed of the redundant circuit where the NFB is located and the 4 FBs within the analysis range.
  • the number of failure combinations formed decreases. For example, when m is 5, the number of 4-element failure combinations is 2, and the number of 5-element failure combinations is 1 .
  • the combination data of the n-element failure combination is saved, and the combined data of the n-element failure combination can be stored in the big data analysis platform.
  • the big data analysis platform stores the combination data of the 2-element failure combination and the combination data of the 3-element failure combination, and also stores the statistical data of the 2-element failure combination and the statistical data of the 3-element failure combination.
  • the combination data of the failure combination is used to describe the type of the redundant circuit where the NFB is located, and the relative positional relationship between the redundant circuit and the FB.
  • the combination data of the binary failure combination is stored in an arrangement of ⁇ x 1 , x 2 , x 3 >, where x 1 represents the type of the redundant circuit where the NFB is located, and when the type of the redundant circuit where the NFB is located is stored.
  • x 2 indicates the relative position of the entire domain to which the FB belongs relative to the entire domain to which the redundant circuit where the NFB belongs.
  • x 2 indicates that the FB belongs to The relative position of the sub-domain relative to the sub-domain to which the redundant circuit where the NFB is located, x 3 is the minimum distance between the FB position and the redundant circuit where the NFB is located.
  • the combination data of the 3-element failure combination is stored in an arrangement of ⁇ x 1 , x 2 , x 3 , x 4 >, where x 1 represents the type of the redundant circuit where the NFB is located, when the redundant circuit where the NFB is located is stored.
  • x 2 indicates the relative position of the entire domain to which the FB belongs relative to the entire domain to which the redundant circuit where the NFB is located.
  • x 2 Indicates the relative position of the sub-domain to which the FB belongs to the sub-domain to which the redundant circuit where the NFB is located
  • x 3 is the minimum distance between the position of the lower FB in the two FBs and the redundant circuit where the NFB is located
  • x 4 is The minimum distance between the position of the higher-order FB in the two FBs and the redundant circuit where the NFB is located.
  • the lower and upper bits are relative to the position of the same bit line.
  • the statistical data of the n-ary failure combination is updated according to the combination data of the n-ary failure combination.
  • the statistical data of the n-ary failure combination is used to count the total number of occurrences of each failure combination,
  • the statistical data of the n-ary failure combination will assign a unique identifier or number to each failure combination, which is used to uniquely identify a failure combination.
  • the number of occurrences of each failure combination in the 2-element failure combination is determined according to the combination data of the 2-element failure combination, wherein the 2-element failure combination includes one or more different failure combinations, and the structured query can be used.
  • the language structured query language, referred to as SQL
  • SQL structured query language
  • this kind of failure combination does not exist in the statistical data of the 2-element failure combination, a number or identification is assigned to this kind of failure combination, and the number of occurrences of this kind of failure combination is taken as the total number of occurrences of this kind of failure combination.
  • the statistical data of the 3-element failure combination is updated according to the same method, which will not be repeated here.
  • the n-element failure mode is obtained according to the statistical data of the n-element failure combination, and the statistical data of the n-element failure mode is stored.
  • the statistical data of the n-element failure combination includes multiple failure combinations, only if certain conditions are met
  • the failure combination can be regarded as the failure mode.
  • the failure combination whose total number of occurrences is greater than the threshold value in the statistical data of the n-ary failure combination is regarded as the n-ary failure mode. Therefore, the statistical data of the n-ary failure mode includes the failure mode of each failure combination. number and total occurrences.
  • the 2-element failure mode can be obtained according to the statistical data of the 2-element failure combination
  • the 3-element failure mode can be obtained according to the statistical data of the 3-element failure combination.
  • the statistical data of 2-element failure combinations includes a total of 10 kinds of failure combinations, among which, only 4 kinds of failure combinations whose total occurrence times are greater than the threshold value are determined as 2-element failures whose total occurrence times are greater than the threshold value. model.
  • a reliability value is determined or estimated for each redundant circuit in the chip according to the obtained failure mode.
  • the reliability value can range from 0 to 1, and a reliability value of 0 indicates redundancy.
  • the circuit is absolutely unreliable. The larger the reliability value is, the more reliable the redundant circuit is. The greater the reliability of the redundant circuit indicates that the redundant circuit is less likely to generate NFB, and the smaller the reliability value of the redundant circuit indicates that the redundant circuit is generated. The more likely NFB is.
  • the reliability value of each redundant circuit in the chip can be stored in the reliability list of redundant circuits, and subsequently the reliability value of each redundant circuit in the reliability list of redundant circuits can be used as the FB in the subdomain. Redundant circuits are allocated, and redundant circuits with high reliability are preferentially allocated to the FBs in the subdomain. The redundant circuits with higher reliability are less likely to generate NFBs later, thus improving the repairing efficiency and repairing accuracy of FBs.
  • FIG. 7 is a flowchart of a method for determining a repairing solution for a failed bit provided in Embodiment 1 of the present application.
  • the method in this embodiment is applied to a chip including multiple sub-fields, such as the chip shown in FIG. 1 , the chip further includes Redundant circuits, redundant circuits are used to patch FBs in subdomains.
  • the method of this embodiment may include the following steps:
  • the wafer test result can be obtained directly from the test program or the test module, or obtained from the test data of the FB in the chip in the database. After the test program or module performs the wafer test, the wafer The test results are saved to the database.
  • the wafer test result may include the location information of FBs in multiple sub-domains.
  • the FB in a sub-domain can be selected from the wafer test results in a certain order as the current target FB to be repaired, and the target FB to be repaired can be determined to be repaired.
  • Available redundant circuits for FB may be used to determine the available redundant circuit for repairing the target FB, which is not limited in this embodiment, for example, according to the target FB , and the number and type of unallocated redundant circuits remaining in the chip, determine the available redundant circuits for patching that target FB.
  • the number of available redundant circuits for patching the target FB is one or more.
  • the reliability list of the redundant circuits includes reliability values of multiple redundant circuits in the chip.
  • the reliability value can be 0-1. The larger the value is, the higher the reliability is.
  • the reliability of the available redundant circuits can be obtained from the reliability list of the redundant circuits.
  • the reliability list of the redundant circuit may be established by other devices and then sent to the electronic device executing the method described in this embodiment, or may be established by the electronic device executing the method described in this embodiment.
  • the reliability list of the redundant circuit is established before step S103.
  • the redundant circuit can be established according to the test data of the failed unit in the chip and the statistical data of the detected failure mode stored in the database.
  • Reliability list of remaining circuits Determine the reliability value of each redundant circuit in the chip according to the test data of the FB in the chip stored in the database and the statistical data of the detected failure mode, and store the reliability value of each redundant circuit in the chip to the reliability list for that redundant circuit.
  • the statistical data of the failure mode includes the identification of the failure combination and the total number of occurrences of the failure combination.
  • a failure combination consists of the redundant circuit where the NFB is located and at least one FB within the statistical range of the redundant circuit where the NFB is located.
  • FB's test data includes multiple wafer test results.
  • the failure mode is obtained by statistics on the NFB in the redundant circuit that has occurred and the FB within the statistical range of the redundant circuit where the NFB is located.
  • Determining the repairing scheme of the target FB in the subdomain refers to selecting a target redundant circuit for the target FB in the subdomain from the available redundant circuits, and using the target redundant circuit as the repairing circuit of the target FB in the subdomain.
  • the redundant circuit with the highest reliability is selected from the multiple available redundant circuits as the target redundant circuit.
  • the target FB in the subdomain has only one available redundant circuit
  • the available redundant circuit is determined as the target redundant circuit.
  • the reliability value of each available redundant circuit is obtained from the reliability list of redundant circuits.
  • the reliability list of the redundant circuits includes reliability values of a plurality of redundant circuits, and a repair scheme of the target FB in the sub-domain is determined according to the reliability values of the available redundant circuits.
  • the redundancy circuit allocated to the FB in the sub-domain for repairing by this method has high reliability, thereby improving the repairing efficiency and repairing accuracy of the FB.
  • FIG. 8 is a flowchart of a method for determining a reliability value of a redundant circuit provided by Embodiment 2 of the present application. As shown in FIG. 8 , the method provided by this embodiment includes the following steps:
  • the method of this embodiment may be sequentially performed on each redundant circuit in the chip, first read the test data of the FB in the chip from the database, and determine the current position according to the position of the current redundant circuit and the position of the FB in the chip. Whether there is an FB in the redundant circuit, if there is no FB in the current redundant circuit, step S202 is performed, and if there is an FB in the current redundant circuit, step S208 is performed.
  • n 2 ⁇ n ⁇ m
  • m is an integer
  • S203 Determine the n-ary failure combination of the current redundant circuit and obtain statistical data of the n-ary failure mode.
  • the n-element failure combination of the current redundant circuit is composed of the current redundant circuit and at least one FB within the statistical range of the current redundant circuit.
  • the specific method of determining the n-element failure combination of the current redundant circuit in this step can refer to the aforementioned statistical data The way of determining the n-ary failure combination of the redundant circuit in the establishment phase of the , will not be repeated here.
  • n 2
  • the 2-element failure combination is determined for the current redundant circuit, and the 2-element failure mode is read from the database.
  • n 3
  • the 3-element failure combination is determined for the current redundant circuit. , and read the 3-element failure mode from the database.
  • the unreliability value of each n-ary failure combination of the current redundant circuit is determined, and then according to the n-ary failure of the current redundant circuit The sum of the combined unreliable values calculates the n-ary unreliable value of the current redundant circuit.
  • the n-element failure combination of the current redundant circuit may include multiple n-element failure combinations.
  • the 2-element failure combination of the current redundant circuit includes multiple 2-element failure combinations, and each failure combination includes two elements. , but the position of the FB in each failure combination is different.
  • the unreliability of the ith n-element failure combination is the largest, and the optional , the unreliability can have a maximum value of 1.
  • the calculation of the n-element unreliable value of the current redundant circuit can be: taking the sum of the unreliable values of the n-element failure combinations of the current redundant circuit and the unreliable value of the current redundant circuit.
  • the larger value among the maximum values of the reliable values is used as the n-ary unreliable value of the current redundant circuit.
  • the n-ary unreliable value Q of the current redundant circuit can be expressed by the following formula: L represents the number of n-ary failure combinations included in the current redundant circuit.
  • step S208 is executed.
  • step S206 is executed.
  • n is not greater than m, return to S203, and if n is greater than m, execute S208.
  • the reliability value of the current redundant circuit is determined according to m-1 n-element unreliable values of the current redundant circuit. For example, when m is 4, the 2-element unreliable value of the current redundant circuit is calculated through the above steps. The reliability value of the current circuit is determined according to the 2-element unreliable value, the 3-element unreliable value and the 4-element unreliable value of the current redundant circuit.
  • the reliability value M of the current redundant circuit can be calculated by the following formula:
  • L represents the n-ary unreliable value of the current redundant circuit, 2 ⁇ n ⁇ m.
  • step S208 is also executed.
  • FB in the current redundant circuit
  • the 2-element unreliable value and the 3-element unreliable value of the current redundant circuit are both maximum.
  • the unreliable value The maximum value of M is 1, then according to the calculation formula of M, the reliability value M of the current redundant circuit is 0, that is, when there is FB in the current redundant circuit, the reliability value of the current redundant circuit is the smallest.
  • FB in the current redundant circuit
  • step S208 is also executed.
  • the reliability value M of the current redundant circuit obtained according to the calculation formula of M is also 0.
  • the 2-element unreliable value of the current redundant circuit is equal to the maximum value, and the calculation of the 3-element unreliable value of the redundant circuit will not be performed. At this time, the 3-element unreliable value of the redundant circuit will not be performed.
  • the value can be considered to be 0.
  • Embodiment 3 of the present application provides a method for determining an n-ary failure mode.
  • FIG. 9 is a flowchart of the method for determining failure mode provided by Embodiment 3 of the present application, as shown in FIG. 9 . As shown, the method provided by this embodiment includes the following steps:
  • the statistical data of the n-ary failure combination is stored in the database, and the statistical data of the n-ary failure combination includes the identification of each failure combination and the total number of occurrences of the failure combination.
  • n 2 as an example, assuming that the 2-element failure combination includes 10 failure combinations, then the 10 2-element failure combinations are arranged in descending order of the total number of occurrences.
  • Fig. 10 is a schematic diagram of a dynamic transformation of the way of determining the first threshold value, as shown in Fig. 10, Fig. 10(a) is a schematic diagram after sorting the total number of occurrences of n-ary failure groups, 10(b) is a pair of Figure (a) is a schematic diagram after differentiation, and Figure 10 (c) is a schematic diagram of the first threshold value.
  • the first threshold value is dynamically obtained through steps S303 to S304.
  • the first threshold value may also be a fixed value, or may be obtained in other ways.
  • n is not greater than m, return to S302, if n is greater than m, end, and by cyclically executing the above process, all failure modes from 2 yuan to m yuan can be obtained.
  • Embodiment 4 of the present application provides a method for establishing statistical data.
  • the process of establishing statistical data is the process of obtaining the combined data and statistical data of n-ary failure combinations.
  • FIG. 11 is the present application.
  • the flowchart of the method for establishing statistical data provided in the fourth embodiment is shown in FIG. 11 .
  • the method provided in this embodiment includes the following steps:
  • the NFB is read from the test data of the NFB in sequence, and the currently read NFB is the target NFB.
  • the information of the target NFB includes the type and location information of the target redundant circuit where the NFB is located.
  • the test data of the NFB includes The information of the NFB that occurs in the redundant circuit of the chip, and the information of the NFB includes the type and position information of the redundant circuit where the NFB is located.
  • S402. Determine, according to the test data of the FB, the FB within the analysis range of the target redundant circuit where the target NFB is located.
  • the minimum number of combination elements of the failure combination is 2, and the maximum number of combination elements of the failure combination is related to the number of FBs within the analysis range of the target redundant circuit. Assuming that the number of FBs within the analysis range of the target redundant circuit is M, then the failure The maximum number of combination elements of the combination is 1+M. Assuming that M is 4, the maximum number of combination elements of the failure combination is 5, that is, a total of 2-element failure combination, 3-element failure combination, 4-element failure combination and 5-element failure combination can be formed. Failed combination.
  • the combination data of the 2-element failure combination is stored in the arrangement of ⁇ x 1 ,x 2 ,x 3 >
  • the combination data of the 3-element failure combination is stored in the arrangement of ⁇ x 1 ,x 2 ,x 3 ,x 4 > mode storage, where x 1 represents the type of the redundant circuit, and x 2 , x 3 , and x 4 are used to represent the redundant circuit and the positional relationship of the FB within the statistical range of the redundant circuit.
  • the statistical data of the n-element failure combination includes the identifier of the detected n-element failure combination and the total number of occurrences.
  • the number of occurrences of the failure combination is accumulated to n
  • an identification is generated for the failure combination, and the identification of the failure combination and the number of occurrences are increased to in the statistics of n-ary failure combinations.
  • the fifth embodiment of the present application takes the maximum value of n as 3 as an example, that is, the value of n is 2 and 3, to illustrate the establishment process of the combined data and statistical data of the n-element failure combination.
  • 12 is a flowchart of the method for establishing statistical data provided by Embodiment 5 of the present application. As shown in FIG. 12 , the method provided by this embodiment includes the following steps:
  • the target redundant circuit contains FB, if the target redundant circuit contains FB, execute 505, and if the target redundant circuit does not contain FB, execute S503.
  • each 2-element failure combination is composed of NFB and one FB in the target redundant circuit.
  • each 3-element failure combination is composed of NFB and two FBs in the target redundant circuit.
  • step S506 If there is an undetected NFB, it will return to step S501, and if there is no undetected NFB, then step S506 will be performed.
  • an electronic analysis device comprising: at least one processor and a memory, the memory storing computer-executable instructions, the at least one processor executing the computer-implemented instructions stored in the memory, such that The at least one processor executes the methods described in the above method embodiments.
  • non-transitory computer-readable storage medium including instructions
  • the non-transitory computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, Tape, floppy disk, and optical data storage devices, etc.
  • Embodiments of the present application further provide a computer program product, including a computer program.
  • a computer program product including a computer program.
  • the computer program is executed by a processor, the method described in the foregoing method embodiment is implemented.
  • the specific implementation manner and technical effect are similar, and details are not repeated here.

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Abstract

一种失效位元的修补方案的确定方法和装置，应用于包含多个子域的芯片，该芯片还包括冗余电路，该冗余电路用于修补子域中的失效位元，该方法包括：在为子域中的当前待修补的目标失效位元确定一个或者多个可用冗余电路之后，从冗余电路的可靠性列表中获取各可用冗余电路的可靠性值，该冗余电路的可靠性列表中包括多个冗余电路的可靠性值，根据该可用冗余电路的可靠性值确定子域中的目标失效位元的修补方案。其中，冗余电路的可靠性值是对已经发生的失效位元以及冗余电路中新失效位元所在的冗余电路的关系进行大数据分析得到的，通过该方法为子域中失效位元分配的冗余电路的可靠性高，从而提高了失效位元的修补效率和修补准确率。

Description

失效位元的修补方案的确定方法和装置
本申请要求于2020年9月11日提交中国专利局、申请号为202010955742.5、申请名称为“失效位元的修补方案的确定方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种失效位元的修补方案的确定方法和装置。
背景技术
芯片在研制、生产和使用过程中产生的失效问题不可避免，可以通过晶圆测试(circuit probe或者chip probe，简称CP)获知芯片中的失效位元(fail bit，FB)位置。
目前可以采用冗余(redundancy，简称RD)电路对芯片中的失效位元进行修补处理然而，也有可能在晶圆测试之后产生失效位元，将在晶圆测试之后产生的失效位元称为新失效位元(new fail bit，NFB)。
RD电路中若产生NFB，相当于对失效位元修补失败，从而导致失效位元的修补效率和修补准确率较低。
发明内容
本申请提供一种失效位元的修补方案的确定方法和装置，用以解决失效位元的修补效率和修补准确率较低的问题。
本申请第一方面提供一种失效位元修补方案的确定方法，应用于包含多个子域的芯片，所述芯片还包括冗余电路，所述冗余电路用于修补所述子域中的失效位元，包括：
获取所述芯片的晶圆测试结果，所述晶圆测试结果中包括所述芯片中的失效位元的位置信息，所述芯片中的失效位元包括所述子域中的失效位元和所述冗余电路中的失效位元；
确定修补所述晶圆测试结果中的所述子域中的目标失效位元的可用冗余电路；
从预先获取的冗余电路的可靠性列表中获取所述可用冗余电路的可靠性值，所述冗余电路的可靠性列表中包括多个冗余电路的可靠性值；
根据所述可用冗余电路的可靠性值确定所述目标失效位元的修补方案。
可选的，从预先获取的冗余电路的可靠性列表中获取所述可用冗余电路的可靠性值之前，还包括：建立所述冗余电路的可靠性列表。
可选的，所述建立所述冗余电路的可靠性列表，包括：
根据数据库中存储的所述芯片中的失效单元的测试数据以及已经检测到的失效模式的统计数据，确定所述芯片中的每个冗余电路的可靠性值，其中，所述失效模式的统计数据中包括多个失效组合的标识和失效组合的总发生次数，所述失效组合由新失效位元所在的冗余电路以及所述新失效位元所在的冗余电路的统计范围内的至少一个失效位元组成，所述芯片中的失效位元测试数据中包括多个晶圆测试结果；
将所述芯片中的每个冗余电路的可靠性值存储到所述冗余电路的可靠性列表中。
可选的，所述根据数据库中存储的所述芯片中的失效单元的测试数据以及已经检测到的失效模式的统计数据，确定所述芯片中的每个冗余电路的可靠性值，包括：
根据所述失效单元的测试数据判断所述芯片中的当前冗余电路是否存在失效位元；
若所述当前冗余电路中存在失效位元，则确定所述当前冗余电路的可靠性值；
若所述当前冗余电路中不存在失效位元，则初始化n的取值为2，确定所述当前冗余电路的n元失效组合并获取n元失效模式的统计数据，所述当前冗余电路的n元失效组合由所述当前冗余电路以及所述当前冗余电路的统计范围内的至少一个失效位元组成；
根据所述当前冗余电路的n元失效组合和所述n元失效模式的统计数据，计算所述当前冗余电路的n元不可靠值；
当所述当前冗余电路的n元不可靠值等于最大值时，则确定所述当前冗余电路的可靠性值；
当所述当前冗余电路的n元不可靠值小于最大值时，将n加1，判断n是否大于m，m为n的最大取值；
当n不大于m时，返回执行确定所述当前冗余电路的n元失效组合并获取n元失效模式的统计数据的步骤；
当n大于m时，根据所述当前冗余电路的m-1个n元不可靠值确定所述当前冗余电路的可靠性值。
可选的，所述方法还包括：
从数据库中获取n元失效组合的统计数据，所述n元失效组合的统计数据中包括各失效组合的标识以及失效组合的总发生次数；
根据所述n元失效组合的统计数据，确定所述n元失效组合对应的n元失效模式。
可选的，所述从数据库中获取n元失效组合的统计数据之前，还包括：
获取n元失效组合的组合数据，所述n元失效组合的组合数据中包括组成失效组合的冗余电路和冗余电路的统计范围内的失效位元的位置关系，以及冗余电路的类型；
从所述n元失效组合的组合数据中获取各失效组合的出现次数；
根据所述各失效组合的出现次数更新所述n元失效组合的统计数据。
可选的，所述获取n元失效组合的组合数据，包括：
从所述芯片的新失效单元的测试数据中，获取未检测过的目标新失效单元的信息，所述目标新失效单元的信息包括所述目标新失效单元所在的目标冗余电路的类型和位置信 息，所述新失效单元测试数据中包括多个芯片的冗余电路中发生的新失效单元的信息，所述新失效单元的信息包括新失效单元所在的冗余电路的类型和位置信息；
根据所述失效单元的测试数据确定所述目标新失效单元所在的目标冗余电路的分析范围内的失效单元；
使用所述目标新失效单元和所述目标冗余电路的分析范围内的失效单元组成所述n元失效组合，其中，所述n元失效组合包括所述目标新失效单元和n-1个失效单元。
本申请提供的失效位元的修补方案的确定方法和装置，在为子域中的当前待修补的目标失效位元确定一个或者多个可用冗余电路之后，从冗余电路的可靠性列表中获取各可用冗余电路的可靠性值，该冗余电路的可靠性列表中包括多个冗余电路的可靠性值，根据该可用冗余电路的可靠性值确定子域中目标失效位元的修补方案。其中，冗余电路的可靠性值是对已经发生的失效位元以及新失效位元所在的冗余电路的关系进行大数据分析都得到的，通过该方法为子域中的失效位元分配的冗余电路的可靠性高，从而提高了失效位元的修补效率和修补准确率。
附图说明
图1为本申请实施例适用的芯片的一种结构示意图；
图2为本申请提供的芯片检测和修补过程的示意图；
图3为冗余字线的分析范围的示意图；
图4为冗余位线的分析范围的示意图；
图5为2元失效组合的示意图；
图6为3元失效组合的示意图；
图7为本申请实施例一提供的失效位元的修补方案的确定方法的流程图；
图8为本申请实施例二提供的冗余电路的可靠性值的确定方法流程图；
图9为本申请实施例三提供的失效模式的确定方法的流程图；
图10为第一门限值的确定方式的一种动态变换示意图；
图11为本申请实施例四提供的建立统计数据的方法的流程图；
图12为本申请实施例五提供的建立统计数据的方法的流程图。
具体实施方式
在一个芯片中，通常包含大量的位元(bit)。示例性的，一个典型的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)芯片有多达6千4百万个位元，这些位元可以按行和列的方式形成阵列，通过字线(word line)和位线(bit line)可以寻址阵列中的位元。
在DRAM芯片的制造过程中，形成的芯片中主要矩阵中的某些位元可能存在着缺陷，即所谓的失效位元(Fail Bit，简称FB)。为了提高芯片的成品率，通常会在芯片上制作 冗余电路，冗余电路可以替代有缺陷的失效位元，使得存储电路可以正常使用。
冗余位元也称为备用电路，冗余电路又分为全域冗余电路(Global Redundancy，GR)和子域冗余电路(Local Redundancy，LR)，全域冗余电路用于修补所属目标全域以及所述目标全域的相邻全域中的任一子域中的失效位元，子域冗余电路用于修补为所述目标冗余电路所属的目标子域以及所述目标子域的相邻子域中的失效位元。全域冗余电路可以为冗余字线(Redundant Word Line，简称RWL)，也称为列冗余电路，子域冗余电路可以为冗余位线(Redundant Bit Line，简称RBL)，也称为行冗余电路。
本申请实施例中，子域是对FB进行修补时的最小修补单位(或者称为最小修补区域)，全域是比子域更大的修补单位，一个全域由字线方向上的多个连续子域构成。
图1为本申请实施例适用的芯片的一种结构示意图，参照图1，芯片100包括主要矩阵区110和冗余单元区120，冗余单元区120用于对主要矩阵区110进行修补。由于芯片100中含有的位元数量较多，为了提高修补的效率，可以将芯片100的主阵列，即主要矩阵区110划分为多个子域111，每个子域111可以包含一定数量的位元。冗余单元区120包括全域冗余电路121和子域冗余电路122，其中，全域冗余电路121用于修补任一子域111中的失效位元，子域冗余电路122用于修补指定的子域111中的失效位元，例如，如图1所示，子域冗余电路122’只能修补子域111’中的失效位元。
可选的，参照图1所示，全域冗余电路121为列冗余电路，可以用于替换字线，从而修补该字线上的失效位元，并且一条全域冗余电路121可以同时修补一个字线上的多个失效位元；而子域冗余电路122为行冗余电路，可以用于替换位线，从而修补该位线上的失效位元，并且一条子域冗余电路122可以同时修补一个位线上的多个失效位元。
现有技术中，在晶圆测试阶段会检测到芯片中的所有FB，芯片的子域和冗余电路都可能发生FB，所以，晶圆测试得到的FB包括芯片的子域中的FB和芯片的冗余电路中的FB。在冗余分配阶段，为所述子域中的FB分配对应的冗余电路进行修补，但是在晶圆测试之后所述冗余电路中也有可能产生FB，若为所述子域中的FB分配的冗余电路产生了新失效位元(new fail bit，NFB)，则导致所述子域中的FB的修补失败。
本申请实施例中，将晶圆测试阶段检测到的失效的位元称为FB，将晶圆测试之后产生的失效位元称为新失效位元(New Fail Bit，NFB)，可以理解，还可以通过其他名称区分两个不同阶段产生的失效位元，例如，将晶圆测试阶段检测到的失效位元称为第一类FB，将晶圆测试之后产生的失效位元称为第二类FB，或者，将晶圆测试阶段检测到的失效位元称为第一FB，将晶圆测试之后产生的失效位元称为第二FB，本实施例不对此进行限制。
本申请实施例为了避免在冗余分配阶段为所述子域中的FB分配可能发生NFB的冗余电路，对芯片的FB的测试结果(即晶圆测试结果)和NFB的测试结果进行统计，得到FB的测试数据(也可以称为FB的历史测试数据)和NFB的测试数据(也可以称为NFB的历史测试数据)，通过对芯片的FB的测试数据和NFB的测试数据进行大数据分析，挖掘出所有冗余电路在晶圆测试后形成的NFB受所述芯片在晶圆测试时形成的FB位置分布影 响的状况，并将这些状况形成失效模式(也可以称为位元失效模式)，进而根据失效模式得到每个冗余电路的可靠性值，后续可以根据冗余电路的可靠性值确定当前晶圆测试得到子域中的FB的修补方案，即优先分配可靠性高的冗余电路给子域中的FB，从而提高了所述子域中的FB的修补效率和修补准确率。
图2为本申请提供的芯片检测和修补过程的示意图，如图2所示，该芯片制造过程包括：晶圆测试阶段、冗余电路的优劣检测阶段、冗余电路的分配阶段以及其他测试阶段。
通过晶圆测试获取到晶圆测试结果，晶圆测试结果中包括芯片中的FB的位置信息，该芯片中的FB包括子域中的FB和冗余电路中的FB，FB的位置信息被存储到应用数据库中，应用数据库中包括第一数据库和第二数据库，第一数据库中存储有的FB测试数据和NFB的测试数据，FB的位置信息具体存储到FB的测试数据中。第二数据库中存储有2元失效模式的统计数据、3元失效模式的统计数据和冗余电路的可靠性列表。
NFB的测试数据中包括芯片的历史NFB测试结果，NFB的测试结果是在对FB进行修补之后测量得到的，即在图2中的其他测试阶段对芯片进行测量得到的。在其他测试阶段子域中的位元和冗余电路中的位元同样都可能发生NFB，所以芯片的NFB同样包括子域中的NFB和冗余电路中的NFB。NFB的测试结果中包括NFB的信息，该冗余电路中的NFB的信息包括NFB的位置、NFB所在的冗余电路的类型和位置信息。冗余电路的类型可以包括：冗余字线和冗余位线。
冗余电路的优劣检测阶段是本申请新增的阶段，现有技术中在晶圆测试之后直接执行冗余电路的分配阶段。本申请实施例中，通过增加冗余电路的优劣检测阶段，可以得到芯片中的每个冗余电路的可靠性值，后续在冗余电路的分配阶段，根据冗余电路的可靠性值为子域中FB分配冗余电路。
可选的，将冗余电路优劣的检测阶段划分为两个子阶段：失效模式建立阶段和失效模式实施阶段。
可选的，失效模式建立阶段包括以下四个过程：定时器的启动、冗余电路的分析范围的定义、统计数据的建立和失效模式的挖掘。
定时器的启动过程是为了获取更多未知的失效模式或者更新已建立失效模式的出现次数，通过定时器可以在固定时间启动，以获取更多未知的失效模式或者更新已建立失效模式的出现次数。由于芯片的FB的测试数据和NFB的测试数据是不断更新的，所以，可能会出现更多未知的失效模式，并且已建立的失效模式也可能在失效模式建立之后出现在其他芯片中，所以已建立失效模式的出现次数也是不断变化的，二者都需要不断更新。
冗余电路的分析范围的定义过程是为了定义各种类型的冗余电路受所述芯片的FB位置影响的范围，其中，该分析范围可以依芯片不同而改变。常见的冗余电路的类型包括：冗余字线和冗余位线。
当冗余电路为冗余字线时，示例性的，冗余电路的分析范围为冗余电路所属的全域(也称为section)以及冗余电路所属全域的相邻全域，冗余电路所属的全域可以称为目标全域。 图3为冗余字线的分析范围的示意图，如图3所示，芯片的位元在位线方向上被划分为多个区域，芯片的位元在字线方向上没有被划分，通过该划分方式形成多个全域。
参考图3，假设冗余电路所属的全域为N，那么，全域N的相邻全域有两个分别为：全域N-1和全域N-1。
当冗余电路为冗余位线时，示例性的，冗余电路的分析范围为冗余电路所属的子域以及冗余电路所属子域的相邻子域，冗余电路所属的子域可以称为目标子域。图4为冗余位线的分析范围的示意图，如图4所示，芯片的位元在位线方向上被划分为多个区域，芯片的位元在字线方向也被划分为多个区域，通过该划分方式形成多个子域。
对于图3和图4，可知，子域是比全域更小的区域，一个全域在字线方向上可以被划分为多个更小区域从而形成子域，或者说位于字线方向上的多个连续子域构成一个全域，图4所示示例中，每个全域包括4个相同大小的子域，这里只是举例说明，一个全域包括的子域的数量本实施例不对此进行限制。
参考图4，冗余电路所属的子域共有4个相邻子域，分别为冗余电路所属的子域的上下左右相邻的子域，可以理解，当冗余电路位于芯片的边缘位置时，冗余电路所属的子域的相邻子域的个数可能小于4个，例如，当冗余电路位于全域N的第一行时，冗余电路的上方没有子域，所以冗余电路只有3个相邻子域，当备用电位于全域N-3的第一行时，冗余电路的左方和上方都没有子域，所以冗余电路只有2个相邻子域。
本实施例中，全域中可能有冗余字线，也可能没有冗余字线，根据全域内是否有冗余字线将全域划分为两类：一类全域中包括主要矩阵(main array，简称MA)和冗余位线，不包括冗余字线。另一类全域中包括MA、冗余位线和冗余字线。
相应的，芯片中的冗余电路也包括子域冗余电路和全域冗余电路，子域冗余电路只可以修补相对应的子域中的FB，全域冗余电路可以修补相对应的全域中的任意子域中的FB。
统计数据的建立是为了获取所述冗余电路中的NFB的测试数据中的每个NFB所在的冗余电路以及NFB所在的冗余电路的统计范围内的FB形成的失效组合。将当前检测的NFB称为目标NFB，从NFB测试数据中读取到该目标NFB的信息，该目标NFB的信息包括目标NFB所在的冗余电路的类型和冗余电路的位置，目标NFB所在的冗余电路可以称为目标冗余电路。
根据该目标冗余电路的类型，确定该目标冗余电路的分析范围，从芯片中的FB的测试数据中获取该目标冗余电路的分析范围内的FB。根据目标冗余电路和该目标冗余电路的分析范围内的FB形成失效组合，其中，每个失效组合中包括该目标冗余电路和该目标冗余电路的分析范围内的至少一个FB组成。
根据失效组合中包括的元素(包括NFB和FB)个数，可以形成n元失效组合，n的取值为2到m，m的最大取值与该目标冗余电路分析范围内的FB个数有关，例如，该目标冗余电路分析范围内的FB个数为4个，那么m的最大取值为5。在实际使用过程中，n的取值可以小于m的最大取值，例如，通常情况下n取2和3即可满足要求，即针对每个 NFB，只需要确定其对应的2元失效组合和3元失效组合。
图5为2元失效组合的示意图，如图5所示，该目标冗余电路的分析范围内共有4个FB，NFB所在的冗余电路分别与该分析范围内的一个FB形成一个2元失效组合，总共可以形成4个2元失效组合。
图6为3元失效组合的示意图，如图6所示，该目标冗余电路的分析范围内共有4个FB，NFB所在的冗余电路分别与该分析范围内的两个FB形成一个3元失效组合，总共可以形成6个3元失效组合。
这里只是举例说明，当该目标冗余电路的分析范围内共有4个FB时，还可以形成4元失效组合和5元失效组合，4元失效组合由NFB所在的冗余电路和该分析范围内的3个FB组成，5元失效组合由NFB所在的冗余电路和该分析范围内的4个FB组成。但是，随着失效组合包括的元素数量的增加形成的失效组合的个数在减小，例如，当m为5时，4元失效组合的数量为2个，5元失效组合的数量为1个。
在确定n元失效组合之后，保存n元失效组合的组合数据，可以将n元失效组合的组合数据存储到大数据分析平台中。示例性的，大数据分析平台中存储有2元失效组合的组合数据、3元失效组合的组合数据，还存储有2元失效组合的统计数据以及3元失效组合的统计数据。
其中，失效组合的组合数据用于描述NFB所在的冗余电路的类型，冗余电路与FB的相对位置关系。示例性的，2元失效组合的组合数据以<x 1,x 2,x 3>的排列方式存储，其中，x 1表示NFB所在的冗余电路的类型，当NFB所在的冗余电路的类型为冗余字线时，x 2表示FB所属的全域相对于NFB所在的冗余电路所属的全域的相对位置，当NFB所在的冗余电路的类型为冗余位线时，x 2表示FB所属的子域相对于NFB所在的冗余电路所属的子域的相对位置，x 3为FB位置与NFB所在的冗余电路的最小距离。
示例性的，3元失效组合的组合数据以<x 1,x 2,x 3,x 4>的排列方式存储，其中，x 1表示NFB所在的冗余电路的类型，当NFB所在的冗余电路的类型为冗余字线时，x 2表示FB所属的全域相对于NFB所在的冗余电路所属的全域的相对位置，当NFB所在的冗余电路的类型为冗余位线时，x 2表示FB所属的子域相对于NFB所在的冗余电路所属的子域的相对位置，x 3为两个FB中较低位的FB的位置与NFB所在的冗余电路的最小距离，x 4为两个FB中较高位的FB的位置与NFB所在的冗余电路的最小距离，较低位和较高位是相对于同一位线的位置来说。
在将NFB的测试数据中的所有NFB都检测之后，根据n元失效组合的组合数据更新n元失效组合的统计数据，n元失效组合的统计数据用于统计每种失效组合的总出现次数，n元失效组合的统计数据会对每种失效组合分配一个唯一的标识或者编号，用于唯一标识一种失效组合。
示例性的，根据2元失效组合的组合数据确定2元失效组合中的每种失效组合的出现次数，其中，2元失效组合中包括一种或者多种不同的失效组合，可以通过结构化查询语 言(structured query language，简称SQL)语法获得每种失效组合的出现次数，如果2元失效组合的统计数据中存在该种失效组合，则将该种失效组合的出现次数累加到统计数据中该种失效组合的总出现次数上。如果2元失效组合的统计数据中不存在该种失效组合，则为该种失效组合分配编号或者标识，则将该种失效组合的出现次数作为该种失效组合的总出现次数。按照同样的方法更新3元失效组合的统计数据，这里不再赘述。
在失效模式的挖掘过程中，根据n元失效组合的统计数据得到n元失效模式，并存储n元失效模式的统计数据，n元失效组合的统计数据中包括多个失效组合，只有满足一定条件的失效组合才能作为失效模式，例如，将n元失效组合的统计数据中总出现次数大于门限值的失效组合作为n元失效模式，所以，n元失效模式的统计数据包括每种失效组合的编号和总出现次数。
例如，可以根据2元失效组合的统计数据得到2元失效模式，根据3元失效组合的统计数据得到3元失效模式。假设2元失效组合的统计数据中共包括10种失效组合，其中，只有4种失效组合的总出现次数大于门限值，则将总出现次数大于门限值的4个失效组合确定为2元失效模式。
在失效模式实施阶段根据已经获取到的失效模式为芯片中的每个冗余电路确定或者预估一个可靠性值，该可靠性值的范围可以为0-1，可靠性值为0表示冗余电路绝对不可靠，可靠性值越大表示冗余电路越可靠，冗余电路的可靠性越大说明冗余电路产生NFB的可能性越小，冗余电路可靠性值越小说明冗余电路产生NFB的可能性越大。
芯片中的每个冗余电路的可靠性值可以存储到冗余电路的可靠性列表中，后续可以根据冗余电路的可靠性列表中的各冗余电路的可靠性值为子域中的FB分配冗余电路，优先为子域中的FB分配可靠性高的冗余电路，可靠性越高的冗余电路后续产生NFB的可能性越低，从而提高了FB的修补效率和修补准确率。
图7为本申请实施例一提供的失效位元的修补方案的确定方法的流程图，本实施例的方法应用在包含多个子域的芯片中，例如图1所示芯片中，该芯片还包括冗余电路，冗余电路用于修补子域中的FB。如图7所示，本实施例的方法可以包括以下步骤：
S101、获取芯片的晶圆测试结果，该晶圆测试结果中包括芯片中的FB的位置信息，芯片中的FB包括子域中的FB和冗余电路中的FB。
该晶圆测试结果可以是从测试程序或者测试模块直接获得的结果，也可以是从数据库中的芯片中的FB的测试数据中获取到的，测试程序或者模块进行晶圆测试之后，将晶圆测试结果保存到数据库中。
S102、确定修补该晶圆测试结果中的目标子域中的FB的可用冗余电路。
该晶圆测试结果中可能包括多个子域中的FB的位置信息，可以按照一定的顺序依次从晶圆测试结果中选择一个子域中的FB作为当前待修补的目标FB，并确定修补该目标FB的可用冗余电路。其中，在确定修补该目标FB的可用冗余电路时，可以采用已有的任意一种方法确定修补该目标FB的可用冗余电路，本实施例并不对此进行限制，例如，根 据该目标FB的位置，以及芯片中剩余未被分配的冗余电路的数量和类型，确定修补该目标FB的可用冗余电路。修补该目标FB的可用冗余电路的数量为一个或者多个。
S103、从预先获取的冗余电路的可靠性列表中获取该可用冗余电路的可靠性值，该冗余电路的可靠性列表中包括多个冗余电路的可靠性值。
该冗余电路的可靠性列表中包括芯片中的多个冗余电路的可靠性值，示例性的，可靠性值的取值可以为0-1，取值越大说明可靠性越高，从该冗余电路的可靠性列表中可以获取到可用冗余电路的可靠性。
其中，该冗余电路的可靠性列表可以由其他设备建立之后发送给执行本实施例所述方法的电子设备，也可以是由执行本实施例所述方法的电子设备建立的。
可选的，在步骤S103之前建立该冗余电路的可靠性列表，示例性的，可以根据数据库中存储的芯片中的失效单元的测试数据以及已经检测到的失效模式的统计数据，建立该冗余电路的可靠性列表。根据数据库中存储的芯片中的FB的测试数据以及已经检测到的失效模式的统计数据确定芯片中的每个冗余电路的可靠性值，将芯片中的每个冗余电路的可靠性值存储到该冗余电路的可靠性列表中。
该失效模式的统计数据中包括失效组合的标识和失效组合的总发生次数，一个失效组合由NFB所在的冗余电路以及该NFB所在的冗余电路的统计范围内的至少一个FB组成，该芯片中的FB的测试数据中包括多个晶圆测试结果。该失效模式是对已经发生的冗余电路中的NFB和该NFB所在的冗余电路的统计范围内的FB进行统计得到的。
S104、根据该可用冗余电路的可靠性值确定子域中的目标FB的修补方案。
确定子域中的目标FB的修补方案是指从可用冗余电路中为该子域中的目标FB选择一个目标冗余电路，将该目标冗余电路作为子域中的目标FB的修补电路。
当子域中的目标FB具有多个可用冗余电路时，从该多个可用冗余电路中选择可靠性最高的冗余电路作为目标冗余电路，当子域中的目标FB只有一个可用冗余电路时，将该可用冗余电路确定为目标冗余电路。
本实施例中，在为子域中的当前待修补的目标FB确定一个或者多个可用冗余电路之后，从冗余电路的可靠性列表中获取各可用冗余电路的可靠性值，该冗余电路的可靠性列表中包括多个冗余电路的可靠性值，根据该可用冗余电路的可靠性值确定子域中的目标FB的修补方案。通过该方法为子域中的FB分配的用于修补的冗余电路的可靠性高，从而提高了FB的修补效率和修补准确率。
在实施例一的基础上，本实施例中将详细介绍如何建立冗余电路的可靠性列表，即如何根据芯片中的FB的测试数据以及已经检测到的失效模式的统计数据，确定芯片中的每个冗余电路的可靠性值。图8为本申请实施例二提供的冗余电路的可靠性值的确定方法流程图，如图8所示，本实施例提供的方法包括以下步骤：
S201、判断当前冗余电路是否存在FB。
可以依序对芯片中的每个冗余电路执行本实施例的方法，先从数据库中读取芯片中的 FB的测试数据，根据当前冗余电路的位置以及芯片中的FB的位置，确定当前冗余电路中是否存在FB，如果当前冗余电路中不存在FB则执行步骤S202，如果当前冗余电路中存在FB则执行步骤S208。
S202、初始化n的取值为2，并设置n的最大取值为m。
本实施例中，n的取值为2≤n≤m，m为整数。
S203、确定当前冗余电路的n元失效组合并获取n元失效模式的统计数据。
当前冗余电路的n元失效组合由当前冗余电路以及当前冗余电路的统计范围内的至少一个FB组成，本步骤中确定当前冗余电路的n元失效组合的具体方式可参照前述统计数据的建立阶段确定冗余电路的n元失效组合的方式，这里不再赘述。
当n的取值为2时，为当前冗余电路确定2元失效组合，并从数据库中读取2元失效模式，当n的取值为3时，为当前冗余电路确定3元失效组合，并从数据库中读取3元失效模式。
S204、根据当前冗余电路的n元失效组合和n元失效模式的统计数据，计算当前冗余电路的n元不可靠值。
示例性的，根据当前冗余电路的n元失效组合和n元失效模式的统计数据，确定当前冗余电路的每个n元失效组合的不可靠值，然后根据当前冗余电路的n元失效组合的不可靠值的总和，计算当前冗余电路的n元不可靠值。
当前冗余电路的n元失效组合中可以包括多个n元的失效组合，例如，当前冗余电路的2元失效组合中包括多个2元的失效组合，各失效组合中均包括两个元素，但是各失效组合中的FB的位置不同。
相应的，针对当前冗余电路的第i个n元失效组合，当第i个n元失效组合属于n元失效模式时，则确定第i个n元失效组合的不可靠性最大，可选的，不可靠性的最大值可以为1。当第i个n元失效组合不属于n元失效模式时，则根据以下公式计算第i个n元失效组合的不可靠性：f n(x i,q i)＝q i×max(q) -1，其中，x i表示第i个n元失效组合，q i表示第i个n元失效组合的总出现次数，max(q)表示当前冗余电路的多个n元失效组合的总出现次数中的最大值，max(q) -1表示max(q)的负一次方。
根据当前冗余电路的n元失效组合的不可靠值的总和，计算当前冗余电路的n元不可靠值，可以为：取当前冗余电路的n元失效组合的不可靠值的总和以及不可靠值的最大值中的较大值作为当前冗余电路的n元不可靠值。
示例性的，不可靠值的最大值为1，则当前冗余电路的n元不可靠值Q可以通过如下公式表示：
Figure PCTCN2021100004-appb-000001
L表示当前冗余电路的中包括的n元失效组合的个数。
S205、判断当前冗余电路的n元不可靠值是否等于最大值。
在当前冗余电路的n元不可靠值等于最大值时，执行步骤S208。当所述当前冗余电路的n元不可靠值小于最大值时，执行步骤S206。
S206、将n加1。
n加1即切换失效组合，从2元失效组合切换到3元失效组合，或者，从3元失效组合切换到4元失效组合。
S207、判断n是否大于m。
如果n不大于m，则返回执行S203，如果n大于m，则执行S208。
S208、确定当前冗余电路的可靠性值。
可选的，根据当前冗余电路的m-1个n元不可靠值确定当前冗余电路的可靠性值，例如，当m取4时，通过上述步骤计算得到当前冗余电路的2元不可靠值、3元不可靠值以及4元不可靠值，则根据当前冗余电路的2元不可靠值、3元不可靠值和4元不可靠值确定当前电路的可靠性值。
示例性的，可以通过如下公式计算当前冗余电路的可靠性值M：
Figure PCTCN2021100004-appb-000002
其中，L表示当前冗余电路的n元不可靠值，2≤n≤m。
如果当前冗余电路存在FB，也会执行步骤S208，该情况下，当前冗余电路存在FB，说明当前冗余电路的2元不可靠值和3元不可靠值均为最大，如果不可靠值的最大值为1，则根据M的计算公式得到当前冗余电路的可靠性值M为0，即当前冗余电路存在FB时，当前冗余电路的可靠性值最小。可选的，如果当前冗余电路存在FB，也可以不通过公式M计算，直接确定当前冗余电路的可靠性值最小。
同样，在当前冗余电路的n元不可靠值等于最大值时，也执行步骤S208，该情况下，根据M的计算公式得到当前冗余电路的可靠性值M也为0。当n的取值为2时，当前冗余电路的2元不可靠值等于最大值，则不会执行冗余电路的3元不可靠值的计算，此时，冗余电路的3元不可靠值可以认为是0。
S209、将当前冗余电路的可靠性值存储到冗余电路的可靠性列表中
在实施例一和实施例二的基础上，本申请实施例三提供一种n元失效模式的确定方法，图9为本申请实施例三提供的失效模式的确定方法的流程图，如图9所示，本实施例提供的方法包括以下步骤：
S301、初始化n的取值为2，并设置n的最大取值为m。
S302、获取n元失效组合的统计数据。
n元失效组合的统计数据存储在数据库中，n元失效组合的统计数据中包括各失效组合的标识以及失效组合的总发生次数。
S303、按照n元失效组合中的各个失效组合的总出现次数从大到小对n元失效组合进行排序。
以n的取值为2为例进行说明，假设2元失效组合中包括10个失效组合，则将该10个2元失效组合按照总出现次数从大到小进行排列。
S304、对排序后的失效组合组成的序列进行微分，得到微分序列。
S305、获取该微分序列中的最大值所在的位置，该最大值所在的位置处的总出现次数为第一门限值。
S306、确定总出现次数大于第一门限值的失效组合为n元失效组合对应的n元失效模式。
图10为第一门限值的确定方式的一种动态变换示意图，如图10所示，图10(a)为对n元失效组的总出现次数排序后的示意图，10(b)为对图(a)进行微分后的示意图，10(c)为第一门限值的示意图。
本实施例中，通过步骤S303至S304动态获取第一门限值，可选的，第一门限值也可以是一个固定值，或者，通过其他方式获取。
S307、将n+1。
S308、判断n是否大于m。
如果n不大于m，则返回执行S302，如果n大于m，则结束，通过循环执行上述流程，可以获取到2元至m元的所有失效模式。
在实施例一至实施例三的基础上，本申请实施例四提供一种建立统计数据的方法，建立统计数据的过程即获取n元失效组合的组合数据和统计数据的过程，图11为本申请实施例四提供的建立统计数据的方法的流程图，如图11所示，本实施例提供的方法包括以下步骤：
S401、从NFB的测试数据中，获取未检测过的目标NFB的信息。
按照顺序依次从NFB的测试数据中读取NFB，当前读取到的NFB为目标NFB，该目标NFB的信息包括NFB所在的目标冗余电路的类型和位置信息，其中，NFB的测试数据中包括芯片的冗余电路中发生的NFB的信息，NFB的信息包括NFB所在的冗余电路的类型和位置信息。
S402、根据FB的测试数据确定目标NFB所在的目标冗余电路的分析范围内的FB。
S403、使用目标NFB和目标冗余电路的分析范围内的FB组成n元失效组合，其中，该n元失效组合包括目标冗余电路和该分析范围内的n-1个FB。
失效组合的最小组合元素数量为2，失效组合的最大组合元素数量与目标冗余电路的分析范围内的FB的数量有关，假设目标冗余电路的分析范围内的FB的数量为M，则失效组合的最大组合元素的数量为1+M，假设M为4，则失效组合的最大组合元素的数量为5，即总共可以组成2元失效组合、3元失效组合、4元失效组合和5元失效组合。
S404、存储n元失效组合的组合数据，n元失效组合的组合数据中包括组成失效组合的冗余电路和冗余电路的统计范围内的FB的位置关系，以及冗余电路的类型。
示例性的，2元失效组合的组合数据以<x 1,x 2,x 3>的排列方式存储，3元失效组合的组合数据以<x 1,x 2,x 3,x 4>的排列方式存储，其中，x 1表示冗余电路的类型，x 2,x 3,x 4用于表示冗余电路和冗余电路的统计范围内的FB的位置关系。
S405、从n元失效组合的组合数据中获取各失效组合的出现次数。
S406、根据各失效组合的出现次数更新n元失效组合的统计数据。
n元失效组合的统计数据中包括已经检测到的n元失效组合的标识以及总出现次数，当步骤S404中获取到的某个失效组合已经存在时，则将该失效组合的出现次数累加到n元失效组合的统计数据中存在的该失效组合的总出现次数上，如果S404中获取到的某个失效组合不存在，则为该失效组合生成标识，将该失效组合的标识和出现次数增加到n元失效组合的统计数据中。
在实施例四的基础上，本申请实施例五以n的最大取值为3为例，即n的取值为2和3，说明n元失效组合的组合数据和统计数据的建立过程，图12为本申请实施例五提供的建立统计数据的方法的流程图，如图12所示，本实施例提供的方法包括以下步骤：
S501、获取未检测过的目标NFB的信息，以及目标NFB所在的目标冗余电路的分析范围内的FB的信息。
从NFB的测试数据中读取未检测过的目标NFB的信息，以及从FB的测试数据中读取NFB所在的目标冗余电路的分析范围内的FB的信息。
S502、判断目标冗余电路中是否包含FB。
根据目标冗余电路的分析范围内的FB的信息，可以判断目标冗余电路中是否包含FB，如果目标冗余电路中包含FB，则执行505，如果目标冗余电路中不包含FB，则执行S503。
S503、获取2元失效组合，将2元失效组合的组合数据存储到大数据分析平台中。
假设目标冗余电路的分析范围内有4个FB，则可以组成4个2元失效组合，每个2元失效组合由目标冗余电路中的NFB和一个FB组成。
S504、获取3元失效组合，将3元失效组合的组合数据存储到大数据分析平台中。
当目标冗余电路的分析范围内有4个FB时，则可以组成6个3元失效组合，每个3元失效组合由目标冗余电路中的NFB和两个FB组成。
S505、判断是否存在未检测过的NFB。
如果存在未检测过的NFB，则将返回执行步骤S501，如果不存在未检测过的NFB，则执行步骤S506。
S506、根据2元失效组合的组合数据更新大数据分析平台中的2元失效组合的统计数据。
从2元失效组合的统计数据中获取各失效组合的出现次数，根据各失效组合的出现次数更新大数据分析平台中的2元失效组合的统计数据，如果某个失效组合已经存在于2元失效组合的统计数据，则将该失效组合的出现次数累加到2元失效组合的统计数据中相同的失效组合的总出现次数上，如果某个失效组合不存在于2元失效组合的统计数据中，则将该失效组合分配一个标识，并将该失效组合的标识和失效次数增加到2元失效组合的统计数据中。
S507、根据3元失效组合的组合数据更新大数据分析平台中的3元失效组合的统计数 据。
从3元失效组合的统计数据中获取各失效组合的出现次数，根据各失效组合的出现次数更新大数据分析平台中的3元失效组合的统计数据，具体更新过程与2元失效组合的统计数据相同，这里不再赘述。
此外，上述附图仅是根据本申请示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
在示例性实施例中，还提供了一种电子析设备，包括：至少一个处理器和存储器，所述存储器存储计算机执行指令，所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行上述方法实施例所述的方法。
在示例性实施例中，还提供了一种包括指令的非临时性计算机可读存储介质，所述非临时性计算机可读存储介质可以是ROM、随机存取存储器(RAM)、CD-ROM、磁带、软盘和光数据存储设备等。当该存储介质中的指令由电子设备的处理器执行时，使得电子设备能够执行上述方法实施例所述的方法。
本申请实施例还提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现如上述方法实施例所述的方法，具体实现方式和技术效果类似，这里不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求书指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (19)

  1. 一种失效位元的修补方案的确定方法，应用于包含多个子域的芯片，所述芯片还包括冗余电路，所述冗余电路用于修补所述子域中的失效位元，其特征在于，包括：
    获取所述芯片的晶圆测试结果，所述晶圆测试结果中包括所述芯片中的失效位元的位置信息，所述芯片中的失效位元包括所述子域中的失效位元和所述冗余电路中的失效位元；
    确定修补所述晶圆测试结果中的所述子域中的目标失效位元的可用冗余电路；
    从预先获取的冗余电路的可靠性列表中获取所述可用冗余电路的可靠性值，所述冗余电路的可靠性列表中包括多个冗余电路的可靠性值；
    根据所述可用冗余电路的可靠性值确定所述目标失效位元的修补方案。
  2. 根据权利要求1所述的失效位元的修补方案的确定方法，其特征在于，所述从预先获取的冗余电路的可靠性列表中获取所述可用冗余电路的可靠性值之前，还包括：
    建立所述冗余电路的可靠性列表。
  3. 根据权利要求2所述的失效位元的修补方案的确定方法，其特征在于，所述建立所述冗余电路的可靠性列表，包括：
    根据数据库中存储的所述芯片中的失效单元的测试数据以及已经检测到的失效模式的统计数据，确定所述芯片中的每个冗余电路的可靠性值，其中，所述失效模式的统计数据中包括多个失效组合的标识和失效组合的总发生次数，所述失效组合由新失效位元所在的冗余电路以及所述新失效位元所在的冗余电路的统计范围内的至少一个失效位元组成，所述芯片中的失效位元测试数据中包括多个晶圆测试结果；
    将所述芯片中的每个冗余电路的可靠性值存储到所述冗余电路的可靠性列表中。
  4. 根据权利要求3所述的失效位元的修补方案的确定方法，其特征在于，所述根据数据库中存储的所述芯片中的失效单元的测试数据以及已经检测到的失效模式的统计数据，确定所述芯片中的每个冗余电路的可靠性值，包括：
    根据所述失效单元的测试数据判断所述芯片中的当前冗余电路是否存在失效位元；
    若所述当前冗余电路中存在失效位元，则确定所述当前冗余电路的可靠性值；
    若所述当前冗余电路中不存在失效位元，则初始化n的取值为2，确定所述当前冗余电路的n元失效组合并获取n元失效模式的统计数据，所述当前冗余电路的n元失效组合由所述当前冗余电路以及所述当前冗余电路的统计范围内的至少一个失效位元组成；
    根据所述当前冗余电路的n元失效组合和所述n元失效模式的统计数据，计算所述当前冗余电路的n元不可靠值；
    当所述当前冗余电路的n元不可靠值等于最大值时，则确定所述当前冗余电路的可靠性值；
    当所述当前冗余电路的n元不可靠值小于最大值时，将n加1，判断n是否大于m，m为n的最大取值；
    当n不大于m时，返回执行确定所述当前冗余电路的n元失效组合并获取n元失效模 式的统计数据的步骤；
    当n大于m时，根据所述当前冗余电路的m-1个n元不可靠值确定所述当前冗余电路的可靠性值。
  5. 根据权利要求4所述的失效位元的修补方案的确定方法，其特征在于，所述当前冗余电路的n元失效组合中包括多个n元的失效组合，所述根据所述当前冗余电路的n元失效组合和所述n元失效模式的统计数据，计算所述当前冗余电路的n元不可靠值，包括：
    针对所述当前冗余电路的第i个n元失效组合，当所述第i个n元失效组合属于所述n元失效模式时，则确定所述第i个n元失效组合的不可靠性最大，当所述第i个n元失效组合不属于所述n元失效模式时，则根据以下公式计算所述第i个n元失效组合的不可靠性：f n(x i,q i)＝q i×max(q) -1，其中，x i表示第i个n元失效组合，q i表示所述第i个n元失效组合的总出现次数，max(q)表示所述当前冗余电路的多个n元失效组合的总出现次数中的最大值；
    取所述当前冗余电路的n元失效组合的不可靠值的总和以及不可靠值的最大值中的较大值作为所述当前冗余电路的n元不可靠值。
  6. 根据权利要求4或5所述的失效位元的修补方案的确定方法，其特征在于，所述根据所述当前冗余电路的m-1个n元不可靠值确定所述当前冗余电路的可靠性值，包括：
    根据以下公式计算所述当前冗余电路的可靠性值M：
    Figure PCTCN2021100004-appb-100001
    其中，L表示所述当前冗余电路的n元不可靠值。
  7. 根据权利要求4或5所述的失效位元的修补方案的确定方法，其特征在于，所述方法还包括：
    从数据库中获取n元失效组合的统计数据，所述n元失效组合的统计数据中包括各失效组合的标识以及失效组合的总发生次数；
    根据所述n元失效组合的统计数据，确定所述n元失效组合对应的n元失效模式。
  8. 根据权利要求7所述的失效位元的修补方案的确定方法，其特征在于，所述根据所述n元失效组合的统计数据，确定所述n元失效组合对应的n元失效模式，包括：
    获取第一门限值；
    确定总出现次数大于所述第一门限值的失效组合为所述n元失效组合对应的n元失效模式。
  9. 根据权利要求8所述的失效位元的修补方案的确定方法，其特征在于，所述获取第一门限值包括：
    按照所述n元失效组合中的各个失效组合的总出现次数从大到小对所述n元失效组合进行排序；
    对排序后的失效组合组成的序列进行微分，得到微分序列；
    获取所述微分序列中的最大值所在的位置，所述最大值所在的位置处的总出现次数为 所述第一门限值。
  10. 根据权利要求7所述的失效位元的修补方案的确定方法，其特征在于，所述从数据库中获取n元失效组合的统计数据之前，还包括：
    获取n元失效组合的组合数据，所述n元失效组合的组合数据中包括组成失效组合的冗余电路和冗余电路的统计范围内的失效位元的位置关系，以及冗余电路的类型；
    从所述n元失效组合的组合数据中获取各失效组合的出现次数；
    根据所述各失效组合的出现次数更新所述n元失效组合的统计数据。
  11. 根据权利要求10所述的失效位元的修补方案的确定方法，其特征在于，所述获取n元失效组合的组合数据，包括：
    从所述芯片的新失效单元的测试数据中，获取未检测过的目标新失效单元的信息，所述目标新失效单元的信息包括所述目标新失效单元所在的目标冗余电路的类型和位置信息，所述新失效单元测试数据中包括多个芯片的冗余电路中发生的新失效单元的信息，所述新失效单元的信息包括新失效单元所在的冗余电路的类型和位置信息；
    根据所述失效单元的测试数据确定所述目标新失效单元所在的目标冗余电路的分析范围内的失效单元；
    使用所述目标新失效单元和所述目标冗余电路的分析范围内的失效单元组成所述n元失效组合，其中，所述n元失效组合包括所述目标新失效单元和n-1个失效单元。
  12. 根据权利要求11所述的失效位元的修补方案的确定方法，其特征在于，当所述目标冗余电路为冗余字线时，所述目标冗余电路的分析范围为所述目标冗余电路所属的目标全域以及所述目标全域的相邻全域，其中，位于字线方向上的多个连续子域构成所述芯片的一个全域。
  13. 根据权利要求11所述的失效位元的修补方案的确定方法，其特征在于，当所述目标冗余电路为冗余位线时，所述目标冗余电路的分析范围为所述目标冗余电路所属的目标子域以及所述目标子域的相邻子域，其中，位于字线方向上的多个连续子域构成所述芯片的一个全域。
  14. 根据权利要求1所述的失效位元的修补方案的确定方法，其特征在于，当所述目标失效位元的可用冗余电路为多个时，所述目标失效位元所述根据所述可用冗余电路的可靠性值确定所述目标失效位元的修补方案，包括：
    所述根据所述可用冗余电路的可靠性值，从多个可用冗余电路中选择可靠性值最高的可用冗余电路对所述目标失效位元进行修补。
  15. 根据权利要求14所述的失效位元的修补方案的确定方法，其特征在于，所述冗余电路的可靠性值的取值为大于等于0且小于等于1，其中，可靠性值越大说明冗余电路越可靠。
  16. 根据权利要求1所述的失效位元的修补方案的确定方法，其特征在于，所述确定修补所述晶圆测试结果中的所述子域中的目标失效位元的可用冗余电路，包括：
    根据所述目标失效位元的位置，以及所述芯片中剩余未被分配的冗余电路的数量和类型，确定修补所述目标失效位元的可用冗余电路。
  17. 一种电子设备，其特征在于，包括处理器和存储器；其中，
    所述存储器，用于存储程序代码；
    所述处理器，用于调用所述存储器中所存储的程度代码，执行权利要求1～13中任一项所述的方法。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当该指令在计算机上运行时，使得计算机执行权利要求1～13中任一项所述的方法。
  19. 一种计算机程序，其特征在于，包括程序代码，当计算机运行所述计算机程序时，所述程序代码执行如权利要求1～13任一项所述的方法。
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