WO2022213844A1

WO2022213844A1 - Sigma-delta analog-to-digital converter and control method thereof

Info

Publication number: WO2022213844A1
Application number: PCT/CN2022/083620
Authority: WO
Inventors: 斯高腾彼得
Original assignee: 大唐恩智浦半导体（徐州）有限公司
Priority date: 2021-04-08
Filing date: 2022-03-29
Publication date: 2022-10-13
Also published as: JP2024512929A; CN115208400A

Abstract

A sigma-delta analog-to-digital converter and a control method thereof. The sigma-delta analog-to-digital converter comprises an integration unit and a comparison unit. The integration unit has a fixed first reference signal. The comparison unit has a variable second reference signal. The amplitude of the second reference signal is directly proportional to the amplitude of an input analog signal of the analog-to-digital converter. The variable second reference signal is provided for the comparison unit, so that the analog-to-digital converter has a larger swing space, which can reduce a power supply voltage and reduce the size of a capacitor, thereby reducing the area required by the analog-to-digital converter.

Description

Sigma-Delta analog-to-digital converter and its control method

technical field

The invention relates to the technical field of electronic circuits, in particular to a Sigma-Delta analog-to-digital converter and a control method thereof.

Background technique

Sigma-Delta analog-to-digital converter (ADC, Analog Digital Converter) is a widely used high-precision analog-to-digital converter. The Sigma-Delta analog-to-digital converter adopts technologies such as oversampling, noise shaping and digital filtering, which have the advantages of high precision and low power consumption.

FIG. 1A is a schematic structural diagram of a Sigma-Delta analog-to-digital converter. A sigma-delta analog-to-digital converter generally includes two components, a sigma-delta modulator 110 and a digital filter 120 . The Sigma-Delta modulator 110 oversamples the analog input signal Input at a speed much higher than the Nyquist sampling rate, and outputs a bit stream (Bit Stream) of one bit. The density of "1" in the bit stream corresponds to the size of the analog input signal Input. The digital filter 120 filters the bit stream to obtain a very high conversion resolution.

FIG. 1B is a schematic structural diagram of a first-order Sigma-Delta modulator. The Sigma-Delta modulator may consist of an integrator 111 and a comparator 112 . The integrator 111 includes an operational amplifier OA1 (Operational Amplifier, OA) and a capacitor C1. The input current signal Iinput is connected to one input terminal of the operational amplifier OA1, and provides a channel of input voltage V1 to the operational amplifier OA1. The reference voltage Vref is connected to the other input terminal of the operational amplifier OA1. The output terminal of the operational amplifier OA1 is connected to an input terminal of the comparator 112 , and the output signal 114 of the operational amplifier OA1 is used as an input signal of the comparator 112 . The reference voltage Vref is also connected to another input terminal of the comparator 112 , and the reference voltage Vref is used as another input signal of the comparator 112 . The comparator 112 is used to compare the output signal 114 with the reference voltage Vref, and outputs a bit stream signal 115 at the output. The output end of the comparator 112 is connected to one end of the switch-mode current source J1, and the switch-mode current source J1 is also connected to the input current signal Iinput to form a feedback loop for adjusting according to the bit stream signal 115 output by the comparator 112 The magnitude of the input voltage V1.

FIG. 1C is a partial signal waveform diagram of the Sigma-Delta modulator shown in FIG. 1B in a working state. The

broken lines

131 and 132 are used to represent the voltage waveform of the output signal 114 of the operational amplifier OA1 ; the

square waves

141 and 142 are used to represent the bit stream signal 115 output by the comparator 112 . The rising segment and the falling segment in the

broken lines

131 and 132 correspond to the charging process and the discharging process of the capacitor C1, respectively. A high level in the

square waves

141 , 142 represents a digital "1" in the bitstream signal 115 and a low level represents a digital "0" in the bitstream signal 115 . The duty cycle (duty-cycle) of the bit stream signal 115 refers to the proportion of the number “1” in the whole cycle in one cycle. The duty cycle of the square wave 141 is relatively small, and the duty cycle of the square wave 142 is relatively large. When the input voltage V1 is low, the output signal 114 of the operational amplifier OA1 is represented by the broken line 131 and corresponds to the bit stream signal 141; when the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is represented by the broken line 132 and corresponds to the bit stream signal 141 Stream signal 142 .

Also shown in FIG. 1C are the supply voltage level Vdd and the common ground level Vss in the circuit of the Sigma-Delta modulator. Referring to FIG. 1C , when the input voltage V1 is low, the output signal 114 of the operational amplifier OA1 is relatively close to the system voltage level Vdd, and the gap M1 between the peak point 133 of the broken line 131 and the power supply voltage level Vdd is small, the gap M1 It can also be called the supply margin; when the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is relatively close to the common ground level Vss, and the gap between the valley point 134 of the broken line 132 and the common ground level Vss M2 is relatively small, and the gap M2 can also be referred to as the ground margin.

According to the Sigma-Delta modulator shown in FIGS. 1A-1C, the power supply margin and ground margin of the output signal 114 of the operational amplifier OA1 are relatively small, that is, the voltage swing allowed by the Sigma-Delta ADC The frame space is small. The voltage swing is limited to the voltage swing space of Vdd-Vref or Vref-Vss. The small voltage swing headroom limits the normal operation of the operational amplifier OA1. The smaller voltage swing space also limits the value of the capacitor C1 in the integrator 111 to not be too large.

However, in order to make the analog-to-digital converter have a higher signal-to-noise ratio, the value of the capacitor C1 should not be too small. However, the large capacitance will affect the accuracy of the integrator for the limited voltage swing space, and will also occupy a large chip area and increase the power consumption of the circuit. Therefore, it is desirable for the analog-to-digital converter to have a larger swing space and to reduce the size of the capacitor C1.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a Sigma-Delta analog-to-digital converter with increased swing space and a control method thereof.

The technical solution adopted by the present invention to solve the above technical problem is a Sigma-Delta analog-to-digital converter, which is characterized in that it includes an integrating unit and a comparing unit, wherein the integrating unit has a fixed first reference signal, and the The comparison unit has a variable second reference signal whose magnitude is proportional to the magnitude of the input analog signal of the analog-to-digital converter.

In an embodiment of the present invention, the integration unit has a first integration input terminal, a second integration input terminal and an integration output terminal, the integration input signal is connected to the first integration input terminal, and the first reference signal connected to the second integral input end, a first capacitor is connected between the first integral input end and the integral output end; and the comparison unit has a first comparison input end and a second comparison input end and a comparison output terminal, the integration output terminal is connected to the first comparison input terminal, the second reference signal is connected to the second comparison input terminal, and the comparison output terminal outputs a bit stream signal; wherein, The magnitude of the integrated input signal is increased or decreased in accordance with the bitstream signal.

In an embodiment of the present invention, a feedback unit is further included, which is connected to the comparison output terminal, and the feedback unit controls the amplitude of the integrated input signal according to the bit stream signal.

In an embodiment of the present invention, when the bit stream signal is 1, the amplitude of the integrated input signal decreases, and the amplitude of the second reference signal decreases; when the bit stream signal is 0 When , the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.

In an embodiment of the present invention, the feedback unit includes a switch-mode current source connected to the input analog signal, and when the bit stream signal is 1, the switch-mode current source is turned on to make the integral The amplitude of the input signal decreases; when the bit stream signal is 0, the switch-mode current source is turned off, so that the amplitude of the integrated input signal increases.

In an embodiment of the present invention, it further includes: a second reference signal generating circuit, including a first impedance and a current source, a first end of the first impedance is connected to the current source, and a first end of the first impedance is connected to the current source. The second terminal is connected to the switch mode current source, and the first terminal provides the second reference signal.

In an embodiment of the present invention, the first impedance includes a nonlinear impedance element.

In order to solve the above technical problem, the present invention also proposes a control method for a Sigma-Delta analog-to-digital converter, wherein the analog-to-digital converter includes an integrating unit and a comparing unit, and is characterized in that it includes: providing a fixed first number to the integrating unit. a reference signal; and a variable second reference signal is provided to the comparison unit, the amplitude of the second reference signal is proportional to the amplitude of the input analog signal of the analog-to-digital converter.

According to the Sigma-Delta analog-to-digital converter and the control method thereof of the present invention, a variable second reference signal is provided for the comparison unit, so that the analog-to-digital converter has a larger swing space. This larger swing headroom allows both supply voltage reduction and capacitor size reduction, thereby reducing the area required for the analog-to-digital conversion circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

1A is a schematic structural diagram of a Sigma-Delta analog-to-digital converter;

1B is a schematic structural diagram of a first-order Sigma-Delta modulator;

Fig. 1C is a partial signal waveform diagram of the Sigma-Delta modulator shown in Fig. 1B in a working state;

2 is a schematic structural diagram of a Sigma-Delta analog-to-digital converter according to an embodiment of the present invention;

3 is a schematic structural diagram of a Sigma-Delta analog-to-digital converter according to another embodiment of the present invention;

FIG. 4 is a partial signal waveform diagram of the Sigma-Delta analog-to-digital converter of the embodiment shown in FIG. 3 in a working state;

FIG. 5 is an exemplary flowchart of a control method of a Sigma-Delta analog-to-digital converter according to an embodiment of the present invention.

Preferred Embodiments of the Invention

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways than those described herein, and thus the present invention is not limited by the specific embodiments disclosed below.

As shown in this application and in the claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. In general, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

In the description of this application, it should be understood that the orientations indicated by the orientation words such as "front, rear, top, bottom, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" etc. Or the positional relationship is usually based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and these orientations do not indicate or imply the indicated device or element unless otherwise stated. It must have a specific orientation or be constructed and operated in a specific orientation, so it cannot be construed as a limitation on the protection scope of the application; the orientation words "inside and outside" refer to the inside and outside relative to the contour of each component itself.

In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood to limit the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and common terms, some terms mentioned in the specification of this application may be chosen by the applicant at his or her judgment, and the detailed meanings of which are set forth herein. described in the relevant section of the description. Furthermore, it is required that the application be understood not only by the actual terms used, but also by the meaning implied by each term.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to," or "contacting" another element, it can be directly between the other element on, connected to or coupled to, or in contact with the other component, or an intervening component may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly in contact with" another element, there are no intervening elements present. Likewise, when a first component is referred to as being "in electrical contact" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow, even without direct contact between conductive components.

Flow diagrams are used in this application to illustrate operations performed by a system according to an embodiment of the application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Rather, the various steps may be processed in reverse order or concurrently. At the same time, other actions are either added to these processes, or a step or steps are removed from these processes.

FIG. 2 is a schematic structural diagram of a Sigma-Delta analog-to-digital converter according to an embodiment of the present invention. Referring to FIG. 2 , the Sigma-Delta analog-to-digital converter 200 (hereinafter referred to as “analog-to-digital converter”) in this embodiment includes: an integrating unit 210 and a comparing unit 220, wherein the integrating unit 210 has a fixed first For the reference signal Vref1 , the comparison unit 220 has a variable second reference signal Vref2 , and the amplitude of the second reference signal Vref2 is proportional to the amplitude of the input analog signal Input of the analog-to-digital converter 200 .

Referring to FIG. 1A , according to the function of the Sigma-Delta analog-to-digital converter, the analog-to-digital converter 200 can output a bit stream signal at the output end 221 of the comparison unit 220 according to the input analog signal Input.

Referring to FIG. 2 , the first reference signal Vref1 has a fixed amplitude. The function of the first reference signal Vref1 to the integrating unit 210 is the same as the function of the reference signal Vref shown in FIG. 1B to the integrator 111 .

Referring to FIG. 2 , the amplitude of the second reference signal Vref2 may change proportionally with the amplitude of the input analog signal Input, that is, when the amplitude of the input analog signal Input increases, the amplitude of the second reference signal Vref2 The amplitude also increases. When the amplitude of the input analog signal Input decreases, the amplitude of the second reference signal Vref2 also decreases.

What is shown in FIG. 2 is only an example, and is not used to limit the specific implementation of how to make the second reference signal Vref2 change with the change of the input analog signal Input. Those skilled in the art can use any method to make the amplitude of the second reference signal Vref2 proportional to the amplitude of the input analog signal Input of the analog-to-digital converter 200 in any manner.

The present invention does not limit the specific electrical signals of the input analog signal Input, the first reference signal Vref1 and the second reference signal Vref2, which may be a current signal or a voltage signal. Unless otherwise specified, the magnitude or level of the signal mentioned in this specification refers to the magnitude of the signal, for the current signal it refers to the magnitude of the current, and for the voltage signal it refers to the magnitude of the voltage.

According to the analog-to-digital converter 200 shown in FIG. 2 , a larger second reference signal Vref2 is used for a larger or higher input analog signal Input, and a smaller second reference signal Vref2 is used for a smaller or lower input analog signal Input The reference signal Vref2 can increase the swing space of the analog-to-digital converter 200 . On this basis, a larger capacitor, such as the first capacitor C1 , can be used in the integration unit 210 to improve the overall performance of the analog-to-digital converter 200 .

FIG. 3 is a schematic structural diagram of a Sigma-Delta analog-to-digital converter according to another embodiment of the present invention. Referring to FIG. 3, the analog-to-digital converter 300 includes an integrating unit 310 and a comparing unit 320, wherein the integrating unit 310 has a first integrating input end 311, a second integrating input end 312 and an integrating output end 313, and integrates the input signal V1 is connected to the first integration input terminal 311, the first reference signal Vref1 is connected to the second integration input terminal 312, and a first capacitor C1 is connected between the first integration input terminal 311 and the integration output terminal 313; the comparison unit 320 has The first comparison input terminal 321, the second comparison input terminal 322 and the comparison output terminal 323, the integral output terminal 313 is connected to the first comparison input terminal 321, the second reference signal Vref2 is connected to the second comparison input terminal 322, and the comparison output terminal The terminal 323 outputs the bit stream signal BS; wherein the amplitude of the integrated input signal V1 increases or decreases according to the bit stream signal BS.

In a preferred embodiment, the integrated input signal V1, the first reference signal Vref1 and the second reference signal Vref2 are all voltage signals, and the input analog signal Input is a current signal.

The amplitude of the integrated input signal V1 is simultaneously affected by the input analog signal Input and the bit stream signal BS. When the input analog signal Input is a current signal, the amplitude of the integrated input signal V1 gradually increases with the input of the input analog signal Input. The first reference signal Vref1 with a fixed amplitude is used as one input signal of the integrating unit 310 , and the integrated input signal V1 is used as another input signal of the integrating unit 310 . According to the function of the integration unit 310, when V1>Vref1, the integration output signal V2 of the integration output terminal 313 of the integration unit 310 will decrease to prevent the integration input signal V1 from continuing to increase.

When the integration output signal V2<Vref2 of the integration unit 310, the comparison unit 320 outputs a high level, that is, the bit stream signal BS=1. When the integrated output signal V2>Vref2 of the integrating unit 310, the comparing unit 320 outputs a low level, that is, the bit stream signal BS=0.

Referring to FIG. 3 , in some embodiments, the analog-to-digital converter 300 of the present invention further includes a feedback unit 330, which can control the amplitude of the integrated input signal V1 according to the bit stream signal BS.

In some embodiments, when the bit stream signal BS=1, the amplitude of the integrated input signal V1 decreases, and the amplitude of the second reference signal Vref2 decreases; when the bit stream signal BS=0, the amplitude of the integrated input signal V1 decreases. As the amplitude increases, the amplitude of the second reference signal Vref2 increases.

The present invention does not limit the specific implementation of the feedback unit 330 .

Referring to FIG. 3 , in some embodiments, the feedback unit 330 includes a switch-mode current source J1 connected to the input analog signal Input. When the bit stream signal BS is 1, the switch-mode current source J1 is turned on to integrate the input signal The amplitude of V1 decreases; when the bit stream signal BS is 0, the switch mode current source J1 is turned off, so that the amplitude of the integral input signal V1 increases.

Referring to FIG. 3 , the switch-mode current source J1 includes three terminals A, B, and C. As shown in FIG. The input analog signal Input is connected to the terminal A, the bit stream signal BS is connected to the terminal C, and the terminal C is connected to the common ground level Vss. The working principle of the feedback unit 330 will be described below.

Assuming that in the initial state, the switch-mode current source J1 is in a closed state, and the integral input signal V1 gradually increases with the input of the input analog signal Input. When V1>Vref1, the integral output signal V2 decreases. When V2<Vref2, the comparison unit 320 outputs a high level, that is, the bit stream signal BS=1. At this time, the switch-mode current source J1 is turned on, causing the integral input signal V1 to be pulled low. When V1<Vref1, the integrated output signal V2 increases. When V2>Vref2, the comparison unit 320 outputs a low level, that is, the bit stream signal BS=0. At this time, the switch-mode current source J1 is turned off, and the amplitude of the integrated input signal V1 is gradually increased again.

In this way, in the working state of the analog-to-digital converter 300 of the present invention, according to the working principle of the control loop described above, the bit stream signal BS output by the comparison unit 320 changes according to the amplitude of the integrated input signal V1, and the bit stream The duty cycle of the signal BS corresponds to the variation law of the integrated input signal V1.

FIG. 4 is a partial signal waveform diagram of a Sigma-Delta analog-to-digital converter in a working state according to an embodiment of the present invention. This part of the signal corresponds to the analog-to-digital converter 300 shown in FIG. 3 .

Referring to FIG. 4 , the

broken lines

411 and 412 represent the integration output signal V2 output by the integration output terminal 313 of the integration unit 310 ; the

square waves

421 and 422 represent the bit stream signal BS output by the comparison output terminal 323 of the comparison unit 320 ; The two dotted lines respectively correspond to the second reference signals Vref2 of two different sizes. The rising segment and the falling segment in the

broken lines

411 and 412 correspond to the charging process and the discharging process of the first capacitor C1, respectively. The broken line 411 corresponds to the case where the integrated input signal V1 is small, and the second reference signal Vref2 is also smaller at this time; the broken line 412 corresponds to the case where the integrated input signal V1 is larger, and the second reference signal Vref2 is also smaller at this time. big.

The high level in the

square waves

421 and 422 represents the digital "1" in the bit stream signal BS, and the low level represents the digital "0" in the bit stream signal BS. The duty cycle (duty-cycle) of the bit stream signal BS refers to the proportion of the number "1" in the whole cycle in one cycle, the duty cycle of the square wave 421 is relatively small, and the duty cycle of the square wave 422 is relatively large.

Also shown in FIG. 4 are the supply voltage level Vdd and the common ground level Vss. Referring to the broken line 411 in FIG. 4 , when the integrated input signal V1 is small, since the second reference voltage Vref2 is also small, the integrated output signal V2 is located in the middle position between Vdd and Vss as a whole, and the peak point 413 of the broken line 411 is the same as the one shown in FIG. The power supply margin between the power supply voltage levels Vdd is M3; when the integrated input signal V1 is large, since the second reference voltage Vref2 is also large, the integrated output signal V2 is still located in the middle position between Vdd and Vss as a whole, the broken line 412 The ground margin between the valley point 414 and the common ground level Vss is M4. Comparing FIG. 4 and FIG. 1C , it is obvious that the analog-to-digital converter 300 of the present invention enables the integrated output signal V2 to have a large power supply margin and a grounding margin, so that the analog-to-digital converter 300 has a large swing space. The larger swing space enables the analog-to-digital converter 300 of the present invention not only to reduce its supply voltage, but also to reduce the size of the first capacitor C1, thereby reducing the occupied area of the entire analog-to-digital converter 300 on the chip. In some cases, when the voltage swing space is doubled, the size of the first capacitor C1 may be half of the original size.

Referring to FIG. 3 , in some embodiments, the analog-to-digital converter 300 of the present invention further includes a second reference signal generating circuit 340, including a first impedance R1 and a current source J2, and the first end 341 of the first impedance R1 is connected to The current source J2 is connected, the second terminal 342 of the first impedance R1 is connected to the switch mode current source J1, and the first terminal 341 provides the second reference signal Vref2.

As shown in FIG. 3, the second end 342 of the first impedance R1 is connected to the terminal B of the switch mode current source J1. Therefore, the second reference signal Vref2 can vary with the variation of the integrated input signal V1. When the integration input signal V1 is larger, the second reference signal Vref2 is also larger; when the integration input signal V1 is smaller, the second reference signal Vref2 is also smaller.

The present invention does not limit the type of the current source J2. In some embodiments, current source J2 and switch-mode current source J1 are the same type of current source.

The present invention does not limit the type and size of the first impedance R1. The first impedance R1 may be an impedance element such as a resistance, an inductance, a capacitance, or the like, or an impedance network composed of a plurality of various impedance elements.

In a preferred embodiment, the first impedance R1 comprises a non-linear impedance element with non-linear characteristics. In this way, it can be avoided that the second reference signal Vref2 is too small to affect the bit stream signal BS output by the comparison unit 320 .

The integrating unit 310 in the analog-to-digital converter 300 shown in FIG. 3 includes an integrator, that is, the analog-to-digital converter 300 is a first-order analog-to-digital converter. Referring to FIG. 3 , in some embodiments, a plurality of integrating units 350 may be further included between the integrating unit 310 and the comparing unit 320 , and the number of the integrating units connected in series determines the order of the analog-to-digital converter 300 . The number of integrating units 350 can be set as required. In these embodiments, the first reference voltage Vref1 serves as a reference signal for a plurality of integration units at the same time.

FIG. 5 is an exemplary flowchart of a control method of a Sigma-Delta analog-to-digital converter according to an embodiment of the present invention. The analog-to-digital converter controlled by the control method of the embodiment of the present invention should include the integration unit and the comparison unit as described above. Referring to Figure 5, the control method of this embodiment includes the following steps:

Step S510: providing a fixed first reference signal to the integrating unit; and

Step S520: Provide a variable second reference signal to the comparison unit, the amplitude of the second reference signal is proportional to the amplitude of the input analog signal of the analog-to-digital converter.

The control method of the present invention can be implemented by the analog-to-digital converter described above, so the foregoing description and accompanying drawings can be used to illustrate the control method of the present invention.

The control method of the present invention can also be performed by other control circuits and analog-to-digital converters.

As mentioned above, in some embodiments, the integration unit has a first integration input terminal, a second integration input terminal, and an integration output terminal, the integration input signal is connected to the first integration input terminal, and the first reference signal is connected to the second integration terminal. The input terminals are connected, and a first capacitor is connected between the first integration input terminal and the integration output terminal; and the comparison unit has a first comparison input terminal, a second comparison input terminal and a comparison output terminal, and the integration output terminal is connected to the first comparison input terminal. A comparison input terminal is connected, the second reference signal is connected to the second comparison input terminal, and the comparison output terminal outputs a bit stream signal; wherein, the amplitude of the integral input signal increases or decreases according to the bit stream signal. In some embodiments, when the bit stream signal is 1, the amplitude of the integrated input signal decreases, and the amplitude of the second reference signal decreases; when the bit stream signal is 0, the amplitude of the integrated input signal increases, The amplitude of the second reference signal increases.

According to the control method of the present invention, a variable second reference signal is provided for the comparison unit, so that the analog-to-digital converter has a larger swing space. This larger swing headroom allows both supply voltage reduction and capacitor size reduction, thereby reducing the area required for the analog-to-digital conversion circuit.

The basic concept has been described above. Obviously, for those skilled in the art, the above disclosure of the invention is only an example, and does not constitute a limitation to the present application. Although not explicitly described herein, various modifications, improvements, and corrections to this application may occur to those skilled in the art. Such modifications, improvements, and corrections are suggested in this application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of this application.

Meanwhile, the present application uses specific words to describe the embodiments of the present application. Such as "one embodiment," "an embodiment," and/or "some embodiments" means a certain feature, structure, or characteristic associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in different places in this specification are not necessarily referring to the same embodiment . Furthermore, certain features, structures or characteristics of the one or more embodiments of the present application may be combined as appropriate.

Some examples use numbers to describe quantities of ingredients and attributes, it should be understood that such numbers used to describe the examples, in some examples, use the modifiers "about", "approximately" or "substantially" to retouch. Unless stated otherwise, "about", "approximately" or "substantially" means that a variation of ±20% is allowed for the stated number. Accordingly, in some embodiments, the numerical parameters set forth in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and use a general digit reservation method. Notwithstanding that the numerical fields and parameters used in some embodiments of the present application to confirm the breadth of their ranges are approximations, in particular embodiments such numerical values are set as precisely as practicable.

Claims

A Sigma-Delta analog-to-digital converter, characterized in that it includes an integrating unit and a comparing unit, wherein the integrating unit has a fixed first reference signal, the comparing unit has a variable second reference signal, and the The magnitude of the second reference signal is proportional to the magnitude of the input analog signal of the analog-to-digital converter.
The analog-to-digital converter according to claim 1, wherein the integration unit has a first integration input terminal, a second integration input terminal and an integration output terminal, and the integration input signal is connected to the first integration input terminal , the first reference signal is connected to the second integral input end, and a first capacitor is connected between the first integral input end and the integral output end; and

The comparison unit has a first comparison input terminal, a second comparison input terminal and a comparison output terminal, the integration output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal. The terminals are connected to each other, and the comparison output terminal outputs a bit stream signal;

Wherein, the amplitude of the integrated input signal is increased or decreased according to the bit stream signal.
The analog-to-digital converter of claim 2, further comprising a feedback unit connected to the comparison output terminal, and the feedback unit controls the amplitude of the integrated input signal according to the bit stream signal.
The analog-to-digital converter according to claim 2, wherein when the bit stream signal is 1, the amplitude of the integrated input signal decreases, and the amplitude of the second reference signal decreases; when When the bit stream signal is 0, the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.
The analog-to-digital converter of claim 3, wherein the feedback unit comprises a switch-mode current source connected to the input analog signal, and when the bit stream signal is 1, the switch-mode current source When the source is turned on, the amplitude of the integrated input signal decreases; when the bit stream signal is 0, the switch-mode current source is turned off, so that the amplitude of the integrated input signal increases.
The analog-to-digital converter of claim 5, further comprising: a second reference signal generating circuit, comprising a first impedance and a current source, a first end of the first impedance being connected to the current source , the second end of the first impedance is connected to the switch mode current source, and the first end provides the second reference signal.
7. The analog-to-digital converter of claim 6, wherein the first impedance comprises a non-linear impedance element.
A control method for a Sigma-Delta analog-to-digital converter, the analog-to-digital converter comprising an integrating unit and a comparison unit, characterized in that, comprising:

providing a fixed first reference signal to the integrating unit; and

A variable second reference signal is provided to the comparison unit, the magnitude of the second reference signal being proportional to the magnitude of the input analog signal of the analog-to-digital converter.
The control method according to claim 8, wherein the integrating unit has a first integrating input end, a second integrating input end and an integrating output end, the integrating input signal is connected to the first integrating input end, and the first reference signal is connected to the second integral input end, and a first capacitor is connected between the first integral input end and the integral output end; and

The comparison unit has a first comparison input terminal, a second comparison input terminal and a comparison output terminal, the integration output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal. The terminals are connected to each other, and the comparison output terminal outputs a bit stream signal;

Wherein, the amplitude of the integrated input signal is increased or decreased according to the bit stream signal.
The control method according to claim 9, wherein when the bit stream signal is 1, the amplitude of the integrated input signal decreases, and the amplitude of the second reference signal decreases; When the bit stream signal is 0, the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.