JP2024512929A - Sigma-delta analog-to-digital converter and its control method - Google Patents

Abstract

The present invention relates to a sigma-delta analog-to-digital converter and a control method thereof, and the sigma-delta analog-to-digital converter of the present invention includes an integrating unit and a comparison unit, in which the integrating unit has a fixed the comparing unit has a variable second reference signal, the amplitude of the second reference signal being proportional to the amplitude of the input analog signal of the analog-to-digital converter; According to the sigma-delta analog-to-digital converter and its control method of the present invention, a variable second reference signal is provided to the comparison unit, so that the analog-to-digital converter has a larger swing space. This large swing space makes it possible to both reduce power supply voltage and capacitor size, reducing the area required for analog-to-digital conversion circuits.

Description

The present invention relates to the technical field of electronic circuits, and more particularly to a sigma-delta analog-to-digital converter and a method for controlling the same.

The Sigma-Delta analog-to-digital converter (ADC) is a high-precision analog-to-digital converter that has been widely applied. Sigma-Delta analog-to-digital converters employ techniques such as oversampling, noise shaping and digital filtering, and have the advantages of high accuracy and low power consumption.

FIG. 1A is a schematic diagram illustrating the configuration of a type of sigma-delta analog-to-digital converter. A sigma-delta analog-to-digital converter typically includes two components: a sigma-delta modulator 110 and a digital filter 120. The sigma-delta modulator 110 oversamples the analog input signal Input at a rate significantly higher than the Nyquist sampling rate, and outputs a 1-bit bit stream. The density of "1"s in the bitstream corresponds to the magnitude of the analog input signal Input. Digital filter 120 filters the bitstream to obtain very high conversion resolution.

FIG. 1B is a schematic diagram illustrating the configuration of a type of first-order sigma-delta modulator. The sigma-delta modulator can be composed of an integrator 111 and a comparator 112. Among these, the integrator 111 includes an operational amplifier OA1 (Operational Amplifier, OA) and a capacitor C1. The input current signal Iinput is connected to one input terminal of the operational amplifier OA1, and supplies one input voltage V1 to the operational amplifier OA1. A reference voltage Vref is connected to the other input terminal of the operational amplifier OA1. The output terminal of the operational amplifier OA1 is connected to one input terminal of the comparator 112, and the output signal 114 of the operational amplifier OA1 becomes one input signal of the comparator 112. The reference voltage Vref, which is the other input signal of the comparator 112, is also connected to the other input terminal of the comparator 112 at the same time. Comparator 112 compares output signal 114 and reference voltage Vref and outputs bitstream signal 115 to an output terminal. The output terminal of the comparator 112 is connected to one end of the switching mode current source J1 which is also connected to the input current signal Iinput, and is used to adjust the magnitude of the input voltage V1 according to the bitstream signal 115 outputted by the comparator 112. Form a feedback loop.

FIG. 1C is a waveform diagram of some signals that cause the sigma-delta modulator shown in FIG. 1B to be in an operating state. Here, the polygonal lines 131 and 132 are used to represent the voltage waveform of the output signal 114 of the operational amplifier OA1, and the rectangular waves 141 and 142 are used to represent the bitstream signal 115 output from the comparator 112. The rising portions and falling portions of the polygonal lines 131 and 132 correspond to the charging process and discharging process of the capacitor C1, respectively. A high potential in the rectangular waves 141 and 142 represents the number "1" in the bitstream signal 115, and a low potential represents the number "0" in the bitstream signal 115. The duty ratio (duty-cycle) of the bit stream signal 115 is the proportion of the number "1" occupied in all cycles in one cycle, the duty of the square wave 141 is relatively small, and the duty of the square wave 142 is comparatively small. relatively large. When the input voltage V1 is low, the output signal 114 of the operational amplifier OA1 is represented by a polygonal line 131 and corresponds to the bitstream signal 141. When the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is represented by the line 132 and corresponds to the bitstream signal 142.

Also shown in FIG. 1C are the power supply voltage level Vdd and the common ground level Vss in the sigma-delta modulator circuit. As shown in FIG. 1(c), when the input voltage V1 is low, the output signal 114 of the operational amplifier OA1 is relatively close to the system voltage level Vdd, and the peak point 133 of the polygonal line 131 and the power supply voltage level Vdd are close to each other. The difference M1 is relatively small, and the difference M1 can also be called a supply margin. When the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is relatively close to the common ground level Vss, and the difference M2 between the valley point 134 of the polygonal line 132 and the common ground level Vss is relatively small. M2 can also be called a ground margin.

According to the sigma-delta modulator shown in FIGS. 1A-1C, both the supply margin and the ground margin of the output signal 114 of the operational amplifier OA1 are relatively small, i.e., tolerated by the sigma-delta analog-to-digital converter. The voltage swing space is relatively small. The voltage swing is limited to a voltage swing space of Vdd-Vref or Vref-Vss. The normal operation of the operational amplifier OA1 is restricted by the small voltage swing space. Also, due to the smaller voltage swing space, the value of capacitor C1 in integrator 111 is limited from being large.

However, in order to increase the S/N ratio of the analog-to-digital converter, the value of capacitor C1 must not be made small. However, for the limited voltage swing space, a large capacitance will affect the accuracy of the integrator, and also occupy a large chip area and increase the power consumption of the circuit. Therefore, it is desirable to increase the swing space of the analog-to-digital converter and reduce the size of the capacitor C1.

The technical problem to be solved by the present invention is to provide a sigma-delta analog-to-digital converter with increased swing space and a method for controlling the same.

The technical idea adopted by the present invention to solve the above technical problem is a sigma-delta analog-to-digital converter, which comprises an integral unit and a comparison unit, in which the integral unit has a fixed the comparison unit has a variable second reference signal, the amplitude of the second reference signal being proportional to the amplitude of the input analog signal of the analog-to-digital converter; It is characterized by

In one embodiment of the invention, the integration unit includes a first integration input terminal, a second integration input terminal, and an integration output terminal, and the integration input signal is connected to the first integration input terminal. , the first reference signal is connected to the second integral input terminal, a first capacitor is connected between the first integral input terminal and the integral output terminal, and the comparison unit comprises: a first comparison input terminal, a second comparison input terminal, and a comparison output terminal, the integral output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal. The comparison output terminal is connected to a comparison input terminal, and the comparison output terminal outputs a bitstream signal, in which the amplitude of the integral input signal is increased or decreased in accordance with the bitstream signal.

An embodiment of the invention further comprises a feedback unit connected to the comparison output terminal, the feedback unit controlling the amplitude of the integral input signal according to the bitstream signal.

In an embodiment of the invention, when the bitstream signal is 1, the amplitude of the integral input signal is decreased, the amplitude of the second reference signal is decreased, and the bitstream signal is 0. At times, the amplitude of the integral input signal is increasing and the amplitude of the second reference signal is increasing.

In one embodiment of the invention, the feedback unit comprises a switching mode current source connected to the input analog signal, and when the bitstream signal is 1, the switching mode current source is turned on and the integral Decreasing the amplitude of the input signal and increasing the amplitude of the integrated input signal when the bitstream signal is zero, the switching mode current source is turned off.

An embodiment of the present invention further includes a second reference signal generation circuit including a first impedance and a current source, a first end of the first impedance is connected to the current source, and the first A second end of the impedance is connected to the switched mode current source, and the first end provides the second reference signal.

In one embodiment of the invention, the first impedance comprises a non-linear impedance element.

The technical idea proposed by the present invention in order to solve the above technical problem is a control method for a sigma-delta analog-to-digital converter comprising an integral unit and a comparison unit, the first providing a reference signal; and providing the comparison unit with a variable second reference signal having an amplitude proportional to the amplitude of the input analog signal of the analog-to-digital converter. do.

In one embodiment of the invention, the integration unit includes a first integration input terminal, a second integration input terminal, and an integration output terminal, and the integration input signal is connected to the first integration input terminal. , the first reference signal is connected to the second integral input terminal, a first capacitor is connected between the first integral input terminal and the integral output terminal, and the comparison unit comprises: a first comparison input terminal, a second comparison input terminal, and a comparison output terminal, the integral output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal. The comparison output terminal is connected to a comparison input terminal, and the comparison output terminal outputs a bitstream signal, in which the amplitude of the integral input signal is increased or decreased in accordance with the bitstream signal.

In an embodiment of the invention, when the bitstream signal is 1, the amplitude of the integral input signal is decreased, the amplitude of the second reference signal is decreased, and the bitstream signal is 0. At times, the amplitude of the integral input signal is increasing and the amplitude of the second reference signal is increasing.

According to the sigma-delta analog-to-digital converter and its control method of the present invention, a variable second reference signal is provided to the comparison unit, so that the analog-to-digital converter has a larger swing space. This large swing space makes it possible to both reduce power supply voltage and capacitor size, reducing the area required for analog-to-digital conversion circuits.

In order to make the above objects, features, and advantages of the present invention more clearly understandable, specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.
FIG. 1A is a schematic diagram illustrating the configuration of a type of sigma-delta analog-to-digital converter. FIG. 1B is a schematic diagram illustrating the configuration of a type of first-order sigma-delta modulator. FIG. 1C is a waveform diagram of some signals that cause the sigma-delta modulator shown in FIG. 1B to be in an operating state. FIG. 2 is a schematic diagram showing the configuration of a sigma-delta analog-to-digital converter according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the configuration of a sigma-delta analog-to-digital converter according to another embodiment of the present invention. FIG. 4 is a waveform diagram of some signals that cause the sigma-delta analog-to-digital converter according to the embodiment shown in FIG. 3 to be in an operating state. FIG. 5 is an exemplary flowchart of a method for controlling a sigma-delta analog-to-digital converter according to an embodiment of the present invention.

In order to make the above objects, features, and advantages of the invention more clearly understandable, specific embodiments of the invention are described in detail below in conjunction with the accompanying drawings.

Although many specific details are set forth in the following description to facilitate a thorough understanding of the invention, the invention may be practiced otherwise than as set forth herein. The invention is not limited to the specific embodiments disclosed below.

As set forth in this application and the claims, unless the context clearly suggests otherwise, terms such as "one," "one," "one," and/or "the" specifically refer to the singular. It does not refer to something, but may include more than one. In general, the terms "comprising" and "comprising" only indicate the inclusion of clearly identified steps and elements, and do not constitute an exclusive enumeration of the method or apparatus. may include other steps or elements.

In the specification of this application, it is to be understood that directional terms such as "front, rear, top, bottom, left, right", "lateral, longitudinal, vertical, horizontal", "top, bottom", etc. The orientations or relationships shown are generally based on the orientations or relationships shown in the drawings, and are only to facilitate and simplify the description of the present application. These orientation terms do not indicate or imply that the designated device or element must have a particular orientation or be constructed or operated in a particular orientation, unless stated to the contrary. Therefore, it cannot be understood as limiting the scope of protection of the present application. The orientation words "inside, outside" refer to the inside and outside of the contour relative to each part itself.

It also needs to be explained that the use of terms such as "first" and "second" to limit parts is simply to make it easier to distinguish between corresponding parts, and there is no need for a separate statement. For example, the above words have no special meaning and cannot be interpreted as limitations on the scope of protection of the present application. Furthermore, although the terms used in this application are selected from known terms, some terms described in the specification of this application may have been selected by the applicant at his/her own discretion. Its detailed meaning is described in the relevant part of this specification. It is also required that the present application be understood not only by the actual terms used, but also by the meanings implied by each term.

When a part is called "on top of another part," "connected to another part," "bonded to another part," or "touching another part," it is directly on top of another part. It should be understood that there may be parts connected, connected, coupled, or in contact with another part, or inserted. In contrast, when a part is referred to as "directly to another part," "directly connected to another part," "directly coupled to another part," or "directly in contact with another part," an inserted part does not exist. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, the relationship between said first component and said second component is There is an electrical path through which current can flow. The electrical path can include capacitors, coupled inductors, and/or other members that can conduct current without direct contact between conductive members.

Flowcharts are used herein to describe operations performed by the system of example embodiments of the present application. It should be understood that the operations above or below are not necessarily performed in exact order. Conversely, the various steps can be processed in reverse order or simultaneously. You can also add other operations to these procedures, or remove one or more step operations from these procedures.

FIG. 2 is a schematic diagram showing the configuration of a sigma-delta analog-to-digital converter according to an embodiment of the present invention. As shown with reference to FIG. 2, the sigma-delta analog-to-digital converter 200 (hereinafter simply referred to as "analog-to-digital converter") of the present embodiment includes an integration unit 210 and a comparison unit 220. Therein, this integrating unit 210 has a fixed first reference signal Vref1, and this comparing unit 220 has a variable first reference signal Vref1 having an amplitude proportional to the amplitude of the input analog signal Input of the analog-to-digital converter 200. It has a second reference signal Vref2.

As shown in FIG. 1A, the analog-to-digital converter 200 outputs a bitstream signal to the output terminal 221 of the comparison unit 220 according to the input analog signal Input using the function of a sigma-delta analog to digital converter. can do.

As shown in FIG. 2, the first reference signal Vref1 has a fixed amplitude. The effect of this first reference signal Vref1 on the integrating section 210 is the same as the effect of the reference signal Vref on the integrator 111 shown in FIG. 1B.

As shown in FIG. 2, the amplitude of the second reference signal Vref2 may change in proportion to the amplitude of the input analog signal Input. That is, as the amplitude of the input analog signal Input increases, the amplitude of the second reference signal Vref2 also increases, and as the amplitude of the input analog signal Input decreases, the amplitude of the second reference signal Vref2 also decreases.

What is shown in FIG. 2 is only an example, and is not intended to limit the specific embodiment of how the second reference signal Vref2 is changed in accordance with changes in the input analog signal Input. Those skilled in the art can make the amplitude of the second reference signal Vref2 proportional to the amplitude of the input analog signal Input of the analog-to-digital converter 200 in any manner based on the idea of the present invention.

The present invention does not specifically limit what kind of electrical signals the input analog signal Input, the first reference signal Vref1, and the second reference signal Vref2 are, and these may be current signals or voltage signals. It may also be a signal. Unless otherwise specified, in this specification, the magnitude or height of a signal means the magnitude of the amplitude of the signal, and for a current signal, it means the amplitude of the current, and for a voltage signal, it means the amplitude of the voltage. are doing.

According to the analog-to-digital converter 200 shown in FIG. 2, a larger second reference signal Vref2 is adopted for a larger or higher input analog signal Input, and a larger second reference signal Vref2 is adopted for a smaller or lower input analog signal Input. By adopting a small second reference signal Vref2, the swing space of the analog-to-digital converter 200 can be increased, based on which a larger capacitor, for example the first capacitor C1, is adopted in the integration unit 210. This makes it possible to improve the overall performance of the analog-to-digital converter 200.

FIG. 3 is a schematic diagram showing the configuration of a sigma-delta analog-to-digital converter according to another embodiment of the present invention. As shown in FIG. 3, the analog-to-digital converter 300 includes an integration unit 310 and a comparison unit 320. Here, the integral unit 310 has a first integral input terminal 311, a second integral input terminal 312, and an integral output terminal 313. The integral input signal V1 is connected to the first integral input terminal 311, the first reference signal Vref1 is connected to the second integral input terminal 312, and the signal is connected between the first integral input terminal 311 and the integral output terminal 313. is connected to the first capacitor C1. Comparison unit 320 has a first comparison input terminal 321 , a second comparison input terminal 322 , and a comparison output terminal 323 . The integral output terminal 313 is connected to the first comparison input terminal 321, the second reference signal Vref2 is connected to the second comparison input terminal 322, and the comparison output terminal 323 outputs the bit stream signal BS. Here, the amplitude of the integral input signal V1 is increased or decreased according to the bitstream signal BS.

In a preferred embodiment, the integral input signal V1, the first reference signal Vref1 and the second reference signal Vref2 are all voltage signals, and the input analog signal Input is a current signal.

The amplitude of the integral input signal V1 is influenced simultaneously by both the input analog signal Input and the bitstream signal BS. When the input analog signal Input is a current signal, the amplitude of the integral input signal V1 gradually increases as the input analog signal Input is input. A first reference signal Vref1 with a fixed amplitude value is used as one input signal of the integration unit 310, and an integral input signal V1 is used as the other input signal of the integration unit 310. Depending on the function of the integration unit 310, if V1>Vref1, the integration output signal V2 at the integration output terminal 313 of the integration unit 310 is reduced to prevent the integration input signal V1 from continuing to increase.

When the integrated output signal V2<Vref2 of the integrating unit 310, the comparing unit 320 outputs a high level, which is the bit stream signal BS=1. When the integral output signal V2>Vref2 of the integrating unit 310, the comparing unit 320 outputs a low level that is the bit stream signal BS=0.

As shown in FIG. 3, in some embodiments, the analog-to-digital converter 300 of the present invention further includes a feedback unit 330 that can control the amplitude of the integral input signal V1 according to the bitstream signal BS.

In some embodiments, when the bitstream signal BS=1, the amplitude of the integral input signal V1 is decreased and the amplitude of the second reference signal Vref2 is decreased. If the bitstream signal BS=0, the amplitude of the integral input signal V1 has increased and the amplitude of the second reference signal Vref2 has increased.

The present invention does not limit the specific embodiment of feedback unit 330.

As shown in FIG. 3, in some embodiments, feedback unit 330 includes a switched mode current source J1 connected to the input analog signal Input. When bitstream signal BS is 1, switch mode current source J1 is turned on to reduce the amplitude of integral input signal V1. When bitstream signal BS is 0, switching mode current source J1 is turned off to increase the amplitude of integral input signal V1.

As shown in FIG. 3, switching mode current source J1 includes three terminals A, B, and C. The input analog signal Input is connected to terminal A, the bit stream signal BS is connected to terminal C, and terminal C is connected to common ground level Vss. Below, the principle of operation of the feedback unit 330 will be explained.

In the initial state, the switching mode current source J1 is off, and the integral input signal V1 gradually increases as the input analog signal Input is input. When V1>Vref1, the integral output signal V2 is decreasing. The comparison unit 320 outputs a high level bit stream signal BS=1 when V2<Vref2. At this time, switching mode current source J1 is turned on and integral input signal V1 is pulled down. When V1<Vref1, the integral output signal V2 is increasing. When V2>Vref2, the comparison unit 320 outputs a low level bit stream signal BS=0. At this time, the switching mode current source J1 is turned off and the amplitude of the integral input signal V1 is gradually increased again.

Thus, when the analog-to-digital converter 300 of the present invention is in operation, the bit stream signal BS output by the comparison unit 320 is changed according to the amplitude of the integral input signal V1 according to the operating principle of the control loop described above. At the same time, the duty ratio of the bit stream signal BS and the law of change of the integral input signal V1 are made to match.

FIG. 4 is a waveform diagram of some signals when the sigma-delta analog-to-digital converter according to an embodiment of the present invention is in an operating state. This partial signal corresponds to the analog-to-digital converter 300 shown in FIG.

As shown in FIG. 4, polygonal lines 411 and 412 indicate the integral output signal V2 output from the integral output terminal 313 of the integral unit 310. Square waves 421, 422 indicate the bitstream signal BS output by the comparison output terminal 323 of the comparison unit 320. The two dotted lines respectively correspond to two types of second reference signals Vref2 having different magnitudes. Rising portions and falling portions of the polygonal lines 411 and 412 correspond to the charging process and discharging process of the first capacitor C1, respectively. Here, the polygonal line 411 corresponds to the case where the integral input signal V1 is small, and the second reference signal Vref2 in this case is also small. The polygonal line 412 corresponds to the case where the integral input signal V1 is large, and the second reference signal Vref2 in this case is also large.

A high potential in the rectangular waves 421, 422 represents the number "1" in the bit stream signal BS, and a low potential represents the number "0" in the bit stream signal BS. The duty ratio (duty-cycle) of the bit stream signal BS is the proportion of the number "1" occupied in all cycles in one cycle, the duty of the square wave 421 is relatively small, and the duty of the square wave 422 is comparatively small. relatively large.

Also shown in FIG. 4 are a power supply voltage level Vdd and a common ground level Vss. As shown by the polygonal line 411 in FIG. The supply margin between 413 and power supply voltage level Vdd is M3. When the integral input signal V1 is large, the second reference voltage Vref2 is also large, so the integral output signal V2 as a whole remains located between Vdd and Vss, and there is a difference between the valley point 414 of the polygonal line 412 and the common ground level Vss. The ground contact margin is M4. As shown by comparing FIG. 4 and FIG. 1C, the analog-to-digital converter 300 of the present invention provides a large supply margin and ground margin for the integrated output signal V2, and provides a large swing space for the analog-to-digital converter 300. Giving is clear. This large swing space allows the analog-to-digital converter 300 of the present invention to reduce both its supply voltage and the size of the first capacitor C1, which allows the analog-to-digital converter 300 on a chip to The overall occupied area can be reduced. In some cases, when the voltage swing space is doubled, the size of the first capacitor C1 can be reduced to half of the conventional size.

As shown in FIG. 3, in some embodiments, the analog-to-digital converter 300 of the present invention further includes a second reference signal generation circuit 340. The second reference signal generation circuit 340 includes a first impedance R1 and a current source J2, a first end 341 of the first impedance R1 is connected to the current source J2, and a first end 341 of the first impedance R1 is connected to the current source J2. The second end 342 is connected to a switching mode current source J1, and the first end 341 provides a second reference signal Vref2.

As shown in FIG. 3, the second end 342 of the first impedance R1 is connected to terminal B of the switching mode current source J1. Thereby, the second reference signal Vref2 can be changed in accordance with changes in the integral input signal V1. When the integral input signal V1 is large, the second reference signal Vref2 is also large. When the integral input signal V1 is small, the second reference signal Vref2 is also small.

The present invention does not limit the type of current source J2. In some embodiments, current source J2 and switched mode current source J1 are the same type of current source.

The present invention does not limit the type and size of the first impedance R1. The first impedance R1 may be an impedance element such as a resistor, an inductance, or a capacitor, or may be an impedance network consisting of a plurality of types of impedance elements.

In a preferred embodiment, the first impedance R1 includes a nonlinear impedance element with nonlinear characteristics. This can prevent the second reference signal Vref2 from becoming too small and affecting the bit stream signal BS output by the comparison unit 320.

Integration unit 310 in analog-to-digital converter 300 shown in FIG. 3 includes one integrator. That is, this analog-to-digital converter 300 is a primary analog-to-digital converter. As shown in FIG. 3, in some embodiments, a plurality of integration units 350 may be included between the integration unit 310 and the comparison unit 320, and the number of integration units connected in series is Determine the order of analog-to-digital converter 300. Note that the number of integrating sections 350 can be set as necessary. In these embodiments, the first reference voltage Vref1 serves as a reference signal for multiple integration units simultaneously.

FIG. 5 is an exemplary flowchart of a method for controlling a sigma-delta analog-to-digital converter according to an embodiment of the present invention. The analog-to-digital converter controlled by the control method of the embodiment of the present invention should include the integration unit and comparison unit as described above. As shown in FIG. 5, the control method of this embodiment includes the following steps:
Step S510: supplying a fixed first reference signal to the integration unit; and Step S520: supplying a variable second reference signal having an amplitude proportional to the amplitude of the input analog signal of the analog-to-digital converter to the comparison unit. To supply.

Since the control method of the present invention can be implemented by the analog-to-digital converter described above, both the above description and the drawings can be used to explain the control method of the present invention.

The control method of the present invention can also be implemented with other control circuits and analog-to-digital converters.

As mentioned above, in some embodiments, the integration unit has a first integration input terminal, a second integration input terminal, and an integration output terminal, and the integration input signal is applied to the first integration input terminal. A first reference signal is connected to a second integral input terminal, and a first capacitor is connected between the first integral input terminal and the integral output terminal. The comparison unit also has a first comparison input terminal, a second comparison input terminal, and a comparison output terminal, the integral output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal. The comparison input terminal is connected to the comparison input terminal, and the comparison output terminal outputs a bitstream signal. Here, the amplitude of the integral input signal is increased or decreased depending on the bitstream signal. In some embodiments, when the bitstream signal is 1, the amplitude of the integral input signal is decreased and the amplitude of the second reference signal is decreased. When the bitstream signal is zero, the amplitude of the integral input signal is increasing and the amplitude of the second reference signal is increasing.

According to the control method of the present invention, by providing the comparison unit with a variable second reference signal, the analog-to-digital converter contains a larger swing space. This large swing space makes it possible to both reduce power supply voltage and capacitor size, reducing the area required for analog-to-digital conversion circuits.

Although the basic concepts have been described above, the above disclosure is clearly intended to be understood by those skilled in the art to be illustrative only and not limiting. Although not explicitly stated herein, various modifications, improvements, and modifications may be made to this application by those skilled in the art. Such modifications, improvements, and modifications are proposed herein and are therefore within the spirit and scope of the exemplary embodiments herein.

At the same time, this application uses specific terminology to describe the embodiments of this application. For example, "an embodiment," "an embodiment," and/or "some embodiments" refer to a feature, configuration, or characteristic associated with at least one embodiment of the present application. Thus, references to "an embodiment" or "an example embodiment" or "an alternative embodiment" mentioned more than once in different places herein do not necessarily refer to the same embodiment. This should be emphasized and noted. Furthermore, several features, configurations, or characteristics of one or more embodiments of the present application may be combined as appropriate.

In some embodiments, numbers are used to describe the number of components, attributes; ” should be understood as being qualified using “. Unless otherwise stated, "about," "approximately," or "approximately" means that the numerical value is allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations, and the approximations may vary depending on the features required for a particular embodiment. can be done. In some embodiments, numerical parameters should take into account a predetermined number of significant digits and employ common digit preservation methods. Although in some examples herein the numerical fields and parameters used to determine the breadth of the range are approximations, in certain examples the setting of such numerical values may Be as accurate as possible within reasonable limits.

Claims (10)

A sigma-delta analog-to-digital converter,
comprising an integral unit and a comparison unit,
the integrating unit has a fixed first reference signal;
the comparison unit has a variable second reference signal;
A sigma-delta analog-to-digital converter, wherein the amplitude of the second reference signal is proportional to the amplitude of the input analog signal of the analog-to-digital converter. The integral unit includes a first integral input terminal, a second integral input terminal, and an integral output terminal, an integral input signal is connected to the first integral input terminal, and the first reference signal is connected to the integral input terminal. a first capacitor connected to the second integral input terminal and between the first integral input terminal and the integral output terminal;
The comparison unit includes a first comparison input terminal, a second comparison input terminal, and a comparison output terminal, the integral output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal, and the comparison output terminal outputs a bitstream signal,
The sigma-delta analog-to-digital converter according to claim 1, wherein the amplitude of the integral input signal is increased or decreased depending on the bitstream signal. further comprising a feedback unit connected to the comparison output terminal,
3. The sigma-delta analog-to-digital converter according to claim 2, wherein the feedback unit controls the amplitude of the integral input signal in response to the bitstream signal. when the bitstream signal is 1, the amplitude of the integral input signal is decreased and the amplitude of the second reference signal is decreased;
3. The sigma-delta analog signal generator of claim 2, wherein when the bitstream signal is zero, the amplitude of the integral input signal is increased and the amplitude of the second reference signal is increased. Digital converter. the feedback unit comprises a switching mode current source connected to the input analog signal;
when the bitstream signal is 1, the switching mode current source is turned on and reduces the amplitude of the integral input signal;
4. The sigma-delta analog-to-digital converter of claim 3, wherein when the bitstream signal is zero, the switching mode current source is turned off to increase the amplitude of the integrated input signal. further comprising a second reference signal generation circuit including a first impedance and a current source,
A first terminal of the first impedance is connected to the current source, a second terminal of the first impedance is connected to the switching mode current source, and the first terminal is connected to the second reference signal. 6. The sigma-delta analog-to-digital converter of claim 5. 7. The sigma-delta analog-to-digital converter according to claim 6, wherein the first impedance comprises a nonlinear impedance element. A method for controlling a sigma-delta analog-to-digital converter comprising an integrating unit and a comparing unit, the method comprising:
providing the integrating unit with a fixed first reference signal; and providing the comparing unit with a variable second reference signal having an amplitude proportional to the amplitude of the input analog signal of the analog-to-digital converter. A method for controlling a sigma-delta analog-to-digital converter, comprising: The integral unit includes a first integral input terminal, a second integral input terminal, and an integral output terminal, an integral input signal is connected to the first integral input terminal, and the first reference signal is connected to the integral input terminal. a first capacitor connected to the second integral input terminal and between the first integral input terminal and the integral output terminal;
The comparison unit includes a first comparison input terminal, a second comparison input terminal, and a comparison output terminal, the integral output terminal is connected to the first comparison input terminal, and the second reference signal is connected to the second comparison input terminal, and the comparison output terminal outputs a bitstream signal,
9. The method of controlling a sigma-delta analog-to-digital converter according to claim 8, wherein the amplitude of the integral input signal is increased or decreased depending on the bitstream signal. when the bitstream signal is 1, the amplitude of the integral input signal is decreased and the amplitude of the second reference signal is decreased;
10. The sigma-delta analog signal generator of claim 9, wherein when the bitstream signal is zero, the amplitude of the integral input signal increases and the amplitude of the second reference signal increases. How to control a digital converter.

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