CN115208400A

CN115208400A - Sigma-Delta analog-to-digital converter and control method thereof

Info

Publication number: CN115208400A
Application number: CN202110379099.0A
Authority: CN
Inventors: 彼得·斯高腾
Original assignee: Datang Nxp Semiconductors Xuzhou Co ltd
Current assignee: Datang NXP Semiconductors Co Ltd
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2022-10-18
Also published as: WO2022213844A1; JP2024512929A

Abstract

The invention relates to a Sigma-Delta analog-to-digital converter and a control method thereof, wherein the Sigma-Delta analog-to-digital converter comprises an integrating unit and a comparing unit, wherein the integrating unit is provided with a fixed first reference signal, the comparing unit is provided with a variable second reference signal, and the amplitude of the second reference signal is in direct proportion to the amplitude of an input analog signal of the analog-to-digital converter. According to the Sigma-Delta analog-digital converter and the control method thereof, a variable second reference signal is provided for the comparison unit, so that the analog-digital converter has a larger swing space. This larger swing space may allow both a reduction in supply voltage and a reduction in capacitor size, thereby reducing the area required for the analog-to-digital conversion circuit.

Description

Sigma-Delta analog-to-digital converter and control method thereof

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a Sigma-Delta analog-to-digital converter and a control method thereof.

Background

A Sigma Delta Analog-to-Digital Converter (ADC) is a widely used high-precision Analog-to-Digital Converter. The Sigma-Delta analog-to-digital converter adopts the technologies of oversampling, noise shaping, digital filtering and the like, and has the advantages of high precision and low power consumption.

Fig. 1A is a schematic diagram of a Sigma-Delta analog-to-digital converter. A Sigma-Delta analog-to-digital converter typically includes two components, a Sigma-Delta modulator 110 and a digital filter 120. The Sigma-Delta modulator 110 oversamples the analog Input signal Input at a rate well above the nyquist sampling rate and outputs a one-Bit bitstream (Bit Stream). The density of "1" s in the bitstream corresponds to the magnitude of the analog Input signal Input. The digital filter 120 filters the bit stream resulting in a very high conversion resolution.

FIG. 1B is a schematic diagram of a first order Sigma-Delta modulator. The Sigma-Delta modulator may consist of an integrator 111 and a comparator 112. The integrator 111 includes an Operational Amplifier OA1 (OA) and a capacitor C1. The input current signal Iinput is connected to an input terminal of the operational amplifier OA1, and provides an input voltage V1 to the operational amplifier OA 1. The reference voltage Vref is connected to the other input of the operational amplifier OA 1. The output of the operational amplifier OA1 is connected to an input of the comparator 112, and the output signal 114 of the operational amplifier OA1 is used as an input signal of the comparator 112. The reference voltage Vref is also connected to the other input of the comparator 112, and serves as the other input signal of the comparator 112. The comparator 112 is configured to compare the output signal 114 with a reference voltage Vref and output a bitstream signal 115 at an output terminal. The output terminal of the comparator 112 is connected to one terminal of a switch-mode current source J1, and the switch-mode current source J1 is further connected to the input current signal Iinput to form a feedback loop, so as to adjust the magnitude of the input voltage V1 according to the bit stream signal 115 output by the comparator 112.

Fig. 1C is a waveform diagram of a portion of the signal of the Sigma-Delta modulator shown in fig. 1B in an operating state. The

broken lines

131 and 132 are used to represent the voltage waveform of the output signal 114 of the operational amplifier OA 1; the

square waves

141, 142 are used to represent the bitstream signal 115 output by the comparator 112. The rising and falling segments of the

folding lines

131, 132 correspond to the charging and discharging processes of the capacitor C1, respectively. A high potential in the

square wave

141, 142 represents a digital "1" in the bitstream signal 115 and a low potential represents a digital "0" in the bitstream signal 115. The duty cycle (duty-cycle) of the bitstream signal 115 refers to the proportion of the digital "1" in a period that occupies the entire period, the duty cycle of the square wave 141 being small and the duty cycle of the square wave 142 being large. When the input voltage V1 is low, the output signal 114 of the operational amplifier OA1 is represented by the broken line 131 and corresponds to the bitstream signal 141; when the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is represented by the polyline 132 and corresponds to the bitstream signal 142.

Also shown in FIG. 1C are the supply voltage level Vdd and the common ground level Vss in the circuitry of the Sigma-Delta modulator. Referring to fig. 1C, when the input voltage V1 is lower, the output signal 114 of the operational amplifier OA1 is relatively close to the system voltage level Vdd, and the difference M1 between the peak point 133 of the polygonal line 131 and the power Supply voltage level Vdd is smaller, where the difference M1 may also be referred to as a Supply margin (Supply margin); when the input voltage V1 is high, the output signal 114 of the operational amplifier OA1 is relatively close to the common Ground level Vss, and the difference M2 between the valley point 134 of the polygonal line 132 and the common Ground level Vss is small, and the difference M2 may also be referred to as Ground margin (Ground margin).

According to the Sigma-Delta modulator shown in fig. 1A-1C, the output signal 114 of the operational amplifier OA1 has a small supply margin and a small ground margin, i.e. the Sigma-Delta analog-to-digital converter allows a small voltage swing. The voltage swing is limited to the voltage swing space of Vdd-Vref or Vref-Vss. The smaller voltage swing space imposes a limitation on the normal operation of the operational amplifier OA 1. The small voltage swing space also limits the value of the capacitor C1 in the integrator 111 to be too large.

However, the value of the capacitor C1 cannot be too small for the analog-to-digital converter to have a high signal-to-noise ratio. However, for a limited voltage swing space, the large capacitor affects the accuracy of the integrator, occupies a large chip area, and increases the power consumption of the circuit. Therefore, it is desirable for the analog-to-digital converter to have a large swing space and to reduce the size of the capacitor C1.

Disclosure of Invention

The invention aims to provide a Sigma-Delta analog-to-digital converter with an increased swing space and a control method thereof.

The invention adopts the technical scheme that the Sigma-Delta analog-to-digital converter is characterized by comprising an integrating unit and a comparing unit, wherein the integrating unit is provided with a fixed first reference signal, the comparing unit is provided with a variable second reference signal, and the amplitude of the second reference signal is in direct proportion to the amplitude of an input analog signal of the analog-to-digital converter.

In an embodiment of the present invention, the integration unit has a first integration input terminal, a second integration input terminal, and an integration output terminal, the integration input signal is connected to the first integration input terminal, the first reference signal is connected to the second integration input terminal, and a first capacitor is connected between the first integration input terminal and the integration output terminal; and the comparison unit has a first comparison input terminal, a second comparison input terminal and a comparison output terminal, the integral output terminal is connected with the first comparison input terminal, the second reference signal is connected with the second comparison input terminal, and the comparison output terminal outputs a bit stream signal; wherein the magnitude of the integrated input signal is increased or decreased in dependence on the bitstream signal.

In an embodiment of the present invention, the apparatus further includes a feedback unit connected to the comparison output terminal, and the feedback unit controls the amplitude of the integrated input signal according to the bitstream signal.

In an embodiment of the present invention, when the bitstream signal is 1, the amplitude of the integrated input signal is decreased, and the amplitude of the second reference signal is decreased; when the bitstream signal is 0, the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.

In an embodiment of the present invention, the feedback unit includes a switch mode current source connected to the input analog signal, and when the bit stream signal is 1, the switch mode current source is turned on to reduce the amplitude of the integrated input signal; when the bit stream signal is 0, the switch mode current source is turned off, so that the amplitude of the integrated input signal is increased.

In an embodiment of the present invention, the method further includes: a second reference signal generating circuit comprising a first impedance and a current source, a first end of the first impedance being connected to the current source, a second end of the first impedance being connected to the switch mode current source, the first end providing the second reference signal.

In an embodiment of the invention, the first impedance comprises a non-linear impedance element.

The present invention further provides a method for controlling a Sigma-Delta analog-to-digital converter to solve the above technical problem, where the analog-to-digital converter includes an integrating unit and a comparing unit, and the method includes: providing a fixed first reference signal to the integration unit; and providing a variable second reference signal to the comparison unit, the magnitude of the second reference signal being proportional to the magnitude of the input analog signal of the analog-to-digital converter.

According to the Sigma-Delta analog-digital converter and the control method thereof, the variable second reference signal is provided for the comparison unit, so that the analog-digital converter has a larger swing space. This larger swing space may allow both a reduction in supply voltage and a reduction in capacitor size, thereby reducing the area required for the analog-to-digital conversion circuit.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1A is a schematic diagram of a Sigma-Delta analog-to-digital converter;

FIG. 1B is a schematic diagram of a first order Sigma-Delta modulator;

FIG. 1C is a partial waveform diagram of the Sigma-Delta modulator shown in FIG. 1B in an operating state;

FIG. 2 is a schematic diagram of a Sigma-Delta analog-to-digital converter according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a Sigma-Delta analog-to-digital converter according to another embodiment of the invention;

FIG. 4 is a waveform diagram of a part of the signal of the Sigma-Delta analog-to-digital converter of the embodiment shown in FIG. 3 in an operating state;

FIG. 5 is an exemplary flow chart of a method for controlling a Sigma-Delta analog-to-digital converter according to one embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements.

In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

Flowcharts are used herein to illustrate the operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. At the same time, other operations are either added to or removed from these processes.

FIG. 2 is a schematic diagram of a Sigma-Delta analog-to-digital converter according to an embodiment of the invention. Referring to fig. 2, a Sigma-Delta analog-to-digital converter 200 (hereinafter referred to simply as an "analog-to-digital converter") of this embodiment includes: an integrating unit 210 and a comparing unit 220, wherein the integrating unit 210 has a fixed first reference signal Vref1, the comparing unit 220 has a variable second reference signal Vref2, and the magnitude of the second reference signal Vref2 is proportional to the magnitude of the Input analog signal Input of the analog-to-digital converter 200.

Referring to fig. 1A, according to the function of the Sigma-Delta analog-to-digital converter, the analog-to-digital converter 200 can output a bitstream signal at an output 221 of the comparing unit 220 according to the Input analog signal Input.

Referring to fig. 2, the first reference signal Vref1 has a fixed magnitude. The effect of the first reference signal Vref1 on the integration unit 210 is the same as the effect of the reference signal Vref on the integrator 111 shown in fig. 1B.

Referring to fig. 2, the amplitude of the second reference signal Vref2 may vary in proportion to the amplitude of the Input analog signal Input, that is, when the amplitude of the Input analog signal Input increases, the amplitude of the second reference signal Vref2 also increases, and when the amplitude of the Input analog signal Input decreases, the amplitude of the second reference signal Vref2 also decreases.

Fig. 2 is only an example, and is not intended to limit the specific embodiment of how the second reference signal Vref2 varies with the variation of the Input analog signal Input. The amplitude of the second reference signal Vref2 may be made proportional to the amplitude of the Input analog signal Input of the analog-to-digital converter 200 in any manner by those skilled in the art based on the idea of the present invention.

The present invention does not limit which kind of electrical signals the Input analog signal Input, the first reference signal Vref1, and the second reference signal Vref2 are, and may be a current signal or a voltage signal. Unless otherwise specified, the magnitude or height of a signal in this specification refers to the magnitude of the amplitude of the signal, the magnitude of a current in the case of a current signal, and the magnitude of a voltage in the case of a voltage signal.

According to the analog-to-digital converter 200 shown in fig. 2, the swing space of the analog-to-digital converter 200 can be increased by using the larger second reference signal Vref2 for the larger or higher Input analog signal Input and using the smaller second reference signal Vref2 for the smaller or lower Input analog signal Input, which can allow the larger capacitor, such as the first capacitor C1, to be used in the integrating unit 210, thereby improving the overall performance of the analog-to-digital converter 200.

FIG. 3 is a schematic diagram of a Sigma-Delta analog-to-digital converter according to another embodiment of the invention. Referring to fig. 3, the analog-to-digital converter 300 includes an integrating unit 310 and a comparing unit 320, wherein the integrating unit 310 has a first integrating input terminal 311, a second integrating input terminal 312 and an integrating output terminal 313, an integrating input signal V1 is connected to the first integrating input terminal 311, a first reference signal Vref1 is connected to the second integrating input terminal 312, and a first capacitor C1 is connected between the first integrating input terminal 311 and the integrating output terminal 313; the comparing unit 320 has a first comparing input 321, a second comparing input 322 and a comparing output 323, the integrating output 313 is connected to the first comparing input 321, the second reference signal Vref2 is connected to the second comparing input 322, the comparing output 323 outputs the bitstream signal BS; wherein the magnitude of the integrated input signal V1 is increased or decreased in dependence on the bitstream signal BS.

In a preferred embodiment, the integrated Input signal V1, the first reference signal Vref1 and the second reference signal Vref2 are all voltage signals and the Input analog signal Input is a current signal.

The amplitude of the integrated Input signal V1 is influenced by both the Input analog signal Input and the bitstream signal BS. When the Input analog signal Input is a current signal, the magnitude of the integrated Input signal V1 gradually increases with the Input of the Input analog signal Input. A first reference signal Vref1 having a fixed magnitude is used as one input signal of the integration unit 310, and the integrated input signal V1 is used as the other input signal of the integration unit 310. Depending on the function of the integration unit 310, when V1> Vref1, the integration output signal V2 at the integration output 313 of the integration unit 310 is decreased to prevent the integration input signal V1 from increasing further.

When the integration output signal V2 of the integration unit 310 < Vref2, the comparison unit 320 outputs a high level, i.e., the bitstream signal BS =1. When the integrated output signal V2> Vref2 of the integrating unit 310, the comparing unit 320 outputs a low level, i.e., the bit stream signal BS =0.

Referring to fig. 3, in some embodiments, the analog-to-digital converter 300 of the present invention further comprises a feedback unit 330, and the feedback unit 330 can control the amplitude of the integrated input signal V1 according to the bitstream signal BS.

In some embodiments, when the bitstream signal BS =1, the magnitude of the integrated input signal V1 decreases, the magnitude of the second reference signal Vref2 decreases; when the bitstream signal BS =0, the magnitude of the integrated input signal V1 increases, and the magnitude of the second reference signal Vref2 increases.

The present invention does not limit the specific implementation manner of the feedback unit 330.

Referring to fig. 3, in some embodiments, the feedback unit 330 includes a switch-mode current source J1 connected to the Input analog signal Input, and when the bit stream signal BS is 1, the switch-mode current source J1 is turned on to reduce the amplitude of the integrated Input signal V1; when the bit stream signal BS is 0, the switch mode current source J1 is turned off, increasing the amplitude of the integrated input signal V1.

Referring to fig. 3, the switch-mode current source J1 includes three terminals a, B, C. The Input analog signal Input is connected to terminal a and the bitstream signal BS is connected to terminal C, which is connected to a common ground level Vss. The operation of the feedback unit 330 is explained below.

Assuming that the switch-mode current source J1 is in the off state in the initial state, the integrated Input signal V1 gradually increases with the Input of the Input analog signal Input. When V1> Vref1, the integrated output signal V2 decreases. When V2< Vref2, the comparison unit 320 outputs a high level, i.e., the bitstream signal BS =1. At this time, the switch mode current source J1 is turned on, pulling the integral input signal V1 low. When V1< Vref1, the integrated output signal V2 increases. When V2> Vref2, the comparison unit 320 outputs a low level, i.e., the bit stream signal BS =0. At this time, the switch-mode current source J1 is turned off, and the amplitude of the integrated input signal V1 is gradually increased again.

In this way, in the operating state of the analog-to-digital converter 300 of the present invention, the bit stream signal BS output by the comparing unit 320 is changed according to the amplitude of the integrated input signal V1 according to the operating principle of the control loop described above, and the duty ratio of the bit stream signal BS corresponds to the changing rule of the integrated input signal V1.

FIG. 4 is a waveform diagram of a part of the signal of the Sigma-Delta analog-to-digital converter in the working state according to the embodiment of the invention. This portion of the signal corresponds to the analog-to-digital converter 300 shown in fig. 3.

Referring to fig. 4, the

broken lines

411 and 412 represent the integration output signal V2 outputted from the integration output 313 of the integration unit 310; the

square waves

421, 422 represent the bit stream signal BS output by the comparison output 323 of the comparison unit 320; the two dashed lines correspond to two different magnitudes of the second reference signal Vref2, respectively. The rising and falling segments of the

fold lines

411, 412 correspond to the charging and discharging processes of the first capacitor C1, respectively. Where, the broken line 411 corresponds to the case where the integrated input signal V1 is smaller, and the second reference signal Vref2 at this time is also smaller; the broken line 412 corresponds to the case where the integrated input signal V1 is large, and the second reference signal Vref2 is also large at this time.

The high potential in the

square waves

421, 422 represents a digital "1" in the bit stream signal BS and the low potential represents a digital "0" in the bit stream signal BS. The duty cycle (duty-cycle) of the bitstream signal BS refers to the proportion of the digital "1" in a period over the whole period, the duty cycle of the square wave 421 being smaller and the duty cycle of the square wave 422 being larger.

Also shown in fig. 4 are a supply voltage level Vdd and a common ground level Vss. Referring to a broken line 411 in fig. 4, when the integrated input signal V1 is small, since the second reference voltage Vref2 is also small, the integrated output signal V2 is entirely located at an intermediate position between Vdd and Vss, and a power supply margin between a peak point 413 of the broken line 411 and the power supply voltage level Vdd is M3; when the integrated input signal V1 is large, since the second reference voltage Vref2 is also large, the integrated output signal V2 is still located at an intermediate position between Vdd and Vss as a whole, and the ground margin between the valley point 414 of the polygonal line 412 and the common ground level Vss is M4. Comparing fig. 4 and fig. 1C, it is clear that the analog-to-digital converter 300 of the present invention provides the integrated output signal V2 with a larger power supply margin and a larger ground margin, and provides the analog-to-digital converter 300 with a larger swing space. The large swing space enables the adc 300 of the present invention to reduce the supply voltage and reduce the size of the first capacitor C1, thereby reducing the occupied area of the whole adc 300 on the chip. In some cases, the size of the first capacitor C1 may be half of the original size when the voltage swing space is increased to twice the original size.

Referring to fig. 3, in some embodiments, the analog-to-digital converter 300 of the present invention further includes a second reference signal generating circuit 340, which includes a first impedance R1 and a current source J2, wherein a first end 341 of the first impedance R1 is connected to the current source J2, a second end 342 of the first impedance R1 is connected to the switch-mode current source J1, and the first end 341 provides a second reference signal Vref2.

As shown in fig. 3, the second end 342 of the first impedance R1 is connected to the terminal B of the switch-mode current source J1. So that the second reference signal Vref2 can be varied with the variation of the integrated input signal V1. When the integrated input signal V1 is large, the second reference signal Vref2 is also large; when the integrated input signal V1 is small, the second reference signal Vref2 is also small.

The present invention does not limit the type of current source J2. In some embodiments, the current source J2 and the switch-mode current source J1 are the same type of current source.

The present invention does not limit the type and size of the first impedance R1. The first impedance R1 may be an impedance element such as a resistor, an inductor, a capacitor, or an impedance network composed of a plurality of impedance elements.

In a preferred embodiment, the first impedance R1 comprises a non-linear impedance element having a non-linear characteristic. In this way, it is avoided that the second reference signal Vref2 is too small to affect the bitstream signal BS output by the comparing unit 320.

The integrating unit 310 in the analog-to-digital converter 300 shown in fig. 3 includes an integrator, that is, the analog-to-digital converter 300 is a first-order analog-to-digital converter. Referring to fig. 3, in some embodiments, a plurality of integration units 350 may be further included between the integration unit 310 and the comparison unit 320, and the number of integration units in series determines the order of the analog-to-digital converter 300. The number of the integration units 350 may be set as necessary. In these embodiments, the first reference voltage Vref1 is simultaneously used as a reference signal for a plurality of integration units.

FIG. 5 is an exemplary flow chart of a method for controlling a Sigma-Delta analog-to-digital converter according to one embodiment of the invention. The analog-to-digital converter controlled by the control method of the embodiment of the present invention should include the integrating unit and the comparing unit as described above. Referring to fig. 5, the control method of this embodiment includes the steps of:

step S510: providing a fixed first reference signal to an integration unit; and

step S520: a variable second reference signal is provided to the comparison unit, the magnitude of the second reference signal being proportional to the magnitude of the input analog signal of the analog-to-digital converter.

The control method of the present invention can be performed by the analog-to-digital converter described above, and therefore, the foregoing description and the accompanying drawings can be used to describe the control method of the present invention.

The control method of the present invention may also be performed by other control circuits and analog-to-digital converters.

As previously mentioned, in some embodiments, the integration unit has a first integration input terminal, a second integration input terminal, and an integration output terminal, the integration input signal is connected to the first integration input terminal, the first reference signal is connected to the second integration input terminal, and a first capacitor is connected between the first integration input terminal and the integration output terminal; the comparison unit is provided with a first comparison input end, a second comparison input end and a comparison output end, the integral output end is connected with the first comparison input end, the second reference signal is connected with the second comparison input end, and the comparison output end outputs a bit stream signal; wherein the magnitude of the integrated input signal is increased or decreased in dependence on the bitstream signal. In some embodiments, when the bitstream signal is 1, the magnitude of the integrated input signal is decreased, and the magnitude of the second reference signal is decreased; when the bitstream signal is 0, the amplitude of the integrated input signal increases and the amplitude of the second reference signal increases.

According to the control method of the invention, the variable second reference signal is provided for the comparison unit, so that the analog-to-digital converter has a larger swing space. This larger swing space allows both a reduction in supply voltage and a reduction in capacitor size, thereby reducing the area required for the analog-to-digital conversion circuit.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.

Also, the present application uses specific words to describe embodiments of the application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means a feature, structure, or characteristic described in connection with at least one embodiment of the application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

Claims

1. A Sigma-Delta analog-to-digital converter is characterized by comprising an integrating unit and a comparing unit, wherein the integrating unit is provided with a fixed first reference signal, the comparing unit is provided with a variable second reference signal, and the amplitude of the second reference signal is proportional to the amplitude of an input analog signal of the analog-to-digital converter.

2. The analog-to-digital converter according to claim 1, characterized in that the integration unit has a first integration input, a second integration input and an integration output, an integration input signal being connected to the first integration input, the first reference signal being connected to the second integration input, a first capacitance being connected between the first integration input and the integration output; and

the comparison unit is provided with a first comparison input end, a second comparison input end and a comparison output end, the integral output end is connected with the first comparison input end, the second reference signal is connected with the second comparison input end, and the comparison output end outputs a bit stream signal;

wherein the magnitude of the integrated input signal is increased or decreased in dependence on the bitstream signal.

3. The analog-to-digital converter of claim 2, further comprising a feedback unit coupled to the comparison output, the feedback unit controlling the magnitude of the integrated input signal based on the bitstream signal.

4. The analog-to-digital converter of claim 2, wherein when the bitstream signal is 1, the magnitude of the integrated input signal decreases and the magnitude of the second reference signal decreases; when the bitstream signal is 0, the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.

5. The analog-to-digital converter of claim 3, wherein the feedback unit comprises a switch-mode current source connected to the input analog signal, the switch-mode current source being turned on to decrease the magnitude of the integrated input signal when the bitstream signal is 1; when the bitstream signal is 0, the switch-mode current source is turned off, increasing the amplitude of the integrated input signal.

6. The analog-to-digital converter of claim 5, further comprising: the second reference signal generating circuit comprises a first impedance and a current source, wherein a first end of the first impedance is connected with the current source, a second end of the first impedance is connected with the switch mode current source, and the first end provides the second reference signal.

7. The analog-to-digital converter of claim 6, wherein the first impedance comprises a non-linear impedance element.

8. A method of controlling a Sigma-Delta analog-to-digital converter, the analog-to-digital converter including an integrating unit and a comparing unit, the method comprising:

providing a fixed first reference signal to the integration unit; and

-providing a variable second reference signal to the comparison unit, the second reference signal having an amplitude proportional to the amplitude of the input analog signal of the analog-to-digital converter.

9. The control method of claim 8, wherein the integration unit has a first integration input, a second integration input, and an integration output, an integration input signal being coupled to the first integration input, the first reference signal being coupled to the second integration input, a first capacitor being coupled between the first integration input and the integration output; and

10. The control method of claim 9, wherein when the bitstream signal is 1, the magnitude of the integrated input signal decreases, and the magnitude of the second reference signal decreases; when the bitstream signal is 0, the amplitude of the integrated input signal increases, and the amplitude of the second reference signal increases.