CN112787672A - Extended count analog-to-digital converter - Google Patents

Extended count analog-to-digital converter Download PDF

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CN112787672A
CN112787672A CN202011608524.0A CN202011608524A CN112787672A CN 112787672 A CN112787672 A CN 112787672A CN 202011608524 A CN202011608524 A CN 202011608524A CN 112787672 A CN112787672 A CN 112787672A
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switch
capacitor
adc
counter
low
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王欣洋
刘洋
李扬
马成
李靖
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Changchun Changguangchenxin Optoelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/32—Delta-sigma modulation with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention provides an extended count analog-to-digital converter, comprising: the sigma delta-ADC and the SS-ADC divide the circuit into two quantization stages of coarse quantization and fine quantization; in the coarse quantization stage, a delta sigma-ADC quantizes a high-bit digital code, in the low quantization stage, an SS-ADC quantizes a low-bit digital code, the quantization time is reduced through two quantization stages, and the power consumption is reduced by sharing one comparator between the delta sigma-ADC and the SS-ADC. In addition, the EC-ADC provided by the invention adjusts the slope of the ramp signal in the low-order conversion stage according to the capacitance mismatch between the sampling capacitor and the feedback capacitor, so that the linearity of the ADC can be improved without calibration, and the complexity of the circuit design is reduced.

Description

Extended count analog-to-digital converter
Technical Field
The invention relates to the technical field of analog integrated circuit design of microelectronics, in particular to a column-level 12-bit extended counting analog-to-digital converter used in a CMOS (complementary metal oxide semiconductor) image sensor.
Background
In recent years, with the development of science and technology, people have more and more extensive applications to portable digital electronic products. CMOS Image Sensors (CIS) are widely used in human life due to their high integration level and low cost. A conventional CIS structure, as shown in fig. 1, generally includes a pixel, correlated double sampling, an analog-to-digital converter and some digital processing modules, where the analog-to-digital converter is an important component in a CMOS image sensor, and has a crucial influence on the performance of the CMOS image sensor.
An Analog/Digital converter (ADC) can convert an Analog signal into a Digital signal, and is a bridge connecting the Analog world and the Digital world. In the CMOS image sensor, applications to the ADC may be divided into a pixel-level ADC, a column-level ADC, and an on-chip ADC. Among them, the column-level RAMP analog-to-digital converter (RAMP-ADC) has become the mainstream ADC structure of the CMOS image sensor at present due to its good balance in the aspects of the image sensor speed, the design complexity, and the power consumption.
Single slope analog-to-digital converters (SS-ADCs) are commonly used in column level ADCs because of their simple structure and easy design. However, the SS-ADC has the disadvantages of low speed and high power consumption due to the unique working principle. The common solution is to divide the quantization process into multiple steps of quantization, which can greatly reduce the quantization time and power consumption. However, this structure also has the disadvantage that during the conversion between coarse quantization and fine quantization, the coarse quantization result needs to be saved, the voltage is often sampled by using a capacitor, and the presence of the sampling capacitor will introduce a large error to the whole ADC circuit. To reduce circuit errors and ensure high precision of the ADC, a digital calibration circuit is usually added for calibration, which increases the design difficulty of the circuit.
Disclosure of Invention
The invention aims to solve the problems that circuit errors are reduced by adopting a sampling capacitor in an SS-ADC (system-to-analog converter), and circuit design difficulty is increased by introducing a digital calibration circuit on the basis of adopting the sampling capacitor, and provides an extended counting analog-to-digital converter so as to improve the quantization speed of the analog-to-digital converter, ensure the precision of the analog-to-digital converter without calibrating the circuit and reduce the complexity of the circuit.
In order to achieve the purpose, the invention adopts the following specific technical scheme:
the invention provides an extended count analog-to-digital converter, comprising: the circuit comprises first to eighth switches, a first capacitor, a second capacitor, an amplifier, a comparator, a high counter, a low counter and a digital signal processing circuit; wherein the content of the first and second substances,
the capacitance value of the second capacitor is twice that of the first capacitor, and parasitic capacitors are respectively connected in parallel at two ends of the first capacitor and the second capacitor and used for causing capacitor mismatch between the first capacitor and the second capacitor;
first terminals of the first switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are connected to a lower pole plate of the first capacitor, and second terminals of the first switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are respectively connected with the analog input voltage VINGround line, input positive reference voltage VREF+And inputting a negative reference voltage VREF-Connecting;
the first terminals of the second switch and the third switch are jointly connected to the upper polar plate of the first capacitor, the second terminals of the second switch and the third switch are respectively connected with the ground wire and the negative phase input end of the amplifier, and the positive phase input end of the amplifier is connected with the ground wire;
the first terminals of the second capacitor and the eighth switch are connected to the negative phase input end of the amplifier, and the second terminals of the second capacitor and the eighth switch are respectively connected with the output signal V of the amplifierAMPConnected to ground and output signal V of the amplifierAMPRespectively connected to two input ends of a comparator, and an output signal D of the output end of the comparatorCMPHigh-order digital code D for controlling enabling end of high-order counter and low-order counter and output of high-order counterUPPERAnd a low-order digital code D output by the low-order counterLOWERAnd the digital signal is output after being digitally processed by the digital signal processing circuit.
Preferably, after being digitally processed by the digital signal processing circuit, the extended count analog-to-digital converter finally outputs DOUTPUT＝2N×DUPPER+DLOWER。
Preferably, the high counter is an Mbit high counter, the low counter is an Nbit low counter, M, N are integers greater than or equal to 1, and N > M.
Preferably, M is 4 and N is 8.
The invention can obtain the following technical effects:
the extended counting analog-to-digital converter is divided into a high-order sigma-delta ADC and a low-order SS-ADC, so that quantization is divided into a coarse quantization stage and a fine quantization stage, and quantization time and power consumption are reduced; the slope of the ramp signal in the low-order conversion stage is adjusted according to the capacitance mismatch between the sampling capacitor and the feedback capacitor, and the ADC linearity can be improved without calibration, so that the complexity of circuit design is reduced.
Drawings
Fig. 1 is a structural view of a conventional CIS;
FIG. 2 is a block diagram of an extended count analog to digital converter according to one embodiment of the present invention;
FIG. 3 is a circuit schematic of an extended count analog to digital converter according to one embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the operation of an extended count analog-to-digital converter according to one embodiment of the present invention;
FIG. 5 is an equivalent circuit diagram of a comparator during high bit quantization for an extended count analog to digital converter according to one embodiment of the present invention;
FIG. 6 is an equivalent circuit diagram of a comparator during low bit quantization for an extended count analog to digital converter according to one embodiment of the present invention;
fig. 7 is a schematic circuit diagram of an extended count analog to digital converter with parasitic capacitance according to one embodiment of the present invention.
Wherein the reference numerals include: first switch S1A second switch S2And a third switch S3And a fourth switch S4The fifth switch S5A sixth switch SR1The seventh switch SR2The eighth switch SRSTA first capacitor CSA second capacitor CFFirst parasitic elementCapacitor CPSA second parasitic capacitor CPFAmplifier AMP, comparator COMP, high counter CNT1, low counter CNT2, digital signal processing circuit DSP.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
The extended count analog-to-digital converter provided by the embodiment of the present invention will be described in detail below.
Fig. 2 shows the structure of an extended count analog-to-digital converter according to an embodiment of the invention.
As shown in fig. 2, the Extended Counting ADC (hereinafter abbreviated as EC-ADC) provided by the present invention includes a sigma-delta analog-to-digital converter (hereinafter abbreviated as sigma-delta-ADC), a single-slope analog-to-digital converter (hereinafter abbreviated as SS-ADC), and a digital signal processing circuit DSP.
The EC-ADC provided by the invention adopts a circuit architecture combining a sigma delta-ADC and an SS-ADC, and divides a circuit into two quantization stages of coarse quantization and fine quantization; in the coarse quantization stage, the delta sigma-ADC quantizes the high-bit digital code, and in the low quantization stage, the SS-ADC quantizes the low-bit digital code. Power consumption is reduced by sharing one comparator between the delta sigma ADC and the SS ADC. In addition, the EC-ADC provided by the invention can adjust the slope of the ramp signal in the low-order conversion stage according to the capacitance mismatch between the sampling capacitor and the feedback capacitor, so that the linearity of the ADC can be improved without calibration.
The sigma delta-ADC is an Mbit sigma delta-ADC and is used for quantizing high M-bit digital codes, the SS-ADC is an NbitSS-ADC and is used for quantizing low N-bit digital codes, the high-bit counter is an Mbit high-bit counter, the low-bit counter is an Nbit low-bit counter, M, N are integers which are larger than or equal to 1, and N is larger than M.
A12-bit EC-ADC is used as an example for explanation, and other bit EC-ADCs can be obtained in the same manner.
In one example of the invention, the Σ Δ -ADC is a 4-bit Σ Δ -ADC for quantizing high four-bit digital codes, and the SS-ADC is an 8-bit SS-ADC for quantizing low eight-bit digital codes. The high counter is a 4-bit high counter, and the low counter is an 8-bit low counter.
Fig. 3 shows the circuit principle of an EC-ADC according to an embodiment of the invention.
As shown in fig. 3, an EC-ADC provided by the embodiment of the present invention includes: first switch S1A second switch S2And a third switch S3And a fourth switch S4The fifth switch S5A sixth switch SR1The seventh switch SR2The eighth switch SRSTA first capacitor CSA second capacitor CF. An amplifier AMP, a comparator COMP, a high counter CNT1, a low counter CNT2, and a digital signal processing circuit DSP; wherein the first capacitor CSAs a sampling capacitor, a second capacitor CFAs a feedback capacitor, a second capacitor CFThe capacitance value is the first capacitance CSTwice the capacity value; first switch S1And a fourth switch S4The fifth switch S5A sixth switch SR1And a seventh switch SR2First terminals of the first and second capacitors are connected to a first capacitor CSLower pole plate of, first switch S1And the analog input voltage VINConnected, fourth switch S4Is connected to ground, a fifth switch S5And input a positive reference voltage VREF+Connected, sixth switch SR1And input a positive reference voltage VREF+Connected, seventh switch SR2And the second terminal of which inputs a negative reference voltage VREF-Connecting; a second switch S2And a third switch S3First terminals of the first and second capacitors are connected to a first capacitor CSUpper pole plate of, the second switch S2Is connected to ground, a third switch S3Is connected to the negative phase input terminal of the amplifier AMP, the positive phase input terminal of the amplifier AMP is connected to ground; second capacitor CFAnd an eighth switch SRSTIs commonly connected to the negative of the amplifier AMPPhase input terminal, second capacitor CFAnd an eighth switch SRSTRespectively with the output signal V of the amplifier AMPAMPConnected to ground and output signal V of amplifier AMPAMPRespectively connected to two input ends of a comparator COMP and an output signal D of an output end of the comparator COMPCMPFor controlling the enable terminals of the high counter CNT1 and the low counter CNT2, the clock input signal CLKN-BIT is the clock signal of the N-BIT low counter, and the high-BIT digital code D output by the high counter CNT1UPPERAnd a low-order digital code D output from the low-order counter CNT2LOWERAnd the digital signal is output after being processed by a digital signal processing circuit DSP.
In this embodiment, the EC-ADC provided by the present invention is used in a CMOS image sensor readout circuit.
Fig. 4 shows an operation timing of the extended count analog-to-digital converter according to an embodiment of the present invention.
As shown in fig. 4, a first switch S1A second switch S2And a third switch S3And a fourth switch S4The fifth switch S5A sixth switch SR1The seventh switch SR2The eighth switch SRSTThe equivalent circuit diagram of the comparator is shown in fig. 5, where (a) is the equivalent circuit of the comparator COMP at step 1, (b) is the equivalent circuit of the comparator COMP at step 16, and (c) is the equivalent circuit of the comparator COMP at step 17.
In the high-order conversion, the EC-ADC operates as a Σ Δ -ADC, and in steps 1 to 16, sampling and integration operations are performed. In step 1, VINIs stored in the first capacitor CSAnd the second capacitance C is applied during samplingFAnd (4) discharging. During the first integration operation, the charge C in the first capacitorS·VINFrom the first to the second capacitance CF. After step 1, VAMP[1]Can be expressed as:
VAMP[1]＝VIN/2 (1)。
when V isAMP[1]When the voltage is higher or lower than the ground level GND, the comparator COMP generates a first outputDCMP[1]The value is +1 or-1.
In steps 2 to 16, during the integration operation, according to DCMP[1]Of (3) controls the sixth switch SR1Or a seventh switch SR2On/off of VREF+Or VREF-Is connected to a first capacitor CS。
In step 17, V is addedREF+Is stored in the first capacitor CSIn combination with a second capacitor CFCharge C inS·VREF+So that the output voltage V of the amplifier AMPAMP[17]Is equal to VREF+/2. After high quadbit quantization, VAMP[17]Can be expressed as:
Figure BDA0002870928950000061
after step 17, comparator COMP enters a low quantization phase and EC-ADC operates as an SS-ADC. Now the sixth switch SR1Set to high level and switch SR to seventh2Set to low level, set VREF-Is connected to the first capacitor. The equivalent circuit of the comparator COMP at this time is shown in fig. 6. During this period, the EC-ADC measures V during the high bit quantizationAMP[17]Quantization is performed to quantize it into an eight-bit digital code. As shown in FIG. 6(a), V is first setREF-Stored in the first capacitor CSIn (1). In FIG. 6(b), the first capacitor CSAnd a second capacitor CFAre connected while the first capacitor CSDoes not pass from the first capacitor CSTo a second capacitor CFInner, therefore VAMPHas the same voltage value as formula (2). Thereafter, VAMPFollowing VREF-Increasing and gradually decreasing, the low counter CNT2 is for the clock signal CLKN_BITCounting to generate a low-bit digital code DLOWER。
Finally, by pair DUPPERAnd DLOWERPerforming digital signal processing to output as OUTPUTIt can be expressed as:
DOUTPUT＝2N×DUPPER+DLOWER (3)。
in order to ensure the precision of low-order quantization, the input range of the input ramp signal during low-order quantization is expanded, and the expansion range is as follows:
Figure BDA0002870928950000062
fig. 7 illustrates the circuit principle of an EC-ADC with parasitic capacitances according to an embodiment of the invention.
As shown in fig. 7, in the first capacitor CSAre connected in parallel with a first parasitic capacitor CPSIn the second capacitor CFAre connected in parallel with a second parasitic capacitance CPFOver an extended input voltage range, due to the first parasitic capacitance CPSAnd a second parasitic capacitance CPFCauses a first capacitance CSAnd a second capacitor CFCapacitance mismatch between them, resulting in V at the high quantization stageRESFrom GND to 2VREF(CS+CPS)/(CF+CPF) In the lower quantization stage, VAMPFrom VRESIs changed into [ V ]RES-2VREF(CS+CPS)/(CF+CPF)]，VAMP2V ofREF(CS+CPS)/(CF+CPF) And VREFThe amount of change in (c) is the same. Thus, the linearity of the EC-ADC provided by the present invention becomes independent of the first capacitance CSAnd a second capacitor CFThe capacitor mismatch between the two circuits is avoided, so that the digital signal is prevented from being calibrated in the later period, and the complexity of the circuit is reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
The above embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.

Claims (4)

1. An extended count analog-to-digital converter, comprising: the circuit comprises first to eighth switches, a first capacitor, a second capacitor, an amplifier, a comparator, a high counter, a low counter and a digital signal processing circuit; wherein the content of the first and second substances,
the second capacitance value is twice of the first capacitance value, and parasitic capacitances are respectively connected in parallel at two ends of the first capacitor and the second capacitor and used for causing capacitance mismatch between the first capacitor and the second capacitor;
first terminals of the first switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are commonly connected to a lower pole plate of the first capacitor, and second terminals of the first switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are respectively connected with an analog input voltage VINGround line, input positive reference voltage VREF+And inputting a negative reference voltage VREF-Connecting;
the first terminals of the second switch and the third switch are jointly connected to the upper polar plate of the first capacitor, the second terminals of the second switch and the third switch are respectively connected with a ground wire and the negative phase input end of the amplifier, and the positive phase input end of the amplifier is connected with the ground wire;
the second capacitor and the first terminal of the eighth switch are connected to the negative phase input end of the amplifier, and the second terminals of the second capacitor and the eighth switch are respectively connected with the output signal V of the amplifierAMPConnected to ground and output signal V of said amplifierAMPRespectively connected to two input ends of the comparator, and output signal D of the output end of the comparatorCMPThe enable end for controlling the high counter and the low counter, and the high digital code D output by the high counterUPPERAnd a low-order digital code D output by the low-order counterLOWERAnd the digital signal is output after being digitally processed by the digital signal processing circuit.
2. The extended count analog-to-digital converter of claim 1, wherein the extended count analog-to-digital converter outputs D after digital processing by the digital signal processing circuitOUTPUT＝2N×DUPPER+DLOWER。
3. The extended count analog-to-digital converter of claim 2, wherein the high counter is an Mbit high counter, the low counter is an Nbit low counter, M, N are integers greater than or equal to 1, and N > M.
4. The extended count analog-to-digital converter of claim 3, wherein M-4 and N-8.
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CN114245041A (en) * 2021-11-18 2022-03-25 北京领丰视芯科技有限责任公司 Pixel circuit and infrared imager
CN114245041B (en) * 2021-11-18 2022-11-11 北京领丰视芯科技有限责任公司 Pixel circuit and infrared imager

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Application publication date: 20210511