CN114584149A - Analog-to-digital converter - Google Patents
Analog-to-digital converter Download PDFInfo
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- CN114584149A CN114584149A CN202210203072.0A CN202210203072A CN114584149A CN 114584149 A CN114584149 A CN 114584149A CN 202210203072 A CN202210203072 A CN 202210203072A CN 114584149 A CN114584149 A CN 114584149A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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Abstract
The present invention provides an analog-to-digital converter comprising: the digital-to-analog conversion module comprises two stages of voltage division units, and the two stages of voltage division units are used for performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage; the sampling comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; and the logic control module performs logic processing on the intermediate digital signal to obtain a first digital signal and a second digital signal. According to the digital-to-analog conversion module, accurate digital-to-analog conversion can be realized while high-precision analog-to-digital conversion is realized, the layout area of an integrated circuit is saved, and the adaptability of the analog-to-digital converter on the aspect that the integration level of the integrated circuit is higher and higher is improved.
Description
Technical Field
The application relates to the technical field of digital-to-analog conversion/analog-to-digital conversion, in particular to an analog-to-digital converter.
Background
A conventional high-precision Successive Approximation (SAR) analog-to-digital converter (ADC) generally includes: digital-to-analog converter (DAC), comparator and logic control module. The DAC in the ADC is mostly in the form of a capacitor to realize the function of converting digital signals into analog signals, and the structure needs to occupy a large layout area. In addition, the analog voltage on the DAC in such an analog-to-digital converter is very sensitive and has no driving capability by itself. Even if the DAC is replaced by a current steering DAC, the output swing of the DAC is limited. In addition, in the conventional comparator, the common mode input range of the dynamic comparator is limited, and the comparison speed of the analog comparator is slow.
Disclosure of Invention
The application provides an analog-to-digital converter, which can solve at least one problem that the traditional analog-to-digital converter occupies larger layout area, analog voltage of a DAC module is sensitive and has no driving capability, and output swing amplitude of the DAC is easily limited.
In one aspect, an embodiment of the present application provides an analog-to-digital converter, including:
the digital-to-analog conversion module is used for receiving a first target control signal, a second target control signal and a reference analog signal which are external; performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage through the first target control signal and the second target control signal; the digital-to-analog conversion module comprises two stages of voltage division units;
the sampling comparison module is used for receiving an external initial analog signal and a target analog signal output by the digital-to-analog conversion module and outputting an intermediate digital signal to a later stage; and (c) a second step of,
and the logic control module is used for receiving the intermediate digital signal output by the sampling comparison module, an external clock signal, an enable signal and an initial control signal, performing logic processing on the intermediate digital signal, outputting a first digital signal and a second digital signal to a rear stage, performing logic processing on the initial control signal, and outputting a first target control signal and a second target control signal to the digital-to-analog conversion module.
Optionally, in the analog-to-digital converter, the digital-to-analog conversion module includes: the device comprises a first pressure dividing unit and a second pressure dividing unit connected with the first pressure dividing unit;
the first voltage division unit includes: the first switch subunit, the first impedance subunit and the second switch subunit are connected in sequence;
the second voltage division unit includes: a second impedance subunit and a third switching subunit connected with the second impedance subunit;
one end of the first impedance subunit is connected with the external reference analog signal, and the other end of the first impedance subunit is grounded; controlling the first switch subunit and the second switch subunit through the first target control signal, and performing voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;
one end of the second impedance subunit is connected with the first intermediate voltage, and the other end of the second impedance subunit is connected with the second intermediate voltage; and controlling the third switch subunit through the second target control signal, and performing voltage division processing on the difference value of the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.
Optionally, in the analog-to-digital converter, the first impedance subunit includes: serially connected 2 in turnMA resistor;
the second impedance subunit includes: serially connected 2 in turnNA resistor; wherein M and N are both integers greater than or equal to 1, and M + N is an integer greater than or equal to 10.
Optionally, in the analog-to-digital converter, the first switch subunit includes: 2MThe first control switches are respectively and sequentially connected with a series node between two adjacent resistors of the first impedance subunit;
the second switch subunit includes: 2MThe second control switches are respectively connected with the series nodes between two adjacent resistors of the first impedance subunit in sequence;
wherein one of the series nodes is staggered between the first control switch and the second control switch.
Optionally, in the analog-to-digital converter, the third switching subunit includes: 2NAnd each third control switch is sequentially connected with a series node between two adjacent resistors of the second impedance subunit.
Optionally, in the analog-to-digital converter, the sampling comparison module includes: the circuit comprises a first selection switch, a second selection switch, a third selection switch, a capacitor and a comparison unit, wherein the first selection switch is connected with the inverting input end of the comparison unit, the positive pole of the capacitor is connected with a connection node between the first selection switch and the inverting input end of the comparison unit, the negative pole of the capacitor is grounded, and the second selection switch and the third selection switch are both connected to the non-inverting input end of the comparison unit;
and the output end of the digital-to-analog conversion module is connected to the non-inverting input end of the comparison unit through the third selection switch.
Optionally, in the analog-to-digital converter, when the analog-to-digital converter operates, the first selection switch and the second selection switch are simultaneously closed, so that the equidirectional input end and the opposite-directional input end of the comparison unit receive the target analog signal.
Optionally, in the analog-to-digital converter, a switch operating state of the third selection switch is opposite to a switch operating state of the first selection switch and a switch operating state of the second selection switch.
Optionally, in the analog-to-digital converter, the comparing unit includes: the current adder, the preamplifier and the dynamic latch are connected in sequence.
Optionally, in the analog-to-digital converter, the analog-to-digital converter further includes: and the buffer module is used for carrying out buffer adjustment on the target analog signal.
The technical scheme at least comprises the following advantages:
(1) according to the digital-to-analog conversion module, accurate digital-to-analog conversion can be realized while high-precision analog-to-digital conversion is realized, the layout area of an integrated circuit is saved, and the adaptability of the analog-to-digital converter on the aspect that the integration level of the integrated circuit is higher and higher is improved.
(2) Furthermore, the digital-to-analog conversion module comprises two stages of voltage division units, and 2 of the first stage can be used for passingMA resistor and 2 in the second stageNThe matching of the resistors obtains a target analog signal with higher precision.
(3) In addition, the digital-to-analog conversion module provided by the application can output a stable target analog signal (analog voltage signal) to a later stage through two-stage voltage division processing, and the digital-to-analog conversion module has driving capability and has a large output swing amplitude.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic circuit diagram of an analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a digital-to-analog conversion module according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a comparison unit according to an embodiment of the present invention;
wherein the reference numerals are as follows:
10-digital-to-analog conversion module, 11-first voltage division unit, 111-first switch subunit, 112-first impedance subunit, 113-second switch subunit, 12-second voltage division unit, 121-second impedance subunit, 122-third switch subunit, 20-sampling comparison module, 21-comparison unit, 211-current adder, 212-preamplifier, 213 dynamic latch, 30-logic control module and 40-buffer module.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a schematic circuit structure diagram of an analog-to-digital converter according to an embodiment of the present invention, where the analog-to-digital converter includes: a digital-to-analog conversion module 10, a sampling comparison module 20 and a logic control module 30.
The digital-to-analog conversion module 10 is configured to receive an external first target control signal CTL1< M:0>, a second target control signal CTL2< N:0> and a reference analog signal VREF; performing digital-to-analog conversion processing on the reference analog signal VREF and outputting a target analog signal DAC _ OUT to a subsequent stage through the first target control signal CTL1< M:0> and the second target control signal CTL2< N:0 >; the digital-to-analog conversion module 10 includes two stages of voltage dividing units. Specifically, referring to fig. 2, fig. 2 is a schematic circuit structure diagram of a digital-to-analog conversion module according to an embodiment of the present invention, where the digital-to-analog conversion module 10 includes: a first pressure dividing unit 11 and a second pressure dividing unit 12 connected to the first pressure dividing unit 11.
Wherein the first voltage division unit 11 includes: a first switching subunit 111, a first impedance subunit 112 and a second switching subunit 113 which are connected in sequence; the second voltage division unit 12 includes: a second impedance subunit 121 and a third switching subunit 122 connected to said second impedance subunit 121.
In this embodiment, one end of the first impedance subunit 112 is connected to the external reference analog signal VREF, and the other end of the first impedance subunit 112 is grounded; the first switch subunit 111 and the second switch subunit 113 are controlled by the first target control signal CTL1< M:0>, and the reference analog signal VREF is subjected to voltage division processing to obtain a first intermediate voltage VOT and a second intermediate voltage VOB. In addition, one end and the other end of the first impedance subunit 112 may be respectively connected to a positive voltage signal and a negative voltage signal of the reference analog signal VREF, and it is only necessary to ensure that a voltage difference exists between the one end and the other end of the first impedance subunit 112.
Further, one end of the second impedance subunit 121 is connected to the first intermediate voltage VOT, and the other end of the second impedance subunit 122 is connected to the second intermediate voltage VOB; the third switch subunit 122 is controlled by the second target control signal CTL2< N:0>, and the difference between the first intermediate voltage VOT and the second intermediate voltage VOB is subjected to voltage division processing to obtain the target analog signal DAC _ OUT.
Preferably, the first impedance subunit 112 includes: serially connected 2 in turnMA plurality of resistors R1; the second impedance subunit 121 includes: serially connected 2 in turnNA resistor R2; wherein M and N may both be integers greater than or equal to 1, and M + N may be an integer greater than or equal to 10.
Preferably, in correspondence with the first impedance subunit 112, the first switching subunit includes: 2MAnd a plurality of first control switches S1, each of the first control switches S1 being sequentially connected to a series node between two adjacent resistors R1 of the first impedance subunit 112. Also, again corresponding to the first impedance subunit 112, the second switching subunit 122 includes: 2MA plurality of second control switches S2, each of the second control switches S2 being sequentially connected to a series node between two adjacent resistors R1 of the first impedance subunit 112; wherein one of the series nodes is staggered between a set of the first control switches S1 and a set of the second control switches S2.
In this embodiment, corresponding to the second impedance subunit 121, the third switching subunit 122 includes: 2NAnd a plurality of third control switches S3, each of the third control switches S3 being sequentially connected to a series node between two adjacent resistors R2 of the second impedance subunit 122.
Further, the sampling comparing module 20 is configured to receive an external initial analog signal VIN and the target analog signal DAC _ OUT output by the digital-to-analog converting module 10, and output an intermediate digital signal CMP _ OUT to a subsequent stage. Specifically, the sampling comparison module 20 includes: the circuit comprises a first selection switch SHSW1, a second selection switch SHSW2, a third selection switch SHSW2, a capacitor CAP and a comparison unit 21, wherein the first selection switch SHSW1 is connected with the reverse input end of the comparison unit 21, the positive pole of the capacitor CAP is connected with a connection node between the first selection switch SHSW1 and the reverse input end of the comparison unit 21, the negative pole of the capacitor CAP is grounded, and the second selection switch SHSW2 and the third selection switch SHSW3 are both connected to the non-inverting input end of the comparison unit 21; wherein, through the third selection switch SHSW3, the output terminal of the digital-to-analog conversion module 10 is connected to the non-inverting input terminal of the comparing unit 21, so that the target analog signal DAC _ OUT can be input to the non-inverting input terminal of the comparing unit 21. Further, the switch operation state of the third selection switch SHSW3 is opposite to the switch operation states of the first selection switch SHSW1 and the second selection switch SHSW2, and in particular, in this embodiment, it is required to ensure that the switch control signals for controlling the second selection switch SHSW2 and the third selection switch SHSW3 are not enabled at the same time, that is, the second selection switch SHSW2 and the third selection switch SHSW3 are not closed at the same time (the switch operation states of the two are opposite), so as to prevent the initial analog signal VIN and the target analog signal DAC _ OUT from being short-circuited. When the analog-to-digital converter is operated, the first selection switch SHSW1 and the second selection switch SHSW2 are simultaneously closed, so that the non-inverting input terminal and the inverting input terminal of the comparison unit 21 receive the initial analog signal VIN, and the input voltage of the comparison unit 21 is balanced.
Preferably, referring to fig. 3, fig. 3 is a schematic circuit structure diagram of a comparing unit according to an embodiment of the present invention, where the comparing unit 21 includes: a current adder 211, a preamplifier 212 and a dynamic latch 213 connected in series. Specifically, the current adder 211 is composed of two current sources and a plurality of MOS transistors; the preamplifier 212 is a low-gain preamplifier and is composed of a plurality of resistors and a plurality of MOS (metal oxide semiconductor) tubes; the dynamic latch 213 is formed by a plurality of MOS transistors. The input signal common mode voltage range of the comparison unit 21 is large (GND-VDD), and the comparison speed is very fast.
Further, the logic control module 30 is configured to receive the intermediate digital signal CMP _ OUT output by the sampling comparison module 20 and an external clock signal ADC _ CLK, enable signals ADC _ EN and CMP _ EN, and an initial control signal DAC < L:0>, logically process the intermediate digital signal CMP _ OUT and output a first digital signal ADC _ OUT < L:0> and a second digital signal ADC _ RDY to a subsequent stage, logically process the initial control signal DAC < L:0> and output the first target control signal CTL1< M:0> and the second target control signal CTL2< N:0> to the digital-to-analog conversion module 10.
In this embodiment, the digital-to-analog conversion module 10 adopts a two-stage voltage dividing unit structure, and the first voltage dividing unit 11 and the second voltage dividing unit 12 respectively adopt 2M、2NThe resistors are connected in series. The first voltage division unit 11 uniformly divides VREF into 2MAssuming that the resistance value of the resistor R1 of the first impedance subunit 112 is R1, the formula of the consumption current is:
according to the first target control signal CTL1<M:0>Electing 2MOne of the voltages (first intermediate voltage VOT-second intermediate voltage VOB), the first intermediate voltage VOT and the second intermediate voltage VOB are respectively connected to both ends of the second impedance subunit 122 through the second switching subunit 122. The second impedance subunit 122 divides this voltage by 2NAnd the output node directly outputs the target analog signal DAC _ OUT. The second voltage division unit 12 is connected in parallel to both ends of the first voltage division unit 11, which causes a relative error. The formula for this relative error is:
wherein r2 is calculated to be twice r1 assuming that the relative error is less than 0.05% and both M and N are 5. When the first impedance subunit 112 outputs the last node, the resistance values of the last switch S1 of the conducting column and the first switch S2 of the conducting column in the first voltage division unit 11, and the resistance values of the first resistor R2 and the last resistor R2 in the second voltage division unit 12 are combined into a unit resistance value R2; when the second impedance subunit 121 outputs the first node, the switch of the second intermediate voltage VOB is controlled to be turned off.
The analog-to-digital converter provided by the present invention utilizes the digital-to-analog conversion module 10 to realize the conversion from digital signal to analog signal, the first selection switch SHSW1 and the capacitor CAP sample and hold the initial analog signal VIN input by gating, and the second selection switch SHSW2 is used to balance the input voltage (initial analog signal VIN) of the comparison unit 21. The comparing unit 21 compares the initial analog signal VIN with the target analog signal DAC _ OUT output by the digital-to-analog converting module 10, and sends the comparison result (the intermediate digital signal CMP _ OUT) to the logic control module 30. The logic control module 30 adopts SAR logic to make the target analog signal DAC _ OUT generated by the digital-to-analog conversion module 10 approach the initial analog signal VIN according to the comparison result (the intermediate digital signal CMP _ OUT). After one analog-to-digital conversion is finished, updating the result of the analog-to-digital conversion, namely updating the first digital signal ADC _ OUT < L:0>, wherein L is M + N.
In this embodiment, the analog-to-digital converter further includes: and an input end of the buffer module 40 is connected to an output end of the digital-to-analog conversion module 10, and is configured to perform buffer adjustment on the target analog signal DAC _ OUT.
In the analog-to-digital converter provided in this embodiment, in the reset mode, the currents of all the blocks of the analog-to-digital converter are turned off, and the output result of the sampling comparison module 20 and the quantization result output by the logic control module 30 are all pulled low.
In summary, the present invention provides an analog-to-digital converter, including: the digital-to-analog conversion module comprises two stages of voltage division units, and the two stages of voltage division units are used for performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage; the sampling comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; and the logic control module performs logic processing on the intermediate digital signal to obtain a first digital signal and a second digital signal. By arranging the digital-to-analog conversion module, high-precision analog-to-digital conversion can be realized at the same timeThe method realizes accurate digital-to-analog conversion, saves the layout area of the integrated circuit, and improves the adaptability of the analog-to-digital converter on the aspect that the integration level of the integrated circuit is higher and higher. Furthermore, the digital-to-analog conversion module comprises two stages of voltage division units, and 2 of the first stage can be used for passingMA resistor and 2 in the second stageNThe matching of the resistors obtains a target analog signal with higher precision. In addition, the digital-to-analog conversion module provided by the application can output a stable target analog signal (analog voltage signal) to a later stage through two-stage voltage division processing, and the digital-to-analog conversion module has driving capability and has a large output swing amplitude.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. An analog-to-digital converter, comprising:
the digital-to-analog conversion module is used for receiving a first target control signal, a second target control signal and a reference analog signal from the outside; performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage through the first target control signal and the second target control signal; the digital-to-analog conversion module comprises two stages of voltage division units;
the sampling comparison module is used for receiving an external initial analog signal and a target analog signal output by the digital-to-analog conversion module and outputting an intermediate digital signal to a later stage; and (c) a second step of,
and the logic control module is used for receiving the intermediate digital signal output by the sampling comparison module, an external clock signal, an enable signal and an initial control signal, performing logic processing on the intermediate digital signal, outputting a first digital signal and a second digital signal to a rear stage, performing logic processing on the initial control signal, and outputting a first target control signal and a second target control signal to the digital-to-analog conversion module.
2. The analog-to-digital converter according to claim 1, wherein the digital-to-analog conversion module comprises: the device comprises a first partial pressure unit and a second partial pressure unit connected with the first partial pressure unit;
the first voltage division unit includes: the first switch subunit, the first impedance subunit and the second switch subunit are connected in sequence;
the second voltage division unit includes: a second impedance subunit and a third switching subunit connected with the second impedance subunit;
one end of the first impedance subunit is connected with the external reference analog signal, and the other end of the first impedance subunit is grounded; controlling the first switch subunit and the second switch subunit through the first target control signal, and performing voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;
one end of the second impedance subunit is connected with the first intermediate voltage, and the other end of the second impedance subunit is connected with the second intermediate voltage; and controlling the third switch subunit through the second target control signal, and performing voltage division processing on the difference value of the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.
3. The analog-to-digital converter according to claim 2, characterized in that the first impedance subunit comprises: serially connected 2 in turnMA resistor;
the second impedance subunit includes: serially connected 2 in turnNA resistor; wherein M and N are both integers greater than or equal to 1, and M + N is an integer greater than or equal to 10.
4. Analog-to-digital converter according to claim 3, characterized in thatCharacterized in that said first switch subunit comprises: 2MEach first control switch is connected with a series node between two adjacent resistors of the first impedance subunit in sequence;
the second switch subunit includes: 2MThe second control switches are respectively and sequentially connected with a series node between two adjacent resistors of the first impedance subunit;
wherein one of the series nodes is staggered between the first control switch and the second control switch.
5. The analog-to-digital converter according to claim 3, wherein the third switching subunit comprises: 2NAnd each third control switch is sequentially connected with a series node between two adjacent resistors of the second impedance subunit.
6. The analog-to-digital converter according to claim 1, wherein the sampling comparison module comprises: the circuit comprises a first selection switch, a second selection switch, a third selection switch, a capacitor and a comparison unit, wherein the first selection switch is connected with the inverting input end of the comparison unit, the positive pole of the capacitor is connected with a connection node between the first selection switch and the inverting input end of the comparison unit, the negative pole of the capacitor is grounded, and the second selection switch and the third selection switch are both connected to the non-inverting input end of the comparison unit;
and the output end of the digital-to-analog conversion module is connected to the non-inverting input end of the comparison unit through the third selection switch.
7. The analog-to-digital converter according to claim 6, wherein when the analog-to-digital converter is in operation, the first selection switch and the second selection switch are simultaneously closed, so that the same-direction input terminal and the reverse-direction input terminal of the comparison unit receive the target analog signal.
8. The analog-to-digital converter according to claim 6, wherein the third selection switch has a switch operation state opposite to the switch operation states of the first selection switch and the second selection switch.
9. The analog-to-digital converter according to claim 6, characterized in that the comparison unit comprises: the current adder, the preamplifier and the dynamic latch are connected in sequence.
10. The analog-to-digital converter according to claim 1, characterized in that it further comprises: and the buffer module is used for carrying out buffer adjustment on the target analog signal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116094512A (en) * | 2023-02-01 | 2023-05-09 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
| CN116436468A (en) * | 2023-04-17 | 2023-07-14 | 北京士模微电子有限责任公司 | Analog-to-digital converter |
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2022
- 2022-03-03 CN CN202210203072.0A patent/CN114584149A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116094512A (en) * | 2023-02-01 | 2023-05-09 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
| CN116094512B (en) * | 2023-02-01 | 2023-12-12 | 无锡宇宁智能科技有限公司 | Analog direct addition circuit and corresponding electronic equipment |
| CN116436468A (en) * | 2023-04-17 | 2023-07-14 | 北京士模微电子有限责任公司 | Analog-to-digital converter |
| CN116436468B (en) * | 2023-04-17 | 2024-05-31 | 北京士模微电子有限责任公司 | Analog-to-digital converter |
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