CN112865765A

CN112865765A - TFT optical fingerprint reading chip, fingerprint signal processing method and fingerprint module

Info

Publication number: CN112865765A
Application number: CN202110009091.5A
Authority: CN
Inventors: 金玉洁; 蒋大钊
Original assignee: Silead Inc
Current assignee: Silead Inc
Priority date: 2021-01-05
Filing date: 2021-01-05
Publication date: 2021-05-28

Abstract

The invention discloses a TFT optical fingerprint reading chip, a fingerprint signal processing method and a fingerprint module. The first class ADC with high utilization precision and high conversion rate in the digital output signal is converted, and the second class ADC with simple structure is converted in the low order in the digital output signal.

Description

TFT optical fingerprint reading chip, fingerprint signal processing method and fingerprint module

Technical Field

The invention relates to the technical field of fingerprint identification, in particular to a TFT optical fingerprint reading chip, a fingerprint signal processing method and a fingerprint module.

Background

Nowadays, fingerprint identification is widely used in personal identification, and the fingerprint identification utilizes rugged patterns formed on the surface of a finger to identify the identity of a person, wherein an optical fingerprint identification technology is one of fingerprint acquisition methods.

The optical fingerprint chip senses optical signals mainly through a CMOS image sensor, and with the development of a fingerprint identification technology, blind touch identification or large-area fingerprint identification is gradually favored, so that the fingerprint identification experience of a user is improved. As the area of the optical fingerprint sensing area of the CMOS image sensor in the optical fingerprint sensor increases, the manufacturing cost of the CMOS image sensor increases too much, so that the application of the CMOS image sensor in the large-area optical fingerprint sensing area is limited. Different from a CMOS image sensor, the TFT (thin Film transistor) photosensitive array sensor has low manufacturing cost and can be directly attached to a display screen for use, so that the large-area optical sensing technical scheme of the TFT photosensitive array sensor is widely applied.

However, the TFT photosensitive material cannot generate a large signal difference for the difference between the fingerprint valley and the fingerprint ridge, and is weaker than that obtained by the CMOS image sensor, so how to convert the fingerprint optical signal collected by the TFT photosensitive sensor array into a clear fingerprint image becomes a problem to be solved in the market application of the optical fingerprint module.

Disclosure of Invention

The invention aims to provide a TFT optical fingerprint reading chip, a fingerprint signal processing method and a fingerprint module, which are used for solving the problem that a TFT photosensitive material in the prior art cannot generate larger signal difference for fingerprint valley and ridge difference.

In order to solve the above technical problem, the present invention provides a TFT optical fingerprint readout chip electrically connected to a TFT photosensitive array sensor, where the TFT optical fingerprint readout chip includes a photosensitive array sensor sampling circuit, an analog-to-digital conversion circuit, and a data processing module, the photosensitive array sensor sampling circuit is configured to receive an analog signal output by the TFT photosensitive array sensor, the analog-to-digital conversion circuit is configured to convert an output signal of the photosensitive array sensor sampling circuit into a digital signal, and the analog-to-digital conversion circuit includes:

the first ADC receives an output signal of the photosensitive array sensor sampling circuit and outputs a first digital signal and an analog residual signal;

the second-class ADC is arranged at the rear stage of the first-class ADC, receives the analog residual signal and outputs a second digital signal;

the data processing module is used for outputting corresponding digital output signals based on the first digital signals and the second digital signals;

the conversion precision of the first class of ADC is higher than that of the second class of ADC, the first digital signal and the second digital signal form the digital output signal, the first digital signal is a high order bit of the digital output signal, and the second digital signal is a low order bit of the digital output signal.

Optionally, the number of bits of the first digital signal is less than the number of bits of the second digital signal.

Optionally, the first ADC is a pipeline ADC and the second ADC is a ramp ADC.

Optionally, the analog residual signal is a pair of differential signals, and the ramp ADC includes a fully differential comparator for accepting the pair of differential signals.

Optionally, the ramp ADC further comprises a ramp generator, an output of the ramp generator being connected to an input of the fully differential comparator.

Optionally, the ramp ADC further comprises an up-down counter connected to an output of the fully differential comparator.

Optionally, the up-down counter includes an input for accepting an initial value from which the up-down counter counts up or down.

Optionally, the up-down counter is provided with a first counting window and a second counting window within a unit duty cycle of the ramp ADC;

and when the first counting window and the second counting window are used, the counting directions of the up-down counter are opposite and the counting values are continuous.

Optionally, the initial value of the up-down counter satisfies the following formula:

(2ⁿ-1)-T2/Tclk≥X>T1/Tclk；

wherein X is the initial value, Tclk is the clock cycle of the up-down counter, T1 is the first count window time, T2 is the second count window time, 2ⁿ-1 is the maximum value that the up-down counter can count within a unit duty cycle of the ramp ADC.

Optionally, the second digital signal is a result of subtracting the initial value from an output of the ramp ADC.

Optionally, the data processing module comprises a first static memory and a second static memory;

the first static memory is used for storing the first digital signal, and the second static memory is used for storing the second digital signal.

Optionally, the data module further comprises a data processing part;

the data processing part is used for performing compensation processing on the output of the first static memory or the output of the second static memory, and the compensation processing comprises the following steps:

and multiplying the output of the first static memory/the second static memory by a compensation coefficient, and splicing the output of the first static memory/the second static memory and the output of the second static memory/the first static memory into the digital output signal with preset bits.

Based on the same inventive concept, the invention also provides a processing method of the TFT optical fingerprint signal, which is used for converting the analog signal output by the TFT photosensitive array sensor into a digital signal, and the processing method comprises the following steps:

sampling the TFT photosensitive array sensor by using a photosensitive array sensor sampling circuit;

a first part of signals in the signals output by the photosensitive array sensor sampling circuit are converted into high-order digital signals with preset digits by using a first ADC;

the difference value between the signal output by the photosensitive array sensor sampling circuit and the first part signal is converted into a low-bit digital signal with preset bits by using a second ADC; and

utilizing a data processing module to splice the low-bit digital signal/the high-bit digital signal multiplied by a compensation coefficient and the high-bit digital signal/the low-bit digital signal into a digital signal with a preset bit;

wherein the conversion precision of the first type of ADC is greater than that of the second type of ADC.

Based on the same inventive concept, the invention also provides a TFT optical fingerprint module, which comprises a TFT photosensitive array sensor and a TFT optical fingerprint reading chip in any one of the above characteristic descriptions;

the pixel array in the TFT photosensitive array sensor is used for acquiring the lines on the surface of the finger and outputting a corresponding analog signal;

the analog-to-digital conversion circuit is used for connecting corresponding columns in the pixel array and converting analog signals in the corresponding columns into digital output signals.

Compared with the prior art, the invention has the following beneficial effects:

1. the TFT optical fingerprint reading chip provided by the invention comprises a TFT photosensitive array sensor, a photosensitive array sensor sampling circuit, an analog-to-digital conversion circuit and a data processing module, wherein the photosensitive array sensor sampling circuit is used for receiving an analog signal output by the TFT photosensitive array sensor, and the analog-to-digital conversion circuit is formed by splicing a first type ADC and a second type ADC. The first class ADC with high utilization precision and high conversion rate in the digital output signal is converted, and the second class ADC with simple structure is converted in the low order in the digital output signal.

2. The mode selector for switching the initial assignment mode or the normal counting mode and the counter with the function of assigning the initial value are added in the up-down counter in the technical scheme of the invention, so that the up-down counter can start to count up or down from the initial value by inputting the initial value externally, and the counting time of the up-down counter is controlled to ensure that the counting of the up-down counter is not triggered to the boundary value of the counting range and then continues to count, and therefore, the wrong counting is not triggered.

The TFT optical fingerprint signal processing method, the fingerprint sensor and the fingerprint identification system belong to the same inventive concept with the TFT optical fingerprint reading chip, and therefore have the same beneficial effects.

Drawings

FIG. 1 is a schematic diagram of a circuit configuration for reading a TFT photosensitive array sensor using a readout circuit configuration of a CMOS image sensor;

fig. 2 is a schematic structural diagram of a TFT optical fingerprint reading chip according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a ramp ADC;

FIG. 4 is a circuit timing diagram generally corresponding to the ramp analog-to-digital converter of FIG. 3;

FIG. 5 is a schematic diagram of a pipeline ADC;

FIG. 6 is a diagram of a transfer function image of a pipeline substage conversion circuit;

FIG. 7 is a block diagram of an embodiment of a ramp ADC according to the present application;

FIG. 8 is a schematic diagram of an embodiment of a fully differential comparator that may be used in FIG. 7;

FIG. 9 is a working example corresponding to the fully differential comparator shown in FIG. 8;

FIG. 10 is an internal timing diagram corresponding to the fully differential comparator shown in FIG. 8;

FIG. 11 is a schematic diagram of a four-stage asynchronous counter used in a conventional ramp generator;

FIG. 12 is a schematic diagram of the internal structure of a one-stage up-down counter;

FIG. 13 is a timing diagram illustrating the operation of the up-down counter of FIG. 11;

FIG. 14 is a diagram illustrating an internal structure of a single-stage counter circuit according to an embodiment of the up-down counter of the present application;

FIG. 15 is a schematic diagram of a plurality of single-stage counter interconnect structures of FIG. 14;

FIG. 16 is a timing diagram illustrating the initial assignment of the up-down counter of FIG. 15;

FIG. 17 is a schematic diagram of the multi-stage counter of FIG. 15 configured as an up-down counter;

FIG. 18 is a schematic diagram of a splicing method of the first digital signal and the second digital signal;

FIG. 19 is a schematic diagram of another splicing method of the first digital signal and the second digital signal;

fig. 20 is a schematic structural diagram of a fingerprint sensor according to another embodiment of the present invention;

wherein: 10-TFT optical fingerprint reading chip.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In order to facilitate understanding of the technical solutions of the present application, the related art related to the present application is briefly described below.

If the structure of the readout circuit for processing the CMOS image sensor is used to read the signal output by the TFT photo sensor array, as shown in fig. 1, such a readout chip needs to include: sampling circuit, ADC and data processing module.

In order to enable the TFT photosensitive array sensor to output a fingerprint signal and finally obtain a relatively clear fingerprint image, the invention provides a TFT optical fingerprint reading chip 10. Please refer to fig. 2 for a schematic diagram. The TFT optical fingerprint reading chip 10 includes a sampling circuit, an analog-to-digital conversion circuit, and a data processing module. The sampling circuit is used for receiving the analog signal output by the TFT photosensitive array sensor. The analog-to-digital conversion circuit is used for converting the output signal of the sampling circuit into a digital signal, and comprises: the first ADC receives the output signal of the sampling circuit and outputs a first digital signal and an analog residual signal; and the second-class ADC is arranged at the rear stage of the first-class ADC and used for receiving the analog residual signal and outputting a second digital signal. The data processing module is used for outputting corresponding digital output signals based on the first digital signals and the second digital signals;

wherein, the conversion precision of the first type of ADC is higher than that of the second type of ADC. The first digital signal is a high order bit of the digital output signal and the second digital signal is a low order bit of the digital output signal. The first type of ADC may employ a pipeline analog-to-digital converter and the second type of ADC may employ a ramp analog-to-digital converter.

Generally, the circuit structure of the ramp adc can be seen from fig. 3, and the circuit structure of the ramp adc can include a ramp generator, a comparator, a counter and a data latch output unit. The basic working principle of the ramp analog-to-digital converter is as follows: the analog signal (channel sampling level) input firstly is sent to the positive phase end of the comparator after passing through the photosensitive array sensor sampling circuit, and the output signal (ramp level) of the ramp generator is sent to the negative phase end of the comparator. Then, based on the previous description of the connection of the input end of the comparator, the comparator compares the two input signals, and when the output level of the ramp generator is less than the channel sampling level, the output of the comparator is low level; when the output level of the ramp generator rises above the channel sample level, the comparator output flips from a low level to a high level. When the comparator outputs a high level, the data latch output unit stops latching and outputs the state of the counter at the moment, so that the conversion from the analog level to the digital level is realized.

Referring to fig. 4, fig. 4 is a circuit timing diagram of a ramp analog-to-digital converter substantially corresponding to fig. 3. As shown in fig. 4, the ramp adc operates with two windows. The first time window is used for collecting the background noise information, so the channel level range is relatively small, and the time for windowing can be shorter; but the second time to acquire signal information, a larger ramp range adaptation is required. The precision of the ramp adc is limited by the clock speed of the counter (counter), and when the number of bits is too large, the flip-flop delay is too long to achieve a higher clock speed, so that a higher precision column-level adc cannot be achieved.

Compared with a ramp analog-to-digital converter, a pipeline analog-to-digital converter (pipeline ADC) has the advantages of higher precision, higher conversion speed and the like. Referring to fig. 5, fig. 5 is a schematic structural diagram of a pipeline analog-to-digital converter. As shown in fig. 5, the pipeline analog-to-digital converter includes a Sample-hold amplifier (SHA) and a K-stage pipeline sub-stage conversion circuit. Each pipeline sub-stage conversion circuit includes 1 low power consumption sub-ADC and 1 residue gain Digital-to-analog Converter (MDAC). Each sub-ADC pair input Vin is first sampled by a sample/hold (S/H) circuit, while the first stage ADC quantizes it to n bits, which are output to an n-bit DAC, the input signal minus the DAC output is amplified 2ⁿAnd (4) feeding the sample to the next stage, and continuously repeating the process, wherein each stage provides n bits until the last stage. For a certain sampling, the results of each stage are aligned in time by a shift register before digital error correction, since each stage gets the transformed result at a different time. As can be seen from fig. 5, the higher the accuracy, the more sub-stage circuits are required, resulting in a larger area of the pipeline ADC. A high-precision pipelined ADC cannot be used on a high-precision small-area column-level analog-to-digital converter.

The difference from the conventional optical readout chip is that the TFT optical fingerprint readout chip 10 provided in the embodiment of the present invention includes a TFT photosensitive array sensor, a photosensitive array sensor sampling circuit, an analog-to-digital conversion circuit, and a data processing module, where the photosensitive array sensor sampling circuit is configured to receive an analog signal output by the TFT photosensitive array sensor, and the analog-to-digital conversion circuit is formed by splicing a first type ADC and a second type ADC. The first class ADC with high utilization precision and high conversion rate in the digital output signal is converted, and the second class ADC with simple structure is converted in the low order in the digital output signal.

It should be noted that, in order to facilitate understanding of the technical solution of the present invention, in the embodiment of the present invention, the first type ADC may adopt a pipeline ADC with high precision and fast conversion rate. Correspondingly, the second class of ADC can adopt a ramp ADC with a simple structure and a small occupied area. To explain the technical solution in the present application more specifically, the following description is made in conjunction with the above-described two ADCs and the number of bits required for the specific conversion of the analog signal. For example, it is necessary to convert an analog signal into a 15-bit digital signal, wherein the pipeline ADC converts the high bits of 2.5 bits, the ramp ADC converts the low bits of 13 bits, and the data processing module finally splices the high bits of 2.5 bits and the low bits of 13 bits into a 15-bit digital signal. It will be appreciated that in other implementations, there are many other ways of splicing. For example, a 16-bit analog-to-digital conversion circuit can be spliced by using a 3-bit pipeline ADC and a 13-bit ramp ADC, a 17-bit analog-to-digital conversion circuit can be spliced by using a 3-bit pipeline ADC and a 14-bit ramp ADC, and many other splicing methods are available. In addition, in other embodiments, the first type of ADC may also be implemented by using other ADCs with high precision and fast conversion rate, and the second type of ADC may also be implemented by using other ADCs with simple structure, which are not described herein in detail.

In the embodiment described herein, the pipelined ADC performs only the conversion of the 2.5-bit high-order data of the 15-bit data when performing the analog-to-digital conversion as the first ADC. The difference signal of the analog signal output by the photosensitive array sensor sampling circuit and the analog signal converted corresponding to 2.5bit high-order data received by the pipeline ADC is used as the input of the second ADC. The photosensitive array sensor sampling circuit is a related double sampling circuit, and the output of the photosensitive array sensor sampling circuit enters a pipeline ADC. As shown in fig. 6, a transfer function image of the pipeline sub-stage conversion circuit is shown. Referring to FIG. 5, Pipe _ inP and Pipe _ inN are differential inputs of the pipeline substage converting circuit, and Pipe _ inP corresponds to the previous differential output V_OPPipe _ inN corresponds to the differential output V of the previous stage_ONThe Pipe _ outP and the Pipe _ outN correspond to the differential output of the stage of ADC, and the differential output is input into the ramp ADC as a residual (the analog residual signal) and is calibrated for the lowest bit output of the 2.5-bit pipeline ADC.

Referring to fig. 5, it can be understood that the output of the pipeline ADC is divided into two types, namely, the first digital signal and the analog residual signal, wherein the first digital signal is directly output to the data processing module, and the analog residual signal is output to the ramp ADC at the next stage. The conversion relationship between the differential signal and the analog residual signal in the pipeline ADC can refer to table 1. The difference between the two outputs of the pipeline ADC, Pipe _ outP and Pipe _ outN, is within a range of ± Vr, and 2Vr is also the full scale of the pipeline ADC, which is also the full scale of the 15-bit analog-to-digital conversion circuit in this embodiment.

TABLE 1

Vip–Vin(Pipe_inP–Pipe_inN)	Vop–Von(Pipe_outP–Pipe_outN)
		(Vip-Vin)>5/8*Vr	4(Vip-Vin)–3*Vr
5/8Vr>(Vip-Vin)>3/8Vr	4(Vip-Vin)–2*Vr
		3/8Vr>(Vip-Vin)>1/8Vr	4(Vip-Vin)–1*Vr
1/8Vr>(Vip-Vin)>-1/8Vr	4(Vip-Vin)–0*Vr
		-1/8Vr>(Vip-Vin)>-3/8Vr	4(Vip-Vin)+1*Vr
-3/8Vr>(Vip-Vin)>-5/8Vr	4(Vip-Vin)+2*Vr
		-5/8*Vr>(Vip-Vin)	4(Vip-Vin)+3*Vr

Referring to fig. 7, the ramp ADC is different from the general ramp ADC in that a fully differential comparator is used to receive the analog residual signal output by the pipeline ADC. As shown in fig. 7, the ramp ADC includes a ramp generator, a fully differential comparator, an up-down counter, and a data latch output unit, which are connected in sequence. The assembly line ADC is connected with the input end of the fully differential comparator, and the ramp generator is used for outputting a ramp level to the fully differential comparator. The fully differential comparator is used for receiving the analog residual signal and the ramp level and outputting a level signal. The up-down counter is used for outputting the second digital signal to the data latch output unit based on the level signal, and the data latch unit is used for outputting the currently latched second digital signal to the data processing module when the level signal is inverted from low level to high level. In the embodiment of the present invention, the ramp ADC is 13 bits, and those skilled in the art can understand that in other embodiments, the ramp ADC may also have other bits, which is not limited herein.

As can be seen from fig. 7, in the embodiment of the present invention, the output terminals of the fully differential comparator include a positive input and a negative input, where the other two inputs are the ramp level Vramp and the common mode level Vcom _ comp of the comparator. The ramp level Vramp is a ramp signal which changes continuously along with time change, when the difference value between the ramp signal Vramp and the comparator common mode signal Vcom _ comp is larger than the difference value between the sampled analog residual signal Pipe _ outP and Pipe _ outN of the previous stage pipeline ADC, the output of the fully differential comparator, that is, the result of the main amplifier, is inverted, and the counter at the rear end is stopped, so that the information of the sampling level of the channel at this time is obtained.

Please refer to fig. 8, which is a schematic diagram of an embodiment of the fully differential comparator in fig. 7. As shown in fig. 8, the fully differential comparator includes a main amplifier, a first stage preamplifier, and a second stage preamplifier. The input ends of the first-stage preamplifier and the second-stage preamplifier are connected with capacitors, as shown in fig. 8, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. The first stage preamplifier and the second stage preamplifier shown in fig. 8 are all fully differential amplifiers. Fig. 9 and 10 correspond to the working example of the fully differential comparator shown in fig. 8 and the internal timing diagram. As can be seen from fig. 9, the embodiment of the fully differential comparator illustrated in fig. 8 can complete the operation of the fully differential comparator illustrated in fig. 7. Therefore, for the working schematic diagram shown in fig. 8 and fig. 9, reference may be made to the description of fig. 7, which is not repeated herein. The following describes the specific operating states of the fully differential comparator shown in fig. 8 at each timing, with reference to fig. 10:

before time t0, the operational amplifier of the ramp generator keeps a reset state, and the output end level keeps the reset level Vcom _ ramp of the operational amplifier;

at the time t0, the voltage at the output end of the ramp generator is pulled down to the initial level Vramp _ rst of the ramp level, and meanwhile, the difference Vramp _ rst-Vcom _ comp between the initial level of the ramp level and the common mode level of the comparator is ensured to be smaller than the differential input Pipe _ output-Pipe _ output, otherwise, the comparator is directly turned over, and effective differential input information cannot be obtained;

at time t1, the comparison time window is opened, and the ramp level output by the ramp generator begins to change along with the time, wherein the ramp level increases along with the time at the speed of the slope K (V/s);

at time t2, the ramp level reaches the comparator trip point, and meets the condition that Vramp-Vcom _ Comp is Pipe _ outP-Pipe _ outN, at this time, the output of the fully differential comparator is reversed, and Comp _ out is pulled high from low level to high level;

at time t3, the comparison window is ended, the ramp generator's operational amplifier is reset, and the output terminal is pulled to Vcom _ ramp to wait for the next comparison time window.

The internal working state of the fully differential comparator proposed in the embodiment of the present invention at the time sequence shown in fig. 12 is as follows:

at time t1, pull high simultaneously

And

holding

At a low level, at this time, the switches s3, s4, s5, s6, s7 and s8 are closed, the switches s5, s6, s7 and s8 are closed to complete the reset of the first-stage preamplifier and the second-stage preamplifier, the switches s3 and s4 are closed to sample the levels of Pipe _ outP and Pipe _ outN to the fifth capacitor C5 and the sixth capacitor C6 respectively, at this time, the level of the node 1 is Pipe _ outP, the level of the node 2 is Pipe _ outN, and the levels of the

nodes

3 and 4 are the reset level Vrst of the first-stage preamplifier;

at time t2, pull low

Holding

At the high level of the voltage, the voltage is high,

when the voltage is at a low level, the reset of the first-stage preamplifier is finished;

at time t3, pull low

Holding

At the low level of the voltage, the voltage is low,

at the high level of the voltage, the voltage is high,

at low level, at which point the second stage preamplifier reset is over,

slightly lags behind

The mutual influence between the two stages of pre-amplifiers can be reduced by pulling down;

at time t4, pull low

Holding

At the low level of the voltage, the voltage is low,

when the voltage is at a low level, the sampling of the output level of the pipeline ADC is completed;

at time t5, pull high

Holding

At low level, the ramp generator voltage Vramp and common mode level Vcom _ comp are sampled onto the fifth capacitor C5 and the sixth capacitor C6, where the level of node 1 is Vramp and the level of node 2 is Vcom _ comp. Due to the characteristic that the voltage difference between the two ends of the capacitor is unchanged, before time t5, the voltage difference between the two ends of the fifth capacitor C5 is Pipe _ outP-Vrst (left-right), the voltage difference between the two ends of the sixth capacitor C6 is Pipe _ outN-Vrst (left-right), after time t5, the voltage difference between the two ends of the fifth capacitor C5 and the sixth capacitor C6 remains unchanged, at this time, the voltage of the node 3 is Vramp- (Pipe _ outP-Vrst), the voltage of the node 4 is Vcom _ comp- (Pipe _ outN-Vrst), as the level of the ramp generator gradually increases, the level of the node 3 gradually approaches the level of the node 4, when the level of the node 3 is equal to the level of the node 4, the output of the comparator is inverted, that is, pulled up from the low level to the high level, that is, when vrop- (Pipe _ outN-Vrst) is equal to pip _ outN-comp- (Pipe _ outN-Vrst), the voltage of the:

Vramp＝Vcom_comp-(Pipe_outP-Pipe_outN)。 (4)

the upper counter and the lower counter are required to be connected behind the fully differential comparator, and because the working mode of the fully differential comparator is continuous comparison and the condition that Vramp-Vcom _ comp is more than or equal to Pipe _ outP-Pipe _ outN is required to be met, the output of the fully differential comparator can be inverted so as to stop the counting of the upper counter and the lower counter at the rear stage, the time required by the basic mode is longer, and the processing speed is slower when the two-time conversion time of the ADC is longer. Through the above description of the operation of the fully differential comparator in the ramp ADC, the following method can be used to increase the conversion speed of the ramp ADC:

the first method comprises the following steps: when the channel sampling level range is small, a voltage value can be added or subtracted through a differential operational amplifier circuit of a first stage in a fully differential comparator in the ramp ADC, so that the difference value of Pipe _ outP-Pipe _ outN is reduced, and the time required by comparison is shortened;

the second method comprises the following steps: when the channel sampling level range is small, the initial level Vramp _ rst of a ramp generator in the ramp ADC and the common mode level Vcom _ comp of the fully differential comparator can be adjusted, and the time required for comparison is shortened.

Fig. 10 is a schematic diagram of an internal timing sequence of the fully differential comparator corresponding to fig. 8, and it should be understood that these are only exemplary descriptions for facilitating understanding of the technical solution of the present application, and do not limit the scope of the patent claimed in the present application.

The counter connected to the output terminal of the comparator in the ramp ADC is further described and illustrated below, and the counter in the present application can avoid erroneous counting and ensure the accuracy and precision of analog-to-digital conversion performed by the ramp ADC. The counter in a common ramp ADC is made up of an asynchronous counter that adds up/down count switching control and holds the current value control. Fig. 11 is a schematic diagram of a four-stage asynchronous counter used in a conventional ramp ADC. Of course, the asynchronous counter may include more stages of counters, which are illustrated and described herein as four stages. As shown in fig. 11, each D flip-flop is an edge flip-flop, RN is a global reset signal, HOLD is a global HOLD signal, the up-down signal is a global control signal for switching to count up or count down, the clkout output of the previous stage is connected to the clkin input of the next stage and used as a clock signal, and count _ out of each stage is the counter output of the stage. The multistage asynchronous counter in the slope ADC is mainly used by being matched with a photosensitive array sensor sampling circuit at the front stage of the slope ADC, and digital related double sampling of the photosensitive array sensor sampling circuit is realized. In conjunction with the operation mode of the counter described in fig. 4, the counter will count twice during the unit operation period of the ramp ADC. In the example schematically depicted in fig. 4, the first count is a down-count and the second count is an up-count. The first counting is to obtain the bottom noise information, and the second counting is to obtain the actual signal information. The real signal information can be obtained after the counting in the two opposite directions is performed through the self subtraction function of the counter. Of course, in other embodiments, the first count may be up and the second count may be down. Therefore, the counter in such a ramp ADC may be referred to as an up-down counter. Fig. 12 is a schematic diagram illustrating an internal configuration of a one-stage up-down counter, and fig. 13 is a timing chart illustrating an operation of the up-down counter shown in fig. 11.

Before comparison, resetting each stage of the counter to 0, pulling up an RST (reset) signal after the reset is finished, pulling up a HOLD signal after the first comparison is finished, and connecting the Q output of the D flip-flop to the D end to be used as input data, so that the output of the D flip-flop cannot be changed by the change of an externally accessed clock signal. When the HOLD signal is held at a high level, the up-down signal is inverted. If counting downwards first, the initial state of the up-down signal is high level, the initial state of the up-down signal is low level after turning over, and the up-down signal enters into an up-counting mode; if count up earlier, the upper and lower signal initial state is the low level, and the upset back is the high level, gets into count down mode, can be as required, and the free choice is to count down the mode, only need guarantee twice opposite direction count can. If the HOLD signal is not pulled high, the toggling of the up and down signals will change the input of the current D flip-flop to the next stage clock signal. Taking default initial count-down as an example, if Q of a certain stage is 1 and QB is 0, the clock output signal clkout will change from 0 to 1 during up-down switching, forming an edge trigger, and making the D flip-flop of the next stage read QB, so that the HOLD signal is pulled high during up-down switching, and the counter result can be kept to keep the value after the first comparison in the time window between two comparisons.

In some embodiments of the present invention, the up-down counter may be implemented using a counter structure as shown in fig. 11, however, the inventors have found in practical applications that the up-down counter structure as shown in fig. 11 has the following disadvantages: the up-down counter with such a structure and operation mode may trigger a count limit value of the counter during counting, and thus may cause erroneous counting. For example, in the embodiment of the present invention, a counter of 13 bits is required, and if a 13-bit counter is used, the range of the counter is 0-8191 (2)¹³-1-8191), if the counter is reset to a default value of 0, the reset signal is compared for the first time to count down to a value below 8191 (e.g. 7500), and if the signal size is smaller than the reset signal size during the second time of counting up, the final counting result may still be a larger value (e.g. 8100) close to 8191, and it may not be determined whether the count has crossed 0 or not reached 0, which may have a great influence on the determination of the conversion result.

Based on the above findings, the inventors propose a novel up-down counter that can be applied in a ramp ADC. The novel up-down counter in the application can be used for counting up or down from the initial value by inputting the initial value of the up-down counter externally, and can ensure that the up-down counter continues counting (namely, false counting) after the up-down counter does not trigger to 0 or 8191 limit value after counting twice by combining with the control of the counting time of the up-down counter.

Please refer to fig. 14, 15 and 16 for a schematic diagram of an embodiment of the novel counter. Fig. 17 is a schematic diagram of an embodiment of the novel counter based on the four-stage connection illustrated in fig. 14, 15 and 16. Fig. 14 is a schematic diagram of an internal structure of a single-stage counter circuit in the up-down counter, fig. 15 is a schematic diagram of a connection structure between stages of the up-down counter, and fig. 16 is a schematic diagram of an initial assignment of the novel up-down counter.

The novel up-down counter comprises a plurality of stages of counters which are connected with each other, and the counters of each stage are connected with each other through a working mode selector. Each stage of counter is provided with an initial value input end and an initial control signal init-hold which corresponds to whether the initial value is controlled to be assigned or not. Each stage of counter comprises an initial data selection mode selector, a trigger and a trigger output end selector. One input end of the initial data selection mode selector is an initial value input end of the counter, and the initial data selection mode selector is controlled by an initial control signal init-hold. The counter has a hold mode and a count up and down mode. Correspondingly, the output end of the flip-flop in the counter is provided with a holding output selector and an up-down counting selector. The input end of the holding output selector is connected with the output of the trigger, and the output end of the holding output selector is connected with one input end of the initial data selection mode selector. The enable signal of the hold output selector is controlled by the counter hold-hold signal. The input end of the up-down counting selector is linked with the output end of the trigger, and the output end of the up-down counting selector is used as one of the output ends of the counter. The enable terminal of the up-down count selector is controlled by an up-down count-up signal. The output end of the trigger is one of the output ends of the counter.

In order to realize the expected initial assignment and normal counting modes of the counters at all stages, the counters at all stages are connected through a working mode selector. The input signal of the working mode selector is one of the output signals of the preceding stage counter, and the other input end is an initial setting clock signal. The enable signal of the operation mode selector is controlled by an initial setting signal init _ set. The connection mode of the working mode selector of the first stage counter is different from that of the working mode selector arranged between the counters of different stages.

The up-down counter also includes a logic gate section. This logic gate section receives the output of the comparator in the ramp ADC. The output of the logic gate circuit is connected with the input end of the working mode selector of the first stage counter. In the embodiment illustrated in fig. 17, this logic gate circuit section includes a first and gate and a second and gate. A first input end of the first AND gate receives a clock signal Counter _ clk of the up-down Counter, and a second input end of the first AND gate receives a comparison enable signal Comp _ en; the output end of the first AND gate is connected with the first input end of the second AND gate, and the second input end of the second AND gate is used for receiving the output signal of the comparator in the ramp ADC after the inversion processing.

It should be noted that in the embodiments of fig. 14 to 17, all the flip-flops illustrated in the counter are implemented by D flip-flops. Due to the characteristics of the D flip-flop, the data at the data input end can be read only after the external clock is excited to be connected. Therefore, the input terminal of the working mode selector receives an initial setting clock signal for an external clock signal required when the counter of the internal D flip-flop receives an initial assignment. In other embodiments, the flip-flop may also be another type of flip-flop, for example, an RS flip-flop, a T flip-flop, or a JK flip-flop, and when the RS flip-flop, the T flip-flop, or the JK flip-flop is selected for implementation, some logic circuits need to be added to implement the same function as the D flip-flop.

Fig. 16 is a timing diagram of the up-down counter in the initial assignment process, and the states of the up-down counter in the initial assignment process described herein are described as follows with reference to fig. 14, fig. 15, and fig. 17:

at the time of t1, raising an init _ hold signal, keeping the init _ set _ clk and init _ set signals in a low level state, when the init _ set is in the low level state, not directly connecting each stage of the counter, in a mode of waiting for an external clock mode to give an initial value, raising the init _ hold signal, cutting off an internal loop of each stage of the counter, entering an external assignment mode, and connecting a D input end of an n-th stage D trigger with external data D < n >;

at the time of t2, pulling up the init _ set _ clk signal, keeping the init _ hold signal in a high level state, keeping the init _ set in a low level state, exciting an external clock of the D trigger at the moment, writing external data D < n > into the D trigger, enabling the output of Count _ out < n > to be D < n >, and finishing the assignment of an initial value;

at the time t3, pulling down the init _ hold, keeping the init _ set _ clk in a high level state, keeping the init _ set in a low level state, and reconnecting the loop of the counter;

at time t4, it keeps init _ hold low, pulls it up _ set, keeps it _ set _ clk high, and each stage of the counter is connected to form an asynchronous counter and starts counting. If init _ set _ clk is already pulled low at time t4, and the clkout of the previous stage is already at a high level, when init _ set is pulled high, the previous stage will receive a rising edge trigger, causing an erroneous count;

at time t5, init _ hold is held low, init _ set is high, and init _ set _ clk is pulled low to reset.

Referring to fig. 17, fig. 17 is a schematic structural diagram of the up-down counter with four-level connection having 13-bit counter function according to the embodiment of the present invention, wherein: counter _ clk is a clock signal of the up-down Counter, and a clock period is set to be Tclk; comp _ en is the comparative active time control signal, and is an active comparative time window when Comp _ en is at a high level; the Comparator _ out is the output of the previous Comparator, i.e. the level signal, and is determined to be within the effective comparison time window, and the time node of the up-down counter is stopped; init _ set _ clk, init _ set, init _ hold, up, down, reset are global control signals, D <3:0> is an initial value to be assigned, each stage of count _ out is the output of a counter of each stage, and each stage of clkout is the clock excitation of the next stage.

13-bit counter is assigned an initial value D<3:0>₂Last (10 system X)₁₀) It is possible to ensure that the counter does not count to 0 or 8191 limits by controlling the length of the time window for the first and second comparisons. Taking the first count down count and the second count up count as an example, taking the first comparison time window as T1 as an example, the period of the current counter is Tclk(s), that is, the counter value is decreased by one every Tclk time, and this period is multiplied by the slope K (V/s) of the ramp generator, so as to obtain the LSB (Least Significant Bit) size of the ramp ADC as Tclk K. The digital correlation double sampling noise reduction method of the ramp ADC needs to be ensured in a comparison time window, the output of the fully differential comparator needs to be capable of being inverted to obtain effective channel level information, and the condition that the output of the fully differential comparator is inverted is Vramp-Vcom _ comp>Pipe _ outP-PipeoutN, so Vramp _ rst + T1/Tclk × ramp LSB is needed>Vcom_comp+(Pipe _ outP-Pipe _ outN), i.e.:

Vramp_rst+T1*K>Vcom_comp+(Pipe_outP–Pipe_outN)(5)

after the range of T1 is determined, the value of the first count-down is T1/Tclk, and only by ensuring that the X of the first assignment is larger than T1/Tclk, the limit value of 0 can not be triggered during the count-down.

In the limit, the time required for the first comparison is very short, the value kept by the counter after the first counting is finished is slightly smaller than the initial value X, and the time window T2 during the second counting needs to ensure that T2/Tclk + X is not more than or equal to 8191 to prevent the overflow of 8191, that is:

T2≤(8191-X)*Tclk (6)

in summary, in conjunction with equations 5 and 6, it can be deduced that the initial value of the up-down counter satisfies:

(2ⁿ-1)-T2/Tclk≥X>T1/Tclk； (7)

wherein X is the initial value, Tclk is the clock cycle of the up-down counter, T1 is the first count window time, T2 is the second count window time, 2ⁿ-1 is the maximum value that the up-down counter can count within a unit duty cycle of the ramp ADC. Setting the initial value to satisfy equation (7) ensures that the final result of the up-down counter will not reach the limit boundaries of 0 and 8191.

Comparing fig. 11 and 17, it can be seen that the up-down counter embodiment described above with respect to fig. 17 differs from the up-down counter embodiment described with respect to fig. 11 in that the up-down counter in the ramp ADC, which is a second type of ADC, includes an input for accepting an initial value by which the up-down counter counts up or down. When the first counting window and the second counting window in the unit working period of the ramp ADC are used, the counting directions of the up-down counter are opposite, and the counting values are continuous.

An up-down counter of the type described in FIG. 17 that can be initialized retains the hold and updown selection modes of the up-down counter described in FIG. 11. However, the up-down counter which can be endowed with the initial value is internally provided with an initial data selection mode selector which can cut off the loop of the output of the holding output selector to the data input end of the D flip-flop. The initial data selection mode selector is controlled by an init _ hold signal, and the other input end of the initial data selection mode selector is connected with initial data to be assigned. And a working mode selector is connected to the joint between each stage, and the selector can be used for switching an initial assignment mode or a normal counting mode. Due to the characteristic of the D flip-flop, the data at the data input end (D) can be read only after the external clock excitation is switched on, and the init _ set _ clk signal input at the input end of the working mode selector provides the external clock excitation required by the initial assignment.

The counters of the up-down counter and each stage of counters can realize the switching of two working modes of an initial assignment mode or a normal counting mode. The up-down counter of the ramp ADC can start to count up or down from the initial value by inputting the initial value externally, and the counting time of the up-down counter is controlled, so that the two times of counting of the up-down counter can be ensured not to trigger the counting to be continued after the limit value of the counting range in one working cycle of the ramp ADC, and therefore, the wrong counting can not be triggered.

Theoretically, since the up-down counter of the ramp ADC sets an initial value, the final result of the up-down counter minus the given initial value needs to be converted into the code of the ramp ADC as the analog residual signal of the pipeline ADC of the previous stage. When the second comparison voltage range of the ramp generator is the same as the range of the pipeline stage ADC, the output results can be spliced directly. Referring to fig. 18, B2, B1, and B0 are values obtained by converting the high bits twice and outputting the pipeline ADC, i.e. the first digital signal, a12 to a0 are final counter results obtained by comparing twice, the initial value is a value assigned in advance by an up-down counter, and a value obtained by subtracting the initial value from a value a12 to a0 is the second digital signal. Since the analog residual signal of the pipeline ADC is output to the ramp ADC, the most significant bit of the ramp ADC needs to be aligned with the least significant bit of the pipeline ADC.

However, due to process engineering issues, the ramp generator range of the ramp ADC and the pipeline ADC range may not be completely coincident, requiring a matchThe final result generated by the up-down counter is compensated. For example, the common mode level of a 2.5bit pipelined ADC is V_COMThe reference voltage of the pipeline ADC is Vr, so that the level range which can be decoded by the pipeline ADC is V_COM-Vr to V_COM+ Vr, the full scale of the pipeline ADC is 2 Vr. Correspondingly, if the range of the ramp ADC is Vramp _ rst to Vramp _ rst + T2 × K, the full scale of the ramp ADC is T2 × K. First, the minimum Vramp _ rst of the ramp ADC needs to be less than V at all temperatures and process corners_COM-Vr; meanwhile, under various temperature and process angles, the maximum value Vramp _ rst + T2K of the ramp ADC is larger than V_COM+ Vr, the channel level has the corresponding code in the 15-bit adc mode corresponding to one-to-one, so T2 × K is slightly larger than 2 Vr. Let T2K m 2Vr, m>1. Since the analog residual signal of the pipeline ADC is converted to the value of the 13-bit ramp ADC, the full scale of the analog residual signal is still 2Vr, which is T2 × K. The LSB of the 13-bit ramp ADC is T2K/2 ^13, and the LSB of the spliced 15-bit ramp ADC is 2Vr/2^ 15. The analog residual signal of the pipeline ADC is the result of amplifying by 4 times, so the LSB of the pipeline ADC mode corresponding to the analog residual signal should be 2Vr/2^ 13. Since T2 × K — m × 2Vr, the LSB of the 13-bit ramp ADC is equal to the LSB of the pipeline ADC mode corresponding to the m times analog residual signal. Due to m>1, the LSB of the analog residual signal at the pipeline ADC is less than the LSB of the ramp ADC. When the 15-bit ADC value is converted and spliced, the final value of an up-down counter of the ramp ADC is multiplied by m and then spliced with the value obtained by high-order decoding, and the value m is defined as a compensation coefficient. Meanwhile, since the initial value is set, the final result of the up-down counter minus the initial value is required to be converted into a code of the ramp ADC as a residual error. Please refer to fig. 18, wherein B2, B1, and B0 are values output by the two-conversion high-bit pipeline ADC, i.e. the first digital signal, a12 to a0 are final counter results after two comparisons, the initial value is a pre-assigned value of the counter, and m is a compensation coefficient. Because of the 2.5bit pipelined ADC, the most significant bit of the ramp ADC needs to be added aligned with the least significant bit of the pipelined ADC decoding. It should be noted that, since the pipeline ADC is 2.5 bits in the embodiment of the present invention, the 2.5bit pipeline ADC and the 13bit ramp AD are usedC is spliced to obtain a 15-bit ADC, in other embodiments, if the pipeline ADC is 3-bit, the pipeline ADC with 3-bit is spliced to the ramp ADC with 13-bit to obtain the 16-bit ADC, and similarly, when the pipeline ADC with Mbit is spliced to the ramp ADC with Nbit, the pipeline ADC with (M + N) bit is finally obtained, wherein M, N is a positive integer.

The above alignment and superposition process for the first digital signal and the second digital signal may be performed in a data processing module. Reference is made to fig. 19, which is a schematic diagram of an embodiment of a TFT optical fingerprint reading chip. The data processing module includes a first static memory and a second static memory. The first static memory is used for storing a first digital signal, and the second static memory is used for storing a second digital signal. The data processing module also comprises a data processing part; the data processing part is used for receiving the output of the first static memory and the second static memory and outputting the corresponding digital output signals.

For the embodiment mentioned in the above description where the first digital signal and the second digital signal cannot be directly spliced, the data processing section is further configured to perform compensation processing on an output of the first static memory or an output of the second static memory, where the compensation processing includes: and multiplying the output of the first static memory/the second static memory by a compensation coefficient, and splicing the output of the first static memory/the second static memory and the output of the second static memory/the first static memory into the digital output signal with preset bits.

For the first method for improving ramp ADC conversion described above, the digital signal spliced by the data processing module, for example, the 15-bit digital signal, is finally translated by an equivalent amount as a result of the whole value, and the difference between the data remains unchanged, so that the normal discrimination can still be realized. For the second method for increasing the conversion speed of the ramp ADC described above, the ratio of the LSB of the ramp ADC to the LSB corresponding to the analog residual signal of the pipeline ADC remains unchanged and is m times. Therefore, the compensation coefficient is not changed, the calculation mode is still unchanged, the result of the digital signals spliced by the data processing module is equivalent to the whole numerical value and is translated by the same amount, the difference among all the data is unchanged, and the normal discrimination can be still realized.

The data processing module can be an intelligent chip or equipment with data processing capability such as an MCU, an MPU, a DSP or an FPGA, and can be specifically selected according to actual needs without limitation.

Based on the same inventive concept, another embodiment of the present invention further provides a TFT optical fingerprint signal processing method, for converting an analog signal output by the TFT photosensitive array sensor into a digital signal, where the processing method includes:

s1: sampling the TFT photosensitive array sensor by using a photosensitive array sensor sampling circuit;

s2: a first part of signals in the signals output by the photosensitive array sensor sampling circuit are converted into high-order digital signals with preset digits by using a first ADC;

s3: the difference value between the signal output by the photosensitive array sensor sampling circuit and the first part signal is converted into a low-bit digital signal with preset bits by using a second ADC; and

s4: utilizing a data processing module to splice the low-bit digital signal/the high-bit digital signal multiplied by a compensation coefficient and the high-bit digital signal/the low-bit digital signal into a digital signal with a preset bit;

Based on the same inventive concept, please refer to fig. 19, yet another embodiment of the present invention further provides a fingerprint sensor, which includes a TFT photosensitive array sensor and the TFT optical fingerprint reading chip 10 described in any of the above features; the pixel array in the TFT photosensitive array sensor is used for acquiring the lines on the surface of the finger and outputting a corresponding analog signal; the analog-to-digital conversion circuit is used for connecting corresponding columns in the pixel array and converting analog signals in the corresponding columns into digital output signals.

Based on the same inventive concept, another embodiment of the present invention further provides a fingerprint identification system, including the fingerprint sensor.

In conclusion, the invention has the following beneficial effects:

1. the TFT optical fingerprint reading chip provided by the invention comprises a TFT photosensitive array sensor, a photosensitive array sensor sampling circuit, an analog-to-digital conversion circuit and a data processing module, wherein the photosensitive array sensor sampling circuit is used for receiving an analog signal output by the TFT photosensitive array sensor, and the analog-to-digital conversion circuit is formed by splicing a production line ADC and a slope ADC. The high-order in the digital output signal is converted by the pipeline ADC with high utilization precision and high conversion rate, and the low-order in the digital output signal is converted by the slope ADC with simple structure.

2. In the above-described embodiment using the ramp ADC as the second type of ADC, if a general ramp ADC is used, the channel level sampled by the sampling circuit of the photosensitive array sensor is directly connected to the comparator, and the voltage cannot be adjusted, if a large voltage is encountered, the comparison is completed by waiting for the ramp level generated by the ramp generator in the ramp ADC to reach a corresponding value, and the comparator turns over to stop counting by the counter. In the ramp ADC provided as the second ADC, if the signal size of the channel is concentrated in a specific range, the difference between the sampling level of the channel and the common mode level can be adjusted by adding/subtracting a DC level value through the fully differential operational amplifier in the fully differential comparator, thereby saving the time required for Vramp of the ramp generator to reach a corresponding size.

3. The up-down counter is added with a mode selector for switching an initial assignment mode or a normal counting mode and a counter with an initial value assignment function, an initial value can be input through the outside, so that the up-down counter can start to count up or down from the initial value, and the counting time of the up-down counter is controlled, so that the up-down counter can be ensured to continue counting after the two times of counting cannot be triggered to a boundary value of a counting range, and therefore, false counting cannot be triggered.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a TFT optics fingerprint reads out chip, with TFT sensitization array sensor electric connection, its characterized in that, TFT optics fingerprint reads out chip includes sensitization array sensor sampling circuit, analog-to-digital conversion circuit and data processing module, sensitization array sensor sampling circuit is used for receiving the analog signal of TFT sensitization array sensor output, analog-to-digital conversion circuit is used for with sensitization array sensor sampling circuit's output signal converts digital signal into, analog-to-digital conversion circuit includes:

2. The TFT optical fingerprint readout chip of claim 1, wherein a number of bits of the first digital signal is less than a number of bits of the second digital signal.

3. The TFT optical fingerprint readout chip of claim 1 wherein the first type of ADC is a pipeline ADC and the second type of ADC is a ramp ADC.

4. The TFT optical fingerprint readout chip of claim 3, wherein the analog residual signal is a pair of differential signals, the ramp ADC comprising a fully differential comparator to accept the pair of differential signals.

5. The TFT optical fingerprint readout chip of claim 4, wherein the ramp ADC further comprises a ramp generator, an output of the ramp generator being connected to an input of the fully differential comparator.

6. The TFT optical fingerprint readout chip of claim 4, wherein the ramp ADC further comprises an up-down counter connected to an output of the fully differential comparator.

7. The TFT optical fingerprint readout chip of claim 6 wherein the up-down counter includes an input for accepting an initial value from which the up-down counter counts up or down.

8. The TFT optical fingerprint readout chip of claim 7, wherein the up-down counter is provided with a first count window and a second count window within a unit duty cycle of the ramp ADC;

9. The TFT optical fingerprint readout chip of claim 8, wherein the initial value of the up-down counter satisfies the following formula:

(2ⁿ-1)-T2/Tclk≥X>T1/Tclk；

10. The TFT optical fingerprint readout chip of claim 7, wherein the second digital signal is a result of subtracting the initial value from an output of the ramp ADC.

11. The TFT optical fingerprint readout chip of claim 1, wherein the data processing module comprises a first static memory and a second static memory;

12. The TFT optical fingerprint readout chip of claim 11, wherein the data module further comprises a data processing portion;

13. A TFT optical fingerprint signal processing method is used for converting an analog signal output by a TFT photosensitive array sensor into a digital signal, and the processing method comprises the following steps:

14. A TFT optical fingerprint module comprising a TFT photosensitive array sensor and a TFT optical fingerprint readout chip according to any one of claims 1 to 12;